LT3509EMSE#TRPBF [Linear]
LT3509 - Dual 36V, 700mA Step-Down Regulator; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LT3509EMSE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3509 - Dual 36V, 700mA Step-Down Regulator; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总24页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3509
Dual 36V, 700mA
Step-Down Regulator
FeaTures
DescripTion
TheLT®3509isadual,currentmode,step-downswitching
regulator, with internal power switches each capable of
providing700mAoutputcurrent.Thisregulatorprovidesa
compactandrobustsolutionformulti-railsystemsinharsh
environments. It incorporates several protection features
including overvoltage lockout and cycle-by-cycle current
limit. Thermal shutdown provides additional protection.
Theloopcompensationcomponentsandtheboostdiodes
are integrated on-chip. Switching frequency is set by a
single external resistor. External synchronization is also
possible. The high maximum switching frequency allows
the use of small inductors and ceramic capacitors for low
ripple. Constant frequency operation above the AM band
avoidsinterferencewithradioreception,makingtheLT3509
well suited for automotive applications. Each regulator
has an independent shutdown and soft-start control pin.
When both converters are powered down, the common
circuitry enters a low current shutdown state.
n
Two 700mA Switching Regulators with Internal
Power Switches
n
Wide 3.6V to 36V Operating Range
n
Overvoltage Lockout Protects Circuit Through 60V
Supply Transients
Short-Circuit Robust
n
n
Low Dropout Voltage: 95% Maximum Duty Cycle
n
Adjustable 300kHz to 2.2MHz Switching Frequency
Synchronizable Over the Full Range
n
Uses Small Inductors and Ceramic Capacitors
n
Integrated Boost Diodes
Internal Compensation
n
n
Thermally Enhanced 14-Lead (4mm × 3mm)
DFN and 16 Lead MSOP Packages
applicaTions
n
Automotive Electronics
n
Industrial Controls
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
n
Wall Transformer Regulation
n
Networking Devices
n
CPU, DSP, or FPGA Power
Typical applicaTion
3.3V and 5V Dual Output Step-Down Converter
Efficiency
6.5V TO 36V
(TRANSIENT TO 60V)
2.2µF
90
V
IN
BD
85
80
75
70
65
60
55
50
V
= 5V
OUT
BOOST1
BOOST2
0.1µF
0.1µF
10µH
6.8µH
V
= 3.3V
OUT
3.3V
700mA
5V
700mA
SW1
SW2
LT3509
31.6k
53.6k
DA1
FB1
DA2
FB2
MBRM140
MBRM140
22µF
RUN/SS1 RUN/SS2
10µF
V
f
= 12V
IN
SW
1nF
SYNC RT
= 700kHz
1nF
10.2k
GND
10.2k
60.4k
0.2 0.3 0.4 0.5 0.6
LOAD CURRENT (A)
0.0
0.7
0.1
3509 TA01a
f
= 700kHz
SW
3509 TA01b
3509fd
1
For more information www.linear.com/LT3509
LT3509
absoluTe MaxiMuM raTings
(Note 1)
V Pin (Note 2) ........................................................60V
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)
IN
BD Pin.......................................................................20V
BOOST Pins ..............................................................60V
BOOST Pins above SW .............................................30V
RUN/SS, FB, RT, SYNC pins........................................6V
Operating Junction Temperature Range (Notes 3, 6)
LT3509E ............................................ –40°C to 125°C
LT3509I ............................................. –40°C to 125°C
LT3509H............................................ –40°C to 150°C
MSOP Package .................................................300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
DA1
BOOST1
SW1
1
2
3
4
5
6
7
14 FB1
1
2
3
4
5
6
7
8
DA1
BOOST1
SW1
16 FB1
13 RUN/SS1
12 BD
15 RUN/SS1
14 AGND
13 BD
V
V
IN
IN
15
17
V
11 SYNC
10 RT
IN
12 SYNC
11 RT
SW2
BOOST2
DA2
SW2
BOOST2
DA2
10 RUN/SS2
9
8
RUN/SS2
FB2
9
FB2
MSE PACKAGE
16-LEAD PLASTIC MSOP
DE14 PACKAGE
θ
JA
= 43°C/W, θ = 4.3°C/W
JC
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
14-LEAD (4mm × 3mm) PLASTIC DFN
θ
= 43°C/W, θ = 4.3°C/W
JC
JA
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LT3509EDE#PBF
LT3509IDE#PBF
TAPE AND REEL
PART MARKING*
3509
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3509EDE#TRPBF
LT3509IDE#TRPBF
LT3509EMSE#TRPBF
LT3509IMSE#TRPBF
LT3509HMSE#TRPBF
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
16-Lead Plastic MSOP with Exposed Pad
16-Lead Plastic MSOP with Exposed Pad
16-Lead Plastic MSOP with Exposed Pad
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
3509
LT3509EMSE#PBF
LT3509IMSE#PBF
LT3509HMSE#PBF
3509
3509
3509
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3509fd
2
For more information www.linear.com/LT3509
LT3509
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V. (Note 3)
PARAMETER CONDITIONS
MIN
TYP
3.3
38.5
1.9
9
MAX
3.6
UNITS
V
V
V
Undervoltage Lockout
Overvoltage Lockout
IN
IN
37
40
V
Input Quiescent Current
Not Switching V > 0.8V
2.2
mA
µA
V
FB
Input Shutdown Current
V(RUN/SS[1,2]) < 0.3V
15
l
Feedback Pin Voltage
0.784
0.4
0.8
0.01
0.6
0.816
Reference Voltage Line Regulation
RUN/SS Shutdown Threshold
3.6V < V < 36V
%/V
V
IN
0.8
2
RUN/SS Voltage for Full I
V
OUT
RUN/SS Pin Pull-up Current
Feedback Pin Bias Current (Note 4)
Switch Current Limit
0.7
1
1.3
500
1.9
1.2
36
µA
nA
A
l
l
V
= 0.8V
= 0.9A
90
FB
1.05
0.7
1.4
0.95
22
DA Comparator Current Threshold
Boost Pin Current
A
I
mA
µA
V
SW
Switch Leakage Current
0.01
0.32
1.5
0.7
0.1
1.0
Switch Saturation Voltage
Minumum Boost Voltage above Switch
Boost Diode Forward Voltage
Boost Diode Leakage
I
I
I
= 0.9A (Note 5)
= 0.9A
SW
SW
2.2
0.9
5
V
= 20mA
V
BD
V = 30V
µA
R
l
l
Switching Frequency
R = 40.2kΩ
0.92
237
2.0
1.0
260
2.15
1.08
290
2.5
MHz
kHz
T
R = 180kΩ
T
R = 14.1kΩ
MHz
T
Sync Pin Input Threshold
Switch Minimum Off-Time
1.0
80
V
150
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device reliability
and lifetime.
over the full –40°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes. Operating lifetime is
derated at junction temperatures greater than 125°C.
Note 4. Current flows out of pin.
Note 2. Absolute Maximum Voltage at the V pin is 60V for non-repetitive
1 second transients and 36V for continuous operation.
Note 3. The LT3509E is guaranteed to meet performance specifications from
0°C to 125°C junction temperature. Specifications over the –40°C to 125°C
operating junction temperature range are assured by design, characterization
and correlation with statistical process controls. The LT3509I is guaranteed
over the full –40°C to 125°C temperature range. The LT3509H is guaranteed
IN
Note 5. Switch Saturation Voltage is guaranteed by design.
Note6.ThisICincludesovertemperatureprotectionthatisintendedtoprotect
the device during momentary overload conditions. Junction temperature will
exceedthemaximumoperatingtemperaturewhenovertemperatureprotection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
3509fd
3
For more information www.linear.com/LT3509
LT3509
Typical perForMance characTerisTics
Efficiency vs Load Current
VOUT = 5V, fSW = 2.0MHz
Efficiency vs Load Current
VOUT = 1.8V, fSW = 0.7MHz
Efficiency vs Load Current
OUT = 3.3V, fSW = 2.0MHz
V
95
90
95
90
85
80
75
70
65
60
T
= 25ºC
T
= 25ºC
A
T
= 25ºC
A
A
90
85
80
75
70
65
60
55
85
80
75
70
65
60
55
50
V
V
= 12V
= 24V
IN
IN
V
= 12V
IN
V
= 12V
IN
0.4
(A)
0.6
0
0.8
0.2
0.4
0.4
(A)
0.6
0
0.2
0.6
0.8
0
0.8
0.2
I
I
(A)
I
LOAD
LOAD
LOAD
3509 G02
3509 G03
3509 G01
Switch VCE(SAT) vs ISW
IBOOST vs ISW
0.35
0.3
25
20
T
= 25ºC
T
= 25ºC
A
A
0.25
0.2
15
10
5
0.15
0.1
0.05
0
0
0.4
0.6
(A)
0
0.8
1.0
0.2
0
0.4
0.6
(A)
0.8
1
0.2
I
I
SW
SW
3509 G04
3509 G05
Boost Diode Characteristics
Frequency vs RT
1.2
1
2.2
2.0
T
= 25ºC
A
T = 25ºC
A
1.5
1.0
0.5
0.8
0.6
0.4
0.2
0
0
50
BOOST DIODE CURRENT (mA)
0
100
150
20 40 60 80
100 120 140 160 180
0
R (kΩ)
T
3509 G06
3509 G07
3509fd
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For more information www.linear.com/LT3509
LT3509
Typical perForMance characTerisTics
Max VIN for Constant Frequency
VOUT = 3.3V, fSW = 2MHz
fSW vs Temperature
FB Pin Voltage vs Temperature
(Measured at 1MHz)
0.810
0.805
0.800
0.795
1.04
1.03
30
25
T
T
= 25ºC
= 85ºC
A
A
1.02
20
15
10
1.01
1.00
0.99
0.98
5
0
0.790
0.97
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–25
0
150
–50
25 50 75 100 125
TEMPERATURE (˚C)
0.2
0
0.4
0.6
0.8
I
(A)
LOAD
3509 G08
3509 G09
3509 G10
Max VIN for Constant Frequency
VOUT = 5V, fSW = 2MHz
Minimum On-Time vs
Temperature, ILOAD = 0.3A
45
40
35
160
140
120
100
80
T
= 25ºC
= 85ºC
A
T
A
30
25
20
15
10
5
60
40
20
0
0
50 75
TEMPERATURE (°C)
0.2
–50 –25
0
25
100 125 150
0
0.4
0.6
0.8
I
(A)
LOAD
3509 G12
3509 G11
ILIM vs Temperature
ILIM vs Duty Cycle
1.5
1.3
1.0
0.9
0.7
0.5
1.8
1.6
1.4
1.2
1
T
= 25ºC
A
SWITCH
DA
0.8
0.6
0.4
0.2
0
50
TEMPERATURE (°C)
–50 –25
0
25
75 100 125 150
40 50 60 70 80 90
100
0
10
20 30
DUTY CYCLE (%)
3509 G13
3509 G14
3509fd
5
For more information www.linear.com/LT3509
LT3509
pin FuncTions (DFN/MSOP)
DA1, DA2 (Pins 1, 7/Pins 1, 8): The DA pins are the anode
connections for the catch diodes. These are connected
internally to the exposed ground pad by current sensing
resistors.
in the case of overvoltage or overtemperature conditions
in order to discharge the soft-start capacitors. The pins
can also be driven by a logic control signal of up to 5.0V.
In this case, it is necessary place a 10k to 50k resistor
in series along with a capacitor from the RUN/SS pin to
ground to ensure that there will be a soft-start for both
initial turn on and in the case of fault conditions. Do not
BOOST1, BOOST2 (Pins 2, 6/Pins 2, 7): The BOOST pins
are used to dynamically boost the power transistor base
above V to minimize the voltage drop and power loss in
IN
tie these pins to V .
IN
the switch. These should be tied to the associated switch
pins through the boost capacitors.
RT (Pin 10/Pin 11): The RT pin is used to set the internal
oscillator frequency. A 40.2k resistor from RT to ground
results in a nominal frequency of 1MHz.
SW1, SW2 (Pins 3, 5/Pins 3, 6): The SW pins are the
internalpowerswitchoutputs.Theseshouldbeconnected
to the associated inductors, catch diode cathodes, and the
boost capacitors.
SYNC (Pin 11/Pin12): The SYNC pin allows the switching
frequency to be synchronized to a external clock. Choose
R resistor to set a free-run frequency at least 12% less
T
V
(Pin 4/Pins 4, 5): The V pins supply power to the
IN
IN
than the external clock frequency for correct operation.
The SYNC pin should not be allowed to float; if not used,
it should be tied low through a resistance 10kΩ or less.
internal power switches and control circuitry. In the MSE
package the V pins must be tied together. The input
IN
capacitor should be placed as close as possible to the
supply pins.
BD(Pin 12/Pin 13):The BDpin is commonanode connec-
tion of the internal Schottky boost diodes. This provides
the power for charging the BOOST capacitors. It should
be locally bypassed for best performance.
FB1, FB2 (Pins 14, 8/Pins 16, 9): The FB pins are used
to set the regulated output voltage relative to the internal
reference. These pins should be connected to a resistor
divider from the regulated output such that the FB pin is
at 0.8V when the output is at the desired voltage.
Exposed Pad (Pin 15/Pin 17): GND. This is the reference
and supply ground for the regulator. The exposed pad
must be soldered to the PCB and electrically connected to
supply ground. Use a large ground plane and thermal vias
to optimize thermal performance. The current in the catch
diodes also flows through the GND pad to the DA pins.
RUN/SS1,RUN/SS2(Pins13,9/Pins15,10):TheRUN/SS
pins enable the associated regulator channel. If both pins
are pulled to ground, the device will shut-down to a low
power state. In the range 0.8V to 2V, the regulators are
enabled but the peak switch current and the DA pin maxi-
mum current are limited to provide a soft-start function.
Above 2V, the full output current is available. The inputs
incorporate a 1µA pull-up so that they will float high or
charge an external capacitor to provide a current limited
soft-start.Thepinsarepulleddownbyapproximately250µA
AGND(Pin14,MSOPPackageOnly):Thisistheconnected
to the ground connection of the chip and may be used as a
separatereturnforthelowcurrentcontrolsidecomponents.
It should not be used as the only ground connection or as
a connection return for load side components.
3509fd
6
For more information www.linear.com/LT3509
LT3509
block DiagraM
COMMON
CIRCUITRY
1 OF 2 REGULATOR CHANNELS SHOWN
V
IN
BD
C1
NOTE: THE BD PIN
IS COMMON TO
BOTH CHANNELS
OVERVOLTAGE
DETECT
BOOST
DIODE
BOOST
RUN/SS1
RUN/SS2
MAIN CURRENT
COMPARATOR
SHUTDOWN
AND
SOFT-START
CONTROL
POWER
SWITCH
C4
L1
SWITCH
LOGIC
SWITCH
DRIVER
C3
SW
DA
V
OUT
DA CURRENT
C2
V
AND
REF
COMPARATOR
CORE
D1
–17mV
VOLTAGE
REGULATOR
V
C
C5
–
SLOPE
R1
ERROR
AMPLIFIER
SYNC
RT
18mΩ
V
REF
0.8V
OSCILLATOR
FB
R2
CLAMP
R
T
3509 BD
GND
Figure 1. Functional Block Diagram
3509fd
7
For more information www.linear.com/LT3509
LT3509
operaTion
Overview
that when the voltage at FB reaches 0.8V, the main current
comparatorthresholdwillfallandreducethepeakinductor
current and hence the average current, until it matches the
load current. By making current the controlled variable in
the loop, the inductor impedance is effectively removed
from the transfer function and the compensation network
is simplified. The main current comparator threshold is
reduced by the slope compensation signal to eliminate
sub-harmonic oscillations at duty cycles >50%.
The LT3509 is a dual, constant frequency, current mode
switching regulator with internal power switches. The two
independent channels share a common voltage reference
andoscillatorandoperateinphase.Theswitchingfrequency
is set by a single resistor and can also be synchronized to
an external clock. Operation can be best understood by
referring to the Block Diagram (Figure 1).
Startup and Shutdown
Current Limiting
When the RUN/SS[1,2] pins are pulled low (<0.4V) the
associatedregulatorchannelisshutdown.Ifbothchannels
are shut down, the common circuitry also enters a low
currentstate.WhentheRUN/SSpinsexceedapproximately
0.8V, the common circuitry and the associated regulator
are enabled but the output current is limited. From 0.8V
up to 2.0V the current limit increases until it reaches the
full value. The RUN/SS pins also incorporate a 1µA pull-
up to approximately 3V, so the regulator will run if they
are left open. A capacitor to ground will cause a current
limited soft-start to occur at power-up. In the case of
undervoltage, overvoltage or overtemperature conditions
the internal circuitry will pull the RUN/SS pins down with
a current of approximately 250µA. Thus a new soft-start
cycle will occur when the fault condition ends.
Current mode control provides cycle-by-cycle current
limiting by means of a clamp on the maximumcurrent that
can be provided by the switch. A comparator monitors the
current flowing through the catch diode via the DA pin.
This comparator delays switching if the diode current is
higher than 0.95A (typical). This current level is indicative
of a fault condition such as a shorted output with a high
input voltage. Switching will only resume once the diode
current has fallen below the 0.95A limit. This way the DA
comparator regulates the valley current of the inductor to
0.95A during a short circuit. This will ensure the part will
survive a short-circuit event.
Over and Undervoltage Shutdown
A basic undervoltage lockout prevents switching if V
IN
Voltage and Current Regulation
is below 3.3V (typical). The overvoltage shutdown stops
the part from switching when V is greater than 38.5V
IN
The power switches are controlled by a current-mode
regulator architecture. The power switch is turned on at
the beginning of each clock cycle and turned off by the
main current comparator. The inductor current will ramp
up while the switch is on until it reaches the peak current
threshold. The current at which it turns off is determined
by the error amp and the internal compensation network.
When the switch turns off, the current in the inductor
will cause the SW pin to fall rapidly until the catch diode,
D1, conducts. The voltage applied to the inductor will
now reverse and the current will linearly fall. The resistor
divider, R1 and R2, sets the desired output voltage such
(typical). This protects the device and its load during
momentary overvoltage events. After the input voltage
falls below 38.5V, the part initiates a soft start sequence
and resumes switching.
BOOST Circuit
To ensure best efficiency and minimum dropout voltage
the output transistor base drive is boosted above V by
IN
the external boost capacitors (C4). When the SW pin is
low the capacitors are charged via the BOOST diodes and
the supply on BD.
3509fd
8
For more information www.linear.com/LT3509
LT3509
applicaTions inForMaTion
Shutdown and Soft Start
Setting The Output Voltage
When the RUN/SS pins are pulled to ground, the part will
shut down to its lowest current state of approximately
9µA. If driving a large capacitive load it may be desirable
to use the current limiting soft-start feature. Connecting
capacitors to ground from the RUN/SS pins will control
the delay until full current is available. The pull-up current
is 1µA and the full current threshold is 2V so the start-up
time is given by:
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistors
according to:
V
R1=R2• OUT –1
0.8
The designators correspond to Figure 1. R2 should be 20k
or less to avoid bias current errors.
6
T = 2 • C • 10 s
Frequency Setting
For example a 0.005µF capacitor will give a time to full
current of 10ms. If both outputs can come up together
then the two inputs can be paralleled and tied to one ca-
pacitor. In this case use twice the capacitor value to obtain
the same start-up time. During the soft-start time both
the peak current threshold and the DA current threshold
will track so the part will skip pulses as required to limit
the maximum inductor current. Starting up into a large
capacitor is not much different to starting into a short-
circuit in this respect.
The timing resistor, R , for any desired frequency in the
T
range 264kHz to 2.2MHz can be calculated from the
following formula:
1.215
fSW
R =
– 0.215 • 40.2
T
where f is in MHz and R is in kΩ.
SW
T
Table 1. Standard E96 Resistors for Common Frequencies
FREQUENCY
264 kHz
300 kHz
400kHz
500kHz
1MHz
TIMING RESISTOR R (kΩ)
T
178
154
V
SW
10V/DIV
113
88.7
40.2
15.8
13.7
I
L
0.2A/DIV
2MHz
V
OUT
5V/DIV
2.2MHz
3509 F02
TIME 1ms/DIV
Note: The device is specified for operation down to 300kHz. The 264kHz
value is to allow external synchronization at 300kHz
Figure 2. Soft-Start
3509fd
9
For more information www.linear.com/LT3509
LT3509
applicaTions inForMaTion
External Synchronization
the input voltage during the switch on time. Depending
on the input and output voltages the boost supply can be
providedbytheinputvoltage, oneoftheregulatedoutputs
or an independent supply such as an LDO.
The external synchronization provides a trigger to the
internal oscillator. As such, it can only raise the frequency
above the free-run value. To allow for device and
component tolerances, the free run frequency should be
set to at least 12% lower than the lowest supplied external
synchronization reference. The oscillator and hence the
switching frequency can then pushed up from 12% above
Input Voltage Range
Firstly, the LT3509 imposes some hard limits due to the
undervoltage lock-out and the overvoltage protection. A
givenapplicationwillalsohaveareduced,normaloperating
range over which maximum efficiency and lowest ripple
are obtained. This usually requires that the device is
operating at a fixed frequency without skipping pulses.
There may also be zones above and below the normal
range where regulation is maintained but efficiency and
ripple may be compromised. At the low end, insufficient
input voltage will cause loss of regulation and increased
ripple—this is the dropout range. At the high end if the
duty cycle becomes too low this will cause pulse skipping
and excessive ripple. This is the pulse-skip region. Both
situationsalsoleadtohighernoiseatfrequenciesotherthan
the chosen switching frequency. Occasional excursions
into pulse-skip mode, during surges for example, may be
tolerable. Pulse skipping will also occur at light loads even
within the normal operating range but ripple is usually not
degraded because at light load the output capacitor can
hold the voltage steady between pulses.
thefree-runfrequency,setbytheselectedR .Forexample,
T
if the minimum external clock is 300kHz, the R should
T
be chosen for 264kHz.
The SYNC input has a threshold of 1.0V nominal so it is
compatible with most logic levels. The duty cycle is not
critical provided the high or low pulse width is at least
80ns. If not used, the SYNC input should be tied low with
10kΩ less to avoid noise pickup.
Design Procedure
Before starting detailed design a number of key design
parameters should be established as these may affect
design decisions and component choices along the way.
Oneofthemainthingstodetermineapartfromthedesired
outputvoltagesistheinputvoltagerange. Boththenormal
operating range and the extreme conditions of surges
and/or dips or brown-outs need to be known. Then the
operating frequency should be considered and if there
are particular requirements to avoid interference. If there
are very specific frequencies that need to be avoided then
externalsynchronizationmaybeneeded.Thiscouldalsobe
desirable if multiple switchers are used as low frequency
beating between similar devices can be undesirable. For
efficientoperationthisconverterrequiresaboostsupplyso
thatthebaseoftheoutputtransistorcanbepumpedabove
For input voltages greater than 30V, there are restrictions
on the inductor value. See the Inductor Selection section
for details.
To ensure the regulator is operating in continuous mode
it is necessary to calculate the duty cycle for the required
output voltage over the full input voltage range. This must
then be compared with minimum and maximum practical
duty cycles.
3509fd
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In any step-down switcher the duty cycle when operating
in continuous, or fixed frequency, mode is dependent
on the step-down ratio. This is because for a constant
average load current the decay of the inductor current
when the switch is off must match the increase in inductor
current when the switch is on. The can be estimated by
the following formula:
The minimum on time increases with increasing tempera-
ture so the value for the maximum operating temperature
shouldbeused.SeetheMinimumOn-TimevsTemperature
graph in the Typical Performance Characteristics.
The maximum input voltage for this duty cycle is given by:
V
OUT + V
DCMIN
VIN(MAX)
=
F − VF + VSW
V
OUT + VF
DC =
VIN − VSW + VF
Above this voltage the only way the LT3509 can maintain
regulation is to skip cycles so the effective frequency will
reduce.Thiswillcauseanincreaseinrippleandtheswitch-
ing noise will shift to a lower frequency. This calculation
will in practice drive the maximum switching frequency
for a desired step-down ratio.
where:
DC = Duty Cycle (Fraction of Cycle when Switch is On)
= Output Voltage
V
OUT
V = Input Voltage
IN
V = Catch Diode Forward Voltage
F
V
OUT
V
SW
= Switch Voltage Drop
100mV/DIV
(AC COUPLED)
Note:Thisformulaneglectsswitchingandinductorlosses
so in practice the duty cycle may be slightly higher.
I
L
0.5A/DIV
Itisclearfromthisequationthatthedutycyclewillapproach
100% as the input voltage is reduced and become smaller
as the input voltage increases. There are practical limits to
the minimum and maximum duty cycles for continuous
operation due to the switch minimum off and on times.
Theseareindependentofoperatingfrequencysoitisclear
thatrangeofusabledutycycleisinverserlyproportionalto
frequency. Therefore at higher frequency the input voltage
range (for constant frequency operation) will narrow.
3509 F03
TIME 1µs/DIV
Figure 3. Continuous Mode
V
OUT
100mV/DIV
(AC COUPLED)
The minimum duty cycle is given by:
I
L
0.5A/DIV
DCMIN = fSW • tON(MIN)
where:
3509 F04
TIME 1µs/DIV
f
t
= Switching Frequency
SW
= Switch Minimum On-Time
Figure 4. Pulse Skipping
ON(MIN)
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Minimum Input Voltage and Boost Architecture
boost capacitors to fully saturate the switch. This is most
problematicwhentheBDpinissuppliedfromtheregulated
output. The net result is that a higher input voltage will be
requiredtostartuptheboostsystem.Thetypicalminimum
input voltage over a range of loads is shown in Figure 5
for 3.3V and Figure 6 for 5V.
The minimum operating voltage is determined either by
the LT3509’s internal undervoltage lockout of ~3.6V or
by its maximum duty cycle. The maximum duty cycle for
fixed frequency operation is given by:
DCMAX =1− tOFF(MIN) • fSW
Whenoperatingatsuchhighdutycyclesthepeakcurrents
in the boost diodes are greater and this will require a the
BD supply to be somewhat higher than would be required
atlessextremedutycycles.Ifoperationatlowinput/output
ratios and low BD supply voltages is required it may be
desirabletoaugmenttheinternalboostdiodeswithexternal
discrete diodes in parallel.
It follows that:
V
OUT + V
VIN(MIN)
=
F − VF + VSW
DCMAX
If a reduction in switching frequency can be tolerated the
minimum input voltage can drop to just above output
voltage. Not only is the output transistor base pumped
above the input voltage by the boost capacitor, the
switch can remain on through multiple switching cycles
resulting in a high effective duty cycle. Thus, this is a
true low dropout regulator. As it is necessary to recharge
the boost capacitor from time to time, a minimum width
off-cyclewillbeforcedoccasionallytomaintainthecharge.
Depending on the operating frequency, the duty cycle can
reach97%to98%,althoughatthispointtheoutputpulses
will be at a sub-multiple of the programmed frequency.
One other consideration is that at very light loads or no
load the part will go into pulse skipping mode. The part
will then have trouble getting enough voltage on to the
Boost Pin Considerations
The boost capacitor, in conjunction with the internal boost
diode,providesabootstrappedsupplyforthepowerswitch
that is above the input voltage. For operation at 1MHz and
above and at reasonable duty cycles a 0.1µF capacitor
will work well. For operation at lower frequencies and/or
higher duty cycles something larger may be needed. A
good rule of thumb is:
1
CBOOST
=
10 • fSW
where f is in MHz and C
is in µF
SW
BOOST
5.5
7
TO START
5
TO START
6.5
4.5
6
4
TO RUN
TO RUN
5.5
3.5
5
4.5
4
3
2.5
2
0.1
0.01
LOAD CURRENT (A)
0.1
0.001
1
0.001
1
0.01
LOAD CURRENT (A)
3509 F05
3509 F06
Figure 5. Minimum VIN for 3.3V VOUT
Figure 6. Minimum VIN for 5V VOUT
3509fd
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Boost Pin Considerations
In any case, be sure that the maximum voltage at the
BOOST pin is less than 60V and the voltage difference
between the BOOST and SW pins is less than 30V.
Figure 7 through Figure 9 show several ways to arrange
the boost circuit. The BOOST pin must be more than 2V
above the SW pin for full efficiency. For outputs of 3.3V
and higher, the standard circuit Figure 7 is best. For lower
output voltages, the boost diode can be tied to the input
Figure 8. The circuit in Figure 7 is more efficient because
the boost pin current comes from a lower voltage source.
Finally, as shown in Figure 9, the BD pin can be tied to
another source that is at least 3V. For example, if you are
generating 3.3V and 1.8V, and the 3.3V is on whenever
the 1.8V is on, the 1.8V boost diode can be connected to
the 3.3V output.
Inductor Selection and Maximum Output Current
A good first choice for the inductor value is:
2.1MHz
L =(VOUT + VF)•
fSW
where V is the voltage drop of the catch diode (~0.5V)
F
and L is in µH.
Theinductor’sRMScurrentratingmustbegreaterthanthe
maximum load current and its saturation current should
be at least 30% higher. For highest efficiency, the series
resistance (DCR) should be less than 0.15Ω. Table 2 lists
several vendors and types that are suitable.
BD
V
V
IN
IN
BOOST
C
BOOST
LT3509
L1
Thecurrentintheinductorisatrianglewavewithanaverage
value equal to the load current. The peak switch current
is equal to the output current plus half the peak-to-peak
inductorripplecurrent.TheLT3509limitsitsswitchcurrent
in order to protect itself and the system from overcurrent
faults. Therefore, the maximum output current that the
LT3509 will deliver depends on the switch current limit,
the inductor value and the input and output voltages.
V
C
SW
DA
OUT
C
IN
D1
OUT
GND
OUT
3509 F07
V
– V ≅ V
SW
BOOST
MAX V
V
≅ V + V
IN OUT
BOOST
≥ 3V
OUT
Figure 7. BD Tied to Regulated Output
V
BD
BD
BD
BOOST
LT3509
V
V
IN
IN
C
BOOST
BOOST
C
BOOST
V
V
IN
IN
L1
V
C
LT3509
SW
OUT
L1
C
IN
V
C
SW
DA
OUT
D1
C
IN
OUT
D1
DA
GND
OUT
GND
3509 F09
V
– V ≅ V
SW BD
3509 F08
BOOST
MAX V
≅ V + V
IN BD
BOOST
V
– V ≅ V
SW
BOOST
IN
IN
V
≥ 3V
BD
MAX V
≅ 2V
BOOST
Figure 9. Separate Boost Supply
Figure 8. Supplied from VIN
3509fd
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When the switch is off, the potential across the inductor is
theoutputvoltageplusthecatchdiodeforwardvoltage.This
gives the peak-to-peak ripple current in the inductor:
There is a limit to the actual minimum duty cycle imposed
bytheminimumon-timeoftheswitch. Forarobustdesign
it is important that inductor that will not saturate when
the switch is at its minimum on-time, the input voltage
is at maximum and the output is short circuited. In this
case the full input voltage, less the drop in the switch, will
appear across the inductor. This doesn’t require an actual
short, just starting into a capacitive load will provide the
same conditions. The Diode current sensing scheme will
ensure that the switch will not turn-on if the inductor
current is above the DA current limit threshold, which has
a maximum of 1.1A. The peak current under short-circuit
conditions can then be calculated from:
V
OUT + VF
∆IL =(1–DC)
L • fSW
where:
DC = Duty Cycle
= Switching Frequency
f
SW
L = Inductor Value
V = Diode Forward Voltage
F
V • tON(MIN)
IN
The peak inductor and switch current is:
IPEAK
=
+1.1A
L
∆IL
2
I
SWPK =ILPK =IOUT +
Theinductorshouldhaveasaturationcurrentgreaterthan
this value. For safe operation with high input voltages this
canoftenmeanusingaphysicallylargerinductorashigher
value inductors often have lower saturation currents for
a given core size. As a general rule the saturation current
shouldbeatleast1.8Atobeshort-circuitproof.However,it’s
generallybettertouseaninductorlargerthantheminimum
value. For robust operation at input voltages greater than
30V, use an inductor with a value of 4.2µH or greater, and
a saturation current rating of 1.8A or higher. The minimum
inductor has large ripple currents which increase core
losses and require large output capacitors to keep output
To maintain output regulation, this peak current must be
less than the LT3509’s switch current limit I . This is
LIM
dependent on duty cycle due to the slope compensation.
For I is at least 1.4A at low duty cycles and decreases
LIM
linearly to 1.0A at DC = 0.8.
The theoretical minimum inductance can now be calcu-
lated as:
V
OUT + VF
1–DCMIN
f
LMIN
=
•
ILIM –IOUT
voltage ripple low. Select an inductor greater than L
MIN
where DC
is the minimum duty cycle called for by the
MIN
that keeps the ripple current below 30% of I
.
LIM
application i.e.:
V
OUT(MAX) + VF
DCMIN
=
V
IN(MIN) – VSW + VF
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Table 2. Recommended Inductors
The prior analysis is valid for continuous mode operation
(I
> ∆I / 2). For details of maximum output current
OUT
LIM
MANUFACTURER/
PART NUMBER
VALUE
(µH)
I
DCR
(W)
HEIGHT
(mm)
SAT
(A)
indiscontinuousmodeoperation, seeLinearTechnology’s
Coilcraft
Application Note 44. Finally, for duty cycles greater than
LPS4018-222ML
LPS5030-332ML
LPS5030-472ML
LPS6225-682ML
LPS6225-103ML
Sumida
2.2
3.3
4.7
6.8
10
2.8
2.5
2.5
2.7
2.1
0.07
0.066
0.083
0.095
0.105
1.7
2.9
2.9
2.4
2.4
50% (V /V > 0.5), a minimum inductance is required
OUT IN
to avoid subharmonic oscillations. This minimum induc-
tance is
1.4
fSW
L
MIN =(VOUT + VF)•
CDRH4D22/HP-2R2N
CDRH4D22/HP-3R5N
CDRH4D22/HP-4R7N
CDRH5D28/HP-6R8N
CDRH5D28/HP-8R2N
CDRH5D28R/HP-100N
Cooper
2.2
3.5
4.7
6.8
8.2
10
3.2
2.5
2.2
3.1
2.7
2.45
0.0035
0.052
0.066
0.049
0.071
0.074
2.4
2.4
2.4
3.0
3.0
3.0
where f is in MHz and L
is in µH.
MIN
SW
If using external synchronization, calculate L using the
R frequency and not the SYNC frequency.
T
MIN
Frequency Compensation
The LT3509 uses current mode control to regulate the
output, which simplifies loop compensation and allows
thenecessaryfiltercomponentstobeintegrated.Thefixed
internal compensation network has been chosen to give
stable operation over a wide range of operating conditions
but assumes a minimum load capacitance. The LT3509
does not depend on the ESR of the output capacitor for
stability so the designer is free to use ceramic capacitors
to achieve low output ripple and small PCB footprint.
SD52-2R2-R
2.2
3.5
2.30
1.82
1.64
1.8
0.0385
0.0503
0.0568
0.045
2.0
2.0
2.0
3.0
3.0
3.0
SD52-3R5-R
SD52-4R7-R
4.7
SD6030-5R8-R
SD7030-8R0-R
SD7030-100-R
Toko
5.8
8.0
1.85
1.7
0.058
10.0
0.065
A997AS-2R2N
A997AS-3R3N
A997AS-4R7M
Würth
2.2
3.3
4.7
1.6
1.2
0.06
0.07
0.1
1.8
1.8
1.8
Figure10showsanequivalentcircuitfortheLT3509control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor is modeled as a
transconductance amplifier generating an output current
proportional to the voltage at the COMP-NODE. The gain
of the power stage (gmp) is 1.1S. Note that the output
capacitor integrates this current and that the internal
capacitor integrates the error amplifier output current,
resulting in two poles in the loop. In most cases, a zero is
required and comes either from the output capacitor ESR
1.07
7447745022
2.2
3.3
4.7
7.6
10
3.5
3.0
2.4
1.8
1.6
0.036
0.045
0.057
0.095
0.12
2.0
2.0
2.0
2.0
2.0
7447745033
7447745047
7447745076
7447445100
3509fd
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You can estimate output ripple with the following
equations.
or from R . This model works well as long as the inductor
C
current ripple is not too low (∆I
> 5% I ) and the
SW
RIPPLE
OUT
loop crossover frequency is less than f /5. An optional
For ceramic capacitors where low capacitance value is
more significant than ESR:
phase lead capacitor (CPL) across the feedback divider
may improve the transient response.
VRIPPLE =∆IL /(8 • fSW •COUT )
LT3509
1.1S
For electrolytic capacitors where ESR is high relative to
capacitive reactance:
V
V
OUT
IN
C
PL
R1
R2
V
RIPPLE =∆IL •ESR
COMP-
NODE
–
+
260µS
1.73M
where∆I isthepeak-to-peakripplecurrentintheinductor.
L
R
75k
95pF
C
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
C
V
= 0.8V
OUT
REF
3509 F10
IC(RMS) =∆IL / 12
Another constraint on the output capacitor is that it must
havegreaterenergystoragethantheinductor;ifthestored
energyintheinductortransferstotheoutput, theresulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
Figure 10. Small-Signal Equivalent Circuit
Output Capacitor Selection
Theoutputcapacitorfilterstheinductorcurrenttogenerate
an output with low voltage ripple. It also stores energy in
order to satisfy transient loads and stabilize the LT3509’s
control loop. Because the LT3509 operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
2
COUT >10•L •(ILIM / VOUT)
The low ESR and small size of ceramic capacitors make
them the preferred type for LT3509 applications. Not all
ceramic capacitors are the same, however. Many of the
higher value capacitors use poor dielectrics with high
temperature and voltage coefficients. In particular, Y5V
3509fd
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and Z5U types lose a large fraction of their capacitance
withappliedvoltageandattemperatureextremes.Because
loop stability and transient response depend on the value
the top feedback resistor. The small-signal model shown
in Figure 10 can be used to model this in a simulator or
to give insight to an empirical design. Figure 11 shows
someloadstepresponseswithdifferingoutputcapacitors
of C , this loss may be unacceptable. Use X7R and X5R
OUT
types.
and C combinations.
PL
The value of the output capacitor greatly affects the
transient response to a load step. It has to supply extra
current demand or absorb excess current delivery until
the feedback loop can respond. The loop response is
dependent on the error amplifier transconductance, the
internal compensation capacitor and the feedback net-
work. Higher output voltages necessarily require a larger
feedback divider ratio. This will also reduce the loop gain
and slow the response time. Fortunately this effect can be
Input Capacitor
The input capacitor needs to supply the pulses of charge
demanded during the on time of the switches. Little total
capacitanceisrequiredasafewhundredmillivoltsofripple
at the V pin will not cause any problems to the device.
IN
When operating at 2MHz and 12V, 2µF will work well. At
thelowestoperatingfrequencyand/oratlowinputvoltages
a larger capacitor such as 4.7µF is preferred.
mitigated by use of a feed-forward capacitor, C , across
PL
I
LOAD
I
LOAD
700mA
300mA
700mA
300mA
V
(AC)
V
(AC)
OUT
OUT
50mV/DIV
50mV/DIV
3509 F11
TIME 20µs/DIV
TIME 20µs/DIV
C
C
= 10µF
C
C
= 10µF
OUT
OUT
PL
= 0
= 82pF
PL
Figure 11. Transient Load Response with Different Combinations
of COUT and CPL Load Current Step from 300mA to 700mA
R1 = 10k, R2 = 32.4k, VIN = 12V, VOUT = 3.3V, fSW = 2.0MHz
3509fd
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Diode Selection
providing the boost supply to the BD pin. In this case the
voltage drop of the other switch will increase and lower
theefficiency.Thiscouldeventuallycausetheparttoreach
the thermal shutdown limit. One other important feature
of the part that needs to be considered is that there is a
parasitic diode in parallel with the power switch. In normal
operation this is reverse biased but it could conduct if the
load can be powered from an alternate source when the
LT3509 has no input. This may occur in battery charging
applications or in battery backup systems where a bat-
tery or some other supply is diode ORed with one of the
LT3509 regulated outputs. If the SW pin is at more than
The catch diode (D1 from Figure 1) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
ID(AVG) =IOUT(VIN – VOUT)/ VIN
The only reason to consider a diode with a larger current
rating than necessary for nominal operation is for the
worst-case condition of shorted output. The diode current
will then increase to the typical peak switch current limit.
If transient input voltages exceed 40V, use a Schottky
diode with a reverse voltage rating of 45V or higher. If
the maximum transient input voltage is under 40V, use a
Schottky diode with a reverse voltage rating greater than
the maximum input voltage. Table 3 lists several Schottky
diodes and their manufacturers:
about4VtheV pincanattainsufficientvoltageforLT3509
IN
control circuitry to power-up to the quiescent bias level
and up to 2mA could be drawn from the backup supply.
This can be minimized if some discreteFETs oropen-drain
buffers are used to pull down the RUN/SS pins. Of course
the gates need to be driven from the standby or battery
backed supply. If there is the possibility of a short circuit
Table 3. Schottky Diodes
MANUFACTURER/
PART NUMBER
V
I
V at 1A
R
AVE
F
(V)
40
40
(A)
(mV)
at the input or just other parallel circuits connected to V
IN
On Semiconductor
MBRM140
it would be best to add a protection diode in series with
1
550
V . This will also protect against a reversed input polarity.
IN
These concepts are illustrated in Figure 12.
MicroSemi
UPS140
1
450
D2
Diodes Inc.
DFLS140L
V
V
BD
IN
IN
40
40
1
1
550
450
BOOST
C
IN
C
1N5819HW
BOOST
L1
LT3509
RUN/SS1
V
OUT
SW
DA
Short and Reverse Protection
Provided the inductors are chosen to not go deep into
their saturation region at the maximum I current the
D1
C
OUT
RUN/SS2
GND
LIMIT
LT3509 will tolerate a short circuit on one or both outputs.
The excess current in the inductor will be detected by the
DA comparator and the frequency will reduced until the
valley current is below the limit. This shouldn’t affect the
other channel unless the channel that is shorted is also
3509 F12
SLEEP
Figure 12. Reverse Bias Protection
3509fd
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Hot Plugging Considerations
• The loop from the regulated outputs through the output
capacitor back to the ground plane. Excess impedance
here will result in excessive ripple at the output.
The small size, reliability and low impedance of ceramic
capacitors make them attractive for the input capacitor.
Unfortunately they can be hazardous to semiconductor
devices if combined with an inductive supply loop and a
fastpowertransitionsuchasthroughamechanicalswitch
or connector. The low loss ceramic capacitor combined
with the just a small amount of wiring inductance forms
an underdamped resonant tank circuit and the voltage at
The area of the SW and BOOST nodes should as small as
possible. Also the feedback components should be placed
as close as possible to the FB pins so that the traces are
short and shielded from the SW and BOOST nodes by the
ground planes.
Figure 13 shows a detail view of a practical board layout
showingjustthetoplayer.Thecompleteboardissomewhat
larger at 7.5cm × 7.5cm. The device has been evaluated
on this board in still air running at 700kHz switching fre-
quency. One channel was set to 5V and the other to 3.3V
and both channels were fully loaded to 700mA. The device
temperature reached approximately 15°C above ambient
for input voltages below 12V. At 24V input it was slightly
higher at 17°C above ambient.
the V pin of the LT3509 can ring to twice the nominal
IN
input voltage. See Linear Technology Application Note 88
for more details.
PCB Layout and Thermal Design
The PCB layout is critical to both the electrical and thermal
performanceoftheLT3509.Mostimportantistheconnec-
tion to the Exposed Pad which provides the main ground
connection and also a thermal path for cooling the chip.
This must be soldered to a topside copper plane which
is also tied to backside and/or internal plane(s) with an
array of thermal vias.
To obtain the best electrical performance particular
attention should be paid to keeping the following current
paths short:
• The loop from the V pin through the input capacitor
IN
back to the ground pad and plane. This sees high di/dt
transitions as the power switches turn on and off. Ex-
cessimpedancewilldegradetheminimumusableinput
voltage and could cause crosstalk between channels.
• The loops from the switch pins to the catch diodes and
back to the DA pins. The fast changing currents and
voltage here combined with long PCB traces will cause
ringing on the switch pin and may result in unwelcome
EMI.
Figure 13. Sample PCB Layout (Top Layer Only)
3509fd
19
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LT3509
Typical applicaTions
1.8V and 3.3V Outputs, Synchronized to 300kHz to 600kHz
V
IN
4.5V TO 36V
(TRANSIENT TO 60V)
2.2µF
V
IN
BD
BOOST1
BOOST2
0.22µF
0.22µF
10µH
15µH
31.6k
V
3.3V
0.7A
V
1.8V
0.7A
OUT
OUT
SW1
SW2
LT3509
UPS140
UPS140
DA1
FB1
DA2
FB2
12.4k
CLOCK
RUN/SS1 RUN/SS2
SYNC RT GND
10k
10k
22µF
22nF
22nF
22µF
1.6V
0.4V
178k
3509 TA03
NOTE: R CHOSEN FOR 264kHz
T
Automotive Accessory Application
5V Logic Supply and 8V for LCD Display with Display Power Controlled by Logic
V
IN
9.4V TO 36V
2.2µF
V
IN
BD
BOOST1
BOOST2
0.22µF
0.22µF
10µH
6.8µH
V
8V
0.7A
V
OUT
OUT
SW1
SW2
5V
0.7A
LT3509
DFLS140L
52.3k
DFLS140L
90.9k
DA1
FB1
DA2
FB2
RUN/SS1 RUN/SS2
SYNC RT GND
10k
10k
10k
22nF
0.1µF
10µF
10µF
40.2k
3509 TA04
DISPLAY POWER
CONTROL
0V = OFF
3.3V = ON
f
= 1MHz
SW
3509fd
20
For more information www.linear.com/LT3509
LT3509
package DescripTion
Please refer to http://www.linear.com/product/LT3509#packaging for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
1.70 ±0.05
3.60 ±0.05
2.20 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
0.40 ±0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.05
TYP
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ±0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DE14) DFN 0806 REV B
7
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3509fd
21
For more information www.linear.com/LT3509
LT3509
package DescripTion
Please refer to http://www.linear.com/product/LT3509#packaging for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3509fd
22
For more information www.linear.com/LT3509
LT3509
revision hisTory (Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
4/10
Changed Pin Name to RT
1, 2, 6, 7, 20,
21, 24
Revised Absolute Maximum Ratings
2
3
Updated Notes and Change/Add Values in Electrical Characteristics
Revised Values in Typical Performance Characteristics
Revised Values in Pin Functions
5
6
Revised Values in Startup and Shutdown Section
Revised Values in Shutdown and Soft-Start, Frequency Setting Sections, and Table 1
8
9
D
01/16 Clarified Sync Pin Function Description
6
Clarified External Synchronization Applications Information
10
3509fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3509
Typical applicaTions
2MHz, 5V and 3.3V Outputs
V
IN
6.5V TO 16V
(TRANSIENT TO 60V)
2.2µF
V
IN
BD
BOOST1
BOOST2
0.1µF
MBRM140
31.6k
6.8µH
0.1µF
4.7µH
V
3.3V
0.7A
V
OUT
OUT
5V
SW1
SW2
0.7A
MBRM140
LT3509
DA1
FB1
DA2
FB2
52.3k
RUN/SS1 RUN/SS2
SYNC RT GND
22nF
10k
10µF
10µF
16.9k
22nF
10k
3509 TA02
f
= 2MHz
SW
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LT1766
LT1936
LT1939
60V, 1.2A (I ), 200kHz, High Efficiency Step-Down DC/DC Converter V : 5.5V to 60V, V
= 1.20V, I = 2.5mA, I < 25µA, TSSOP16/E
Q SD
OUT
IN
OUT
Package
36V, 1.4A (I ) , 500kHz High Efficiency Step-Down DC/DC Converter V : 36V to 36V, V
= 1.20V, I = 1.9mA, I < 1µA, MS8E
Q SD
OUT
IN
OUT
Package
25V, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO Controller V : 3.6V to 25V, V
= 0.8V, I = 2.5µA, I < 10µA, 3mm × 3mm
Q SD
IN
OUT
OUT
OUT
OUT
DFN-10
LT1976/
LT1977
LT3434/
LT3435
60V, 1.2A (I ), 200/500kHz, High Efficiency Step-Down
V : 3.3V to 60V, V
= 1.20V, I = 100µA, I < 1µA, TSSOP16E
Q SD
OUT
IN
DC/DC Converter with Burst Mode® Operation
Package
60V, 2.4A (I ), 200/500kHz, High Efficiency Step-Down
V : 3.3V to 60V, V
= 1.20V, I = 100µA, I < 1µA, TSSOP16E
Q SD
OUT
IN
DC/DC Converter with Burst Mode Operation
Package
LT3437
LT3480
LT3481
LT3493
LT3500
LT3501
LT3505
60V, 400mA (I ), MicroPower Step-Down DC/DC Converter
V : 3.3V to 60V, V
= 1.25V, I = 100µA, I < 1µA, 3mm × 3mm
Q SD
OUT
IN
with Burst Mode Operation
DFN-10, TSSOP-16E Package
V : 3.6V to 38V, V = 0.78V, I = 70µA, I < 1µA, 3mm × 3mm
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High
OUT
IN
OUT
Q
SD
Efficiency Step-Down DC/DC Converter with Burst Mode Operation DFN-10, MSOP-10E Package
34V with Transient Protection to 36V, 2A (I ), 2.8MHz, High V : 3.6V to 34V, V = 1.26V, I = 50µA, I < 1µA, 3mm × 3mm
OUT
IN
OUT
Q
SD
Efficiency Step-Down DC/DC Converter with Burst Mode Operation DFN-10, MSOP-10E Package
36V, 1.4A(I ), 750kHz High Efficiency Step-Down DC/DC
V : 36V to 36V, V
= 0.8V, I = 1.9mA, I < 1µA, 2mm × 3mm
OUT Q SD
OUT
IN
Converter
DFN-6 Package
36V, 40Vmax, 2A, 2.5MHz High Efficiency DC/DC Converter
and LDO Controller
V : 3.6V to 36V, V
= 0.8V, I = 2.5mA, I < 10µA, 3mm × 3mm
Q SD
IN
OUT
OUT
OUT
DFN-10
25V, Dual 3A (I ), 1.5MHz High Efficiency Step-Down
V : 3.3V to 25V, V
= 0.8V, I = 3.7mA, I = 10µA, TSSOP-20E
Q SD
OUT
IN
DC/DC Converter
Package
36V with Transient Protection to 40V, 1.4A (I ), 3MHz,
V : 3.6V to 34V, V
= 0.78V, I = 2mA, I < 2µA, 3mm × 3mm
Q SD
OUT
IN
High Efficiency Step-Down DC/DC Converter
DFN-8, MSOP-8E Package
V : 3.6V to 25V, V = 0.8V, I = 3.8mA, I = 30µA, 5mm × 4mm
LT3506/
LT3506A
25V, Dual 1.6A (I ), 575kHz,/1.1MHz High Efficiency
OUT
IN
OUT
Q
SD
Step-Down DC/DC Converter
DFN-16 TSSOP-16E Package
LT3507
LT3508
LT3510
LT3684
LT3685
36V 2.5MHz, Triple (2.4A + 1.5A + 1.5A (I )) with LDO
V : 4V to 36V, V
= 0.8V, I = 7mA, I = 1µA, 5mm × 7mm
OUT Q SD
OUT
IN
Controller High Efficiency Step-Down DC/DC Converter
QFN-38
36V with Transient Protection to 40V, Dual 1.4A (I ), 3MHz,
V : 3.7V to 37V, V
= 0.8V, I = 4.6mA, I = 1µA, 4mm × 4mm
OUT Q SD
OUT
IN
High Efficiency Step-Down DC/DC Converter
QFN-24, TSSOP-16E Package
25V, Dual 2A (I ), 1.5MHz High Efficiency Step-Down
V : 3.3V to 25V, V
= 0.8V, I = 3.7mA, I = 10µA, TSSOP-20E
Q SD
OUT
IN
OUT
OUT
DC/DC Converter
Package
34V with Transient Protection to 36V, 2A (I ), 2.8MHz,
V : 3.6V to 34V, V
= 1.26V, I = 850µA, I < 1µA, 3mm × 3mm
Q SD
OUT
IN
High Efficiency Step-Down DC/DC Converter
DFN-10, MSOP-10E Package
V : 3.6V to 38V, V = 0.78V, I = 70µA, I < 1µA, 3mm × 3mm
36V with Transient Protection to 60V, 2A (I ), 2.4MHz,
OUT
IN
OUT
Q
SD
High Efficiency Step-Down DC/DC Converter
DFN-10, MSOP-10E Package
3509fd
LT 0116 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
LINEAR TECHNOLOGY CORPORATION 2007
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT3509
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