LT3513IUHF-PBF [Linear]
2MHz High Current 5-Output Regulator for TFT-LCD Panels; 2MHz，高电流5路输出稳压器，用于TFT -LCD面板
| 型号： | LT3513IUHF-PBF |
| 厂家： | 
Linear |
| 描述： | 2MHz High Current 5-Output Regulator for TFT-LCD Panels |
| 文件： | 总20页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3513
2MHz High Current
5-Output Regulator
for TFT-LCD Panels
FEATURES
DESCRIPTION
The LT®3513 5-output adjustable switching regulator
provides power for large TFT-LCD panels. The 38-pin
5mm × 7mm QFN device can generate a 3.3V or 5V logic
supply along with the triple output supply required for the
TFT-LCD panel. A lower voltage secondary logic supply
may also be generated with the addition of an external
NPN driven by the internal linear regulator. A step-down
n
4.5V to 30V Input Voltage Range
Four Integrated Switches: 2.2A Buck, 1.5A Boost,
n
0.25A Boost, 0.25A Inverter (Guaranteed Minimum
Current Limit)
n
External NPN LDO Driver
n
Fixed Frequency, Low Noise Outputs
n
Inductor Current Sense for Buck
n
Soft-Start for All Outputs
regulator provides a low voltage output, V
, with up
LOGIC
n
Externally Programmable V Delay
to 1.2A of current while capable of operating from a wide
input range of 4.5V to 30V. A high power step-up con-
verter, a lower power step-up converter and an inverting
converter provide the three independent output voltages:
ON
n
n
n
n
Three Integrated Schottky Diodes
PGOOD Pin for AV Output Disconnect
DD
PanelProtectTM Circuitry Disables V Upon Fault
ON
Thermally Enhanced 38-Lead 5mm × 7mm QFN
Package
AV , V andV requiredbytheLCDpanel. Ahigh-side
DD ON OFF
PNP provides delayed turn-on of the V signal and can
ON
handle up to 30mA. Protection circuitry ensures that V
ON
is disabled if any of the four outputs are more than 10%
APPLICATIONS
below the programmed voltage.
n
Automotive TFT-LCD Displays
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
PanelProtect is a trademark of Linear Technology Corporation.
n
Large TFT-LCD Desktop Monitors
All other trademarks are the property of their respective owners.
n
Flat Panel Televisions
TYPICAL APPLICATION
10μH
V
V
IN
LOGIC
5V
8V TO 16V
10μF
178k
53.6k
10k
100k
10μF
0.47μF
V
OFF
–10V
60.4k
20mA
UVLO LDOPWR
SW4
V
SW2
FB2
IN
AV
DD
2.2μF
10μH
8V
Start-Up Waveforms
80mA
69.8k
10k
D4
PGOOD
NFB4
BIAS
RUN-SS1
RUN-SS2
RUN/SS 2V/DIV
BOOST
RUN-SS3/4
V
5V/DIV
LOGIC
AV 10V/DIV
0.22μF
4.7μH
C
T
DD
OFF
V
47nF
15nF
15nF
15nF
SW1
LOGIC
5V
0.5A
V
10V/DIV
LT3513
+
SENSE
SENSE
FB1
–
30.1k
V
V
ON_CLK
ON_CLK
V
ON
V
ON
22V
22μF
10k
232k
20mA
V
ONSINK
E3
V
20V/DIV
E3
V
20V/DIV
1A/DIV
ON
6.8μH
165k
10k
V
I
LOGIC
IN(AVG)
BD
FB5
SW3
FB3
5V
V
3.3V
0.5A
LDO
0.47μF
3513 TA01b
5ms/DIV
V
V
GND
V
V
C4
C1
C2
C3
42.2k
10k
2.2μF
10μF
7.5k
2.7nF
4.7k
30k
13k
2.2nF
4.7nF 1.5nF
3513fa
1
LT3513
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , LDOPWR Voltage...............................................32V
IN
UVLO Voltage............................................................32V
SW2, SW3, SW4 Voltage ..........................................40V
E3 Pin Voltage...........................................................40V
38 37 36 35 34 33 32
+
–
FB5
1
2
31 SENSE
30 SENSE
V
C1
V , V
Voltage ................................................40V
ON ONSINK
RUN-SS3/4
FB3
BIAS
3
29
28
PGOOD Voltage.........................................................40V
D4 Voltage ........................................................1V, –40V
BOOST Voltage .........................................................37V
BOOST Over SW1 .......................................................8V
BOOST
4
RUN-SS2
SW3
5
27 LDOPWR
BD
26
6
39
E3
7
25 SW4
24 D4
+
–
SENSE , SENSE Voltage..........................................10V
Voltage........................................................10V
V
ON
8
V
9
23 NFB4
22 RUN-SS1
V
ONSINK
ON_CLK
ON_CLK
V
10
BIAS, BD Voltage ......................................................10V
T
PGOOD 11
12
21
20
V
V
C4
C2
C Pin Voltage.............................................................5V
V
C3
RUN-SS1, RUN-SS2, RUN-SS3/4 Voltage ..................5V
FB1, FB2, FB3, FB5 Voltage.........................................5V
NFB4 Voltage ...................................................... 5V, –5V
13 14 15 16 17 18 19
UHF PACKAGE
V , V , V , V Voltage ..........................................5V
38-LEAD (5mm s 7mm) PLASTIC QFN
= 125°C, θ = 34°C/W, θ = 1°C/W
C1 C2 C3 C4
T
JMAX
JA
JC
Junction Temperature ........................................... 125°C
Operating Temperature Range (Note 2)..–40°C to 125°C
Storage Temperature Range...................–65°C to 125°C
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3513EUHF#PBF
LT3513IUHF#PBF
TAPE AND REEL
PART MARKING*
3513
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3513EUHF#TRPBF
LT3513IUHF#TRPBF
–40°C to 125°C
–40°C to 125°C
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
3513
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BIAS = 3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
Minimum Input Voltage
Quiescent Current
4.5
V
Not Switching
RUNSS1
7.5
30
12
65
mA
μA
V
= 0V
RUN-SS1, RUN-SS2, RUN-SS3/4 Pin Current
RUN-SS1= RUN-SS2 = RUN-SS3
= RUN-SS4 = 0.4V
2
μA
RUN-SS1, RUN-SS2, RUN-SS3/4 Threshold
BIAS Pin Voltage to Begin RUN-SS2, RUN-SS3/4
BIAS Pin Current
0.8
V
V
l
2.25
16.5
2.7
20
BIAS = 3.1V, All Switches Off
mA
3513fa
2
LT3513
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BIAS = 3V, unless otherwise noted.
PARAMETER
FB Threshold Offset to Begin C Charge
CONDITIONS
(Note 3)
MIN
90
16
1
TYP
125
20
MAX
160
25
UNITS
mV
μA
V
T
C Pin Current Source
T
All FB Pins = 1.5V
All FB Pins = 1.5V
C Threshold to Power V
1.1
200
50
1.2
T
ON
V
Switch Drop
V
V
Current = 30mA
= 30V
400
mV
mA
V
ON
ON
E3
l
Maximum V Current
30
ON
V
V
V
Input Voltage High
Input Voltage Low
Voltage On
1.5
ON_CLK
ON_CLK
ONSINK
0.3
1.2
V
●
●
V
Current = 1μA
V
ONSINK
Master Oscillator Frequency
1.90
1.80
2
2.12
2.22
MHz
MHz
Foldback Switching Frequency
UVLO Pin Threshold
UVLO Pin Hysteresis Current
PGOOD Threshold Offset
PGOOD Sink Current
PGOOD Pin Leakage
All FB = 0V
200
1.25
3.9
kHz
V
UVLO Pin Voltage Rising
V
UVLO
= 1V
3.4
90
4
4.4
μA
mV
mA
μA
125
160
PGOOD Connected to 40V Through 100k
= 40V
V
1
PGOOD
Switch 1 (2.2A Buck)
FB1 Voltage
1.215
1.205
1.235
1.255
1.265
V
V
●
●
FB1 Voltage Line Regulation
FB1 Pin Bias Current
4.5V < V < 32V
0.01
30
0.03
200
%/V
nA
IN
(Note 4)
Error Amplifier 1 Voltage Gain
Error Amplifier 1 Transconductance
Maximum Duty Cycle
250
220
85
V/V
μmhos
%
ΔI = 10μA
●
75
Switch 1 Current Limit
Duty Cycle = 35% (Note 5)
2.2
3
3.5
A
Switch 1 V
I
= 1.5A
SW
430
0.1
1.8
30
mV
μA
CESAT
Switch 1 Leakage Current
Minimum BOOST Voltage Above SW1 Pin
BOOST Pin Current
FB1 = 1.5V
10
2.5
50
I
I
= 1.5A (Note 6)
= 1.5A
V
SW
SW
mA
mV
BOOST Schottky Diode Drop
Switch 2 (1.5A BOOST)
FB2 Voltage
I = 170mA
700
1.20
1.19
1.22
1.24
1.25
V
V
●
●
FB2 Voltage Line Regulation
FB2 Pin Bias Current
4.5V < V < 32V
0.01
30
0.03
200
%/V
nA
IN
(Note 4)
Error Amplifier 2 Voltage Gain
Error Amplifier 2 Transconductance
Switch 2 Current Limit
250
220
1.85
360
0.1
45
V/V
μmhos
A
ΔI = 10μA
1.5
75
2.3
1
Switch 2 V
I
= 1.2A
SW2
mV
μA
CESAT
Switch 2 Leakage Current
BIAS Pin Current Due to SW2
Maximum Duty Cycle (SW2)
FB2 = 1.5V
= 1.2A
I
mA
%
SW2
●
90
3513fa
3
LT3513
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BIAS = 3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switch 3 (250mA BOOST)
FB3 Voltage
1.20
1.19
1.22
1.24
1.25
V
V
●
●
FB3 Voltage Line Regulation
FB3 Pin Bias Current
4.5V < V < 32V
0.01
30
0.03
200
%/V
nA
IN
(Note 4)
Error Amplifier 3 Voltage Gain
Error Amplifier 3 Transconductance
Switch 3 Current Limit
250
220
0.3
200
0.1
18
V/V
μmhos
A
ΔI = 10μA
0.25
84
0.38
1
Switch 3 V
I
= 0.2A
SW3
mV
μA
CESAT
Switch 3 Leakage Current
BIAS Pin Current Due to SW3
Maximum Duty Cycle (SW3)
Schottky Diode Drop
FB3 = 1.5V
= 0.2A
I
mA
%
SW3
●
88
I = 170mA
900
mV
Switch 4 (250mA Inverter)
NFB4 Voltage
–1.205
–1.215
–1.180
–1.155
–1.145
V
V
●
●
NFB4 Voltage Line Regulation
NFB4 Pin Bias Current
4.5V < V < 32V
0.01
5
0.03
16
%/V
μA
IN
(Note 4)
Error Amplifier 4 Voltage Gain
Error Amplifier 4 Transconductance
Switch 4 Current Limit
200
220
0.3
200
0.1
18
V/V
μmhos
A
ΔI = 10μA
0.28
84
0.40
1
Switch 4 V
I
= 0.2A
SW4
mV
μA
CESAT
Switch 4 Leakage Current
BIAS Pin Current Due to SW4
Maximum Duty Cycle (SW4)
Schottky Diode Drop (D4)
NPN LDO
NFB4 = –1.5V
= 0.2A
I
mA
%
SW4
88
I = 170mA
700
mV
FB5 Voltage
0.61
0.6
0.625
8
0.63
0.65
V
V
●
Base Drive Current
FB5 = 0.5V
BD = 3.5V
6
10
mA
V
LDOPWR Minimum Voltage
4.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Current flows out of FB1, FB2, FB3 and NFB4.
Note 5: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 6: This is the minimum voltage across the boost capacitor needed to
Note 2: The LT3513E is guaranteed to meet specified performance from
0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3513I is guarenteed over the full –40°C to 125°C operating junction
temperature range.
guarantee full saturation of the internal power switch.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
range when overtemperature protection is active. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 3: The C pin is held low until FB1, FB2, FB3 and NFB4 all ramp
T
above the FB threshold offset.
3513fa
4
LT3513
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Output Current for
V
LOGIC = 3.3V
SW1 Current Limit vs Duty Cycle
Start and Run VLOGIC = 3.3V
3.0
2.5
2.6
2.4
2.2
8
7
6
5
4
3
2
1
SW1 CURRENT LIMIT
vs DUTY CYCLE
L = 4.3μH
V
V
START
RUN
IN(MIN)
2.0
1.5
MINIMUM
L = 2.4μH
IN(MIN)
2.0
1.8
1.6
1.4
1.2
1.0
0.5
0
0
5
10
(V)
20
25
35
45
55
65
75
0
15
0.001
0.01
0.1
1
DUTY CYCLE (%)
V
LOAD CURRENT (A)
IN
3513 G03
3513 G02
3513 G01
BOOST Pin Current
SW3 Current Limit
SW2 Current Limit
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
70
60
50
40
30
20
10
0
500
450
400
350
300
250
200
150
100
–40
10
35
60
85
110
–50 –30
30 50
AMBIENT TEMPERATURE (°C)
–15
–10 10
70 90
110
2000
SWITCH CURRENT (mA)
3000
0
500
1000 1500
2500
AMBIENT TEMPERATURE (°C)
3513 G05
3513 G06
3513 G04
SW4 Current Limit
SW1 VCESAT
SW2 VCESAT
600
500
500
450
400
350
300
250
200
150
100
1000
900
800
700
600
500
400
300
200
100
0
400
300
200
100
0
30 50
–50 –30 –10 10
AMBIENT TEMPERATURE (°C)
70 90 110
0
500
1500 2000 2500 3000
1000
SW1 CURRENT (mA)
0
400
800
I
1200
(mA)
1600
2000
SW2
3513 G07
3513 G08
3513 G09
3513fa
5
LT3513
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
SW3 VCESAT
SW4 VCESAT
VON Current Limit
300
250
200
150
350
300
45
40
35
30
25
20
15
10
5
250
200
150
100
50
100
50
0
0
0
200
300 350
0
50
100 150
250
200
300 350
0
50
100 150
250
0
5
10
15
V
35
20
(V)
25
30
I
(mA)
I
(mA)
SW3
SW
E3
3513 G10
3513 G11
3513 G12
Oscillator Frequency
Frequency Foldback
Reference Voltage
1.25
1.24
1.23
1.22
1.21
1.20
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
2500
2000
1500
1000
500
0
50
–50
0
100
–40 –15
10
35
60
85
600
110
0
150 300 450
750 900 1050 1200
TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
V
FB
(mV)
3513 G13
3513 G15
3513 G14
BIAS Pin Current
Efficiency, AVDD = 13V
Efficiency, VLOGIC = 5V
100
90
80
70
60
50
40
60
50
100
90
L2 = 10μH
L3 = 10μH
L4 = 10μH
40
30
80
70
I
I
I
= 0A
= 0A
= 0A
SW2
SW3
SW4
20
10
0
60
50
40
900 1300 1500
1100
–50
0
50
TEMPERATURE (°C)
100
150
100 300 500 700
1
100
200
300
400
500
LOAD CURRENT (mA)
I
(mA)
OUT
3513 G16
3513 G18
3513 G17
3513fa
6
LT3513
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
LDO Current Limit vs Temperature
VUVLO vs Temperature
Reference Voltage for FB5, LDO
670
660
1.33
1.32
1.31
9
8
7
6
5
4
3
2
1
UVLO FOR
START
650
640
630
620
610
1.30
1.29
1.28
1.27
1.26
UVLO MINIMUM
FOR RUN
600
0
60
TEMPERATURE (°C)
110
–40 –15
10
35
85
0
50
–50
100
–50 –25
0
25
125
50
75 100
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (°C)
3513 G21
3513 G20
3513 G19
PIN FUNCTIONS
FB5 (Pin 1): Feedback Pin. Tie the resistor tap to this pin
For slower start-up use a larger capacitor. For complete
shutdown tie RUN-SS2 to ground.
and set the output of the LDO according to V = 0.625 •
LDO
(1 + R14/R15). Reference designators refer to Figure 1.
SW3 (Pin 6): Switch Node. The SW3 pin is the collector of
the internal NPN bipolar transistor for switching regulator
3. Minimize trace area at this pin to keep EMI down.
V
(Pin 2): Control Voltage and Compensation Pin for
C1
Internal Error Amplifier. Connect a series RC from this pin
to ground to compensate switching regulator 1.
E3 (Pin 7): This is switching regulator 3’s output and
the emitter of the output disconnect PNP. Tie the output
capacitor and resistor divider here.
RUN-SS3/4 (Pin 3): Run/Soft-Start Pin. This is the soft-
startpinforswitchingregulators3and4.Placeasoft-start
capacitor here to limit start-up inrush current and output
voltage ramp rate. When the BIAS pin reaches 2.8V, a 2μA
current source charges the capacitor. When the voltage at
this pin reaches 0.8V, switches 3 and 4 turn on and begin
switching. For slower start-up use a larger capacitor. For
complete shutdown tie RUN-SS3/4 to ground.
V
(Pin 8): This is the delayed output for switching
ON
regulator 3. V reaches its programmed voltage after the
ON
internal C timer times out. Protection circuitry ensures
T
V
ON
is disabled if any of the four outputs are more than
10% below normal voltage. This output is also disabled
when V is high.
ON_CLK
FB3 (Pin 4): Feedback Pin. Tie the resistor tap to this
V
(Pin 9): This is an open-collector output con-
ONSINK
trolled by the V
pin and set V according to V = 1.23V • (1 + R8/R9)
ON
ON
pin. When V
is low, this
ON_CLK
ON_CLK
– 150mV. Reference designators refer to Figure 1.
pin draws no current and when V
draws current.
is high, this pin
ON_CLK
RUN-SS2(Pin5):Run/Soft-StartPin. Thisisthesoft-start
pin for switching regulator 2. Place a soft-start capacitor
here to limit start-up inrush current and output voltage
ramp rate. When the BIAS pin reaches 2.25V, a 2μA cur-
rent source charges the capacitor. When the voltage at this
pin reaches 0.8V, switch 2 turns on and begins switching.
V
(Pin 10): This pin controls the output disconnect
ON_CLK
device and the open collector of V
. When this pin is
ONSINK
low, the V pin is enabled and the V
pin is a high
ON
ONSINK
impedance. When this pin is high, the V pin is disabled
ON
and the V
pin sinks current to ground.
ONSINK
3513fa
7
LT3513
PIN FUNCTIONS
PGOOD (Pin 11): Power Good Comparator Output. This is
the open collector output of the power good comparator
and can be used in conjunction with an external P-chan-
V
(Pin 21): Control Voltage and Compensation Pin for
C4
Internal Error Amplifier. Connect a series RC from this pin
to ground to compensate switching regulator 4.
nel MOSFET to provide output disconnect for AV as
DD
RUN-SS1(Pin22):Run/Soft-StartPin.Thisisthesoft-start
pin for switching regulator 1. Place a soft-start capacitor
here to limit start-up inrush current and output voltage
shown in Figure 2. When switcher 2’s output reaches
approximately 90% of its programmed voltage, PGOOD
will be pulled to ground. This will pull down on the gate
ramp rate. When power is applied to the V pin, a 2μA
IN
of the MOSFET, connecting AV . A 100k pull-up resistor
DD
current source charges the capacitor. When the voltage
at this pin reaches 0.8V, switch 1 turns on and begins
switching. For slower start-up use a larger capacitor. For
complete shutdown tie RUN-SS1 to ground.
betweenthesourceandthegateoftheP-channelMOSFET
keeps it off when switcher 2’s output is low.
V
(Pin 12): Control Voltage and Compensation Pin for
C3
Internal Error Amplifier. Connect a series RC from this pin
NFB4 (Pin 23): Negative Feedback Pin. Tie the resistor di-
to ground to compensate switching regulator 3.
vidertaptothispinandsetV accordingtoV =–1.18•
OFF
OFF
C (Pin 13): Timing Capacitor Pin. This is the input to
(1 + R3/R4). Reference designators refer to Figure 2.
T
the V timer and programs the time delay from all four
ON
D4 (Pin 24): Internal Schottky Diode Pin. This pin is the
anode of an internal Schottky diode with the other end
connected to ground. This Schottky diode is used in
feedback pins reaching 1.125V to V turning on. The C
ON
T
capacitor value can be set using the equation C = (20μA
• t )/1.1V.
DELAY
generating the V output.
OFF
GND (Pins 14, 17, 33): Ground.
SW4(Pin25):SwitchNode.TheSW4pinisthecollectorof
the internal NPN bipolar transistor for switching regulator
4. Minimize trace area at this pin to keep EMI down.
SW2 (Pins 15, 16): Switch Node. The SW2 pin is the col-
lector of the internal NPN bipolar transistor for switching
regulator 2. Minimize trace area at this pin to keep EMI
down.
BD (Note 26): NPN LDO Base Drive. This pin controls the
base of the external NPN LDO transistor.
BIAS (Pins 18, 29): The BIAS pin is used to improve ef-
ficiencywhenoperatingathigherinputvoltages. Connect-
ing this pin to the output of switching regulator 1 forces
most of the internal circuitry to draw its operating current
LDOPWR (Pin 27): Input Voltage for LDO Driver. This pin
suppliesthecurrentfortheNPNLDObase. Thispincanbe
connected to V . To save power at high V voltages, the
IN
IN
pin can alternatively be connected to the AV supply.
DD
from V
rather than V . The drivers of switches 2, 3,
LOGIC
IN
BOOST (Pin 28): The BOOST pin is used to provide a
4 and 5 are supplied by BIAS. Switches 2, 3, 4 and 5 will
drive voltage higher than V to the switch 1 drive circuit.
not switch until the BIAS pin reaches approximately 2.7V.
IN
An internal Schottky diode is connected between BIAS
and BOOST. A capacitor needs to be connected between
BOOST and SW1.
Both BIAS pins must be tied to V
.
LOGIC
FB2 (Pin 19): Feedback Pin. Tie the resistor divider tap
to this pin and set AV according to AV = 1.23V •
DD
DD
–
SENSE (Pin 30) Negative Current Sense Input. This pin
(1 + R5/R6). Reference designators refer to Figure 2.
+
(along with the SENSE pin) is used to sense the inductor
V
(Pin 20): Control Voltage and Compensation Pin for
C2
current for the buck switching regulator.
Internal Error Amplifier. Connect a series RC from this pin
to ground to compensate switching regulator 2.
3513fa
8
LT3513
PIN FUNCTIONS
+
SENSE (Pin 31) Positive Current Sense Input. This pin
UVLO (Pin 38): Undervoltage Lockout. A resistor divider
–
(along with the SENSE pin) is used to sense the inductor
connectedtoV istiedtothispintoprogramtheminimum
IN
current for the buck switching regulator.
input voltage at which the LT3513 will operate. This pin is
compared to the internal 1.25V reference. When UVLO is
less than 1.25V, the switching regulators are not allowed
to operate (the RUN/SS pins are still used to turn on each
switching regulator). When this pin falls below 1.25V,
3.9μAwillbepulledfromthepintoprovideprogrammable
hysteresis for UVLO.
FB1 (Pin 32): Feedback Pin. Tie the resistor divider tap
to this pin and set V
according to V
= 1.23V •
LOGIC
LOGIC
(1 + R1/R2). Reference designators refer to Figure 2.
SW1 (Pins 34, 35): Switch Node. The SW1 pins are the
emitter of the internal NPN bipolar power transistor for
switching regulator 1. These points must be tied together
for proper operation. Connect these pins to the inductor,
catch diode and boost capacitor.
Exposed Pad (Pin 39): Ground. The Exposed Pad of the
package provides both electrical contact to ground and
good thermal contact to the printed circuit board. The
Exposed Pad must be soldered to the circuit board for
proper operation.
V (Pins 36, 37): Input Voltage. This pin supplies current
IN
to the internal circuitry of the LT3513. This pin must be
locally bypassed with a capacitor.
3513fa
9
LT3513
BLOCK DIAGRAM
LDOPWR
27
–
+
V
ON_CLK
g
m
+
10
9
0.625V
BD
26
V
ONSINK
MASTER
OSCILLATOR
2MHz
V
FB5
1
ON_CLK
V
IN
36,37
V
C1
2
–
+
–
+
INTERNAL
REGULATOR
AND REFERENCE
RUN-SS1
BIAS
g
m
22
32
11
+
1.234V
FB1
BOOST
IN
28
R
V
PGOOD
SLOPE COMP/
ONE-SHOT
S
Q
–
+
FB2
DRIVER
SW1
34, 35
+
+
1.1V
SENSE
31
FB2
19
13
–
SENSE
30
20
CURRENT
SENSE AMP
–
V
C2
C
T
–
+
–
–
–
+
–
+
BIAS
g
m
+
18, 29
SW2
1.234V
+
15, 16
R
1.1V
FOLDBACK
OSCILLATOR
S
Q
DRIVER
+
–
1.25V
UVLO
UVLO
38
3μA
V
C4
21
23
–
+
100k
100k
–
+
NFB4
SW4
–
+
g
m
+
1.18V
RUN-SS3/4
SW3
LOCKOUT
BIAS
3
5
25
24
–
+
R
BIAS
FOLDBACK
OSCILLATOR
S
Q
2.7V
DRIVER
D4
RUN-SS2
FB3
SW2
LOCKOUT
V
C3
12
6
–
+
–
+
g
m
+
4
8
1.23V
SW3
E3
BIAS
V
ON
R
–
+
FOLDBACK
OSCILLATOR
S
Q
DRIVER
GND
1.1V
14,17,33
V
ON_CLK
7
3513 F01
Figure 1
3513fa
10
LT3513
OPERATION
TheLT3513isahighlyintegratedpowersupplyICcontain-
ing four separate switching regulators and a low dropout
linear regulator (LDO). Switching regulator 1 is a step-
down 2.5A regulator with inductor current sense and an
integratedboostSchottkydiode.Switchingregulator 2can
be configured as a step-up or SEPIC converter and has a
1.2A switch. Switching regulator 3 consists of a step-up
regulator with a 0.25A switch as well as an integrated
Schottkydiode. Switchingregulator4isanegativeregula-
tor with a switch current limit of 0.25A and an integrated
Schottky diode. Linear regulator 5 is capable of providing
8mA of current to the base of an external NPN transistor.
The regulators share common circuitry including input
source, voltage reference and master oscillator. Operation
can be best understood by referring to the Block Diagram
as shown in Figure 1.
A power good comparator monitors AV and turns on
DD
when FB2 is at or above 90% of its regulated value. The
output is an open-collector transistor that is off when the
output is out of regulation, allowing an external resistor
to pull the pin high. This pin can be used with a P-chan-
nel MOSFET that functions as an output disconnect for
AV .
DD
The four switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
duringeachcycle.Comparedtovoltagemodecontrol,cur-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
RUN-SS 2V/DIV
If the RUN-SS1 pin is pulled to ground, the LT3513 is shut
down and draws 30μA from the input source tied to V .
V
5V/DIV
1A/DIV
LOGIC
I
L1
IN
An internal 2μA current source charges the external soft-
start capacitor, generating a voltage ramp at this pin. If the
RUN-SS1 pin exceeds 0.6V, the internal bias circuits turn
on, including the internal regulator, reference and 2MHz
master oscillator. The master oscillator generates four
clock signals, one for each of the switching regulators.
Switching regulator 1 will only begin to operate when the
SS-234 2V/DIV
AV 10V/DIV
DD
I
L2
500μA/DIV
PGOOD 20V/DIV
3513 F02a
5ms/DIV
RUN-SS1 pin reaches 0.8V. Switcher 1 generates V
,
LOGIC
(2a)
whichmustbetiedtotheBIASpin.WhenBIASreaches2.8V,
the NPNs pulling down on the RUN-SS2 and RUN-SS3/4
pins turns off, allowing an internal 2μA current source
to charge the external capacitors tied to RUN-SS2 and
RUN-SS3/4 pins. When the voltage on RUN-SS2 reaches
0.8V, switcher 2 is enabled. Correspondingly, when the
voltage on RUN-SS3/4 reaches 0.8V, switchers 3 and 4
are enabled. AV , E3 and V will then begin rising at a
V
2V/DIV
SS3/4
V
OFF
10V/DIV
I
I
500mA/DIV
L4
V
E3
20V/DIV
DD
OFF
500mA/DIV
L3
ratedeterminedbythecapacitorstiedtotheRUN-SS2and
RUN-SS3/4 pins. When all four switching outputs reach
90% of their programmed voltages, the NPN pulling down
V
CT
2V/DIV
V
ON
20V/DIV
on the C pin will turn off, and an internal 20μA current
T
3513 F02b
source will charge the external capacitor tied to the C pin.
5ms/DIV
T
When the C pin reaches 1.1V, the output disconnect PNP
T
(2b)
turns on, connecting V to E3. In the event of any of the
ON
four outputs dropping below 10% of their programmed
Figure 2. LT3513 Power-Up Sequence. (Traces from Both Photos
are Synchnonized to the Same Trigger)
voltage, PanelProtect circuitry pulls the C pin to GND,
T
disabling V .
ON
3513fa
11
LT3513
OPERATION
All four switchers employ a constant-frequency current
mode control scheme. Switcher 1, the step-down regula-
tor, differs slightly from the others with inductor current
sense. Instead of monitoring the current at the switch,
current nodes are used to measure the current through
the inductor. Inductor current sense does not suffer from
minimum on-time problems, therefore always keep-
ing the switch current limited with any input-to-output
voltage ratio. Switcher 1 is always synchronized to the
master oscillator. The other three switchers each have
their own slave oscillator. The slave oscillator reduces the
frequency when the feedback voltage dips below 0.75V
and decreases linearly below the threshold as shown in
thePerformanceCharacteristics’FrequencyFoldbackplot.
Otherthanthesetwodifferences,thecontrolloopissimilar
in all four switchers. A pulse from the master oscillator
for switcher 1 or a pulse from the slave oscillator for the
other three switchers sets the RS latch and turns on the
internal NPN bipolar power switch. Current in the switch
and the external inductor begins to increase. When this
INPUT VOLTAGE RANGE STEP-DOWN CONSIDERATION
Theminimumoperatingvoltageofswitcher1isdetermined
either by the LT3513’s undervoltage lockout of ~4V or by
its maximum duty cycle. A user defined undervoltage
lockout may be set with the UVLO pin at a voltage higher
than the internal undervoltage lockout. The duty cycle is
the fraction of time that the internal switch is on and is
determined by the input and output voltages:
VOUT + VF
DC =
V – VSW + VF
IN
where V is the forward voltage drop of the catch diode
F
(~0.4V) and V is the voltage drop of the internal switch
SW
(~0.3V at maximum load). This leads to a minimum input
voltage of:
VOUT + VF
DCMAX – VF + VSW
V
=
IN(MIN)
with DC
= 0.75.
MAX
currentexceedsaleveldeterminedbythevoltageatV ,the
C
The user defined undervoltage is set by a resistor divider
connected to the UVLO pin. The comparator pulls 3μA
from the pin when the UVLO pin is higher than 1.25V.
The hysteresis and minimum input voltage equations are
as follows:
currentcomparatorresetsthelatch,turningofftheswitch.
The current in the inductor flows through the Schottky
diode and begins to decrease. The cycle begins again at
the next pulse from the oscillator. In this way, the voltage
on the V pin controls the current through the inductor to
C
theoutput.Theinternalerroramplifierregulatestheoutput
VHYS = R2+2k •3.9µA
(
)
by continually adjusting the V pin voltage. The threshold
C
for switching on the V pin is 0.8V, and an active clamp
C
R1+R2
VIN(MIN) =1.25V
of 1.8V limits the V voltage. Switchers 2, 3 and 4 also
C
R1
contain an independent current limit not dependent on V
C
or duty cycle. Switcher 1’s current limit is controlled by
V
IN
the V voltage and varies with duty cycle. All four switch-
C
ers also use slope compensation to ensure stability with
the current mode scheme at duty cycles above 50%. The
RUN-SS1, RUN-SS2 and RUN-SS3/4 pins control the rate
of rise of the feedback pins.
R2
UVLO
38
R1
TheswitchdriverforSW1operateseitherfromV orfrom
IN
3513 A1
the BOOST pin. An external capacitor and an integrated
SchottkydiodeareusedtogenerateavoltageattheBOOST
pin that is higher than the input supply. This allows the
driver to saturate the internal bipolar NPN power switch
for efficient operation.
3513fa
12
LT3513
OPERATION
INDUCTOR SELECTION AND MAXIMUM OUTPUT
CURRENT
inductance is required to avoid subharmonic oscillations,
see Application Note 19.
A good first choice for the inductor value is:
Thecurrentintheinductorisatrianglewavewithanaverage
value equal to the load current. The peak switch current
is equal to the output current plus half the peak-to-peak
inductor ripple current. The LT3513 limits its switch cur-
rent in order to protect itself and the system from overload
faults. Therefore, the maximum output current that the
LT3513willdeliverdependsontheswitchcurrentlimit,the
inductor value, and the input and output voltages. When
the switch is off, the potential across the inductor is the
output voltage plus the catch diode drop. This gives the
peak-to-peak ripple current in the inductor:
VOUT + VF
L =
1.8
whereV isthevoltagedropofthecatchdiode(~0.4V)andL
F
isinμH.Theinductor’sRMScurrentratingmustbegreater
than the maximum load current and its saturation current
should be at least 30% higher. For highest efficiency, the
series resistance (DCR) should be less than 0.1Ω. Table 1
lists several vendors and types that are suitable.
Table 1. Inductor Vendors
1–DC VOUT + VF
VENDOR
Coilcraft
Murata
TDK
URL
PART SERIES
MSS7341
LQH55D
SLF7045
SLF10145
TYPE
Shielded
Open
Shielded
Shielded
Shielded
Shielded
Shielded
Open
Open
Shielded
Shielded
Open
(
)
(
)
ΔIL =
www.coilcraft.com
www.murata.com
www.component.tdk.com
L • f
where f is the switching frequency of the LT3513 and L
is the value of the inductor. The peak inductor and switch
current is:
Toko
www.toko.com
DC62CB
D63CB
D75C
ΔIL
2
D75F
ISW(PK) =ILPK =IOUT
+
Sumida
www.sumida.com
CR54
CDRH74
CDRH6D38
CR75
To maintain output regulation, this peak current must be
lessthantheLT3513’sswitchcurrentlimitofI .ForSW1,
LIM
I
is at least 2A at DC = 0.35, and decreases linearly to
LIM
The optimum inductor for a given application may differ
fromtheoneindicatedbythissimpledesignguide.Alarger
value inductor provides a higher maximum load current,
andreducestheoutputvoltageripple. Ifyourloadislower
than the maximum load current, then you can relax the
value of the inductor and operate with higher ripple cur-
rent. This allows you to use a physically smaller inductor
or one with a lower DCR resulting in higher efficiency. Be
aware that the maximum load current depends on input
voltage. A graph in the Typical Performance Character-
istics section of this data sheet shows the maximum
load current as a function of input voltage and inductor
value for VOUT = 3.3V. In addition, low inductance may
result in discontinuous mode operation, which further
reduces maximum load current. For details of maximum
output current and discontinuous mode operation, see
Linear Technology’s Application Note 44. Finally, for duty
cycles greater than 50% (VOUT/VIN > 0.5), a minimum
1.5A at DC = 0.75 as shown in the Typical Performance
Characteristics section. The maximum output current is
a function of the chosen inductor value:
ΔIL
2
ΔIL
2
IOUT(MAX) =ILIM
–
= 2.5A • 1–0.57•DC –
(
)
Choosing an inductor value so that the ripple current is
smallwillallowamaximumoutputcurrentneartheswitch
current limit. One approach to choosing the inductor is to
start with the simple rule given above, look at the available
inductors and choose one to meet cost or space goals.
Then use these equations to check that the LT3513 will
be able to deliver the required output current. Note again
that these equations assume that the inductor current is
continuous. Discontinuous operation occurs when I
OUT
is less than ΔI /2.
L
3513fa
13
LT3513
OPERATION
OUTPUT CAPACITOR SELECTION
valuecapacitorsusepoordielectricswithhightemperature
and voltage coefficients. In particular, Y5V and Z5U types
lose a large fraction of their capacitance with applied volt-
age and at temperature extremes.
For 5V and 3.3V outputs, a 10μF 6.3V ceramic capacitor
(X5R or X7R) at the output results in very low output volt-
age ripple and good transient response. Other types and
values will also work; the following discussion explores
tradeoffs in output ripple and transient performance.
Because loop stability and transient response depend on
the value of C , this loss may be unacceptable. Use X7R
OUT
and X5R types. Electrolytic capacitors are also an option.
The ESRs of most aluminum electrolytic capacitors are
too large to deliver low output ripple. Tantalum and newer,
lower ESR organic electrolytic capacitors intended for
power supply use are suitable, and the manufacturers will
specify the ESR. Chose a capacitor with a low enough ESR
for the required output ripple. Because the volume of the
capacitor determines its ESR, both the size and the value
will be larger than a ceramic capacitor that would give
similar ripple performance. One benefit is that the larger
capacitance may give better transient response for large
changes in load current. Table 2 lists several capacitor
vendors.
Theoutputcapacitorfilterstheinductorcurrenttogenerate
an output with low voltage ripple. It also stores energy in
order satisfy transient loads and stabilizes the LT3513’s
control loop. Because the LT3513 operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
You can estimate output ripple with the following
equations:
ΔIL
8• f •COUT
VRIPPLE
=
for ceramic capacitors, and
Table 2. Low ESR Surface Mount Capacitors
VENDOR
Taiyo Yuden
AVX
TYPE
SERIES
V
=ΔI •ESRforelectrolyticcapacitors(tantalum
RIPPLE
and aluminum)
L
Ceramic
X5R, X7R
Ceramic
Tantalum
X5R, X7R
TPS
whereΔI isthepeak-to-peakripplecurrentintheinductor.
L
Kemet
Tantalum
Ta Organic
Al Organic
T491, T494, T495
T520
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
A700
Sanyo
Panasonic
TDK
Ta or Al Organic
Al Organic
POSCAP
SP CAP
ΔIL
12
IC(RMS)
=
Ceramic
X5R, X7R
DIODE SELECTION
Another constraint on the output capacitor is that it must
havegreaterenergystoragethantheinductor;ifthestored
energyintheinductortransferstotheoutput, theresulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
The catch diode (D1 from Figure 1) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
V – VOUT
IN
2
ID(AVG) =IOUT
⎛
⎞
ILIM
V
IN
COUT >10•L •
⎜
⎟
V
⎝
⎠
OUT
The only reason to consider a diode with a larger current
rating than necessary for nominal operation is for the
worst-case condition of shorted output. The diode current
will then increase to the typical peak switch current. Peak
reverse voltage is equal to the regulator input voltage.
3513fa
The low ESR and small size of ceramic capacitors make
them the preferred type for LT3513 applications. However,
notallceramiccapacitorsarethesame.Manyofthehigher
14
LT3513
OPERATION
Use a diode with a reverse voltage rating greater than the
input voltage. Table 3 lists several Schottky diodes and
their manufacturers.
V
1.25
⎛
⎞
⎠
OUT
R3=R4
–1
⎜
⎝
⎟
R4 should be 10k or less to avoid bias current errors.
Table 3. Schottky Diodes
PART NUMBER
On Semiconductor
MBRM120E
MBRM140
MBRS240
MBRA340
Diodes Inc.
B120
V (V)
I
(A)
V
FAT
1A (mV)
V at 2A (mV)
R
AVE
F
Regulating Negative Output Voltages
The LT3513 contains an inverting op amp with a gain of
1. The NFB4 pin works just as the other FB pins. Choose
the resistors according to:
20
40
40
40
1
530
550
1
2
3
450
VOUT •R5
R6=
–R5
1.25
20
40
40
1
2
3
500
B240
500
450
R5 should be 2.5kΩ or less to avoid bias current errors.
B340A
–V
OUT
R6
BOOST PIN CONSIDERATIONS
NFB4
22
The minimum operating voltage of an LT3513 application
is limited by the undervoltage lockout ~4V and by the
maximum duty cycle. The boost circuit also limits the
minimum input voltage for proper start-up. If the input
voltage ramps slowly or the LT3513 turns on when the
output is already in regulation, the boost capacitor may
not be fully charged. Because the boost capacitor charges
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on input
and output voltages. The Typical Performance Character-
istics section shows a plot of the minimum load current
to start as a function of input voltage for a 3.3V output.
The minimum load current generally goes to zero once the
circuit has started. Even without an output load current, in
many cases the discharged output capacitor will present
a load to the switcher that will allow it to start.
R5
3513 A2
Duty Cycle Range
The maximum duty cycle (DC) of the LT3513 switching
regulator is 75% for SW2, and 84% for SW3 and SW4.
The duty cycle for a given application using the step-up
or charge pump topology is:
VOUT – V
IN
DC =
VOUT
The duty cycle for a given application using the inverter
or SEPIC is:
VOUT
V + VOUT
DC =
IN
INVERTER/STEP-UP CONSIDERATIONS
Regulating Positive Output Voltages
TheLT3513canstillbeusedinapplicationswheretheduty
cycle, as calculated above, is greater than the maximum.
However,thepartmustbeoperatedindiscontinuousmode
so that the actual duty cycle is reduced.
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistors
according to:
3513fa
15
LT3513
OPERATION
current greater than the load current and rated to handle
the maximum diode voltage. The average diode current in
the step-up and SEPIC is equal to the load current. Each of
the two diodes in the charge pump configurations carries
an average diode current equal to the load current. The
ground connected diode in the charge pump is integrated
into the LT3513. The maximum diode voltage in the step-
Inductor Selection
Table 1 lists several inductor vendors and types that are
suitabletousewiththeLT3513.Consulteachmanufacturer
for detailed information and for their entire selection of
related parts. Use ferrite core inductors to obtain the best
efficiency, as core losses at frequencies above 1MHz are
much lower for ferrite cores than for powdered-iron units.
A 10μH to 22μH inductor will be the best choice for most
LT3513 step-up and charge pump designs. Choose an
inductor that can carry the entire switch current without
saturating. For inverting and SEPIC regulators, a coupled
inductor, or two separate inductors is an option. When
using coupled inductors, choose one that can handle
at least the switch current without saturating. If using
uncoupled inductors, each inductor need only handle ap-
proximately one-half of the total switch current. A 4.7μH
to 15μH coupled inductor or two 10μH to 22μH uncoupled
inductors will usually be the best choice for most LT3513
inverting and SEPIC designs.
up and charge pump configurations is equal to |V |.
OUT
The maximum diode voltage in the SEPIC and inverting
configurations is V + |V |.
IN
OUT
Input Capacitor Selection
BypasstheinputoftheLT3513circuitwitha4.7μForhigher
ceramic capacitor of X7R or X5R type. A lower value or
a less expensive Y5V type will work if there is additional
bypassingprovidedbybulkelectrolyticcapacitorsorifthe
input source impedance is low. The following paragraphs
describetheinputcapacitorconsiderationsinmoredetail.
Step-down regulators draw current from the input sup-
ply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage ripple
at the LT3513 input and to force this switching current
into a tight local loop, minimizing EMI. The input capaci-
tor must have low impedance at the switching frequency
to do this effectively and it must have an adequate ripple
current rating. The input capacitor RMS current can be
calculatedfromthestep-downoutputvoltageandcurrent,
and the input voltage:
Output Capacitor Selection
Use low ESR (equivalent series resistance) capacitors at
theoutputtominimizetheoutputripplevoltage.Multilayer
ceramic capacitors are an excellent choice, as they have
an extremely low ESR and are available in very small pack-
ages. X7R dielectrics are preferred, followed by X5R, as
these materials retain their capacitance over wide voltage
and temperature ranges. A 10μF to 22μF output capaci-
tor is sufficient for most LT3513 applications. Even less
VOUT V – V
(
)
<
IOUT
2
IN
OUT
capacitance is required for outputs with |V | > 20V or
CIN(RMS) =IOUT
OUT
V
IN
|I | < 100mA. Solid tantalum or OS-CON capacitors will
OUT
also work, but they will occupy more board area and will
have a higher ESR than a ceramic capacitor. Always use
a capacitor with a sufficient voltage rating.
and is largest when VIN = 2VOUT (50% duty cycle). The
ripple current contribution from the other channels will
be minimal. Considering that the maximum load current
from switcher 1 is ~3A, RMS ripple current will always be
less than 1.5A. The high frequency of the LT3513 reduces
theenergystoragerequirementsoftheinputcapacitor, so
that the capacitance required is less than 10μF. The com-
bination of small size and low impedance (low equivalent
series resistance or ESR) of ceramic capacitors makes
Diode Selection
A Schottky diode is recommended for use with the
LT3513 switcher 2 and switcher 4. The Schottky diode for
switcher 3 is integrated inside the LT3513. Choose diodes
for switcher 2 and switcher 4 rated to handle an average
3513fa
16
LT3513
OPERATION
them the preferred choice. The low ESR results in very
low voltage ripple. Ceramic capacitors can handle larger
magnitudesofripplecurrentthanothercapacitortypesof
the same value. Use X5R and X7R types. An alternative to
a high value ceramic capacitor is a lower value along with
a larger electrolytic capacitor, for example a 1μF ceramic
capacitorinparallelwithalowESRtantalumcapacitor.For
the electrolytic capacitor, a value larger than 10μF will be
requiredtomeettheESRandripplecurrentrequirements.
Because the input capacitor is likely to see high surge
currents when the input source is applied, only consider
atantalumcapacitorifithastheappropriatesurgecurrent
rating. The manufacturer may also recommend operation
below the rated voltage of the capacitor. Be sure to place
the 1μF ceramic as close as possible to the VIN and GND
pins on the IC for optimal noise immunity.
current will generate a voltage ramp on these pins. This
voltage clamps the V pin, limiting the peak switch current
C
and therefore input current during start-up. The RUN-SS1
pin clamps V , the RUN-SS2 pin clamps V and the
C1
C1
RUN-SS3/4 pin clamps the V and V pins. A good value
C3
C4
for the soft-start capacitors is C /10,000, where C
OUT
OUT
is the value of the largest output capacitor.
V
Pin Considerations
ON
TheV pinisthedelayedoutputforswitchingregulator 3.
ON
When the C pin reaches 1.1V, the output disconnect PNP
T
turns on, connecting V to E3. The V pin is current
ON
ON
limited and will protect the LT3513 and input source from
a shorted output.
The V pin output is also controlled from the V
ON
ON_CLK
pin. When V
is low, the V output will turn on if the
ON_CLK
ON
A final caution is in order regarding the use of ceramic
capacitors at the input. A ceramic input capacitor can
combine with stray inductance to form a resonant tank
circuit.Ifpowerisappliedquickly(forexamplebyplugging
the circuit into a live power source), this tank can ring,
doubling the input voltage and damaging the LT3513. The
solution is to either clamp the input voltage or dampen the
tank circuit by adding a lossy capacitor (an electrolytic)
in parallel with the ceramic capacitor. For details, see Ap-
plication Note 88.
C pin is greater than 1.1V. When V
is high, greater
ON_CLK
T
than 1.5V, the V output is disabled and the V
open
ON
ONSINK
pin is connected
collector device turns on. If the V
ONSINK
ON
may be synced to the horizontal
to V through a resistor, the V voltage will decay with
ON
a high V
. V
ON_CLK ON_CLK
scanning frequency to improve LCD image quality.
Low Voltage Dropout Linear Regulator
The LT3513 features an output to drive an external NPN
transistorLDOtoprovidealowervoltagelogicsupplyvolt-
age. The output is capable of providing 10mA of current to
the base of the NPN. The output of the LDO is controlled
by the FB5 pin. Choose the resistor values according to:
Soft-Start and Shutdown
The RUN-SS1(Run/Soft-Start) pin is used to place the
switching regulators and the internal bias circuits in
shutdown mode. It also provides a soft-start function,
along with RUN-SS2 and RUN-SS3/4. If the RUN-SS1
pin is pulled to ground, the LT3513 enters its shutdown
modewithallregulatorsoffandquiescentcurrentreduced
to ~30μA. An internal 2μA current source pulls up on the
RUN-SS1,RUN-SS2,andRUN-SS3/4pins.IftheRUN-SS1
pin reaches ~0.6V, the internal bias circuits start and the
quiescent currents increase to their nominal levels.
VLDO
0.625V
⎛
⎞
⎠
R8=R7
–1
⎜
⎝
⎟
R8 should be 10k or less to avoid bias current errors.
The internal compensation of the LDO relies on a low ESR
ceramic capacitor between the values of 2.2μF and 20μF.
X7R dielectrics are preferred, followed by X5R, as these
materials retain their capacitance over wide voltage and
temperature ranges.
If a capacitor is tied from the RUN-SS1, RUN-SS2 or
RUN-SS3/4 pins to ground, then the internal pull-up
3513fa
17
LT3513
OPERATION
Printed Circuit Board Layout
the output capacitor C2. Additionally, keep the SW and
BOOST nodes as small as possible.
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 3
shows the high current paths in the step-down regula-
tor circuit. Note that in the step-down regulators, large,
switched currents flow in the power switch, the catch
diode and the input capacitor. In the step-up regulators,
large, switched currents flow through the power switch,
theswitchingdiodeandtheoutputcapacitor. InSEPICand
inverting regulators, the switched currents flow through
thepowerswitch, theswitchingdiodeandthetankcapaci-
tor. The loop formed by the components in the switched
current path should be as small as possible. Place these
components,alongwiththeinductorandoutputcapacitor,
on the same side of the circuit board, and connect them
on that layer. Place a local, unbroken ground plane below
these components, and tie this ground plane to system
ground at one location, ideally at the ground terminal of
Thermal Considerations
The PCB must provide heat sinking to keep the LT3513
cool. The Exposed Pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to other copper layers below with thermal vias; these lay-
ers will spread the heat dissipated by the LT3513. Place
additional vias near the catch diodes. Adding more copper
to the top and bottom layers and tying this copper to the
internal planes with vias can reduce thermal resistance
further. With these steps, the thermal resistance from die
(or junction) to ambient can be reduced to θ = 25°C
JA
or less. With 100LFPM airflow, this resistance can fall
by another 25%. Further increases in airflow will lead to
lower thermal resistance.
V
IN
SW
GND
(3a)
V
IN
SW
GND
(3b)
V
SW
L1
V
SW
IN
I
C1
C1
D1
C2
GND
Figure 4. Topside PCB Layout
3519 F03
(3c)
Figure 3. Subtracting the Current When the Switch is On (3a)
from the Current When the Switch is Off (3b) Reveals the Path of
the High Frequency Switching Current (3c) Keep this Loop Small.
The Voltage on the SW and BOOST Nodes will Also be Switched;
Keep These Nodes as Small as Possible. Finally, Make Sure The
Circuit is Shielded with a Local Ground Plane
3513fa
18
LT3513
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 p 0.05
5.50 p 0.05
4.10 p 0.05
3.00 REF
5.15 0.05
3.15 0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
0.75 p 0.05
3.00 REF
5.00 p 0.10
37
38
0.00 – 0.05
0.40 p0.10
PIN 1
TOP MARK
1
2
(SEE NOTE 6)
5.15 0.10
5.50 REF
7.00 p 0.10
3.15 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 p 0.05
R = 0.125
TYP
R = 0.10
TYP
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3513fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT3513
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DESCRIPTION
COMMENTS
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I
< 16μA, TSSOP16E Package
LT3475
Dual 1.5A (I ), 36V, 2MHz Step-Down LED Driver
V : 4V to 36V, V
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LT3476
Quad Output 1.5A, 2MHz High Current LED Driver with
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V : 2.8V to 16V, V
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Q
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I
< 10μA, 5mm × 7mm QFN10 Package
LT3478/LT3478-1
LT3486
42V, 4.5A (I ), 2.25MHz, LED Drivers with 3,000:1 True V : 2.8V to 36V, V
= 42V, I = 6.1mA, I < 3μA,
Q SD
SW
IN
OUT(MAX)
Color PWM Dimming
TSSOP16E Package
Dual 1.3A, 2MHz High Current LED Driver
V : 2.5V to 24V, V
= 36V, I = 1,000:1 True Color PWM,
Q
IN
OUT(MAX)
OUT(MAX)
I
< 1μA, 5mm × 3mm DFN, TSSOP16E Packages
SD
LT3491
Constant Current, 2.3MHz, High Efficiency White LED
Boost Regulator with Integrated Schottky Diode
V : 2.5V to 12V, V
= 27V, I = 2.6mA, I < 8μA,
Q SD
IN
2mm × 2mm DFN6, SC70 Packages
LT3494/LT3494A
LT3497
40V, 180mA/350mA Micropower Low Noise Boost
Converters with Output Disconnect
V : 2.3V to 16V, V = 40V, I = 65μA, I < 1μA,
IN
OUT(MAX)
Q
SD
3mm × 2mm DFN8 Package
Dual 2.3MHz, Full Function LED Driver with Integrated
Schottkys and 250:1 True Color PWM Dimming
V : 2.5V to 10V, V = 32V, I = 6mA, I < 12μA,
IN
OUT(MAX)
Q
SD
3mm × 2mm DFN10 Package
LT3498
2.3MHz, 20mA LED Driver and OLED Driver with
Integrated Schottkys
V : 2.5V to 12V, V = 32V, I = 1.65mA, I < 9μA,
IN
OUT(MAX)
Q
SD
3mm × 2mm DFN12 Package
Constant Current, 1MHz, High Efficiency White LED Boost V : 2.5V to 12V, V = 40V, I = 4mA, I < 9μA,
IN OUT(MAX)
LT3591
Q
SD
Regulator with Integrated Schottky Diode and 80:1 True
Color PWM Dimming
3mm × 2mm DFN8 Package
LT3595
16-Channel 48V, 2MHz Buck Mode LED Driver with
3000:1 True Color PWM Dimming
V : 4.5V to 50V, I = 3,000:1 True Color PWM, I < 3μA,
IN
Q
SD
5mm × 9mm QFN56 Package
True Color PWM and ThinSOT are trademarks of Linear Technology Corporation.
3513fa
LT 1108 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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