LT3581EMSE#PBF [Linear]
LT3581 - 3.3A Boost/Inverting DC/DC Converter with Fault Protection; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LT3581EMSE#PBF |
厂家: | Linear |
描述: | LT3581 - 3.3A Boost/Inverting DC/DC Converter with Fault Protection; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
文件: | 总36页 (文件大小:456K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT3581
3.3A Boost/Inverting DC/DC
Converter with Fault Protection
FEATURES
DESCRIPTION
The LT®3581 is a PWM DC/DC converter with built-in fault
protection features to aid in protecting against output
shorts, input/output overvoltages, and overtemperature
conditions. The part consists of a 42V master switch, and
a 42V slave switch that can be tied together for a total
current limit of 3.3A.
n
3.3A, 42V Combined Power Switch
n
Master/Slave (1.9A/1.4A) Switch Design
n
Output Short Circuit Protection
Wide Input Range: 2.5V to 22V Operating,
40V Maximum Transient
Switching Frequency Up to 2.5MHz
Easily Configurable as a Boost, SEPIC, Inverting or
Flyback Converter
User Configurable Undervoltage Lockout
n
n
n
The LT3581 is ideal for many local power supply designs. It
canbeeasilyconfiguredinBoost,SEPIC,InvertingorFlyback
configurations, and is capable of generating 12V at 830mA,
or –12V at 625mA from a 5V input. In addition, the LT3581’s
slaveswitchallowstheparttobeconfiguredinhighvoltage,
high power charge pump topologies that are very efficient
and require fewer components than traditional circuits.
n
n
Low V
Switch: 250mV at 2.75A (Typical)
CESAT
n
n
n
Can be Synchronized to External Clock
Can Be Synchronized to other Switching Regulators
High Gain SHDN Pin Accepts Slowly Varying Input
Signals
n
TheLT3581’sswitchingfrequencyrangecanbesetbetween
200kHz and 2.5MHz. The part may be clocked internally at
a frequency set by the resistor from the RT pin to ground,
or it may be synchronized to an external clock. A buffered
version of the clock signal is driven out of the CLKOUT
pin, and may be used to synchronize other compatible
switching regulator ICs to the LT3581.
14-Pin 4mm × 3mm DFN and 16-Lead MSE Packages
APPLICATIONS
n
Local Power Supply
n
Vacuum Fluorescent Display (VFD) Bias Supplies
n
TFT-LCD Bias Supplies
Automotive Engine Control Unit (ECU) Power
TheLT3581alsofeaturesinnovativeSHDNpincircuitrythat
allows for slowly varying input signals and an adjustable
undervoltage lockout function. Additional features such
as frequency foldback and soft-start are integrated. The
LT3581 is available in 14-Pin 4mm × 3mm DFN and 16-
Lead MSE packages.
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7579816.
Efficiency and Power Loss vs
Load Current
TYPICAL APPLICATION
100
95
90
85
80
75
70
65
60
55
50
2000
1800
1600
1400
1200
1000
800
Output Short Protected, 5V to 12V Boost Converter Operating at 2MHz
1.5µH
V
OUT
V
IN
12V
5V
830mA
4.7µF
130k
6.04k
SW1 SW2
18.7k
V
FB
GATE
IN
100k
FAULT
V
IN
4.7µF
SHDN
CLKOUT
600
RT
V
C
LT3581
4.7µF
10k
400
56pF
SYNC
SS
10.5k
1nF
43.2k
200
GND
0.1µF
0
3581 TA01
0
200
600
LOAD CURRENT (mA)
800
1000
400
3581 TA01b
3581fb
1
For more information www.linear.com/LT3581
LT3581
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V Voltage................................................. –0.3V to 40V
FAULT Current..................................................... 500µA
CLKOUT Voltage .......................................... –0.3V to 3V
CLKOUT Current.......................................................1mA
Operating Junction Temperature Range
LT3581E (Notes 2, 4).........................–40°C to 125°C
LT3581I (Notes 2, 4)..........................–40°C to 125°C
LT3581H (Notes 2, 4).........................–40°C to 150°C
Storage Temperature Range ..................–65°C to 150°C
IN
SW1/SW2 Voltage ..................................... –0.4V to 42V
RT Voltage ................................................... –0.3V to 5V
SS, FB Voltage .......................................... –0.3V to 2.5V
V Voltage.................................................... –0.3V to 2V
C
SHDN Voltage ............................................ –0.3V to 40V
SYNC Voltage............................................ –0.3V to 5.5V
GATE Voltage ............................................. –0.3V to 80V
FAULT Voltage ............................................ –0.3V to 40V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
FB
1
2
3
4
5
6
7
14 SYNC
13 SS
1
2
3
4
5
6
7
8
FB
16 SYNC
15 SS
V
C
V
C
GATE
12 RT
GATE
14 RT
15
FAULT
17
GND
13 SHDN
12 CLKOUT
11 SW2
10 SW2
FAULT
11 SHDN
10 CLKOUT
GND
V
IN
V
SW1
SW1
SW1
IN
SW1
SW1
9
8
SW2
SW2
9
SW2
MSE PACKAGE
16-LEAD PLASTIC MSOP
= 125°C, θ = 45°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
DE14 PACKAGE
T
JMAX
14-PIN (4mm × 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W, θ = 4.3°C/W
JA JC
JMAX
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3581EDE#PBF
LT3581IDE#PBF
LT3581HDE#PBF
LT3581EMSE#PBF
LT3581IMSE#PBF
TAPE AND REEL
PART MARKING*
3581
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3581EDE#TRPBF
LT3581IDE#TRPBF
LT3581HDE#TRPBF
LT3581EMSE#TRPBF
LT3581IMSE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
16-Lead Plastic MSOP
3581
3581
3581
3581
16-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3581fb
For more information www.linear.com/LT3581
2
LT3581
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2).
PARAMETER
CONDITIONS
MIN
TYP
2.3
MAX
2.5
UNITS
V
l
Minimum Input Voltage
V
Overvoltage Lockout
22.1
1.195
3
23.5
1.215
9
25
V
IN
l
l
l
l
Positive Feedback Voltage
Negative Feedback Voltage
Positive FB Pin Bias Current
Negative FB Pin Bias Current
Error Amp Transconductance
Error Amp Voltage Gain
1.230
16
V
mV
µA
V
V
= Positive Feedback Voltage, Current into Pin
= Negative Feedback Voltage, Current out of Pin
81
83.3
83.3
270
70
85
FB
FB
81
85.5
µA
ΔI = 10μA
µmhos
V/V
mA
µA
Quiescent Current
Not Switching
1.9
2.3
1
Quiescent Current in Shutdown
Reference Line Regulation
V
= 0V
0
SHDN
2.5V ≤ V ≤ 20V
0.01
2.5
0.05
2.75
220
%/V
MHz
kHz
ratio
kHz
V
IN
l
l
Switching Frequency, f
R = 34k
2.25
180
OSC
T
R = 432k
200
1/6
T
Switching Frequency in Foldback
Switching Frequency Range
Compared to Normal f
OSC
l
l
l
Free-Running or Synchronizing
200
1.3
2500
SYNC High Level for Synchronization
SYNC Low Level for Synchronization
SYNC Clock Pulse Duty Cycle
0.4
80
V
V
= 0V to 2V
20
%
SYNC
Recommended Minimum SYNC Ratio
SYNC OSC
3/4
f
/f
Minimum Off-Time
45
55
ns
ns
A
Minimum On-Time
l
l
SW1 Current Limit
At All Duty Cycles
1.9
3.3
2.4
78
3
Current Sharing (SW2/SW1)
SW1 + SW2 Current Limit
%
At All Duty Cycles, SW2/SW1 = 78% (Note 3)
4.3
250
0.01
0.01
5.4
A
Switch V
SW1 & SW2 Tied Together, I
+ I = 2.75A
SW2
mV
µA
µA
CESAT
SW1
SW1 Leakage Current
SW2 Leakage Current
V
V
= 5V
= 5V
1
1
SW1
SW2
3581fb
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For more information www.linear.com/LT3581
LT3581
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2).
PARAMETER
CONDITIONS
V = 30mV, Current Flows Out of SS pin
SS
MIN
5.7
TYP
8.7
8.7
1.8
50
MAX
11.3
11.3
1.95
85
UNITS
µA
l
l
l
l
Soft-Start Charge Current
Soft-Start Discharge Current
Soft-Start High Detection Voltage
Soft-Start Low Detection Voltage
SHDN Minimum Input Voltage High
Part in FAULT, V = 2.1V, Current Flows into SS Pin
5.7
µA
SS
Part in FAULT
1.65
30
V
Part Exiting FAULT
mV
l
l
l
Active Mode, SHDN Rising (LT3581E, LT3581I)
Active Mode, SHDN Rising (LT3581H)
Active Mode, SHDN Falling (LT3581E, LT3581I, LT3581H)
1.27
1.27
1.24
1.33
1.33
1.3
1.41
1.44
1.38
V
V
V
l
SHDN Input Voltage Low
SHDN Pin Bias Current
Shutdown Mode
0.3
V
V
SHDN
V
SHDN
V
SHDN
= 3V
= 1.3V
= 0V
40
11.4
0
60
13.4
0.1
µA
µA
µA
9.7
1.9
CLKOUT Output Voltage High
CLKOUT Output Voltage Low
CLKOUT Duty Cycle
C
C
= 50pF
= 50pF
2.1
5
2.3
V
mV
%
CLKOUT
CLKOUT
200
T = 25°C
J
42
12
8
CLKOUT Rise Time
C
C
= 50pF
= 50pF
ns
CLKOUT
CLKOUT
CLKOUT Fall Time
ns
l
l
l
GATE Pull Down Current
V
V
V
= 3V (LT3581E, LT3581I)
= 3V (LT3581H)
= 80V (LT3581E, LT3581I, LT3581H)
800
700
800
933
900
933
1100
1100
1100
µA
µA
µA
GATE
GATE
GATE
GATE Leakage Current
V
= 50V, GATE Off
0.01
1
µA
GATE
l
l
FAULT Output Voltage Low
50μA into FAULT Pin (LT3581E, LT3581I)
50μA into FAULT Pin (LT3581H)
100
100
300
400
mV
mV
FAULT Leakage Current
FAULT Input Voltage Low
FAULT Input Voltage High
V
= 40V, FAULT Off
0.01
750
1
µA
mV
mV
FAULT
l
l
700
950
800
1050
1000
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
guaranteed over the full –40°C to 150°C operating junction temperature
range. Operating lifetime is derated at junction temperatures greater than
125°C.
Note 3: Current limit guaranteed by design and/or correlation to static test.
Note 2: The LT3581E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LT3581I is guaranteed over the full
–40°C to 125°C operating junction temperature range. The LT3581H is
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
3581fb
For more information www.linear.com/LT3581
4
LT3581
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Fault Current Limit vs
Duty Cycle
Switch Saturation Voltage with
SW1 and SW2 Tied Together
Current Sharing Between SW1 and
SW2 When Tied Together
6
5
4
3
2
1
0
450
400
350
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
0
60
DUTY CYCLE (%)
70
20
30
40
50
80
0
1
2
3
4
5
0
1
2
3
4
5
SW1 + SW2 CURRENT (A)
SW1 + SW2 CURRENT (A)
3581 G01
3581 G02
3581 G03
Switch Fault Current Limit vs
Temperature
Positive Feedback Voltage
vs Temperature
CLKOUT Duty Cycle
vs Temperature
6
5
4
3
2
1
0
1.2200
1.2175
1.2150
1.2125
1.2100
80
70
60
50
40
30
20
10
–50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3581 G04
3581 G06
3581 G05
Oscillator Frequency
Frequency Foldback
Gate Current vs Gate Voltage
3200
2800
2400
2000
1600
1200
800
1000
900
800
700
600
500
400
300
200
100
0
1
–40°C
R
T
= 34k
125°C
25°C
1/2
1/3
1/4
1/5
1/6
400
INVERTING
CONFIGURATIONS
BOOSTING
CONFIGURATIONS
R
T
= 432k
0
0
–50 –25
0
25 50 75 100 125 150
0
20
40
GATE VOLTAGE (V)
60
80
0
0.2
0.4
0.6
0.8 1.0
1.2
FB VOLTAGE (V)
TEMPERATURE (°C)
3581 G08
3581 G07
3581 G09
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For more information www.linear.com/LT3581
LT3581
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Commanded Current Limit vs
SS Voltage
SHDN Voltage Threshold with
Hysteresis
Gate Current vs SS Voltage
1000
900
800
700
600
500
400
300
200
100
0
5
4
3
2
1
0
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
SHDN RISING
SHDN FALLING
0
0.25 0.50 0.75 1.00
SS VOLTAGE (V)
1.25 1.50
0
0.2
0.4
0.6
0.8
1.0
1.2
–50 –25
0
25 50 75 100 125 150
SS VOLTAGE (V)
TEMPERATURE (°C)
3581 G10
3580 G11
3581 G12
SHDN Pin Current
SHDN Pin Current
Internal UVLO
32
28
24
20
16
12
8
250
200
150
100
50
2.40
2.38
2.36
2.34
2.32
2.30
2.28
2.26
2.24
2.22
2.20
–40°C
25°C
25°C
125°C
125°C
4
–40°C
0
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0
5
10 15 20 25 30 35 40
–50 –25
0
25 50 75 100 125 150
SHDN VOLTAGE (V)
SHDN VOLTAGE (V)
TEMPERATURE (°C)
3581 G14
3581 G15
3581 G13
FAULT Input Voltage Threshold
with Hysteresis
CLKOUT Rise Time at 1MHz
VIN OVLO
50
45
40
35
30
25
20
15
10
5
30
28
26
24
22
20
18
16
1.25
1.00
0.75
0.50
0.25
0
FAULT RISING
FAULT FALLING
CLKOUT RISE TIME
CLKOUT FALL TIME
0
0
50
100
150
200
250
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
CLKOUT CAPACITIVE LOAD (pF)
TEMPERATURE (°C)
TEMPERATURE (°C)
3581 G16
3581 G17
3581 G18
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6
LT3581
PIN FUNCTIONS (DFN/MSOP)
FB (Pin 1/Pin 1): Positive and Negative Feedback Pin. For
CLKOUT (Pin 10/Pin 12): Clock Output Pin. Use this pin
to synchronize one or more other compatible switching
regulatorICstotheLT3581. Theclockthatthispinoutputs
runs at the same frequency as the internal oscillator of the
part or as the SYNC pin. CLKOUT may also be used as a
temperature monitor since the CLKOUT pin’s duty cycle
varies linearly with the part’s junction temperature. Note
that the CLKOUT pin is only meant to drive capacitive
loads up to 50pF.
a Boost or Inverting Converter, tie a resistor from the FB
pin to V
according to the following equations:
OUT
V
–1.215V
OUT
RFB =
;Boost or SEPIC Converter
83.3•10–6
|V |+ 9mV
OUT
RFB =
;InvertingConverter
83.3•10–6
V (Pin 2/Pin 2): Error Amplifier Output Pin. Tie external
C
SHDN (Pin 11/Pin 13): Shutdown Pin. In conjunction
with the UVLO (undervoltage lockout) circuit, this pin is
used to enable/disable the chip and restart the soft-start
sequence. Drive below 300mV to disable the chip. Drive
above 1.33V (typical) to activate the chip and restart the
soft-start sequence. Do not float this pin.
compensation network to this pin.
GATE (Pin 3/Pin 3): PMOS Gate Drive Pin. The GATE pin
is a pull-down current source, used to drive the gate of
an external PMOS for output short circuit protection or
outputdisconnect.TheGATEpincurrentincreaseslinearly
with the SS pin’s voltage, with a maximum pull-down
current of 933µA at SS voltages exceeding 500mV. Note
that if the SS voltage is greater than 500mVand the GATE
pin voltage is less than 2V, then the GATE pin looks like
a 2kΩ impedance to ground. See the Appendix for more
information.
RT (Pin 12/Pin 14): Timing Resistor Pin. Adjusts the
LT3581’s switching frequency. Place a resistor from this
pin to ground to set the frequency to a fixed free running
level. Do not float this pin.
SS (Pin 13/Pin 15): Soft-Start Pin. Place a soft-start
capacitor here. Upon start-up, the SS pin will be charged
by a (nominally) 250k resistor to about 2.1V. During a
fault, the SS pin will be slowly charged up and eventually
discharged as part of a timeout sequence (see the State
Diagram for more information on the SS pin’s role during
a fault event).
FAULT (Pin 4/Pin 4): Fault Indication Pin. This active low,
bidirectional pin can either be pulled low (below 750mV)
by an external source, or internally by the chip to indicate a
fault. When pulled low, this pin causes the power switches
to turn off, the GATE pin to become high impedance, the
CLKOUT pin to become disabled, and the SS pin to go
through a charge/discharge sequence. The end/absence
of a fault is indicated when the voltage on this pin exceeds
1V. A pull-up resistor or current source is needed on this
pin to pull it above 1V in the absence of a fault.
SYNC (Pin 14/Pin 16): To synchronize the switching
frequency to an outside clock, simply drive this pin with
a clock. The high voltage level of the clock must exceed
1.3V, and the low level must be less than 0.4V. Drive this
pin to less than 0.4V to revert to the internal free running
clock. See the Applications Information section for more
information.
V
(Pin 5/Pin 5): Input Supply Pin. Must be locally by-
IN
passed.
SW1(Pins6,7/Pins6,7,8):MasterSwitchPin.Thisisthe
collector of the internal master NPN power switch.
Minimize the metal trace area connected to this pin to
minimize EMI.
GND (Exposed Pad Pin 15/Exposed Pad Pin 17): Ground.
Exposed pad must be soldered directly to local ground
plane.
SW2 (Pins 8, 9/Pins 9, 10, 11): Slave Switch Pin. This
is the collector of the internal slave NPN power switch.
Minimize the metal trace area connected to this pin to
minimize EMI.
3581fb
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For more information www.linear.com/LT3581
LT3581
BLOCK DIAGRAM
OPTIONAL
M1
D1
L1
V
IN
V
OUT
C
IN
C
OUT1
C
OUT2
R
FAULT
R
GATE
GATE
FAULT
22V
MIN
933µA
SOFT-
START
DIE TEMP
V
V
C
165°C
750mV
IN
SW1
+
–
2.1V
**
42V
MIN
SAMPLE MODE BLOCK
50mV
+
–
SW2
+
–
STARTUP
AND FAULT
LOGIC
**
42V
MIN
1.8V
LDO
+
–
–
+
1.17V
250k
I
SW1
+
–
FB
SS
+
–
1.9A
MIN
DRIVER
DISABLE
SW2
45mV
C
SS
TD ~ 30ns
SAMPLE
+ VBE • 0.9
R
FB
SHDN
–
SW1
Q1
+
–
Q2
COMPARATOR
1.33V
27mΩ
SR1
S
DRIVER
UVLO
–
R
Q
V
IN
A3
1.215V
REFERENCE
+
+
+
–
R
S
20mΩ
14.6k
A4
A1
∑
–
FB
RAMP
GENERATOR
GND
+
–
÷N
FREQUENCY
FOLDBACK
ADJUSTABLE
OSCILLATOR
14.6k
A2
SS
SYNC
BLOCK
V
C
RT
SYNC
CLKOUT
R
C
R
T
C
C
3581 BD
**SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3581 DURING SW OVERVOLTAGE EVENTS
Figure 1. Block Diagram
3581fb
For more information www.linear.com/LT3581
8
LT3581
STATE DIAGRAM
SHDN < 1.33V (TYPICAL)
or
V
IN
< 2.3V (TYPICAL)
CHIP OFF
• ALL SWITCHES DISABLED
• I OFF
GATE
• FAULTS CLEARED
SHDN > 1.33V (TYPICAL)
AND
> 2.3V (TYPICAL)
V
IN
INITIALIZE
• SS PULLED LOW
FAULT1
FAULT1
FAULT2
FAULT DETECTED
• SS CHARGES UP
SS < 50mV
• IGATE OFF
• FAULT PIN PULLED LOW
INTERNALLY BY LT3581
• SWITCHER DISABLED
• CLKOUT DISABLED
SOFT START
ENABLED
• I
GATE
• SS CHARGES UP
• SWITCHER ENABLED
SS > 1.8V AND
NO FAULT1 CONDITIONS
STILL DETECTED
POST FAULT DELAY
• SS SLOWLY DISCHARGES
FAULT1
SAMPLE MODE
• Q1 & Q2 SWITCHES
FORCED ON EVERY CYCLE
FOR AT LEAST MINIMUM
ON TIME
FAULT1
SS < 50mV
• I
FULLY ACTIVATED
GATE
WHEN SS > 500mV
LOCAL FAULT OVER
• INTERNAL FAULT PIN PULLDOWN
RELEASED BY LT3581
FAULT1
• SS CONTINUES DISCHARGING
TO GND
IF |V | DROPS CAUSING:
OUT
FB < 1.17V (BOOST)
OR
NORMAL MODE
FAULT PIN > 1.0V
FB > 45mV (INVERTING)
• NORMAL OPERATION
• CLKOUT ENABLED WHEN
SS > 1.8V
FAULT1
FAULT1 = OVER VOLTAGE PROTECTION ON V (V > 22V MIN)
IN IN
OVER TEMPERATURE (T
OVER CURRENT ON SW1 (I
> 165°C)
JUNCTION
SW1
> 1.9A MIN)
OVER VOLTAGE PROTECTION ON SW1 (V
OVER VOLTAGE PROTECTION ON SW2 (V
> 42V MIN)
> 42V MIN)
SW1
SW2
FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V)
3581 SD
Figure 2. State Diagram
3581fb
9
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LT3581
OPERATION
OPERATION – OVERVIEW
V
IN
V
IN
TheLT3581usesaconstant-frequency,currentmodecon-
trol scheme to provide excellent line and load regulation.
Thepart’sundervoltagelockout(UVLO)function,together
with soft-start and frequency foldback, offers a controlled
meansofstartingup. Faultfeaturesareincorporatedinthe
LT3581 to aid in the detection of output shorts, over-volt-
age, and overtemperature conditions. Refer to the Block
Diagram (Figure 1) and the State Diagram (Figure 2) for
the following description of the part’s operation.
ACTIVE/
1.33V
–
+
R
UVLO1
LOCKOUT
SHDN
11.6µA
AT 1.33V
R
UVLO2
(OPTIONAL)
GND
3581 F03
Figure 3. Configurable UVLO
The LT3581 also has internal UVLO circuitry that disables
OPERATION – START-UP
the chip when V < 2.3V (typical).
IN
Several functions are provided to enable a very clean
start-up for the LT3581:
Soft-Start of Switch Current
The soft-start circuitry provides for a gradual ramp-up
of the switch current (refer to Commanded Current Limit
vs SS Voltage in Typical Performance Characteristics).
When the part is brought out of shutdown, the external
SS capacitor is first discharged which resets the states
of the logic circuits in the chip. Then an integrated 250k
resistor pulls the SS pin to ~1.8V. The ramp rate of the SS
pin voltage is set by this 250k resistor and the external
capacitor connected to this pin. Once SS gets to 1.8V, the
CLKOUT pin is enabled, and an internal regulator pulls
the pin up quickly to ~2.1V. Typical values for the external
soft-start capacitor range from 100nF to 1μF.
Precise Turn-On Voltage
The SHDN pin is compared to an internal voltage reference
to give a precise turn on voltage level. Taking the SHDN pin
above1.33V(typical)enablesthepart.TakingtheSHDNpin
below 300mV shuts down the chip, resulting in extremely
lowquiescentcurrent.TheSHDNpinhas30mVofhysteresis
to protect against glitches and slow ramping.
Undervoltage Lockout (UVLO)
The SHDN pin can also be used to create a configurable
UVLO.TheUVLOfunctionsetstheturnon/offoftheLT3581
at a desired input voltage (V
). Figure 3 shows how a
INUVLO
Soft-Start of External PMOS (if used)
resistor divider (or single resistor) from V to the SHDN
IN
pin can be used to set V
. R
is optional. It may
The soft-start circuitry also gradually ramps up the GATE
pin pull-down current which allows an external PMOS to
slowlyturnon(M1inBlockDiagram).TheGATEpincurrent
increases linearly with the SS voltage, with a maximum
current of 933µA when the SS voltage gets above 500mV.
Note that if the GATE pin voltage is less than 2V for SS
voltages exceeding 500mV, then the GATE pin impedance
to ground is 2kΩ. The soft turn on of the external PMOS
helps limit inrush current at start-up, making hot-plugs
of LT3581s feasible and safe.
INUVLO UVLO2
be left out, in which case set it to infinite in the equation
below. For increased accuracy, set R
≤ 10k. Pick
UVLO2
R
UVLO1
as follows:
V
UVLO –1.33V
IN
RUVLO1
=
1.33V
+ 11.6µA
R
UVLO2
3581fb
For more information www.linear.com/LT3581
10
LT3581
OPERATION
Sample Mode
Q1’semittercurrentflowsthroughacurrentsenseresistor
(R ) generating a voltage proportional to the total switch
S
Sample Mode is the mechanism used by the LT3581 to
aid in the detection of output shorts. It refers to a state of
the LT3581 where the master and slave power switches
(Q1 and Q2) are turned on for a minimum period of time
every clock cycle (or every few clock cycles in frequency
foldback) in order to “sample” the inductor current. If the
sampledcurrentthroughQ1exceedsthemasterswitchcur-
rentlimitof1.9A(min),theLT3581triggersanovercurrent
fault internally (see Operation-Fault section for details).
Sample Mode is active when FB is out of regulation by
more than approximately 3.7% (45mV < FB < 1.17V).
current. This voltage (amplified by A4) is added to a sta-
bilizing ramp and the resulting sum is fed into the positive
terminal of the PWM comparator A3. When the voltage on
thepositiveinputofA3exceedsthevoltageonthenegative
input,theSRlatchisreset,turningoffthemasterandslave
power switches. The voltage on the negative input of A3
(V pin) is set by A1 (or A2), which is simply an amplified
C
difference between the FB pin voltage and the reference
voltage (1.215V if the LT3581 is configured as a boost
converter, or 9mV if configured as an inverting converter).
In this manner, the error amplifier sets the correct peak
current level to maintain output regulation.
Frequency Foldback
As long as the part is not in fault (see Operation – Fault
section)andtheSSpinexceeds1.8V, theLT3581drivesits
CLKOUTpinatthefrequencysetbytheRTpinortheSYNC
pin. The CLKOUT pin can be used to synchronize other
compatible switching regulator ICs (including additional
LT3581s) with the LT3581. Additionally, CLKOUT’s duty
cycle varies linearly with the part’s junction temperature,
and may be used as a temperature monitor.
The frequency foldback circuit reduces the switching fre-
quency when 350mV < FB < 900mV (typical). This feature
lowers the minimum duty cycle that the part can achieve,
thus allowing better control of the inductor current dur-
ing start-up. When the FB voltage is pulled outside of this
range, the switching frequency returns to normal.
Notethatthepeakinductorcurrentatstart-upisafunction
ofmanyvariablesincludingloadprofile,outputcapacitance,
target V , V , switching frequency, etc. Test each and
OUT IN
OPERATION – FAULT
everyapplication’sperformanceatstart-uptoensurethat
the peak inductor current does not exceed the minimum
fault current limit.
The LT3581’s FAULT pin is an active low, bidirectional pin
that is pulled low to indicate a fault. Each of the following
events can trigger a fault in the LT3581:
OPERATION – REGULATION
A. FAULT1 events:
1. SW Overcurrent:
The following description of the LT3581’s operation as-
sumes that the FB voltage is close enough to its regulation
target so that the part is not in sample mode. Use the
Block Diagram as a reference when stepping through the
followingdescriptionoftheLT3581operatinginregulation.
At the start of each oscillator cycle, the SR latch (SR1) is
set, which turns on the power switches Q1 and Q2. The
collector current through the master switch, Q1, is ~1.3
times the collector current through the slave switch, Q2,
when the collectors of the two switches are tied together.
a. I
> 1.9A (minimum)
SW1
b. (I
+ I
) > 3.3A (minimum)
SW1
SW2
2. V Voltage > 22V (minimum)
IN
3. SW1 Voltage and/or SW2 Voltage > 42V
(minimum)
4. Die Temperature > 165°C
B. FAULT2 events:
1. Pulling the FAULT pin low externally
3581fb
11
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LT3581
OPERATION
Refer to the State Diagram (Figure 2) for the following
description of the LT3581’s operation during a fault event.
When a fault is detected, in addition to the FAULT pin being
pulled low internally, the LT3581 also disables its CLKOUT
pin,turnsoffitspowerswitches,andtheGATEpinbecomes
high impedance. The external PMOS, M1, turns off when
the gate of M1 is pulled up to its source by the external
and thermal stress for a minimum amount of time as set
by the voltage ramp rate on the SS pin.
In the absence of faults, the FAULT pin is pulled high by the
external R
resistor (typically 100k). Figure 4 shows
FAULT
the events that accompany the detection of an output
short on the LT3581.
V
R
resistor (see Block Diagram). With the external
OUT
GATE
10V/DIV
PMOS turned off, the power path from V to V
is cut
IN
OUT
V
FAULT
5V/DIV
off, protecting power components downstream.
V
CLKOUT
2V/DIV
At the same time, a timeout sequence commences where
the SS pin is charged up to 1.8V(the SS pin will continue
charging up to 2.1V and be held there in the case of a
FAULT1eventthathasstillnotended),andthendischarged
to 50mV. This timeout period relieves the part, the PMOS,
and other downstream power components from electrical
I
L
2A/DIV
3581 F04
5µs/DIV
Figure 4. Output Short Circuit Protection of the LT3581
3581fb
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12
LT3581
APPLICATIONS INFORMATION
BOOST CONVERTER COMPONENT SELECTION
Table 1. Boost Design Equations
PARAMETERS/EQUATIONS
D1
20V, 2A
OPTIONAL
L1
1.5µH
V
Step 1: Pick V , V , and f
to calculate equations below.
PMOS
OUT
12V
IN OUT
OSC
V
IN
Inputs
5V
C
OUT1
I
< 0.83A
OUT
R
GATE
6.04k
4.7µF
SW1 SW2
VOUT – V + 0.5V
VOUT + 0.5V –0.3V
IN
Step 2:
DC
DC ≅
V
FB
IN
C
IN
R
FAULT
100k
R
LT3581
FB
4.7µF
130k
FAULT
GATE
C
OUT2
4.7µF
V – 0.3V • DC
(
(
)
IN
SHDN
CLKOUT
LTYP
LMIN
LMAX
=
=
(1)
(2)
(3)
fOSC • 1A
RT
V
C
C
F
R
C
56pF
V – 0.3V • 2• DC – 1
)
(
)
SYNC
SS
10.5k
IN
R
T
C
SS
0.1µF
GND
C
C
43.2k
2.2A • fOSC • 1– DC
(
)
1nF
Step 3:
L1
3581 F05
V – 0.3V • DC
fOSC • 0.35A
(
)
IN
=
Figure 5. Boost Converter – The Component Values and Voltages
Given Are Typical Values for a 2MHz, 5V to 12V Boost
• Pick L1 out of a range of inductor values where the minimum
value of the range is set by L or L , whichever is higher.
TYP
MIN
The maximum value of the range is set by L
. See appendix
MAX
The LT3581 can be configured as a Boost converter as
in Figure 5. This topology allows for positive output volt-
ages that are higher than the input voltage. An external
PMOS (optional) driven by the GATE pin of the LT3581 can
achieve input or output disconnect during a fault event.
A single feedback resistor sets the output voltage. For
output voltages higher than 40V, see the Charge Pump
Aided Regulators section.
on how to choose current rating for inductor value chosen.
V –0.3V • DC
(
=
)
IN
Step 4:
RIPPLE
IRIPPLE
fOSC • L1
I
I
RIPPLE
2
Step 5:
OUT
IOUT = 3.3A –
• 1– DC
(
)
I
Step 6:
D1
VR > VOUT; IAVG > IOUT
COUT1 = COUT2
≥
Table 1 is a step-by-step set of equations to calculate
component values for the LT3581 when operating as a
boost converter. Input parameters are input and output
IOUT • DC
fOSC 0.01•VOUT – 0.50•IOUT • RDSON_PMOS
Step 7:
OUT1
OUT2
C
C
,
voltage, and switching frequency (V , V
and f
re-
IN OUT
OSC
• If PMOS is not used, then use just one capacitor where
= C + C
C
OUT
.
OUT2
spectively). Refer to the Appendix for further information
on the design equations presented in Table 1.
OUT1
CIN ≥ CVIN + CPWR
3.3A • DC
45• fOSC • 0.005• V
≥
IRIPPLE
8•fOSC •0.005• V
+
Step 8:
Variable Definitions:
IN
IN
C
IN
V = Input Voltage
OUT
DC = Power Switch Duty Cycle
• Refer to Input Capacitor Selection in Appendix for definition of
and C
IN
V
C
VIN
.
PWR
= Output Voltage
VOUT – 1.215V
83.3µA
Step 9:
FB
RFB
=
R
f
I
I
= Switching Frequency
OSC
OUT
= Maximum Average Output Current
87.6
fOSC
Step 10:
RT =
–1; fOSC inMHz andRT inkΩ
= Inductor Ripple Current
RIPPLE
R
T
R
= R
of External PMOS (set to 0 if not
DSON_PMOS
DSON
Only needed for input or output disconnect. See PMOS Selection
Step 11:
PMOS
using PMOS)
in the Appendix for information on sizing the PMOS, R
picking appropriae UVLO components.
and
GATE
Note 1: The maximum design target for peak switch current is 3.3A and is
used in this table.
Note 2: The final values for C
, C
and C may deviate from the
OUT1 OUT2 IN
above equations in order to obtain desired load transient performance.
3581fb
13
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LT3581
APPLICATIONS INFORMATION
SEPIC CONVERTER COMPONENT SELECTION
(COUPLED OR UN-COUPLED INDUCTORS)
Table 2. SEPIC Design Equations
PARAMETERS/EQUATIONS
Step 1: Pick V , V , and f
to calculate equations below.
IN OUT
OSC
C1
1µF
D1
30V, 2A
L1
3.3µH
Inputs
V
IN
3V TO 16V
V
OUT
5V
C
VOUT + 0.5V
C
OUT
IN
22µF
Step 2:
DC
DC ≅
22µF
L2
3.3µH
I
I
< 0.9A (V = 3V)
< 1.5A (V = 12V)
IN
OUT
OUT
IN
SW1 SW2
LT3581
×2
FB
45.3k
V + V + 0.5V –0.3V
IN
OUT
•
R
V
FB
V – 0.3V • DC
IN
(
)
IN
R
FAULT
LTYP
LMIN
LMAX
=
=
(1)
(2)
(3)
100k
fOSC • 1A
FAULT
SHDN
RT
GATE
ENABLE
CLKOUT
V – 0.3V • 2• DC – 1
(
)
(
)
IN
V
C
R
2.2A • fOSC • 1– DC
(
)
T
R
C
C
SS
124k
SYNC
SS
C
F
7.87k
C
1µF
100pF
GND
C
2.2nF
V – 0.3V • DC
fOSC • 0.35A
(
)
IN
=
Step 3:
L
3581 F06
• Pick L out of a range of inductor values where the minimum
value of the range is set by L or L , whichever is higher.
Figure 6. SEPIC Converter – The Component Values and Voltages
Given Are Typical Values for a 700kHz, Wide Input Range (3V to
16V) SEPIC Converter with 5V Out
TYP
MIN
The maximum value of the range is set by L
. See
MAX
Appendix on how to choose current rating for inductor value
chosen.
• Pick L1 = L2 = L for coupled inductors.
• Pick L1L2 = L for un-coupled inductors.
TheLT3581canalsobeconfiguredasaSEPICasshownin
Figure 6. This topology allows for positive output voltages
that are lower, equal, or higher than the input voltage. Out-
put disconnect is inherently built into the SEPIC topology,
meaning no DC path exists between the input and output
due to capacitor C1. This implies that a PMOS controlled
by the GATE pin is not required in the power path.
V –0.3V • DC
(
=
)
IN
IRIPPLE
fOSC • L
Step 4:
RIPPLE
I
• L = L1 = L2 for coupled inductors.
• L = L1L2 for un-coupled inductors.
I
RIPPLE
2
Step 5:
IOUT = 3.3A –
• 1– DC
(
)
I
OUT
Table 2 is a step-by-step set of equations to calculate
component values for the LT3581 when operating as a
SEPIC converter. Input parameters are input and output
Step 6:
D1
VR > V + VOUT; IAVG > IOUT
IN
Step 7:
C1
C1≥ 1µF; VRATING ≥ V
voltage, and switching frequency (V , V
and f
re-
IN
IN OUT
OSC
spectively). Refer to the Appendix for further information
on the design equations presented in Table 2.
IOUT • DC
fOSC • 0.005• VOUT
Step 8:
COUT
≥
C
OUT
Variable Definitions:
CIN ≥ CVIN + CPWR
≥
3.3A • DC
45• fOSC • 0.005• V
IRIPPLE
8•fOSC •0.005• V
V = Input Voltage
OUT
DC = Power Switch Duty Cycle
IN
V
+
Step 9:
IN
= Output Voltage
IN
IN
C
• Refer to Input Capacitor Selection in Appendix for definition
of C and C
.
f
I
I
= Switching Frequency
VIN
PWR
OSC
OUT
= Maximum Average Output Current
= Inductor Ripple Current
VOUT – 1.215V
83.3µA
Step 10:
RFB
=
R
FB
RIPPLE
87.6
fOSC
Step 11:
T
RT =
–1; fOSC inMHz andRT inkΩ
R
Note 1: The maximum design target for peak switch current is 3.3A and is
used in this table.
Note 2: The final values for C , C and C1 may deviate from the above
OUT IN
equations in order to obtain desired load transient performance.
3581fb
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14
LT3581
APPLICATIONS INFORMATION
DUAL INDUCTOR INVERTING CONVERTER COMPONENT
SELECTION (COUPLED OR UN-COUPLED INDUCTORS)
Table 3. Dual Inductor Inverting Design Equations
PARAMETERS/EQUATIONS
Step 1: Inputs Pick V , V , and f to calculate equations below.
C1
1µF
IN OUT
OSC
L1
3.3µH
L2
3.3µH
|VOUT | + 0.5V
V + |VOUT |+0.5V –0.3V
V
IN
5V
V
OUT
–12V
< 625mA
DC ≅
Step 2: DC
C
C
IN
3.3µF
OUT
4.7µF
D1
20V
1A
IN
I
OUT
SW1 SW2
LT3581
R
FB
143k
V – 0.3V • DC
(
(
)
IN
LTYP
LMIN
LMAX
=
=
(1)
(2)
(3)
V
FB
IN
fOSC • 1A
R
FAULT
100k
FAULT
SHDN
RT
V – 0.3V • 2• DC – 1
GATE
CLKOUT
)
(
)
IN
ENABLE
2.2A • fOSC • 1– DC
(
)
V
C
R
T
V – 0.3V • DC
fOSC • 0.35A
(
)
R
C
C
IN
SS
43.2k
SYNC
SS
C
F
=
11k
C
100nF
47pF
Step 3: L
GND
C
1nF
3581 F07
• Pick L out of a range of inductor values where the
minimum value of the range is set by L or L
,
MIN
TYP
whichever is higher. The maximum value of the range
Figure 7. Dual Inductor Inverting Converter – The Component
Values and Voltages Given Are Typical Values for a 2MHz, 5V to
–12V Inverting Topology Using Coupled Inductors
is set by L
. See Appendix on how to choose current
MAX
rating for inductor value chosen.
• Pick L1 = L2 = L for coupled inductors.
• Pick L1L2 = L for un-coupled inductors.
Due to its unique FB pin, the LT3581 can work in a Dual
Inductor Inverting configuration as in Figure 7. Changing
the connections of L2 and the Schottky diode in the SEPIC
topology results in generating negative output voltages.
This solution results in very low output voltage ripple
due to inductor L2 being in series with the output. Output
disconnect is inherently built into this topology due to the
capacitor C1.
V –0.3V • DC
(
=
)
IN
IRIPPLE
fOSC • L
Step 4: I
RIPPLE
• L = L1 = L2 for coupled inductors.
• L = L1L2 for un-coupled inductors.
I
RIPPLE
2
IOUT = 3.3A –
• 1– DC
(
)
Step 5: I
OUT
VR > V + |VOUT |; IAVG > IOUT
Step 6: D1
Step 7: C1
IN
Table 3 is a step-by-step set of equations to calculate
component values for the LT3581 when operating as a
dual inductor inverting converter. Input parameters are
C1≥ 1µF; VRATING ≥ V + |VOUT
|
IN
IRIPPLE
COUT
≥
Step 8: C
OUT
8 • fOSC 0.005• |V
|
(
)
OUT
input and output voltage, and switching frequency (V ,
IN
V
OUT
and f
respectively). Refer to the Appendix for
OSC
CIN ≥ CVIN + CPWR
3.3A • DC
≥
further information on the design equations presented
in Table 3.
IRIPPLE
8•fOSC •0.005• V
+
Step 9: C
IN
45• fOSC • 0.005• V
IN
IN
• Refer to Input Capacitor Selection in Appendix for
definition of C and C
Variable Definitions:
.
PWR
VIN
V = Input Voltage
OUT
DC = Power Switch Duty Cycle
IN
V
|VOUT | + 5mV
RFB
=
Step 10: R
Step 11: R
= Output Voltage
FB
83.3µA
87.6
fOSC
f
I
I
= Switching Frequency
OSC
OUT
RT =
–1; fOSC inMHz andRT inkΩ
T
= Maximum Average Output Current
= Inductor Ripple Current
RIPPLE
Note 1: The maximum design target for peak switch current is 3.3A and is
used in this table.
Note 2: The final values for C , C and C1 may deviate from the above
OUT IN
equations in order to obtain desired load transient performance.
3581fb
15
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LT3581
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov-
erning switch, diode D1, output capacitor C
, and
OUT1
General Layout Guidelines
groundreturnasshortaspossibletominimizeparasitic
inductive spikes at the switch node during switching.
• To optimize thermal performance, solder the exposed
ground pad of the LT3581 to the ground plane, with
multiple vias around the pad connecting to additional
ground planes.
• Agroundplaneshouldbeusedundertheswitchercircuitry
to prevent interplane coupling and overall noise.
SEPIC Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov-
erning switch, flying capacitor C1, diode D1, output
capacitor C , and ground return as short as possible
OUT
• High speed switching path (see specific topology for
more information) must be kept as short as possible.
tominimizeparasiticinductivespikesattheswitchnode
during switching.
• The V , FB, and RT components should be placed as
C
Inverting Topology Specific Layout Guidelines
close to the LT3581 as possible, while being as far
away as practically possible from the switch node. The
groundforthesecomponentsshouldbeseparatedfrom
the switch current path.
• Keep ground return path from the cathode of D1 (to
chip) separated from output capacitor C ’s ground
OUT
return path (to chip) in order to minimize switching
noise coupling into the output.
• Place the bypass capacitor for the V pin as close as
IN
• Keeplengthofloop(highspeedswitchingpath)govern-
ing switch, flying capacitor C1, diode D1, and ground
return as short as possible to minimize parasitic induc-
tive spikes at the switch node during switching.
possible to the LT3581.
• Place the bypass capacitor for the inductor as close as
possible to the inductor.
• The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
17
17
SHDN
SHDN
CLKOUT
CLKOUT
C
IN
C
IN
B
–
B
C
A
A
OUT
V
OUT
+
–
C
OUT1
–
–
V
IN
+
V
IN
+
V
M1
D1
OUT
C
OUT
D1
D2
L2
C1
L1
+
L1
3581 F09
R
GATE
3581 F08
A: RETURN C AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
IN
TO NOT COMBINE C AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
IN
A: RETURN C GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT
IN
COMBINE C GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN C
OUT
TO NOT COMBINE C
B: RETURN C
TO NOT COMBINE C
OUT
GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
OUT
IN
AND C
OUT
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
OUT1
AND C
OUT1
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED
PERFORMANCE.
Figure 8. Suggested Component Placement for Boost Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
Figure 9. Suggested Component Placement for SEPIC Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
3581fb
For more information www.linear.com/LT3581
16
LT3581
APPLICATIONS INFORMATION
the heat generated within the package. This can be
accomplished by taking advantage of the thermal pad on
the underside of the IC. It is recommended that multiple
vias in the printed circuit board be used to conduct heat
away from the IC and into a copper plane with as much
area as possible.
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
17
SHDN
CLKOUT
C
IN
Power and Thermal Calculations
A
C
B
–
IN
+
Power dissipation in the LT3581 chip comes from four
V
2
GND
primary sources: switch I R losses, switch dynamic
C1
C
OUT
losses, NPN base drive DC losses, and miscellaneous
input current losses. These formulas assume continuous
modeoperation,sotheyshouldnotbeusedforcalculating
thermal losses or efficiency in discontinuous mode or at
light load currents.
D1
– V
OUT
L1
L2
3581 F10
A: RETURN C GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
IN
TO NOT COMBINE C GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
IN
B: RETURN C
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
OUT
TO NOT COMBINE C
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
OUT
C: RETURN D1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR
IMPROVED PERFORMANCE.
The following example calculates the power dissipa-
tion in the LT3581 for a particular boost application
(V =5V,V =12V,I =0.83A,f =2MHz,V =0.45V,
Figure 10. Suggested Component Placement for Dual Inductor
Inverting Topology (MSOP Shown, DFN Similar, Not to Scale.)
Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which
Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
IN
CESAT
OUT
= 0.21V).
OUT
OSC
D
V
To calculate die junction temperature, use the appropriate
thermalresistancenumberandaddinworst-caseambient
temperature:
THERMAL CONSIDERATIONS
Overview
T = T + θ • P
TOTAL
J
A
JA
For the LT3581 to deliver its full output power, it is imp-
erative that a good thermal path be provided to dissipate
Table 4. Power Calculations Example for Boost Converter with VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz, VD = 0.45V, VCESAT = 0.21V
DEFINITION OF VARIABLES
EQUATIONS
DESIGN EXAMPLE
VALUE
DC = SWITCH DUTY CYCLE
DC = 60.9%
VOUT – V + VD
VOUT + VD – VCESAT
12V –5V + 0.45V
12V + 0.45V –0.21V
IN
DC =
DC =
I
= Average Switch Current
I
= 2.3A
IN
IN
VOUT • IOUT
12V • 0.83A
5V • 0.88
I
=
I =
IN
IN
η = Power Conversion Efficiency
V • η
IN
(typically 88% at high currents)
2
P
R
= Switch I R Loss (DC)
P
P
= 290mW
SWDC
SWDC
2
PSWDC = DC • I • RSW
PSWDC = 0.609 • (2.3A)2 • 90mΩ
= Switch Resistance (typically
90mΩ combined SW1 and SW2)
IN
SW
P
= Switch Dynamic Loss (AC)
= 718mW
= 156mW
SWAC
SWAC
PSWAC = 13ns • I • V
• fOSC
PSWAC = 13ns • 2.3A • 12V • 2MHz
IN
OUT
P
= Base Drive Loss (DC)
= Input Power Loss
P
BDC
BDC
V • I • DC
5V • 2.3A • 0.609
IN IN
P
=
P
=
BDC
BDC
45
45
P
P
= 45mW
P
= 9mA • V
P = 9mA • 5V
INP
INP
INP
INP
IN
P
= 1.209W
TOTAL
3581fb
17
For more information www.linear.com/LT3581
LT3581
APPLICATIONS INFORMATION
where T = Die Junction Temperature, T = Ambient Tem-
Thermal Lockout
J
A
perature, P
is the final result from the calculations
TOTAL
Afaultconditionoccurswhenthedietemperatureexceeds
165°C (see Operation Section), and the part goes into
thermal lockout. The fault condition ceases when the die
temperature drops by ~5°C (nominal).
shown in Table 4, and θ is the thermal resistance from
JA
the silicon junction to the ambient air.
The published (http://www.linear.com/designtools/pack-
aging/Linear_Technology_Thermal_Resistance_Table.
pdf) θ value is 43°C/W for the 4mm × 3mm 14-pin DFN
JA
SWITCHING FREQUENCY
package and 45°C/W for the 16-lead MSOP package. In
There are several considerations in selecting the operat-
ing frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz and in
that case a 1.5MHz switching converter frequency may be
employed. The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The tradeoff is efficiency, since the losses due to switch-
ing dynamics (see Thermal Considerations), Schottky
diode charge, and other capacitive loss terms increase
proportionally with frequency.
practice, lower θ values are realizable if board layout is
JA
performedwithappropriategrounding(accountingforheat
sinking properties of the board) and other considerations
listed in the Layout Guidelines section. For instance, a
θ
value of ~24°C/W was consistently achieved for both
JA
MSE and DFN packages of the LT3581 (at V = 5V, V
=
IN
OUT
12V, I
= 0.83A, f
= 2MHz) when board layout was
OUT
OSC
optimized as per the suggestions in the Board Layout
Guidelines section.
Junction Temperature Measurement
The duty cycle of the CLKOUT signal is linearly propor-
tionaltodiejunctiontemperature, T . Togetatemperature
J
reading, measure the duty cycle of the CLKOUT signal and
use the following equation to approximate the junction
temperature:
Oscillator Timing Resistor (R )
T
DCCLKOUT –35%
The operating frequency of the LT3581 can be set by the
internalfree-runningoscillator.WhentheSYNCpinisdriven
low (< 0.4V), the frequency of operation is set by a resistor
TJ =
0.3%
where DC
is the CLKOUT duty cycle in % and T
J
CLKOUT
from the R pin to ground. An internally trimmed timing
T
is the die junction temperature in °C. Although the actual
die temperature can deviate from the above equation by
15°C, the relationship between change in CLKOUT duty
cycle and change in die temperature is well defined. Basi-
cally a 1% change in CLKOUT duty cycle corresponds to a
3.33°C change in die temperature. Note that the CLKOUT
pin is only meant to drive capacitive loads up to 50pF.
capacitor resides inside the IC. The oscillator frequency
is calculated using the following formula:
87.6
RT + 1
fOSC
=
where f
is in MHz and R is in k. Conversely, R (in k)
OSC
T
T
can be calculated from the desired frequency (in MHz)
using:
87.6
fOSC
RT =
–1
3581fb
For more information www.linear.com/LT3581
18
LT3581
APPLICATIONS INFORMATION
Clock Synchronization
2.2µF
1.5µH
V
–12V
OUT
450mA
143k
The operating frequency of the LT3581 can be set by an
external source by simply providing a digital clock signal
4.7µF
SW1
GATE
SW2
FB
into the SYNC pin (R resistor still required). The LT3581
V
CLKOUT
T
IN
LT3581
will revert to its internal free-running oscillator clock (set
SLAVE
SHDN
FAULT
RT
V
C
by the R resistor) when the SYNC pin is driven below
T
100pF
10k
2.2nF
SS
0.1µF
0.4V for a few free-running clock periods.
GND
SYNC
43.2k
Driving SYNC high for an extended period of time effec-
tively stops the operating clock and prevents latch SR1
from becoming set (see Block Diagram). As a result, the
switchingoperationoftheLT3581willstopandtheCLKOUT
pin will be held at ground.
1.5µH
V
OUT
12V
830mA
V
5V
IN
6.8µF
GATE
4.7µF
6.8µF
10k
130k
SW1 SW2
CLKOUT
V
FB
IN
LT3581
MASTER
The duty cycle of the SYNC signal must be between 20%
and 80% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
100k
FAULT
SHDN
RT
V
C
10.5k
1nF
ENABLE
SS
0.1µF
56pF
GND
SYNC
43.2k
(1) SYNC may not toggle outside the frequency range of
200kHz to 2.5MHz unless it is stopped low (below
0.4V) to enable the free-running oscillator.
3581 F11
Figure 11. A Single Inductor Inverting Topology Is Synchronized
with a Boost Regulator to Generate –12V and 12V Outputs. The
External PMOS Helps Disconnect the Input from the Power Paths
During Fault Events
(2) The SYNC frequency can always be higher than the
free-running oscillator frequency (as set by the R
T
resistor), f , but should not be less than 25%
OSC
Also, the FAULT pins can be tied together so that a fault
condition from one LT3581 causes all of the LT3581s to
enter fault, until the fault condition disappears.
below f
.
OSC
CLOCK SYNCHRONIZATION OF ADDITIONAL
REGULATORS
CHARGE PUMP AIDED REGULATORS
The CLKOUT pin of the LT3581 can be used to synchronize
one or more other compatible switching regulator ICs as
shown in Figure 11.
Designing charge pumps with the LT3581 can offer ef-
ficient solutions with fewer components than traditional
circuits because of the master/slave switch configuration
on the IC. Although the slave switch, SW2, operates in
phase with the master switch, SW1, it is only the current
through the master switch (SW1) that is sensed by the
current comparator (A4 in Block Diagram) as part of the
current feedback loop. This method of operation by the
master/slave switches can offer the following benefits to
charge pump designs:
The frequency of the master LT3581 is set by the external
R resistor. The SYNC pin of the slave LT3581 is driven
T
by the CLKOUT pin of the master LT3581. Note that the
RT pin of the slave LT3581 must have a resistor tied to
ground. It takes a few clock cycles for the CLKOUT signal
to begin oscillating, and it’s preferable for all LT3581s to
have the same internal free-running frequency. Therefore,
in general, use the same value R resistor for all of the
T
synchronized LT3581s.
3581fb
19
For more information www.linear.com/LT3581
LT3581
APPLICATIONS INFORMATION
V
97V
140mA
OUT2
• The slave switch, by not performing a current sense
operationlikethemasterswitch, cansustainfairlylarge
current spikes when the flying capacitors charge up.
Since this current spike flows through SW2, it does
not affect the operation of the current comparator (A4
in Block Diagram).
2.2µF
2.2µF
2.2µF
2.2µF
V
65V
OUT1
70mA
• The master switch, immune from the capacitor current
spike (seen only by the slave switch) can sense the
inductor current more accurately.
V
12V
IN
10µH
2.2µF
2.2µF
SW1 SW2
8.06k
• Since the slave switch can sustain large current spikes,
thediodesthatfeedcurrentintotheflyingcapacitorsdo
not need current limiting resistors, leading to efficiency
and thermal improvements.
V
FB
IN
100k
370k
FAULT
SHDN
RT
GATE
2.2µF
CLKOUT
V
LT3581
C
24k
1nF
SYNC
SS
100pF
GND
43.2k
High V
Charge Pump Topology
OUT
0.47µF
3581 F12
The LT3581 can be used in a charge-pump topology as
shown in Figure 12, multiplying the output of an inductive
boost converter. The master switch (SW1) can be used to
drive the inductive boost converter (first stage of charge
pump), while the slave switch (SW2) can be used to drive
one or more other charge pump stages. This topology is
useful for high voltage applications including VFD bias
supplies.
Figure 12. High VOUT Charge Pump Topology Can Be Used to
Build VFD Bias Supplies
C1
D1
D3
L1
V
OUT
< 0V
V
C
IN
AND |V | > |V
|
IN
OUT
D2
C
OUT
IN
R
FB
SW1
GATE
SW2
FB
V
CLKOUT
LT3581
Single Inductor Inverting Topology
IN
100k
FAULT
SHDN
RT
V
C
If there is a need to use just one inductor to generate a
negative output voltage whose magnitude is greater than
V ,thesingleinductorinvertingtopology(showninFigure
IN
ENABLE
R
SS
VC
C
VC2
C
SS
GND
SYNC
C
VC1
R
T
13) can be used. Since the master and slave switches are
isolated by a Schottky diode, the current spike through C1
willflowonlythroughtheslaveswitch, therebypreventing
the current comparator, (A4 in the Block Diagram), from
falsely tripping. Output disconnect is inherently built into
the single inductor topology.
3579 F13
Figure 13. Single Inductor Inverting Topology
3581fb
For more information www.linear.com/LT3581
20
LT3581
APPLICATIONS INFORMATION
HOT-PLUG
capacitor to the output. An 18Ω resistive load was used
and a 2.2µF capacitor was placed on SS. Figure 14 shows
theresultsofhot-pluggingthisre-configuredcircuit.Notice
how the inductor current is well behaved.
The high inrush current associated with hot-plugging V
IN
canbelargelyrejectedwiththeuseofanexternalPMOS. A
simple hot-plug controller can be designed by connecting
an external PMOS in series with V , with the gate of the
IN
V
IN
PMOS being driven by the GATE pin of the LT3581. Since
the GATE pin pull-down current is linearly proportional to
theSSvoltage,andtheSSchargeuptimeisrelativelyslow,
the GATE pin pull-down current will increase gradually,
thereby turning on the external PMOS slowly. Controlled
in this manner, the PMOS acts as an input current limiter
5V/DIV
V
OUT
10V/DIV
I
L
5A/DIV
SS
1V/DIV
when V hot-plugs or ramps up sharply.
IN
3581 F14
1s/DIV
Likewise, when the PMOS is connected in series with the
output, inrush currents into the output capacitor can be
limitedduringahot-plugevent.Toillustratethis,thecircuit
in Figure 18 was re-configured by adding a large 1500µF
Figure 14. Inrush Current Is Well Controlled in Spite Of Hot-
Plugging the Re-configured Boost Converter in Figure 18
3581fb
21
For more information www.linear.com/LT3581
LT3581
APPENDIX
SETTING THE OUTPUT VOLTAGE
For the SEPIC or Dual Inductor Inverting topology (see
Figures 6 and 7):
The output voltage is set by connecting a resistor (R )
FB
from V
to the FB pin. R is determined by using the
VD + |VOUT
|
OUT
FB
DCSEPIC_&_INVERT
≅
following equation:
V + |V | + VD − V
IN
OUT
CESAT
|VOUT – V |
FB
For the Single Inductor Inverting topology (see Figure 13):
|VOUT |−V + V + 3• VD
RFB =
83.3µA
IN
CESAT
DCSI_INVERT
=
where V is 1.215V (typical) for non-inverting topologies
FB
|VOUT | + 3• VD
(i.e. boost and SEPIC regulators) and 5mV (typical) for
inverting topologies.
The LT3581 can be used in configurations where the duty
cycle is higher than DC , but it must be operated in
MAX
POWER SWITCH DUTY CYCLE
the discontinuous conduction mode so that the effective
duty cycle is reduced.
In order to maintain loop stability and deliver adequate
current to the load, the power NPNs (Q1 and Q2 in the
BlockDiagram)cannotremain“on”for100%ofeachclock
cycle. The maximum allowable duty cycle is given by:
INDUCTOR SELECTION
General Guidelines: The high frequency operation of the
LT3581allowsfortheuseofsmallsurfacemountinductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. Also
toimproveefficiency, chooseinductorswithmorevolume
for a given inductance. The inductor should have low
T –MinOffTime
(
)
•100%
P
DCMAX
=
TP
where T is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 60ns.
P
2
DCR (copper-wire resistance) to reduce I R losses, and
Conversely, the power NPNs (Q1 and Q2 in the Block Dia-
gram) cannot remain “off” for 100% of each clock cycle,
andwillturnonforaminimumontime(MinOnTime)when
in regulation. This MinOnTime governs the minimum al-
lowable duty cycle given by:
must be able to handle the peak inductor current without
saturating. Note that in some applications, the current
handling requirements of the inductor can be lower, such
as in the SEPIC topology where each inductor only carries
one half of the total switch current. Molded chokes or chip
inductorsusuallydonothaveenoughcoreareatosupport
peak inductor currents in the 2A to 6A range. To minimize
radiated noise, use a toroidal or shielded inductor. See
Table 5 for a list of inductor manufacturers.
MinOnTime
(
)
•100%
DCMIN
=
TP
Where T is the clock period and MinOnTime (found in
P
the Electrical Characteristics) is typically 100ns.
Table 5. Inductor Manufacturers
Theapplicationshouldbedesignedsuchthattheoperating
Sumida
CDR6D28MN and CDR7D28MN
Series
www.sumida.com
www.coilcraft.com
duty cycle is between DC
and DC
.
MIN
MAX
Dutycycleequationsforseveralcommontopologiesaregiven
belowwhereV isthediodeforwardvoltagedropandV
Coilcraft
Vishay
MSD7342 Series
D
CESAT
IHLP-1616BZ-01, IHLP-2020BZ-01 www.vishay.com
and IHLP-2525CZ-01 Series
is the collector to emitter saturation voltage of the switch.
, with SW1 and SW2 tied together, is typically 250mV
Taiyo Yuden NR Series
www.t-yuden.com
www.we-online.com
www.tdk.com
V
CESAT
when the combined switch current (I
+ I ) is 2.75A.
SW1 SW2
Wurth
TDK
WE-PD Series
VLF, SLF and RLF Series
For the boost topology (see Figure 5):
VOUT – V + VD
VOUT + VD – VCESAT
IN
DCBOOST
≅
3581fb
For more information www.linear.com/LT3581
22
LT3581
APPENDIX
Minimum Inductance
Negative values of L
or L
indicate that the out-
BOOST
DUAL
put load current, I , exceeds the switch current limit
OUT
Although there can be a tradeoff with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditions that limit the minimum inductance: (1) provid-
ing adequate load current, (2) avoidance of subharmonic
oscillations and (3) supplying a minimum ripple current
to avoid false tripping of the current comparator.
capability of the LT3581.
Avoiding Sub-Harmonic Oscillations
The LT3581’s internal slope compensation circuit will
prevent sub-harmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the
inductance exceeds a certain minimum value. In applica-
tions that operate with duty cycles greater than 50%, the
inductance must be at least:
Adequate Load Current
Smallvalueinductorsresultinincreasedripplecurrentsand
thus, due to the limited peak switch current, decrease the
average current that can be provided to the load. In order
to provide adequate load current, L should be at least:
V − V
• 2• DC− 1
(
)
)
(
=
IN
CESAT
LMIN
2.2A• fOSC • 1− DC
(
)
where:
DC• V − V
(
)
IN
CESAT
LBOOST
>
L
L
= L for Boost Topologies (see Figure 5)
MIN
MIN
1
Boost
|VOUT |• IOUT
= L = L for Coupled Dual Inductor
2• fOSC• IPK
−
1
2
Topology
V • η
IN
Topologies (see Figures 6 and 7)
L
MIN
= L || L for Uncoupled Dual Inductor
or
1
2
Topologies (see Figures 6 and 7)
SEPIC
or
Inverting
Topologies
DC• V − V
(
)
IN
CESAT
LDUAL
>
|VOUT|• IOUT
Maximum Inductance
2•fOSC• IPK−
−IOUT
V • η
IN
Excessive inductance can reduce ripple current to levels
thataredifficultforthecurrentcomparator(A4intheBlock
Diagram) to cleanly discriminate, causing duty cycle jitter
and/or poor regulation. The maximum inductance can be
calculated by:
where:
L
L
= L for Boost Topologies (see Figure 5)
1
BOOST
DUAL
= L = L for Coupled Dual Inductor
1
2
Topologies (see Figures 6 and 7)
V − V
DC
fOSC
IN
CESAT
LMAX
=
•
L
DUAL
= L || L for Uncoupled Dual Inductor
1
2
350mA
Topologies (see Figures 6 and 7)
= SwitchDutyCycle(seePowerSwitchDuty
Cycle section in Appendix)
= Maximum Peak Switch Current; should not
exceed 3.3A for a combined SW1 + SW2
current, or 1.9A of SW1 current if SW1 is
being used by itself.
= Power Conversion Efficiency (typically 88%
for Boost and 75% for Dual Inductor
Topologies at High Currents)
where:
DC
L
L
= L for Boost Topologies (see Figure 5)
1
MAX
MAX
I
PK
= L = L for Coupled Dual Inductor
1
2
Topologies (see Figures 6 and 7)
= L || L for Uncoupled Dual Inductor
L
MAX
1
2
Topologies (see Figures 6 and 7)
η
f
I
= Switching Frequency
= Maximum Output Current
OSC
OUT
3581fb
23
For more information www.linear.com/LT3581
LT3581
APPENDIX
Inductor Current Rating
Multilayer ceramic capacitors are an excellent choice, as
they have extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
these materials retain their capacitance over wide voltage
and temperature ranges. A 10μF to 22μF output capacitor
is sufficient for most applications, but systems with very
low output currents may need only 2.2μF to 10μF. Always
use a capacitor with a sufficient voltage rating. Many
ceramic capacitors, particularly 0805 or 0603 case sizes,
have greatly reduced capacitance at the desired output
voltage. Tantalum Polymer or OS-CON capacitors can be
used, but it is likely that these capacitors will occupy more
board area than a ceramic, and will have higher ESR with
greater output ripple.
Inductors must have a rating greater than their peak
operating current, or else they could saturate and hence
contribute to losses in efficiency. The maximum inductor
current(consideringstart-upandsteady-stateconditions)
is given by:
V • T
IN
MIN_PROP
IL _PEAK = ILIM
where:
+
L
I
= Peak Inductor Current in L for a Boost
L_PEAK
1
Topology, or the Peak of the sum of the
Inductor Currents in L1 and L2 for Dual
Inductor Topologies.
I
**
= 3.3A with SW1 and SW2 Tied Together,
or 1.9A with just SW1 (This assumes
usage of an inductor whose core
material soft-saturates such as
powdered iron core).
= 100ns (Propagation Delay through the
Current Feedback Loop).
LIM
INPUT CAPACITOR SELECTION
Ceramic capacitors make a good choice for the input
decoupling capacitor, and should be placed such that it is
in close proximity to the V of the chip as well as to the
IN
T
MIN_PROP
inductor connected to the input of the power path. If it is
not possible to optimally place a single input capacitor,
then use two separate capacitors—use one at the V of
IN
**If using an inductor whose core material saturates
the chip (see equation for C in Tables 1, 2 and 3) and
VIN
hard (e.g., ferrite), then pick I to be 5.4A with SW1
LIM
one at the input to the power path (see equation for C
PWR
and SW2 tied together, or 3A when just SW1 is used.
in Tables 1, 2 and 3) A 4.7μF to 20μF input capacitor is
Note that these equations offer conservative results for
the required inductor current ratings. The current ratings
could be lower for applications with light loads, if the SS
capacitor is sized appropriately to limit inductor currents
at start-up.
sufficient for most applications.
Table 6 shows a list of several ceramic capacitor man-
ufacturers. Consult the manufacturers for detailed infor-
mation on their entire selection of ceramic parts.
Table 6: Ceramic Capacitor Manufacturers
DIODE SELECTION
AVX
www.avxcorp.com
www.murata.com
www.t-yuden.com
Schottky diodes, with their low forward voltage drops and
fast switching speeds, are recommended for use with the
LT3581.ChooseaSchottkydiodewithlowparasiticcapaci-
tance to reduce reverse current spikes through the power
switch of the LT3581. The Central Semiconductor Corp.
CMMSH2-40diodeisaverygoodchoicewitha40Vreverse
voltage rating and an average forward current of 2A.
Murata
Taiyo Yuden
PMOS SELECTION
An external PMOS, controlled by the LT3581’s GATE pin,
can be used to facilitate input or output disconnect. The
GATE pin turns on the PMOS gradually during start-up
(seeSoft-StartofExternalPMOSintheOperationsection),
and turns the PMOS off when the LT3581 is in shutdown
or in fault.
OUTPUT CAPACITOR SELECTION
Low ESR (equivalent series resistance) capacitors should
beusedattheoutputtominimizetheoutputripplevoltage.
3581fb
For more information www.linear.com/LT3581
24
LT3581
APPENDIX
The use of the external PMOS, controlled by the GATE pin,
is particularly beneficial when dealing with unintended
output shorts in a boost regulator. In a conventional boost
regulator,theinductor,Schottkydiode,andpowerswitches
are susceptible to damage in the event of an output short
toground.UsinganexternalPMOSintheboostregulator’s
event of hard shorts. The resistor divider from V to the
IN
SHDN pin sets a UVLO of 4V for this application.
ConnectingthePMOSinserieswiththeoutputofferscertain
advantages over connecting it in series with the input:
• Since the load current is always less than the input
current for a boost converter, the current rating of the
PMOS goes down.
powerpath(pathfromV toV )controlledbytheGATE
IN
OUT
pin, will serve to disconnect the input from the output
when the output has a short to ground, thereby helping
save the IC, and the other components in the power path
fromdamage. Ensurethatboth, thediodeandtheinductor
can survive low duty cycle current pulses of 3 to 4 times
their steady state levels.
• A PMOS in series with the output can be biased with
a higher overdrive voltage than a PMOS used in series
with the input, since V
> V . This higher overdrive
OUT
IN
results in a lower R
rating for the PMOS, thereby
DSON
improving the efficiency of the regulator.
The PMOS chosen must be capable of handling the maxi-
mum input or output current depending on whether the
PMOS is used at the input (see Figure 11) or the output
(see Figure 18).
In contrast, an input connected PMOS works as a simple
hot-plug controller (covered in more detail in the Hot-Plug
section). The input connected PMOS also functions as an
inexpensive means of protecting against multiple output
shorts in boost applications that synchronize the LT3581
with other compatible ICs (see Figure 11).
Ensure that the PMOS is biased with enough source to
gate voltage (V ) to enhance the device into the triode
SG
mode of operation. The higher the V voltage that biases
SG
Table 7 shows a list of several discrete PMOS manufa-
cturers.Consultthemanufacturersfordetailedinformation
on their entire selection of PMOS devices.
the PMOS into triode, the lower the R
of the PMOS,
DSON
thereby lowering power dissipation in the device during
normal operation, as well as improving the efficiency of
the application in which the PMOS is used. The follow-
Table 7. Discrete PMOS Manufacturers
Vishay
www.vishay.com
ing equations show the relationship between R
(see
GATE
Fairchild Semiconductor
www.fairchildsemi.com
Block Diagram) and the desired V that the PMOS is
SG
biased with:
COMPENSATION – ADJUSTMENT
RGATE
+ 2kΩ
V
if VGATE < 2V
IN
To compensate the feedback loop of the LT3581, a series
resistor-capacitor network in parallel with an optional
single capacitor should be connected from the V pin to
R
VSG
=
GATE
933µA•RGATE if VGATE ≥ 2V
C
GND. For most applications, choose a series capacitor in
the range of 1nF to 10nF with 2.2nF being a good starting
value.Theoptionalparallelcapacitorshouldrangeinvalue
from 47pF to 160pF with 100pF being a good starting
WhenusingaPMOS,itisadvisabletoconfigurethespecific
application for undervoltage lockout (see the Operations
section). The goal is to have V get to a certain minimum
IN
voltage where the PMOS has sufficient headroom to attain
value. The compensation resistor, R , is usually in the
C
range of 5k to 50k with 10k being a good starting value.
A good technique to compensate a new application is to
a high enough V , which prevents it from entering the
SG
saturation mode of operation during start-up.
usea100kpotentiometerinplaceoftheseriesresistorR .
C
Figure 18 shows the PMOS connected in series with the
output to act as an output disconnect during a fault con-
dition. The Schottky diode from the V pin to the GATE
pin is optional and helps turn off the PMOS quicker in the
With the series and parallel capacitors at 2.2nF and 100pF
respectively, adjust the potentiometer while observing the
IN
transient response and the optimum value for R can be
C
3581fb
25
For more information www.linear.com/LT3581
LT3581
APPENDIX
found. Figures 15a to 15c illustrate this process for the
circuit of Figure 18 with a load current stepped between
540mA and 800mA. Figure 15a shows the transient re-
COMPENSATION – THEORY
Likeallothercurrentmodeswitchingregulators,theLT3581
needs to be compensated for stable and efficient operation.
Two feedback loops are used in the LT3581: a fast current
loop which does not require compensation, and a slower
voltageloopwhichdoes.StandardBodeplotanalysiscanbe
used to understand and adjust the voltage feedback loop.
sponse with R equal to 1k. The phase margin is poor as
C
evidenced by the excessive ringing in the output voltage
and inductor current. In Figure 15b, the value of R is
C
increasedto3k,whichresultsinamoredampedresponse.
Figure 15c shows the results when R is increased further
C
to 10.5k. The transient response is nicely damped and the
As with any feedback loop, identifying the gain and
phase contribution of the various elements in the loop
is critical. Figure 16 shows the key equivalent elements
of a boost converter. Because of the fast current control
loop, the power stage of the IC, inductor and diode
have been replaced by a combination of the equivalent
compensation procedure is complete.
V
OUT
AC-COUPLED
500mV/DIV
transconductanceamplifierg andthecurrentcontrolled
current source (which converts I to ηV /V
mp
I
L
1A/DIV
• I ).
IN OUT VIN
VIN
g
VIN
acts as a current source where the peak input current,
mp
I
, is proportional to the V voltage. η is the efficiency
C
3581 F15a
50µs/DIV
of the switching regulator and is typically about 80%.
Figure 15a. Transient Response Shows Excessive Ringing
Note that the maximum output currents of the g and
mp
g
stages are finite. The output of the g stage is
ma
mp
limitedbytheminimumswitchcurrentlimit(seeElectrical
V
OUT
Specifications)andtheoutputoftheg stageisnominally
ma
AC-COUPLED
500mV/DIV
limited to about 12μA.
–
I
L
1A/DIV
V
OUT
g
mp
I
VIN
η
V
IN
+
•
I
R
R
L
•
VIN
ESR
V
OUT
3581 F15b
C
50µs/DIV
OUT
1.215V
REFERENCE
C
R1
PL
Figure 15b. Transient Response is Better
+
V
C
g
R2
R2
ma
C
FB
F
R
R
O
C
–
V
OUT
C
AC-COUPLED
500mV/DIV
C
3581 F16
C : COMPENSATION CAPACITOR
C
I
L
C
C
: OUTPUT CAPACITOR
: PHASE LEAD CAPACITOR
OUT
PL
1A/DIV
C : HIGH FREQUENCY FILTER CAPACITOR
F
ma
mp
g
g
: TRANSCONDUCTOR AMPLIFIER INSIDE IC
: POWER STAGE TRANSCONDUCTANCE AMPLIFIER
3581 F15c
R : COMPENSATION RESISTOR
50µs/DIV
C
R : OUTPUT RESISTANCE DEFINED AS V /I
L
OUT LOAD(MAX)
R : OUTPUT RESISTANCE OF g
O
ma
Figure 15c. Transient Response is Well Damped
R1, R2; FEEDBACK RESISTOR DIVIDER NETWORK
: OUTPUT CAPACITOR ESR
R
ESR
Figure 16. Boost Converter Equivalent Model
3581fb
For more information www.linear.com/LT3581
26
LT3581
APPENDIX
From Figure 16, the DC gain, poles and zeros can be
calculated as follows:
UsingthecircuitinFigure18asanexample, Table8shows
the parameters used to generate the Bode plot shown in
Figure 17.
DC Gain:
Table 8. Bode Plot Parameters
(Breaking loop at FB pin)
PARAMETER
VALUE
14.5
9.4
UNITS
Ω
COMMENT
Application Specific
Application Specific
Application Specific
Not Adjustable
Adjustable
∂VC ∂IVIN ∂VOUT ∂V
R
FB
L
ADC = AOL(0)=
•
•
•
=
C
µF
∂V
∂VC ∂IVIN ∂VOUT
OUT
FB
R
R
1
mΩ
kΩ
pF
ESR
O
V
VOUT
RL
2
0.5R2
R1+ 0.5R2
IN
305
1000
56
g •R • gmp • η•
•
•
(
)
ma
O
C
C
C
C
pF
Optional/Adjustable
Optional/Adjustable
Adjustable
2
F
Output Pole:P1=
0
pF
PL
2• π •RL •COUT
R
10.5
130
14.6
1.215
12
kΩ
kΩ
kΩ
V
C
1
R1
R2
V
Adjustable
Error AmpPole:P2 =
Error Amp Zero: Z1=
ESR Zero: Z2 =
2• π • R + R •C
C
O
C
Not Adjustable
Not Adjustable
Application Specific
Application Specific
Not Adjustable
Not Adjustable
Application Specific
Adjustable
1
REF
V
V
g
V
OUT
IN
2• π •RC •CC
5
V
1
270
15.1
1.5
µmho
mho
µH
ma
mp
2• π •RESR •COUT
g
L
V
2 •RL
IN
RHP Zero: Z3 =
f
2
MHz
OSC
2• π • VOUT2 •L
From Figure 17, the phase is –130° when the gain reaches
0dBgivingaphasemarginof50°.Thecrossoverfrequency
is 17kHz, which is more than three times lower than the
frequency of the RHP zero Z3 to achieve adequate phase
margin.
fS
3
HighFrequency Pole:P3>
1
PhaseLead Zero: Z4 =
2• π •R1•CPL
1
170
150
130
110
0
PhaseLeadPole:P4 =
R2
2
–40
R1•
PHASE
–80
2• π •
•CPL
R2
R1+
2
–120
–160
–180
–200
–240
–280
–320
–360
90
70
Error AmpFilter Pole:
50
30
1
CC
,CF <
10
P5 =
GAIN
RC •RO
RC + RO
10
2• π •
•CF
–10
–30
10
100
1k
10k
100k
1M
The current mode zero (Z3) is a right half plane zero which
can be an issue in feedback control design, but is manage-
able with proper external component selection.
FREQUENCY (Hz)
3851 F17
Figure 17. Bode Plot for Example Boost Converter
3581fb
27
For more information www.linear.com/LT3581
LT3581
TYPICAL APPLICATIONS
L1
1.5µH
D1
FB
V
M1
OUT
V
IN
12V
5V
C2
4.7µF
830mA
SW1 SW2
6.04k
18.7k
V
IN
D2
130k
100k
FAULT
GATE
V
IN
C1
4.7µF
C3
4.7µF
SHDN
RT
CLKOUT
V
LT3581
C
10k
56pF
SYNC
SS
10.5k
1nF
43.2k
GND
0.1µF
3581 F18
C1: 4.7µF, 16V, X7R, 1206
D2: VISHAY MSS2P3
L1: SUMIDA CDR6D28MN-IR5
C2, C3: 4.7µF, 25V, X7R, 1206
D1: DIODES INC. PD3S230H-7 M1: VISHAY SILICONIX SI7123DN
Figure 18. 2MHz, 5V to 12V, 830mA Boost Converter with Output Short Circuit Protection
Transient Response with 430mA to 830mA to 430mA Load Step Switching Waveforms with 830mA Load
V
OUT
AC-COUPLED
200mV/DIV
V
OUT
AC-COUPLED
1V/DIV
I
L
1A/DIV
I
L
1A/DIV
V
SW
0.5A/DIV
LOAD
0.5A/DIV
V
CLKOUT
(BW LIMIT)
2V/DIV
3581 TA02a
3581 TA02b
50µs/DIV
500ns/DIV
2MHz, 5V, 1.1A Boost Converter Operates from an Input Range of 2.8V to 4.2V
L1
D1
Efficiency and Power Loss at VIN = 3.3V
0.68µH
V
OUT
V
IN
5V
90
85
80
75
70
65
60
55
50
2000
2.8V TO 4.2V
1.1A
1800
1600
1400
1200
1000
800
SW1 SW2
FB
V
IN
C1
3.3µF
C2
45.3k
68pF
LT3581
22µF
100k
FAULT
GATE
SHDN
CLKOUT
RT
V
C
6.98k
SYNC
SS
600
43.2k
GND
0.1µF
400
1.5nF
200
3581 TA03a
0
C1: 3.3µF, 16V, X7R, 1206
C2: 22µF, 16V, X7R, 1210
D1: DIODES INC. PD3S230H-7
L1: VISHAY IHLP1616 BZ-01-OR68 (ONLY 4.1mm × 4.5mm × 2mm)
0
200
600
800 1000 1200
400
LOAD CURRENT (mA)
3581 TA03b
3581fb
For more information www.linear.com/LT3581
28
LT3581
TYPICAL APPLICATIONS
High Efficiency, VFD (Vacuum Fluorescent Display) Power Supply Switches at 2MHz to Avoid AM Band
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
V
OUT2
D6
97V
90mA (V = 9V)
C7
IN
140mA (V = 12V)
IN
2.2µF
D5
D4
180mA (V = 16V)
IN
C5
2.2µF
V
OUT1
65V
60mA (V = 9V)
C6
2.2µF
IN
70mA (V = 12V)
IN
D3
90mA (V = 16V)
IN
C4
2.2µF
D7
D2
L1
10µH
D1
M1*
V
IN
9V TO 16V
C2
2.2µF
C1
2.2µF
32.6k
SW1 SW2
8.06k
V
FB
IN
D9*
10V
365k
D8*
100k
FAULT
SHDN
RT
GATE
V
IN
CLKOUT
V
LT3581
C
C3
2.2µF
10k
24k
SYNC
SS
100pF
GND
43.2k
1nF
0.47µF
3581 TA04a
C1: 2.2µF, 25V, X7R, 1206
D8: CENTRAL SEMI CMDSH-3TR
D9: CENTRAL SEMI CMHZ5240B-LTZ
L1: TAIYO YUDEN NR6045T100M
M1: VISHAY SILICONIX SI7611DN
*OPTIONAL,
FOR OUTPUT SHORT-CIRCUIT
PROTECTION
C2 TO C7: 2.2µF, 50V, X7R, 1206
D1 TO D7: CENTRAL SEMI SOD123F
Transient Response with 60mA to 140mA to 60mA
Load Step on VOUT2 (VIN = 12V)
Start-Up Waveforms
V
OUT
AC-COUPLED
2V/DIV
V
OUT2
50V/DIV
V
OUT1
50V/DIV
I
L
0.5A/DIV
I
L
0.5A/DIV
I
LOAD
0.1A/DIV
V
SS
1V/DIV
3581 TA04b
3581 TA04c
100µs/DIV
100ms/DIV
Efficiency and Power Loss at VIN = 12V
90
85
80
75
70
3.0
2.5
2.0
1.5
1.0
0
4
12
16
20
8
TOTAL OUTPUT POWER (W)
3581 TA04d
3581fb
29
For more information www.linear.com/LT3581
LT3581
TYPICAL APPLICATIONS
2MHz, 12V SEPIC Converter Can Accept Input Voltages from 9V to 16V
C2
2.2µF
L1
3.3µH
D1
V
OUT
12V
V
IN
9V TO 16V
1A (V = 9V)
IN
1.1A (V = 12V)
IN
L2
3.3µH
1.3A (V = 16V)
IN
•
SW1 SW2
LT3581
FB
V
IN
130k
C1
3.3µF
C3
10µF
SHDN
GATE
CLKOUT
100k
FAULT
RT
V
C
100pF
0.1µF
10k
2.2nF
SYNC
SS
43.2k
GND
3581 TA06a
C1: 3.3µF, 25V, X7R, 1206
C2: 2.2µF, 50V, X7R, 1206
C3: 10µF, 25V, X7R, 1210
D1: CENTRAL SEMI CTLSH2-40M832
L1, L2: COILCRAFT MSD7342-332MLB
Efficiency
Line Regulation with No Load
100
95
90
85
80
75
70
65
60
55
50
12.000
11.998
11.996
11.994
11.992
11.990
LINE REGULATION ~0.0044%/V
V
= 9V
IN
V
= 16V
IN
V
IN
= 12V
8
9
10 11 12 13 14 15 16 17
(V)
0
300
600
900
1200
1500
V
LOAD CURRENT (mA)
IN
3581 TA06b
3581 TA06c
Load Regulation at VIN = 12
12.01
12.00
11.99
11.98
11.97
11.96
LOAD REGULATION ~0.25%/A
0
200 400 600 800 1000 1200 1400
(mA)
I
LOAD
3581 TA06d
3581fb
For more information www.linear.com/LT3581
30
LT3581
TYPICAL APPLICATIONS
Wide Input Range, 3.3V SEPIC Converter Can Operate from 3V to 36V
C4
2.2µF
L1
3.3µH
D3
D2
V
OUT
V
BAT
3.3V
3V TO 36V
0.9A (3V < V
1.5A (V
< 9V)
C1
10µF
BAT
= 9V)
(V
AT START-UP = 6V TO 16V)
BAT
200k
10k
L2
3.3µH
BAT
•
470pF
SW1 SW2
LT3581
M1
FB
V
IN
24.9k
SHDN
GATE
C5
100k
D1
18V
47µF
FAULT
RT
V
C
C3
4.7µF
×2
47pF
1µF
SS
10k
2.2nF
C2
10nF
SYNC
CLKOUT
174k
GND
Q1
10k
3581 TA07a
C1: 10µF, 50V, X7R, 1210
C2: 10nF, 25V, X7R, 0603
C3: 4.7µF, 25V, X7R, 1206
C4: 2.2µF, 50V, X7R, 1206
C5: 47µF, 10V, X7R, 1210
D2: CENTRAL SEMI CMMSH2-40
D3: DIODES INC. PD3S230H-7
L1, L2: COILCRAFT MSD7342-332MLB
M1: 2N7002
Q1: MMBT3904
D1: CENTRAL SEMI CMHZ5248B-LTZ
Efficiency
Wide Input Range SEPIC Can Ride Through VBAT
Voltages that Are Higher than VIN_OVP
80
75
70
65
60
55
50
V
= 9V
BAT
V
= 12V
BAT
V
BAT
V
= 31V
BAT
10V/DIV
V
= 17V
BAT
V
= 3V
BAT
V
= 3.3V
OUT
V
OUT
2V/DIV
I
L
2A/DIV
3581 TA07c
1s/DIV
0
800
1200
1600
400
LOAD CURRENT (mA)
3581 TA07b
3581fb
31
For more information www.linear.com/LT3581
LT3581
TYPICAL APPLICATIONS
1MHz, 12V Charge Pump Topology Uses Only Single Inductor
Efficiency and Power Loss with
Symmetric Load
C3
1µF
D5
90
85
80
75
70
65
60
55
50
1800
–
V
OUT
–12V
0.27A
1600
1400
1200
1000
800
600
400
200
0
C5
10µF
D4
R1
*2.4k
C2
1µF
L1
8.2µH
D1
+
D3
V
12V
OUT
V
IN
5V
0.27A
D2
SW1
SW2
LT3581
FB
V
IN
130k
SHDN
GATE
C1
3.3µF
C4
10µF
100k
FAULT
CLKOUT
RT
V
C
0
50
100
150
200
250
300
100pF
0.1µF
16.9k
2.2nF
LOAD CURRENT (mA)
SYNC
SS
86.6k
3581 TA08b
GND
3581 TA08a
C1: 3.3µF, 25V, X7R, 1206
C2, C3: 1µF, 25V, X7R, 1206
C4, C5: 10µF, 50V, X7R, 1210
*IF DRIVING ASYMMMETRICAL LOADS,
PLACE A 2.4k, 2W RESISTOR FROM THE 12V
OUTPUT TO THE –12V OUTPUT FOR IMPROVED
D1 TO D5: DIODES INC. PD3S230H-7 LOAD REGULATION OF THE –12V OUTPUT
L1: VISHAY IHLP-2525CZ-01-8R2
R1: 2.4k, 2W
700kHz, –5V Inverting Converter Can Accept Input Voltages from 3V to 16V
Efficiency
C2
90
85
80
75
70
65
60
55
50
L1
3.3µH
L2
3.3µH
1µF
V
OUT
V
IN
3V TO 16V
–5V
V
IN
= 12V
V
IN
= 3.3V
0.9A (V = 3.3V)
D1
IN
1.5A (V = 12V)
IN
1.6A (V = 16V)
SW1 SW2
LT3581
IN
FB
V
V
IN
= 16V
IN
60.4k
SHDN
GATE
C1
22µF
C3
22µF
100k
FAULT
CLKOUT
RT
V
C
56pF
6.19k
2.2nF
SYNC
SS
124k
GND
0.1µF
0
600
900 1200 1500 1800
300
3581 TA09a
LOAD CURRENT (mA)
3581 TA09b
C1: 22µF, 25V, X7R, 1210
C2: 1µF, 50V, X7R, 1206
C3: 22µF, 16V, X7R, 1210
D1: VISHAY SSB44
L1, L2: COILCRAFT MSD7342-332MLB
700kHz, 5V SEPIC Can Accept Input Voltages from 3V to 16V
Efficiency
C2
90
85
80
75
70
65
60
55
50
L1
3.3µH
1µF
D1
V
OUT
5V
0.9A (V = 3V)
V
IN
3V TO 16V
V
= 3.3V
V
= 12V
IN
IN
IN
1.5A (12V ≤ V ≤ 16V)
L2
3.3µH
IN
•
SW1 SW2
LT3581
V
IN
= 16V
FB
V
IN
45.3k
C1
22µF
C3
SHDN
GATE
22µF
100k
×2
FAULT
CLKOUT
RT
V
C
100pF
1µF
7.87k
2.2nF
SYNC
SS
124k
GND
0
400
800
1200
1600
LOAD CURRENT (mA)
3581 TA10b
3581 TA10a
C1: 22µF, 25V, X7R, 1210
C2: 1µF, 50V, X7R, 1206
C3: 22µF, 16V, X7R, 1210
D1: DIODES INC. B230LA
L1, L2: COILCRAFT MSD7342-332MLB
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For more information www.linear.com/LT3581
32
LT3581
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
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33
For more information www.linear.com/LT3581
LT3581
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
R = 0.115
TYP
0.40 ± 0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.05
0.70 ±0.05
TYP
3.30 ±0.05
1.70 ± 0.05
3.30 ±0.10
3.60 ±0.05
2.20 ±0.05
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
PACKAGE
OUTLINE
CHAMFER
(DE14) DFN 0806 REV B
7
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.50 BSC
3.00 REF
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
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For more information www.linear.com/LT3581
34
LT3581
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/13 Added H-grade to Absolute Maximum Ratings table and Order Information table
Clarified Electrical Characteristics
2
4
4
B
07/14 Clarified FAULT Output Voltage Low on Electrical Characteristics table, Typ was 150, changed to 100
3581fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LT3581
TYPICAL APPLICATION
5V to –12V Inverting Converter Switches at 2MHz
Efficiency and Power Loss
C2
L1
3.3µH
L2
3.3µH
1µF
90
85
80
75
70
65
60
55
50
2000
1800
1600
1400
1200
1000
800
V
OUT
V
IN
–12V
5V
625mA
D1
SW1 SW2
LT3581
FB
V
IN
143k
SHDN
GATE
C1
3.3µF
C3
4.7µF
100k
FAULT
CLKOUT
RT
V
C
600
47pF
0.1µF
400
11k
1nF
SYNC
SS
43.2k
200
GND
0
3581 TA05a
0
125
375
LOAD CURRENT (mA)
500
625
250
3581 TA05b
C1: 3.3µF, 16V, X7R, 1206
C2: 1µF, 25V, X7R, 1206
C3: 4.7µF, 25V, X7R, 1206
D1: DIODES INC. PD3S230H-7
L1, L2: COILCRAFT MSD7342-332MLB
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
= 2.5V to 32V, V
LT3580
LT3471
LT3479
LT3477
2A (I ), 2.5MHz, High Efficiency Step-Up DC/DC Converter
V
= 42V, I = 1mA, I < 1µA,
OUT(MAX) Q SD
SW
IN
3mm × 3mm DFN-8, MSOP-8E Packages
Dual Output 1.3A (I ), 1.2MHz, High Efficiency Step-Up DC/DC
Converter
V
= 2.4V to 16V, V 40V, I = 2.5mA, I < 1µA,
=
OUT(MAX)
SW
IN
Q
SD
3mm × 3mm DFN-10 Package
40V, 3A, Full Featured DC/DC Converter with Soft-Start and Inrush
Current Protection
V
SD
= 2.5V to 24V, V
< 1µA, DFN, TSSOP Packages
= 40V, I = Analog/PWM,
OUT(MAX) Q
IN
I
40V, 3A, Full Featured DC/DC Converter
V
SD
= 2.5V to 25V, V
< 1µA, QFN, TSSOP-20E Packages
= 40V, I = Analog/PWM,
OUT(MAX) Q
IN
I
LT1946/LT1946A 1.5A (I ), 1.2MHz/2.7MHz, High Efficiency Step-Up DC/DC Converter
V
= 2.6V to 16V, V
= 34V, I = 3.2mA, I < 1µA,
Q SD
SW
IN
OUT(MAX)
OUT(MAX)
OUT(MAX)
MS8E Package
LT1935
LT1310
LT3436
2A (I ), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter
V
= 2.3V to 16V, V
= 40V, I = 3mA, I < 1µA,
Q SD
SW
IN
ThinSOT Package
2A (I ), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter
V
= 2.3V to 16V, V
= 40V, I = 3mA, I < 1µA,
Q SD
SW
IN
ThinSOT Package
3A (I ), 800kHz, 34V Step-Up DC/DC Converter
V
= 3V to 25V, V
= 34V, I = 0.9mA, I < 6µA,
OUT(MAX) Q SD
SW
IN
TSSOP-16E Package
3581fb
LT 0714 REV B • PRINTED IN USA
36 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT3581
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