LT3582-5_15_技术文档

VOSꢅuS2rV pꢅꢁnie

VPrwi fV iqSiꢂclꢂn

LT3582/LT3582-5/LT3582-12

Boost and Single Inductor

Inverting DC/DC Converters with

2

Optional I C Programing and OTP

FEATURES

DESCRIPTION

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OSꢅuSꢅV2rpꢅꢁnie:

TheLT^®3582/LT3582-5/LT3582-12aredualDC/DCconverters

V 3.12VꢅrV±1.77ꢃ2VꢁꢂdV–±.12VꢅrV–±3.9ꢃ2V(LT3ꢃ81)

V ꢃ2VꢁꢂdV–ꢃ2V(LT3ꢃ81-ꢃ)

featuringpositiveandnegativeoutputsandintegratedfeedback

resistors.TheLT3582,withitsbuilt-inOneTimeProgramming

2

V ±12VꢁꢂdV–±12V(LT3ꢃ81-±1)

(OTP), has conﬁgurable output settings via the I C interface,

1

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DlnlꢅꢁppyVRi-PfrnfꢁooꢁbpiV(LT3ꢃ81)VvlꢁVꢄ CVꢀrf:

including output voltage settings, power-up sequencing,

power-downdischarge,andoutputvoltageramprates.LT3582

settings can be changed adaptively in the ﬁnal product, or set

during manufacturing and made permanent using the built in

non-volatile OTP memory. The positive output voltage can be

set between 3.2V and 12.775V in 25mV steps. The negative

output voltage can be set between –1.2V and –13.95V in

–50mVsteps.TheLT3582-5andLT3582-12arepre-conﬁgured

at the factory for 5V and 12V outputs respectively, and as

V OSꢅuSꢅV2rpꢅꢁniVRꢁouVRꢁꢅie

Prwif-UuVDiꢀꢁSpꢅeV iꢅꢅꢁbpiVwlꢅhVNrꢂ-2rpꢁꢅlpiVOTPV

(LT3ꢃ81)

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1

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ꢄ CVCrouꢁꢅlbpiVꢄꢂꢅifꢀꢁciV( ꢅꢁꢂdꢁfdVMrdi*)

AppVPrwifV wlꢅchieVꢄꢂꢅinfꢁꢅid

V 3ꢃ0oAVCSffiꢂꢅVLlolꢅV(Brreꢅ)

V 600oAVCSffiꢂꢅVLlolꢅV(ꢄꢂvifꢅlꢂn)

AppVFiidbꢁckVRieleꢅrfeVꢄꢂꢅinfꢁꢅid

ꢄꢂuSꢅV2rpꢅꢁniVRꢁꢂni:V1.ꢃꢃ2VꢅrVꢃ.ꢃ2

Low Quiescent Current

2

such, don’t require the use of the I C interface.

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The LT3582 series includes two monolithic converters,

one Boost and one Inverting. The Boost converter has an

integrated power switch and output disconnect switch.

The Inverting converter uses a single inductor topology

and includes an integrated power switch. Both Boost

and Inverting converters use a novel** control scheme

resultinginlowoutputvoltageripplewhileallowingforhigh

conversion efﬁciency over a wide load current range. The

LT3582 series is available in a 16-pin 3mm × 3mm QFN.

325μA in Active Mode

0.01μA in Shutdown Mode

Integrated Output Disconnect

Tiny 16-Pin 3mm × 3mm QFN Package

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APPLICATIONS

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AMOLED Power

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

CCD Power

*

Input thresholds are reduced to allow communication with low voltage digital ICs.

(See Electrical Characteristics).

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General Purpose DC/DC Conversion

** Patent Pending

TYPICAL APPLICATION

±±12V SuuplieVꢀfroVꢁV lꢂnpiVꢃ2VꢄꢂuSꢅ

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree

350

300

250

200

150

100

95

85

75

65

55

45

35

SWN

SHDN

V

OUTP

OUTN

INPUT

V

IN

4.5V TO 5.5V

6.8ꢀH

1ꢀF

SWP

GND

4.7ꢀF

LT3582

10ꢀF

V

CAPP

NEG

–12V

V

OUTN

V

85mA

POS

2

V

OUTP

12V

I C

SDA

SCL

CA

80mA

INTERFACE

OPTIONAL ON

50

0

V

PP

4.7ꢀF

ꢀ

ꢁ

LT3582-5/LT3582-12

RAMPP RAMPN

3582512 TA01a

0.1

1

10

100

LOAD CURRENT (mA)

10nF

3582512 TA01b

3582512fb

1

LT3582/LT3582-5/LT3582-12

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(NrꢅiV±)

TOP VIEW

V Voltage..................................................................6V

IN

SWP Voltage.............................................................15V

SWN Voltage........................................................–16.5V

CAPP Voltage............................................................15V

16 15 14 13

CA

1

2

3

4

12 SWP

11 CAPP

V

17

GND

OUTN

CAPP-V

Voltage.................................... –0.8V to 8V

OUTP

SWN

CAPP

10

9

I

V

....................................................... 300mA

SWN

V

OUTP

CAPP-VOUTP

Voltage...........................................................15V

5

6

7

8

OUTP

Voltage......................................................–16.5V

OUTN

RAMPP Voltage ..........................................................3V

RAMPN Voltage ..........................................................3V

SHDN Voltage ................................................ –0.5 to 6V

UD PACKAGE

16-PIN (3mm × 3mm) PLASTIC QFN

T

= 125°C, θ = 68°C/W

JA

JMAX

EXPOSED PAD (PIN #17) IS GND, MUST BE SOLDERED TO PCB

V

Voltage...................................................–0.2 to 16V

PP

SDA, CA, SCL Voltage.................................... –0.5 to 6V

Operating Junction Temperature Range (Notes 3, 5)

LT3582E ............................................ –40°C to 125°C

Storage Temperature Range .............. –65°C to 150°C

ORDER INFORMATION

LEADVFREEVFꢄNꢄ H

TAPEVANDVREEL

PARTVMARKꢄNG

LDDB

PACKAGEVDE CRꢄPTꢄON

TEMPERATUREVRANGE

LT3582EUD#PBF

LT3582EUD#TRPBF

LT3582EUD-5#TRPBF

LT3582EUD-12#TRPBF

–40°C to 125°C

16-Pin (3mm × 3mm) Plastic QFN

LT3582EUD-5#PBF

LT3582EUD-12#PBF

LDVG

LDVH

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

VTh

L

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E

V

CTRICAL CHARACTERISTICS

lVdiꢂrꢅieVꢅhiVeuiclﬁVcꢁꢅlrꢂeVwhlchVꢁuupyVrvifVꢅhiVꢀSppVruifꢁꢅlꢂnV

ꢅiouifꢁꢅSfiVfꢁꢂni,VrꢅhifwleiVeuiclﬁVcꢁꢅlrꢂeVꢁfiVꢁꢅVT_AV=V1ꢃ°C.V2_ꢄNV=V3.62,V2_SHDNV=V2_ꢄNVSꢂpieeVrꢅhifwleiVꢂrꢅid.V(NrꢅiV3)

wlꢅchlꢂnVRinSpꢁꢅrfVChꢁfꢁcꢅifleꢅlce

YMBOL

PARAMETER

CONDꢄTꢄON

MꢄN

2.4

TYP

MAX

UNꢄT

l

V

Minimum Operating Voltage

Maximum Operating Voltage

2.475

2.55

V

IN_MIN

IN_MAX

VIN

5.5

I

V

Quiescent Current

Ramp Current Conﬁgured to 1μA,

SWOFF Bit Active

325

450

ꢀA

IN

I

V

Quiescent Current in Shutdown

V

= 0

0.01

0

0.5

ꢀA

ns

VIN_SHDN

IN

SHDN

CAPP Quiescent Current in Shutdown

Minimum Switch Off Time

= 0, V

= 5.0V, V

= 0V

OUTP

CAPP_SHDN

CAPP

T

Boost Switch

100

125

OFF_MINP

Minimum Switch Off Time

Inverting Switch

OFF_MINN

3582512fb

2

LT3582/LT3582-5/LT3582-12

E

VTh

L

i

E

V

CTRICAL CHARACTERISTICS

lVdiꢂrꢅieVꢅhiVeuiclﬁVcꢁꢅlrꢂeVwhlchVꢁuupyVrvifVꢅhiVꢀSppVruifꢁꢅlꢂnV

ꢅiouifꢁꢅSfiVfꢁꢂni,VrꢅhifwleiVeuiclﬁVcꢁꢅlrꢂeVꢁfiVꢁꢅVT_AV=V1ꢃ°C.V2_ꢄNV=V3.62,V2_SHDNV=V2_ꢄNVSꢂpieeVrꢅhifwleiVꢂrꢅid.V(NrꢅiV3)

wlꢅchlꢂnVRinSpꢁꢅrfVChꢁfꢁcꢅifleꢅlce

YMBOL

PARAMETER

CONDꢄTꢄON

MꢄN

TYP

10

MAX

UNꢄT

ꢀs

T

Maximum Switch On-Time

Boost Switch Current Limit

Inverting Switch Current Limit

Boost Switch On-Resistance

Inverting Switch On-Resistance

Inverting and Boost Switches

ON_MAX

LIMIT_P

LIMIT_N

l

I

285

490

350

600

500

560

0.01

430

720

mA

R

I

= 200mA

= –400mA

= 5V

mΩ

ꢀA

ON_P

ON_N

OFF_P

SWP

SWN

I

Boost Switch Leakage Current into

SWP Pin

V

0.5

1

SWP

Inverting Switch Leakage Current Out of

SWN Pin

= 5.0, V = 0.0

SWN

0.01

1.4

ꢀA

Ω

OFF_N

IN

R

Output Disconnect Switch

On-Resistance

= 10V, RAMPP > 1.4V

ON_DIS

CAPP

l

I

Output Disconnect Current Limit

124

2.4

155

4.8

186

8.8

mA

μs

LIMIT_DIS

V

Power-Down Discharge Current

V

= 8V

VOUTP_PDS

CAPP_PDS

VOUTN_PDS

OUTP

CAPP Power-Down Discharge Current

Power-Down Discharge Current

CAPP = 8V

1.2

2.4

4.4

V

= –8V

OUTN

–1.4

–2.8

64

–4.2

128

OUTN

2

l

T

Conﬁguration Start-Up Delay

V > V

and SHDN > V

to I C

START-UP

IN

IN_MIN

SHDN_VIH

Enabled and Power-Up Sequencing Start

PfrnfꢁooꢁbpiVOSꢅuSꢅVChꢁfꢁcꢅifleꢅlceV(NrꢅiV6)

YMBOL

PARAMETER

CONDꢄTꢄON

MꢄN

TYP

MAX

UNꢄT

l

V

Positive Output Voltage

LT3582-5

LT3582-12

4.95

11.88

5

12

5.05

12.1

V

VOUTP

N_V

Positive V

Resolution (Note 2)

9

Bits

mV

V

OUTP

V

LSB (Note 2)

25

VOUTP_LSB

OUTP

l

V

Full-Scale Voltage (Note 2)

Minimum Voltage (Note 2)

Line Regulation

Code = BFh, V

Code = 00h, V

= 1

= 0

12.56

3.152

12.775

3.20

12.94

3.248

VOUTP_FS

PLUS

V

VOUTP_MIN

PLUS

V

Code = BFh, 2.575 < V < 5.5

–0.02

%/V

VOUTP_LR

IN

l

V

Negative Output Voltage

LT3582-5

LT3582-12

–5.075

–12.1

–5

–12

–4.925

–11.868

V

VOUTN

N_V

Negative V Resolution (Note 2)

8

Bits

mV

V

OUTN

V

LSB (Note 2)

–50

VOUTN_LSB

OUTN

OUTP

OUTN

l

V

Full-Scale Voltage (Note 2)

Minimum Voltage (Note 2)

Line Regulation

Code = FFh

Code = 00h

–14.2

–1.23

–13.95

–1.205

–0.01

–13.7

–1.18

VOUTN_FS

V

VOUTN_MIN

V

Code = FFh, 2.575 < V < 5.5

%/V

LSB

ꢀA

VOUTN_LR

IN

l

INL_V

Integral Nonlinearity (Notes 2, 4)

Differential Nonlinearity (Notes 2, 4)

Integral Nonlinearity (Note 2)

Differential Nonlinearity (Note 2)

0.6

OUTP

DNL_V

OUTP

OUTN

INL_V

0.85

1.3

DNL_V

OUTN

RAMP00

I

RAMPP/RAMPN Pull-Up Current

IRMP Code = 00

V

= 0.0V

0.7

1.4

1.0

2.0

RAMPP

RAMPN

l

I

RAMPP/RAMPN Pull-Up Current (Note 2)

IRMP Code = 01

V

= 0.0V

2.6

ꢀA

RAMP01

RAMPP

RAMPN

3582512fb

3

LT3582/LT3582-5/LT3582-12

E

VTh

L

i

E

V

CTRICAL CHARACTERISTICS

lVdiꢂrꢅieVꢅhiVeuiclﬁVcꢁꢅlrꢂeVwhlchVꢁuupyVrvifVꢅhiVꢀSppVruifꢁꢅlꢂnV

ꢅiouifꢁꢅSfiVfꢁꢂni,VrꢅhifwleiVeuiclﬁVcꢁꢅlrꢂeVꢁfiVꢁꢅVT_AV=V1ꢃ°C.V2_ꢄNV=V3.62,V2_SHDNV=V2_ꢄNVSꢂpieeVrꢅhifwleiVꢂrꢅid.V(NrꢅiV3)

PfrnfꢁooꢁbpiVOSꢅuSꢅVChꢁfꢁcꢅifleꢅlce

YMBOL

PARAMETER

CONDꢄTꢄON

MꢄN

TYP

MAX

UNꢄT

l

I

RAMPP/RAMPN Pull-Up Current (Note 2)

IRMP Code = 10

V

= 0.0V

2.8

4.0

5.2

ꢀA

RAMP10

RAMPP

RAMPN

I

RAMPP/RAMPN Pull-Up Current (Note 2)

IRMP Code = 11

V

= 0.0V

5.6

8.0

25

10.4

ꢀA

RAMP11

RAMPP

RAMPN

V

Voltage Increase When V Bit is

PLUS

mV

VPLUS

OUTP

Set from 0 to 1 (Note 2)

ꢄꢂuSꢅ/OSꢅuSꢅVPlꢂVChꢁfꢁcꢅifleꢅlce

YMBOL

PARAMETER

CONDꢄTꢄON

MꢄN

TYP

MAX

0.3

UNꢄT

V

l

V

SHDN Input Voltage High

SHDN Input Voltage Low

SHDN Input Hysteresis

SHDN Pin Bias Current

CA Input Voltage High

CA Input Voltage Low

SDA Input Voltage High

SDA Input Voltage Low

SCL Input Voltage High

SCL Input Voltage Low

Input Hysteresis

1.1

SHDN_VIH

SHDN_VIL

V

50

mV

ꢀA

V

HYST_SHDN

SHDN_BIAS

I

V

SHDN

= 1V

2.5

4.5

6.5

l

V

0.7 × V

CA_VIH

CA_VIL

IN

V

0.3 × V

0.85

IN

1.25

V

SDA_VIH

SDA_VIL

SCL_VIH

SCL_VIL

HYST

V

0.85

V

SDA, SCL Pins

80

3

mV

ꢀA

pF

V

l

I

CA Input Leakage Current

SCL Input Leakage Current

SDA Input Leakage Current

Input Capacitance

CA = 0V and 5.5V

SCL = 0V and 5.5V

SDA = 0V and 5.5V

SDA, SCL Pins

1

LEAK_CA

LEAK_SCL

LEAK_SDA

C

V

IN

l

SDA Output Low Voltage

3mA into SDA Pin

0.4

15

SDA_OL

PP_RANGE

PPUVLO

V

Voltage Range for OTP Write (Note 2)

13

V

PP

Undervoltage Lockout for V Pin (Note 2)

12.05

12.45

12.85

V

PP

ꢄ¹CVTlolꢂnVChꢁfꢁcꢅifleꢅlce

YMBOL

PARAMETER

CONDꢄTꢄON

MꢄN

TYP

MAX

UNꢄT

kHz

ꢀs

l

f

t

Serial Clock Frequency

Serial Clock Low Period

Serial Clock High Period

Bus Free Time Between Stop and Start

Start Condition Hold Time

Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time Transmitting

Data Hold Time Receiving

Data Setup Time

100

SCL

4.7

4.0

4.7

4.0

4.7

4.0

300

0

LOW

ꢀs

HIGH

ꢀs

BUF

ꢀs

HD,STA

SU,STA

SU,STO

HD,DATXMIT

HD,DATRCV

SU,DAT

F

ꢀs

LT3582 Sending Data to Host

ns

LT3582 Receiving Data from Host

ns

250

ns

SDA Fall Time

400pF Load, V ≥ 2.5V

250

ns

IN

3582512fb

4

LT3582/LT3582-5/LT3582-12

ELECTRICAL CHARACTERISTICS

NrꢅiV±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

NrꢅiVꢃ: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed the maximum operating junction temperature

when overtemperature protection is active. Continuous operation above

the speciﬁed maximum operating junction temperature may impair device

reliability.

NrꢅiV1: LT3582 only.

NrꢅiV3: The LT3582E is guaranteed to meet performance speciﬁcations

from 0°C to 125°C junction temperature. Speciﬁcations over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlations with statistical process controls.

NrꢅiV6: Output voltage is measured under non-switching test conditions

approximating a moderate load current from the output.

NrꢅiV4: These speciﬁcations apply to the V trim bits in REG0 using a

P

50mV LSB and do not include the additional V

trim bit. See Registers

PLUS

and OTP in the Applications Information section.

3582512fb

5

LT3582/LT3582-5/LT3582-12

V

T_AV=V1ꢃ°CVSꢂpieeVrꢅhifwleiVꢂrꢅid.V

TYPICAL PERFORMANCE CHARACTERISTICS

wlꢅchlꢂnVFfiqSiꢂclieV(FlnSfiV±3)

LrꢁdVRinSpꢁꢅlrꢂV(FlnSfiV±3)V

OSꢅuSꢅV2rpꢅꢁniV(FlnSfiV±3)

1.00

0.75

0.50

0.25

0

10000

1000

100

0.45

0.30

0.15

V

OUTP

V

OUTN

V

OUTP

0

–0.15

–0.30

–0.45

V

OUTN

OUTP

–0.25

–0.50

–0.75

–1.00

V

OUTN

10

0

20

40

60

80

100

0

20

40

60

80

100

–50 –25

0

25

50

75

100 125

LOAD CURRENT (mA)

TEMPERATURE (°C)

3582512 G02

3582512 G01

3582512 G03

QSlieciꢂꢅVCSffiꢂꢅV–VNrꢅV wlꢅchlꢂn

wlꢅchVRieleꢅꢁꢂci

wlꢅchVCSffiꢂꢅVLlolꢅV

390

370

350

330

310

290

270

250

700

600

500

400

300

200

O.7

0.6

0.5

0.4

0.3

0.2

0.1

0

SWN

V

OUTN

OUTP

V

SWP

2.5

3

3.5

4

4.5

5

5.5

–50 –25

0

25

50

75 100 125

2.5

3

3.5

4

4.5

5

5.5

V

(V)

TEMPERATURE (°C)

INPUT VOLTAGE (V)

IN

3582512 G04

3582512 G06

3582512 G05

2

_OUTPVꢁꢂdV2_OUTNVPlꢂVCSffiꢂꢅV

OSꢅuSꢅVDlecrꢂꢂicꢅVPMO VCSffiꢂꢅV

LlolꢅVDSflꢂnVNrfoꢁpVOuifꢁꢅlrꢂV

OSꢅuSꢅVDlecrꢂꢂicꢅVPMO V

Oꢂ-RieleꢅꢁꢂciV

DSflꢂnVNrfoꢁpVOuifꢁꢅlrꢂ

200

180

160

140

120

100

80

60

2.5

2

CURRENT INTO

OUTP

V

CODE

P

40

SET TO 12V

20

V

CODE

P

SET TO 5V

1.5

1

0

V

N

CODE

–20

–40

–60

–80

–100

SET TO –5V

V

N

CODE

SET TO –12V

0.5

0

CURRENT OUT

OF V

OUTN

–50 –25

0

25

50

75 100 125

0

2.5

5

7.5

10

12.5

15

2

4

6

8

10

12

TEMPERATURE (°C)

|V | (V)

OUT

V

(V)

CAPP

3582512 G08

3582512 G07

3582512 G09

3582512fb

6

LT3582/LT3582-5/LT3582-12

TYPICAL PERFORMANCE CHARACTERISTICS

Nrꢅi:VAppVwꢁviꢀrfoeVrꢂVꢅhleVuꢁniVꢁuupyVꢅrVFlnSfiV±3.

wlꢅchlꢂnVWꢁviꢀrfoVꢁꢅV±oAVLrꢁdV

(Brreꢅ)

wlꢅchlꢂnVWꢁviꢀrfoVꢁꢅV±0oAV

LrꢁdV(Brreꢅ)

wlꢅchlꢂnVWꢁviꢀrfoVꢁꢅV±00oAV

LrꢁdV(Brreꢅ)V

V

SWP

5V/DIV

V

SWP

5V/DIV

V

VOUTP

V

VOUTP

10mV/DIV

AC COUPLED

I

L2

0.2A/DIV

3582512 G10

3582512 G11

3582512 G12

2μs/DIV

200ns/DIV

5μs/DIV

wlꢅchlꢂnVWꢁviꢀrfoVꢁꢅV±oAVLrꢁdV

(ꢄꢂvifꢅlꢂn)

wlꢅchlꢂnVWꢁviꢀrfoVꢁꢅV±0oAV

LrꢁdV(ꢄꢂvifꢅlꢂn)

LrꢁdVTfꢁꢂeliꢂꢅ,V2_OUTN,V30oAVꢅrV

60oAVꢅrV30oAV ꢅiueV

V

SWN

V

SWN

10V/DIV

V

VOUTN

0.1V/DIV

AC COUPLED

V

VOUTN

V

VOUTN

20mV/DIV

50mV/DIV

AC COUPLED

LOAD

CURRENT

–20mA/DIV

I

L1

I

L1

0.2A/DIV

3582512 G13

3582512 G15

3582512 G14

5μs/DIV

50μs/DIV

5μs/DIV

Prwif-DrwꢂVDlechꢁfniV

WꢁviꢀrfoeV

(PU EQV=V±±,VPDDꢄ V=V±)

LrꢁdVTfꢁꢂeliꢂꢅ,V2_OUTP,V30oAVꢅrV

60oAVꢅrV30oAV ꢅiue

Prwif-UuV iqSiꢂclꢂnVWꢁviꢀrfoeV

(PU EQV=V±±)

V

RAMPN

1V/DIV

V

OUTP

0.2V/DIV

V

RAMPP

1V/DIV

AC COUPLED

V

RAMPN

1V/DIV

LOAD

CURRENT

20mA/DIV

V

RAMPP

1V/DIV

V

VOUTP

V

VOUTP

5V/DIV

I

L2

V

VOUTN

0.2A/DIV

5V/DIV

3582512 G16

3582512 G18

3582512 G17

50μs/DIV

5ms/DIV

3582512fb

7

LT3582/LT3582-5/LT3582-12

PIN FUNCTIONS

CAV(PlꢂV±):I C Address Select Pin. Tie this pin to V to set

the 7-bit address to 0110 001. Tie to GND for 1000 101.

2

CAPPV(PlꢂeV±0,V±±): Connect the Boost output capacitor

from these pins to GND. During shutdown, the voltage on

these pins will remain close to the input voltage due to

the path through the Boost inductor and Schottky. During

normal operation, CAPP will be boosted slightly higher

than the programmed output voltage.

IN

2

V(PlꢂV1):NegativeOutputVoltagePin.Whenthecon-

OUTN

verterisoperating,thispinisregulatedtotheprogrammed

negative output voltage. Place a ceramic capacitor from

this pin to GND.

WPV(PlꢂV±1): Positive Switching Node for the Boost

Converter. This is the drain of the internal NMOS power

switch. Connect one end of the Boost inductor to this pin.

Keep the trace area on this pin as small as possible.

WNV(PlꢂeV3,V4): Negative Switching Node for the In-

verting Converter. This is the drain of the internal PMOS

power switch. Connect one end of the Inverting inductor

to these pins. Keep the trace area on these pins as small

as possible.

GNDV(PlꢂV±3): Ground Pin. Tie to a local ground plane.

Proper PCB layout is required to achieve advertised per-

formance; see the Applications Information section for

more information.

2 V(PlꢂVꢃ): Input Supply Pin and Source of the PMOS

ꢄN

Power Switch. This pin must be bypassed locally with a

ceramic capacitor. The operating voltage range of this pin

is 2.55V to 5.5V.

2 V(PlꢂV±4): Programming Voltage Pin. Drive this pin

PP

to 13-15V when programming the OTP memory. Float

RAMPNV(PlꢂV6): Soft-Start Ramp Pin for the Inverting

Converter. Place a capacitor from this pin to GND. A

programmable current of 1μA to 8μA (LT3582) or 1ꢀA

(LT3582-5/LT3582-12) charges this pin during start-up,

otherwise. A bypass capacitor should be placed from this

node to GND if V is used for programming. If V falls

PP

below 13V during OTP programming, an internal FAULT

2

bit, which can be read through the I C interface, can be

limiting the ramp rate of V

GND during shutdown.

. This pin is discharged to

OUTN

set high.

2

DAV(PlꢂV±ꢃ): I C Bidirectional Data Pin. Tie to GND or

RAMPPV(PlꢂV7):Soft-StartRampPinfortheBoostConvert-

er.PlaceacapacitorfromthispintoGND.Aprogrammable

currentof1μAto8μA(LT3582)or1ꢀA(LT3582-5/LT3582-12)

charges this pin during start-up, limiting the ramp rate of

V if unused.

IN

2

CLV(PlꢂV±6): I C Clock Pin. Tie to GND or V if un-

IN

used.

V . This pin is discharged to GND in shutdown.

OUTP

ExureidVPꢁdV(PlꢂV±7): Ground Pin. Tie to a local ground

plane. Proper PCB layout is required to achieve advertised

performance;seetheApplicationsInformationsectionfor

more information.

SHDNV(PlꢂV8): Shutdown Pin. Drive this pin to 1.1V or

higher to enable the part. Drive to 0.3V or lower to shut

down. Includes an integrated 222k pull-down resistor.

2

V(PlꢂV9): Output of the Boost Converter Output

OUTP

Disconnect Circuit. A ceramic capacitor should be placed

from this node to GND. During shutdown, this pin is

disconnected from the Boost network which allows this

pin to discharge to GND, assuming a load is present to

discharge the capacitance.

3582512fb

8

LT3582/LT3582-5/LT3582-12

BLOCK DIAGRAM

V

SWP

CAPP CAPP

V

OUTP

IN

Q

S

R

S

R

Q

VARIABLE DELAY

Q

DISCONNECT

CONTROL

SWN

OTP

+

–

GND

+

–

I

T

I

T

PEAK OFF

CONTROL

FBP

+

–

+

V

OUTN

VCN

VCP

0.80V

CHIP ENABLE

SHDN

FBN

–

222k

OTP

V

IN

PP

–

+

0.80V

SCL

SDA

CA

+

2V

SERIAL INTERFACE,

LOGIC AND OTP

V

OUTP

CAPP

OTP ADJUST

IN

RAMPN

0.75V

+

FBP

–

OUTPUT SEQUENCING

BY OTP

3582512 BD

V

OUTN

+

–

FBN

2V

50mV

OUTPUT SEQUENCING

OTP ADJUST

RAMPP

3582512fb

9

LT3582/LT3582-5/LT3582-12

OPERATION

TheLT3582seriesaredualDC/DCconverters,eachcontain-

ing both a Boost and an Inverting converter. Operation can

be best understood by referring to the Block Diagram. The

Boost and Inverting converters each use a novel control

technique,whichsimultaneouslyvariesbothpeakinductor

current and switch off time. This results in high efﬁciency

over a large load range and low output voltage ripple. In

addition, this technique further minimizes output ripple

when the switching frequency is in the audio band.

can be conﬁgured such that (1) they both rise simultane-

ously, (2) V rises to regulation before V rises, (3)

OUTP

OUTN

rises, or(4)neither

V

risestoregulationbeforeV

OUTN

OUTP

output rises. The outputs of the LT3582-5 and LT3582-12

are pre-conﬁgured to rise simultaneously.

The ramp rates of the outputs are proportional to the ramp

rates of their respective RAMP pins. A capacitor is placed

between each RAMP pin and ground. The RAMP pins are

discharged during shutdown. Once enabled, conﬁgurable

(LT3582) or pre-conﬁgured (LT3582-5/LT3582-12) cur-

rents charge each RAMP pin in the desired sequence

causing the outputs to rise.

BrreꢅVCrꢂvifꢅif: The Boost converter uses a grounded

source NMOS power transistor as the main switching ele-

ment.ThecurrentintheNMOSisconstantlymonitoredand

controlled, along with the off-time of the switch to achieve

OSꢅuSꢅVPrwif-DrwꢂVDlechꢁfni: The power-down dis-

charge feature is permanently enabled on the LT3582-5

and LT3582-12 and can be enabled or disabled through

regulation of V . The V

OUTP

voltage is divided by the

OUTP

internal programmable (LT3582 only) resistor divider to

create FBP. The voltage on FBP is compared to an internal

reference and ampliﬁed, creating an error signal on the

VCPnodewhichcommandstheappropriatepeakinductor

current and off time for the subsequent switching cycle.

2

I C on the LT3582. Upon SHDN falling, and when power-

down discharge is enabled, internal transistors will acti-

vate to assist in discharging the outputs toward ground.

When power-down discharge is disabled, the chip powers

down immediately after SHDN falls and the outputs will

discharge on their own depending on their external load

capacitances and currents.

ꢄꢂvifꢅlꢂnVCrꢂvifꢅif:TheInvertingconverterusesapower

PMOS transistor with the source connected to V . This

topology requires only one external inductor, instead of

the normally required two inductors plus ﬂying capacitor.

Regulation is achieved in a similar manner as the Boost.

IN

OTPVMiorfyV(LT3ꢃ81VOꢂpy):The LT3582 includes 22 bits

ofuserprogrammableoutputsettingsand1programming

lockoutbit.Parameterssuchaspositiveandnegativeoutput

voltages and power sequencing settings can be changed

OSꢅuSꢅVPrwif-UuV iqSiꢂclꢂn: After an initial start-up

delay (T

OUTN

= 64μs typical), the outputs V

and

START-UP

OUTP

2

V

rise(inmagnitude)simultaneouslywiththeLT3582-5/

in real time with the integrated I C interface. Settings can

LT3582-12 or in one of four selectable sequences with

the LT3582. Using the I C interface, the LT3582 outputs

then be made permanent by programming to the on-chip

non-volatile OTP (One Time Programmable) memory.

2

3582512fb

10

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

ꢄ CVꢄꢂꢅifꢀꢁci

1

ACKꢂrwpidni

2

The LT3582 series contains an I C compatible interface

The acknowledge signal (ACK) is used in handshaking

between transmitter and receiver to indicate that the most

recent byte of data was received. The transmitter always

releases the SDA line during the acknowledge clock pulse.

When the slave is the receiver, it pulls down the SDA line

so that it remains LOW during this pulse to acknowledge

receipt of the data. If the slave fails to acknowledge

by leaving SDA high, then the master may abort the

transmission by generating a STOP condition. When the

master is receiving data from the slave, the master pulls

downtheSDAlineduringtheclockpulsetoindicatereceipt

ofthedata. Afterthelastbytehasbeenreceivedthemaster

leaves the SDA line HIGH (not acknowledge) and issues a

stop condition to terminate the transmission.

allowingittobedigitallyconﬁgured.Theuseofthisinterface

is optional for the LT3582-5 and LT3582-12 as these parts

are pre-conﬁgured at the factory. The CA, SDA and SCL

2

pins can be grounded if the I C interface is unused.

2

The I C interface has reduced input threshold voltages to

allow for direct communication with low voltage digital

2

ICs (see Electrical Characteristics). I C communication

2

is disabled when SHDN is low. After SHDN rises, I C

communicationisre-enabledafteradelayof64μs(typical).

The chip is a read-write slave device which allows the user

to read the current settings and, for the LT3582, write

new ones. Most settings can be made permanent via the

One-Time-Programmable memory. The chip will always

enable using the data stored in OTP and the LT3582 can

be reconﬁgured after power-up.

DivlciVAddfieelꢂn

The LT3582 series supports two 7-bit chip addresses

depending on the logic state of the CA pin. The addresses

are 0110 001 (CA = 1) and 1000 101 (CA = 0). Also, there

are seven internal data byte locations as shown in Table 1.

OTP0-OTP2 are the OTP memory bytes. REG0-REG2

are the corresponding volatile registers used for storing

alternatesettings. Finally, theCommandRegister(CMDR)

is used for additional control of the chip.

TARTVꢁꢂdV TOPVCrꢂdlꢅlrꢂe

When the bus is idle, both SCL and SDA are high. A bus

mastersignalsthebeginningofatransmissionwithaSTART

condition by transitioning SDA from high to low while SCL

ishigh,asshowninFigure1.Whenthemasterhasﬁnished

communicating with the slave, it issues a STOP condition

by transitioning SDA from low to high while SCL is high.

The bus is then free for another transmission.

SDA

SCL

A6 - A0

1-7

B7 - B0

8

9

1-7

8

9

1-7

8

9

S

P

START

CONDITION

CHIP

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

CONDITION

3582512 F01

FlnSfiV±.VDꢁꢅꢁVTfꢁꢂeꢀifVOvifVꢄ¹CVBSe

3582512fb

11

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

LT3ꢃ81VChluVCrꢂﬁVnSfꢁꢅlrꢂV

All data bytes can be read from their assigned register

addresses. Since they share the same register addresses,

reads of the OTP and REG data bytes are differentiated

by their corresponding RSEL (Register Select) bits in the

CMDRregister. Alldatawrittentoregisteraddresses0-2is

stored in REGO-REG2. Regardless of the RSEL bits, OTP

bytescannotbewrittendirectly.SeetheOTPProgramming

section for more information.

Settings such as output voltages and sequencing are

digitallyprogrammable.Thechipusessettingsfromeither

the REG or OTP bytes, depending on the states of the

corresponding RSEL bits (0 for OTP and 1 for REG).

During shutdown the RSEL bits are reset low. As a result,

the initial conﬁguration comes from the OTP data bytes.

Afterpower-up,theconﬁgurationcanbechangedbywriting

new settings to the appropriate REG data byte(s) then

setting the corresponding RSEL bit(s).

DꢁꢅꢁVTfꢁꢂeꢀifVPfrꢅrcrp

The LT3582 series supports 8-bit data transfers in the

transaction formats shown in Figures 2 and 3. Multiple

data bytes can only be transferred by issuing multiple

transactions.

Finally, data in the REG bytes can be permanently

programmed to OTP by applying voltage to the V pin

PP

and setting the WOTP bit in the Command Register. See

the OTP Programming section for more information.

Figure 2 shows the required format for writing a byte of

datatotheLT3582series.Again,thechipaddressdepends

on the CA pin logic state.

LT3ꢃ81-ꢃ/LT3ꢃ81-±1VChluVCrꢂﬁVnSfꢁꢅlrꢂ

TheLT3582-5/LT3582-12areshippedfromthefactorywith

the OTP memory pre-programmed and LOCKed which

prohibits subsequent changes to the conﬁguration. The

CHꢄPVADDR

W

A

REGVADDR

A

DATA

A

P

0110 001 OR

1000 101

0

00000b2:b0

0

b7:b0

0

2

conﬁguration can still be read through the I C bus and

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

the RST and SWOFF bits of the CMDR register (described

later) are functional. The following sections describe the

various conﬁgurable features of the LT3582. The LT3582-5

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

and LT3582-12 are pre-conﬁgured as follows: V and V

P

N

are programmed for 5V or 12V respectively, LOCK = 1,

FlnSfiV1.Vꢄ¹CVByꢅiVWflꢅiVTfꢁꢂeꢁcꢅlrꢂ

IRMP = 00, PDDIS = 1, PUSEQ = 11 and V may be 1

PLUS

or 0. Since LOCK = 1, subsequent conﬁguration changes

are prohibited. See Conﬁguration Lockout (LOCK Bit) for

more information.

A byte of data is read from the LT3582 series using the

2

formatshowninFigure3.ThistransactionrequiresfourI C

bytes to read one byte of chip data and must be repeated

for each subsequent byte of data that is read.

RinleꢅifeVꢁꢂdVOTP

The registers and OTP bytes for the LT3582 series are

organized as shown in Table 1. The CMDR is reset to 00h

uponpower-up,duringshutdownandduringundervoltage

andthermallockouts.REG0-REG2areneverresetandmust

always be loaded with valid data before use. The LT3582’s

OTP memory is shipped with all 0’s, and as a result, the

PUSEQ bits are conﬁgured to disable the outputs. The

PUSEQ bits must be reconﬁgured to enable the outputs.

CHꢄPVADDR

W

A

REGVADDR

A

0110 001 OR

1000 101

0

00000b2:b0

0

CHꢄPVADDR

R

A

DATA

A

P

0110 001 OR

1000 101

1

0

b7:b0

1

FlnSfiV3.Vꢄ¹CVByꢅiVRiꢁdVTfꢁꢂeꢁcꢅlrꢂ

3582512fb

12

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

CMDR: The Command Register is used to control various

functions of the chip. During shutdown and power-up the

CMDR is initialized to 00h.

TꢁbpiV±:VLT3ꢃ81V iflieVRinleꢅifVMꢁu

REGꢄ TERV REGꢄ - BꢄT

BꢄTV DE CRꢄPTꢄON

NAME

ADDRE

TER

NAME

The RSEL (Register Select) bits are functional only for

the LT3582. The LT3582-5 and LT3582-12 function as if

the RSEL bits are always “0”. These bits perform three

functions:

00h

REG0/ 7:0

OTP0

V

Output Voltage (00h=3.2V,

OUTP

P

BFh = 12.75V)

01h

REG1/ 7:0

OTP1

V

Output Voltage (00h=1.2V,

OUTN

N

FFh = 13.95V)

7

6

-

Reserved, Write to 0

• Each RSEL bit instructs the chip whether to use the

conﬁguration data from the corresponding OTP byte

(RSELx = 0) or the REG byte (RSELx = 1). Changing an

RSELx bit immediately updates the chip conﬁguration.

LOCK Lockout Bit: See the OTP

Programming Lockout Section.

REG2/

OTP2

5

V

Output Voltage Bit: Increase

by ~25mV

PLUS

OUTP

02h

4:3 IRMP RAMPP and RAMPN Pull-Up

2

IRMP

Current: I

= (2)

ꢀA

• Each RSEL bit determines if I C reads return data from

RAMP

2

PDDIS Power-Down Discharge Enable.

PUSEQ Must be 11 if Set.

the corresponding OTP byte (RSELx = 0) or the REG

byte (RSELx = 1).

1:0 PUSEQ Power-Up Sequencing: 00 =

Outputs Disabled, 01 = V

• OTPprogrammingonlyprogramsdatatothebyteswith

corresponding RSEL bits set high.

OUTN

Ramp 1st, 10 = V

11 = Both Ramp Together

Ramp 1st,

OUTP

Setting the SWOFF bit immediately disables the Boost

and Inverting power switches and opens the output dis-

connect PMOS switch. It is recommended to set this bit

before writing new conﬁguration data. This can prevent

unexpected chip behavior while modifying the conﬁgura-

tion and also forces a soft-start after SWOFF is cleared

(see Soft-Start and Power-Up Sequencing). Writing “1”

7

6

WOTP Write OTP Memory

CF/

Clear Fault/OTP Programming

FAULT Fault

5

4

3

2

RST Reset

SWOFF Switches-Off

04h

CMDR

-

Reserved, Write to 0

RSEL2 Register Select 2 (0 = OTP2,

1 = REG2)

2

to the RST bit resets the internal I C logic and the CMDR

1

0

RSEL1 Register Select 1 (0 = OTP1,

1 = REG1)

register. Reading bit 6 of the CMDR returns the FAULT bit

indicatingifanOTPprogrammingattemptmayhavefailed.

FAULTisclearedduringreset,power-up,orbywritinga“1”

to the CF (Clear Fault) bit. Conditions that set the FAULT

RSEL0 Register Select 0 (0 = OTP0,

1 = REG0)

OTP0/REG0VꢁꢂdVOTP±/REG±: Data in addresses 00h and

01h is used to set the output voltages of the Boost and

Inverting converters respectively. See Setting the Output

Voltages for more information.

bit are (1) OTP programming in which the V voltage

PP

is too low or (2) attempted OTP programming when the

LOCK bit is set. OTP write attempts that set the FAULT bit

due to low V voltage should be considered failures and

PP

the device should be discarded. Attempts to re-program

the OTP memory after the FAULT bit has been set are not

recommended. Finally, setting the WOTP bit starts the

OTP programming.

3582512fb

13

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

OTP1/REG1: Data in address 02h conﬁgures the output

voltage sequencing, sets a ﬁne voltage adjust for V

anddeterminesiffurtherOTPprogrammingispermittedor

not. Proper uses of the bits in address 02h are discussed

in the following sections.

rꢀꢅ- ꢅꢁfꢅ/OSꢅuSꢅV2rpꢅꢁniVRꢁoulꢂnV(ꢄRMPVBlꢅe)

,

OUTP

TheLT3582seriescontainssoft-startcircuitrytocontrolthe

output voltage ramp rates, therefore limiting peak switch

currentsduringstart-up.Highswitchcurrentsareinherent

in switching regulators during start-up since the feedback

loop is saturated due to V

being far from its ﬁnal value.

OUT

iꢅꢅlꢂnVꢅhiVOSꢅuSꢅV2rpꢅꢁnieV(2 ,V2

VꢁꢂdV2 VBlꢅe)

N

PV PLU

Theregulatortriestochargetheoutputcapacitorasquickly

TheLT3582seriescontainstworesistordividerswhichare

programmable in the LT3582, to set the output voltages.

as possible which results in large currents.

Capacitors must be connected from RAMPP and RAMPN

to ground for soft-start. During shutdown or when the

SWOFF bit is set, the RAMP capacitors are discharged

to ground. After SHDN rises or SWOFF is cleared, the

capacitors are charged by programmable (LT3582 only)

The positive output voltage V

is adjustable in 25mV

OUTP

steps by setting the V bits in REG0/OTP0 in addition to

P

the V

bit in REG2/OTP2.

PLUS

V

= 3.2V + (V • 50mV) + (V • 25mV)

PLUS

OUTP

P

currents, thus creating linear voltage ramps. The V

OUT

where:

V = an integer value from 0 to 191

voltages ramp in proportion to their respective RAMP

P

PLUS

voltages according to:

V

= 0 or 1

⎛

⎜

⎝

⎞

⎟

⎠

V

0.8V

I_RAMP

⎛

⎞

OUT

The V

voltage is adjustable in –50mV steps by setting

V_OUT_RAMP_RATE =

•

Volts / Sec

OUTN

⎜

⎝

⎟

⎠

C

RAMP

the V bits in REG1/OTP1.

N

V

= –1.2V – (V • 50mV)

N

OUTN

Proportionality Constant

where:

RAMP pin ramp rate (V/Sec)

where:

V = an integer value from 0 to 255

N

DyꢂꢁolcꢁppyVChꢁꢂnlꢂnVꢅhiVOSꢅuSꢅV2rpꢅꢁniV(LT3ꢃ81VOꢂpy):

After output regulation has been reached, it’s possible to

change the output voltages by writing new values to the

I

= RAMP pin charging current set by IRMP

bits (1μA, 2μA, 4μA or 8μA for LT3582,

1ꢀA for LT3582-5/LT3582-12)

= External RAMP pin capacitor (Farads)

= Output voltage during regulation

RAMP

V or V bits. When reducing the magnitude of an out-

N

P

C

V

RAMP

OUT

put voltage, it will decay at a rate dependent on the load

current and capacitance. Conﬁguring a large increase in

magnitude of an output voltage can cause a large increase

in switch current to charge the output capacitor. Before

reconﬁguring the outputs, consider forcing a soft-start

For example, selecting I

OUTP

(see Figure 6).

= 1μA, C

= 10nF and

RAMP

V

= 12V results in a power-up ramp rate of 1.5Volt/ms

by asserting the SWOFF bit before writing the new V or

Ramp rates less than 1-10V/ms generally result in good

start-upcharacteristics.Theoutputsshouldlinearlyfollow

the RAMPx voltages with no distortions. Figure 7 shows

an excessive start-up ramp rate of ~120V/ms in which

P

V codes. Subsequently clearing SWOFF initiates the new

N

soft-start sequence.

3582512fb

14

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

several start-up issues have occurred: A) the expected

The LT3582 series incorporates an output disconnect

V

ramp up path is not followed B) inductor current

PMOS allowing V

to be grounded during shutdown.

OUTP

ringing occurs C) the V

ramp rate is limited due to

Once enabled, the Disconnect Control circuit actively

OUTP

the output disconnect current limit being reached D) ad-

ditional ringing occurs when the CAPP pin starts charging

E) output voltage overshoot occurs because the inductor

currents are maximized during the output ramp-up.

drives the PMOS gate allowing V

to ramp up linearly

reaches regulation,

OUTP

as shown in Figure 6. Once V

OUTP

the PMOS is fully turned “on” to reduce resistance and

improve efﬁciency.

In some cases it may be desirable to use only one RAMP

pin capacitor. In cases where PUSEQ = 11 (see the Power-

Up Sequencing section) the RAMPP and RAMPN pins

can be connected together and to a single capacitor. In

this case the capacitor will charge with twice the current

conﬁgured by the IRMP bits.

Prwif-UuV iqSiꢂclꢂnV(PU EQVblꢅe)

Once enabled, the part requires a delay of T

(64μs

START-UP

typ)toproperlyconﬁgureitself.Onceconﬁgured,theorder

in which V and V ramp to regulation is controlled

OUTP

OUTN

by the PUSEQ bits. The combinations available for the

LT3582 are shown in Table 2. The LT3582-5/LT3582-12

are pre-conﬁgured with the 11 combination.

RꢁoulꢂnV2

VꢀfroVGfrSꢂd: The LT3582 series has

OUTP

the unique ability to generate a smooth V

voltage

OUTP

TꢁbpiV1.VPrwif-UuV iqSiꢂcie

PU EQ[±:0] Prwif-UuV iqSiꢂci

ramp starting from ground and continuing all the way up

to regulation (see Figure 6). This ability is not possible

with typical Boost converters in which the output is taken

from the cathode of the Schottky diode (CAPP node in

Figure 5).

00

01

10

11

Outputs are disabled, neither output ramps up

V

ramps up 1st, followed by V

OUTN

OUTP

OUTN

Both V

and V

ramp-up starting at the same time.

OUTN

OUTP

L1

Selecting the 01 or 10 combinations cause one of the out-

SWP

LT3582

D1

puts to start ramping shortly after SHDN rises. The ramp

CAPP

SERIES

V

OUTP

rate of V

is controlled by the RAMP pin as discussed

OUT

C1

intheSoft-Startsection. AfterV

nearsitstargetregula-

OUT

C3

LOAD

C2

DISCONNECT

CONTROL

V

IN

A

E

V

RAMPP

0.5V/DIV

3582512 F05

FlnSfiVꢃ.VBrreꢅVCrꢂvifꢅifVTrurprny

B

D

CAPP

3V/DIV

V

OUTP

3V/DIV

C

I

L2

0.2A/DIV

CAPP

2V/DIV

3582512 F07

50μs/DIV

V

OUTP

FlnSfiV7.V2_OUTPV rꢀꢅ- ꢅꢁfꢅVwlꢅhVExcieelviVRꢁouVRꢁꢅi

2V/DIV

V

RAMPP

0.2V/DIV

I

L2

0.2A/DIV

3582512 F06

1ms/DIV

FlnSfiV6.V2_OUTPV rꢀꢅ- ꢅꢁfꢅVRꢁoulꢂnVꢀfroVGfrSꢂd

3582512fb

15

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

tion voltage, the remaining output is activated and ramps

under control of its respective RAMP pin (see Figure 8).

The power-up sequencing concludes when both outputs

have reached regulation.

The PDDIS bit must only be set in conjunction with

PUSEQ being set to 11. Driving SHDN low, with power-

down discharge enabled (PDDIS = 1) causes the chip to

power-down after ﬁrst discharging the output voltages.

Speciﬁcally, driving SHDN low causes the following se-

quence of events to happen:

EvꢁpSꢁꢅlꢂnVPU EQV iꢅꢅlꢂneV(LT3ꢃ81VOꢂpy): After SHDN

rises, the LT3582 uses the PUSEQ conﬁguration found

in OTP. The effects of differing PUSEQ settings can be

observed without writing to OTP by taking the following

actions:

1. Both converters are turned off.

2. Discharge currents are enabled to discharge the output

capacitors

1. Write the SWOFF bit high, stopping both converters

and discharging the RAMP pins.

• See Electrical Characteristics for I

and

VOUTP-PDS

I

which help discharge V

and CAPP

CAPP-PDS

OUTP

2. Write the desired settings to the PUSEQ bits in REG2.

• See Electrical Characteristics for I

which

VOUTN-PDS

3. Set the RSEL2 bit high which selects the REG2 con-

ﬁguration settings.

helps discharge V

OUTN

3. Thechipwaitsuntiltheoutputvoltageshave discharged

to within ~0.5V to ~1.5V of ground.

4. Write SWOFF low which restarts both converters.

This will initiate the desired power-up sequence that can

be observed with an oscilloscope.

4. DischargecurrentsaredisabledandtheLT3582powers

down.

Since the LT3582 series won’t power-down until both

outputs are discharged (when power-down sequencing is

Prwif-DrwꢂVDlechꢁfniV(PDDꢄ Vblꢅ)

The PDDIS bit is used to enable power-down discharge.

This bit is pre-conﬁgured to a “1” for the LT3582-5 and

LT3582-12, thus enabling power-down discharge.Setting

PDDIS = 0 disables the power-down discharge causing

the chip to shut down immediately after SHDN falls.

enabled), make sure V

and V

can be grounded.

OUTP

OUTN

This is not a problem in most topologies. However, read

the section Output Disconnect Operating Limits for ad-

ditional information.

RAMPP

V

RAMPP

RAMPN

0.5V/DIV

V

RAMPN

0.5V/DIV

V

VOUTP

5V/DIV

V

VOUTN

5V/DIV

3582512 F08

5ms/DIV

FlnSfiV8.VPrwif-UuV iqSiꢂclꢂnV(PU EQV=V±0)

3582512fb

16

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

is programmed at a time to reduce noise on V caused

CrꢂﬁVnSfꢁꢅlrꢂVLrckrSꢅV(LOCKVblꢅ)

PP

by the sudden change in current. A 1-10μF V bypass

PP

After a desired conﬁguration is programmed into OTP, the

LOCK bit can be set to prohibit subsequent changes to the

conﬁguration. The LT3582-5 and LT3582-12 are precon-

ﬁgured with the LOCK bit set to a logic “1” which:

capacitor is also recommended to prevent voltage droop

after programming begins. Also, avoid hot-plugging V

PP

which results in very fast voltage ramp rates and can lead

to excessive voltage on the V pin.

PP

• Forces the chip to use the OTP conﬁguration only.

ExꢁoupiVOTPVPfrnfꢁoolꢂnVApnrflꢅho:

2

• Forces all I C reads from addresses 0-2 to return OTP

1. Apply 15V to the V pin. This can be done at any

data.

P-P

time before step 5.

• ProhibitsanyfurtherprogrammingoftheOTPmemory.

Any further attempts to program OTP leaves the OTP

memory unchanged and sets the FAULT bit in the

CMDR.

2. Write 50h to the CMDR. This disables the power

switches during programming by setting the SWOFF

bit in the CMDR. This also clears the FAULT bit.

3. Write desired data to REG0-REG2.

The LOCK OTP bit is set by programming a logic “1” into

2

bit 6 of OTP2. Regardless of the RSEL2 setting, I C reads

4. Write 11h to the CMDR. This selects REG0 for pro-

gramming while keeping the switches off.

of the LOCK bit always indicate the LOCKed or unlocked

state of the OTP memory.

5. Write 91h to the CMDR. This programs the REG0 data

to OTP0.

OTPVPfrnfꢁoolꢂnV(LT3ꢃ81Vrꢂpy)

6. Write11htotheCMDR.Thiscommandcanbesentim-

mediately after step 5. This stops the programming.

The LT3582 contains One Time Programmable non-vola-

tile memory to permanently store the chip conﬁguration.

Before programming, it’s recommended to set the SWOFF

bit to disable switching activity and prevent unexpected

chip behavior while the conﬁguration is being changed.

Programming involves the transfer of information from

the REG bytes to the OTP bytes. Therefore, valid data must

ﬁrst be written to the desired REG bytes. After the REG

bytes are written, they are selected by setting the cor-

responding RSEL bits in the CMDR. This forces the chip

into the desired conﬁguration and selects those bytes for

7. Read the CMDR and verify that the FAULT bit is not

set.

8. Repeat steps 4-7 for the remaining bytes that need

programming.

9. Write 10h to the CMDR. This selects the OTP data for

read veriﬁcation.

10. Read the OTP data and verify the contents.

programming to OTP. After 15V has been applied to V ,

11. Write 00h to CMDR. This enables the power switches

and the chip will operate from the OTP conﬁgura-

tion.

PP

theWOTPbitissetintheCMDRtostarttheprogramming.

Finally, the WOTP bit is cleared to ﬁnish the programming.

An example programming algorithm is given below.

12. Float the V pin. This can be done at any time after

PP

OTP programming draws about 3mA to 6mA per bit from

step 8.

the V pin. It is possible to program all 23 bits simultane-

PP

ously(upto~138mA),butitisrecommendedthatonebyte

3582512fb

17

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

ChrrelꢂnVꢄꢂdScꢅrfe

PiꢁkVCSffiꢂꢅVRꢁꢅlꢂn:Realinductorscanexperienceadrop

in inductance as current and temperature increase. The

inductors should have saturation current ratings higher

than the peak inductor currents. The peak inductor cur-

rents can be calculated as:

Several series of inductors that work well with the LT3582

series are listed in Table 3. This table is not complete, and

there are many other manufacturers and parts that can

be used. Consult each manufacturer for more detailed

information and for their entire selection of related parts,

as many different sizes and shapes are available.

V_LSWON•T

I_PK≅I_LIMIT

where:

+

^OSmA

L

TꢁbpiV3.VꢄꢂdScꢅrfVMꢁꢂSꢀꢁcꢅSfife

Coilcraft

LPS3008-LPS4018 Series, www.coilcraft.com

XPL2010 Series

I

= Peak inductor current

= Typically 350mA for Boost and 600mA

for Inverting

= Inductance in ꢀH

= Maximum inductor voltage when the

power switch is “on.” Typically max V

for the Boost and Inverting converters.

= 100 for Boost and 125 for Inverting

PK

LIMIT

Murata

Sumida

LQH32C, LQH43C Series

www.murata.com

CDRH26D09, CDRH26D11, www.sumida.com

CDRH3D14 Series

L

V

TDK

VLF and VLCF Series

www.tdk.com

LSWON

OS

Würth

Elektronik

WE-TPC Series Type T, TH, www.we-online.com

XS and S

IN

T

Inductances of 2.2μH to 10ꢀH typically result in a good

tradeoff between inductor size and system performance.

More inductance typically yields an increase in efﬁciency

at the expense of increased output ripple. Less inductance

may be used in a given application depending on required

efﬁciencyandoutputcurrent.Forhigherefﬁciency,choose

inductorswithhighfrequencycorematerial,suchasferrite,

to reduce core losses. Also to improve efﬁciency, choose

inductors with more volume for a given inductance. The

inductor should have low DCR (copper-wire resistance)

2

to reduce I R losses, and must be able to handle the peak

inductor current without saturating. To minimize radiated

noise, use a toroidal or shielded inductor (note that the

inductance of shielded types will drop more as current

increases, and will saturate more easily).

3582512fb

18

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

MꢁxloSoVLrꢁdVCSffiꢂꢅe:VUse one of the following equa-

tions to estimate the maximum output load current for the

positive and negative output voltages:

CꢁuꢁclꢅrfV ipicꢅlrꢂ

The small size and low ESR of ceramic capacitors makes

them suitable for most LT3582 series applications. X5R

andX7Rtypesarerecommendedbecausetheyretaintheir

capacitance over wider voltage and temperature ranges

thanothertypessuchasY5VorZ5U. A4.7μFinputcapaci-

tor and a 2.2μF to 10μF output capacitor are sufﬁcient for

most LT3582 series applications. Always use a capacitor

with a sufﬁcient voltage rating. Many capacitors rated at

2.2μF to 10μF, particularly 0805 or 0603 case sizes, have

greatly reduced capacitance at the desired output voltage.

Generally a 1206 capacitor will be adequate. A 0.22μF to

1μF capacitor placed on the CAPP node is recommended

to ﬁlter the inductor current while the larger 2.2μF to 10μF

I_OUTP

=

⎛

⎜

⎝

_IN(MIN)⎞ ⎛

⎞

⎟

⎠

V

T_{OFF _MIN}•(V_OUTP+ 0.5 – V

)

IN(MIN)

• I

–

•0.8η

⎟ ⎜_PK

V

2 •L

⎠ ⎝

OUTP

or I_OUTN

=

⎛

⎞

⎛

⎞

V

T_{OFF _MIN}•(|V_OUTN|+0.5)

IN(MIN)

⎜

⎝

⎟

• I

–

•0.8η

⎜

⎟

⎠

PK

V_IN(MIN)+|V_OUTN

|

2 •L

⎝

⎠

where:

placed on the V

and V

nodes will give excellent

OUTP

OUTN

V

PK

= Regulation voltage

= Minimum input voltage.

OUT

IN(MIN)

transient response and stability. Avoid placing large value

capacitors (generally > 6.8μF) on brꢅh CAPP and V

.

OUTP

I

= Peak inductor current. See the Peak

This conﬁguration can be less stable since it creates two

poles, one at the CAPP pin and the other at the V

Current Rating section. Use minimum

rating for these calculations.

OUTP

I

LIMIT

pin, which can be near each other in frequency. Table 4

shows a list of several capacitor manufacturers. Consult

the manufacturers for more detailed information and for

their entire selection of related parts.

η

= Power conversion efﬁciency (about 88%

for Boost or 78% for Inverting)

= Minimum switch off time. Typically 100ns

for Boost and 125ns for Inverting.

= Output load current

T

OFF_MIN

I

TꢁbpiV4.VCifꢁolcVCꢁuꢁclꢅrfVMꢁꢂSꢀꢁcꢅSfife

OUT

MANUFACTURER

Kemet

PHONE

URL

For example, if V

= 10V, V

= –10V, V = 5V, and

OUTN IN

OUTP

408-986-0424

814-237-1431

408-573-4150

847-803-6100

www.kemet.com

www.murata.com

www.t-yuden.com

www.tdk.com

L = 4.7μH then I

= 117mA and I

= 105mA.

OUTN

Murata

Note: The 155mA (Typ) current limit of the output dis-

connect PMOS (see Electrical Characteristics) may limit

Taiyo Yuden

TDK

maximum I

unless CAPP is shorted to V

. See the

OUTP

Improving Boost Converter Efﬁciency section.

DlrdiV ipicꢅlrꢂ

MꢁxloSoV piwVRꢁꢅi: Lower inductance causes higher

Schottky diodes, with their low forward voltage drops and

fast switching speeds, are recommended for use with the

LT3582 series. The Diodes Inc. B0540WS is a very good

choice in a small SOD-323 package. This diode is rated to

handleanaverageforwardcurrentof500mAandperforms

well across a wide temperature range. Schottky diodes

with very low forward voltage drops are also available.

Thesediodesmayimproveefﬁciencyatmoderateandcold

temperatures, but will likely reduce efﬁciency at higher

temperatures due to excessive reverse leakage currents.

current slew rates which can lead to current limit over-

shoot. Choose an inductance higher than L

the overshoot:

to limit

MIN

L

= V

• 0.2ꢀH

MIN

IN(MAX)

where V

is the maximum input voltage. Using the

IN(MAX)

previous example V = 3V, L

= 0.6μH.

IN

MIN

3582512fb

19

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

OSꢅuSꢅVDlecrꢂꢂicꢅVOuifꢁꢅlꢂnVLlolꢅe

ꢄoufrvlꢂnVBrreꢅVCrꢂvifꢅifVEꢀﬁVcliꢂcy

The LT3582 series has a PMOS output disconnect switch

The efﬁciency of the Boost converter can be improved by

connected between CAPP and V

. During normal

shortingtheCAPPpintotheV

pin(seeFigure11).The

OUTP

operation, the switch is closed and current is internally

limited to about 155mA (see Figure 9). Make sure that the

outputloadcurrentdoesn’texceedthePMOScurrentlimit.

ExceedingthecurrentlimitcausesasigniﬁcantriseinPMOS

power consumption which may damage the device.

power loss in the PMOS disconnect circuit is then made

negligible. In most applications, the associated CAPP pin

capacitor can be removed and the larger V

can adequately ﬁlter the output voltage.

capacitor

OUTP

During shutdown, the PMOS switch is open and CAPP is

isolated from V

up to a voltage difference of 5-5.5V.

OUTP

In most cases this allows V

to discharge to ground.

I

CAPP-VOUTP

20ꢀA/DIV

OUTP

However, when the Boost inductor input exceeds 5.5V, the

CAPP-V voltagemayexceed5Vallowingsomecurrent

OUTP

ﬂowthroughthePMOSswitch.Inaddition,applyingCAPP-

voltages in excess of 5.7V(typical) may activate

V

OUTP

internal protection circuitry which turns the PMOS “on”

(see Figure 10). If the current is not limited, this can lead

to a sharp increase in the PMOS power consumption and

maydamagethedevice.Ifthissituationcannotbeavoided,

limitPMOSpowerconsumptiontolessthan1/3Watt(about

50mA at 7V) to avoid damaging the device. Refer to the

Absolute Maximum Ratings table for maximum limits on

3582512 F11

V

1V/DIV

CAPP-VOUTP

FlnSfiV±0.VPMO VCSffiꢂꢅVveV2rpꢅꢁniVDSflꢂnV hSꢅdrwꢂ

4

3

12

5

SWN

SWP

CAPP-V

voltages and currents.

V

IN

OUTP

11

10

180

160

140

120

100

80

CAPP

13

2

GND

C1

I

LOAD

LT3582

9

V

OUTP

V

OUTN

14

15

16

1

V

PP

SDA

SCL

CA

60

8

SHDN

RAMPP RAMPN

40

7

6

3582512 F12

20

0

FlnSfiV±±.VꢄoufrvidVEꢀﬁVcliꢂcy

0

100

200

CAPP-V

300

(mV)

400

500

OUTP

3582512 F10

FlnSfiV9.VPMO VCSffiꢂꢅVveV2rpꢅꢁniVDSflꢂnVNrfoꢁpVOuifꢁꢅlrꢂ

3582512fb

20

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

the switching regulator to minimize interplane coupling.

Suggested component placement is shown in Figure 12.

Make sure to include the ground plane cuts as shown in

Figure12.Theswitchingactionoftheregulatorscancause

large current steps in the ground plane. The cuts reduce

noise by recombining the current steps into a continuous

ﬂow under the chip, thus reducing di/dt related ground

noise in the ground plane.

NotethattheripplevoltageonV

willtypicallyincrease

OUTP

in this conﬁguration since the output disconnect PMOS,

when not shorted, helps to create an RC ﬁlter at the

output. Also, if the V

pin is shorted to CAPP, the

OUTP

power-down discharge should not be enabled. V

OUTP

cannot be discharged to ground during shutdown due to

the path from V to V through the external inductor

IN

OUTP

and diode. Finally, due to the path from V to V

,

IN

OUTP

current will ﬂow through the integrated feedback resistor

CA SCL SDA VPP

whenever voltage is present on V .

IN

C

VPP

(OPT)

ꢄꢂfSehVCSffiꢂꢅ

16

15

14

13

When the Boost inductor input voltage (usually V ) is

IN

L1

V

OUTN

1

2

12

stepped from ground to the operating voltage, a high

level of inrush current may ﬂow through the inductor

and Schottky diode into the CAPP capacitor. Conditions

that increase inrush current include a larger more abrupt

voltage step at the inductor input, larger CAPP capacitors

and inductors with low inductances and/or low saturation

currents.Forcircuitsthatuseoutputcapacitorvalueswithin

the recommended range and have input voltages of less

than 5V, inrush current remains low, posing no hazard to

the devices. In cases where there are large input voltage

steps (more than 5V) and/or a large CAPP capacitor is

used, inrush current should be measured to ensure safe

operation.

C

OUTN

C

17

CAPP

11

3

4

10

9

L2

GND

OUTP

C

5

6

7

8

IN

V

OUTP

SHDN

V

IN

VIAS TO GROUND PLANE UNDER

PIN 17 REQUIRED TO IMPROVE

THERMAL PERFORMANCE

ThifoꢁpVLrckrSꢅ

If the die temperature reaches approximately 147°C, the

part will go into thermal lockout. In this event, the chip

is reset which turns off the power switches and starts to

dischargetheRAMPcapacitors.Thepartwillbere-enabled

when the die temperature drops by about 3.5°C.

GROUND PLANE

BrꢁfdVLꢁyrSꢅVCrꢂeldifꢁꢅlrꢂe

3582512 F13

As with all switching regulators, careful attention must be

paidtothePCBboardlayoutandcomponentplacement.To

maximize efﬁciency, switch rise and fall times are made as

shortaspossible.Topreventelectromagneticinterference

(EMI) problems, proper layout of the high frequency

switching path is essential. The voltage signals of the

SWP and SWN pins have sharp rising and falling edges.

Minimize the length and area of all traces connected to

the SWP/SWN pins and always use a ground plane under

FlnSfiV±1.V SnnieꢅidVCrourꢂiꢂꢅVPpꢁcioiꢂꢅV(NrꢅVꢅrV cꢁpi)

3582512fb

21

LT3582/LT3582-5/LT3582-12

APPLICATIONS INFORMATION

SWN

SHDN

INPUT

V

IN

4.5V TO 5.5V

D1

L1

SWP

6.8ꢀH

L2

6.8ꢀH

GND

C1

4.7ꢀF

D2

LT3582

C4

1ꢀF

C2

4.7ꢀF

V

CAPP

NEG

–12V

V

OUTN

85mA

V

POS

2

SDA

SCL

CA

I C

12V

V

OUTP

INTERFACE

OPTIONAL ON

LT3582-12

80mA

V

PP

C3

ꢀ

ꢁ

RAMPP RAMPN

3582512 TA05a

C5

10nF

C6

10nF

REG0/OTP0 = B0h D1-D2: DIODES INC. B0540WS-7

REG1/OTP1 = D8h L1-L2: COILCRAFT XPL2010-682

REG2/OTP2 = 03h C1: 4.7ꢀF, 6.3V, X5R, 0805

C2: 4.7ꢀF, 16V, X5R, 0805

C3: 1s 4.7ꢀF OR 2s 4.7ꢀF OR 10ꢀF

16V, X5R, 0805

C4: 1ꢀF, 16V, X5R, 0603

C5-C6: 10nF, 0603

FlnSfiV±3.V±±12VOSꢅuSꢅeVꢀfroVꢁV lꢂnpiVꢃ2VꢄꢂuSꢅ

2_OUTPVRluupi

2_OUTNVRluupiVꢁꢂdVC1V ipicꢅlrꢂ

80

60

40

20

0

25

20

15

10

5

4.7ꢀF 16V 0805 X5R

10ꢀF 16V 0805 X5R

2× 4.7ꢀF 16V 0805 X5R

0

20

40

60

80

0

20

40

60

80

LOAD CURRENT (mA)

3582512 TA05c

3582512 TA05b

AperV iiVTyulcꢁpVChꢁfꢁcꢅifleꢅlceVꢁꢂdVFfrꢂꢅVPꢁniVꢀrfVAddlꢅlrꢂꢁpVDꢁꢅꢁ

3582512fb

22

LT3582/LT3582-5/LT3582-12

TYPICAL APPLICATION

±ꢃ2VOSꢅuSꢅeVꢀfroVꢁV lꢂnpiV1.72VꢅrV3.82VꢄꢂuSꢅ

SWN

SHDN

INPUT

V

IN

D1

L1

2.7V TO 3.8V

6.8ꢀH

SWP

L2

6.8ꢀH

GND

C1

4.7ꢀF

D2

C4

1ꢀF

LT3582

C2

10ꢀF

V

NEG

CAPP

–5V

V

OUTN

100mA (V ≥ 2.7V)

IN

V

POS

5V

100mA (V ≥ 2.7V)

124mA (V ≥ 3.3V)

IN

125mA (V ≥ 3.3V)

IN

2

SDA

SCL

CA

I C

V

OUTP

IN

INTERFACE

OPTIONAL ON

LT3582-5

V

PP

C3

10ꢀF

ꢀ

ꢁ

RAMPP RAMPN

3582512 TA02a

C5

22nF

C6

22nF

REG0/OTP0 = 24h D1-D2: DIODES INC. B0540WS-7

REG1/OTP1 = 4Ch L1-L2: COILCRAFT LPS4018-682ML

REG2/OTP2 = 03h C1: 4.7ꢀF, 6.3V, X5R, 0805

C2-C3: 10ꢀF, 6.3V, X5R 0805

C4: 1ꢀF, 6.3V, X5R, 0603

C5-C6: 22nF, 0603

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTPVꢅrVGND

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTNVꢅrVGND

100

90

80

70

60

50

40

30

20

10

0

95

85

75

65

55

45

35

180

160

140

120

100

80

95

85

75

65

55

45

35

V

= 3.3V

V

= 3.3V

IN

60

40

20

0

100

0.1

1

10

100

0.1

1

10

LOAD CURRENT (mA)

3582512 TA02b

3582512 TA02c

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTPVꢅrV2_OUTN

300

250

200

150

100

50

95

85

75

65

55

45

35

V

= 3.3V

IN

0

100

0.1

1

10

LOAD CURRENT (mA)

3582512 TA02d

3582512fb

23

LT3582/LT3582-5/LT3582-12

TYPICAL APPLICATION

±ꢃ2VOSꢅuSꢅeVꢀfroVꢁV lꢂnpiV1.72VꢅrV3.82VꢄꢂuSꢅV(ꢄoufrvidVEꢀﬁVcliꢂcy)

SWN

SHDN

INPUT

V

IN

D1

L1

2.7V TO 3.8V

6.8ꢀH

SWP

L2

6.8ꢀH

GND

C1

4.7ꢀF

D2

C3

10ꢀF

LT3582

C2

10ꢀF

V

NEG

CAPP

–5V

V

OUTN

100mA (V ≥ 2.7V)

IN

V

POS

125mA (V ≥ 3.3V)

IN

2

5V

SDA

SCL

CA

I C

V

OUTP

110mA (V ≥ 2.7V)

150mA (V ≥ 3.3V)

IN

INTERFACE

OPTIONAL ON

LT3582-5

V

PP

ꢀ

ꢁ

RAMPP RAMPN

3582512 TA03

C5

22nF

C6

22nF

REG0/OTP0 = 24h D1-D2: DIODES INC. B0540WS-7

REG1/OTP1 = 4Ch L1-L2: COILCRAFT LPS4018-682ML

REG2/OTP2 = 03h C1: 4.7ꢀF, 6.3V, X5R, 0805

C2-C3: 10ꢀF, 6.3V, X5R, 0805

C4: 1ꢀF, 6.3V, X5R, 0603

C5-C6: 22nF, 0603

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTPVꢅrVGND

95

85

75

65

55

45

35

80

70

60

50

40

30

20

10

0

V

= 3.3V

IN

0.1

1

10

100

LOAD CURRENT (mA)

3582512 TA03a

3582512fb

24

LT3582/LT3582-5/LT3582-12

TYPICAL APPLICATION

±12VꢁꢂdV–ꢃ2VOSꢅuSꢅeVꢀfroVꢁV lꢂnpiV1.72VꢅrVꢃ.ꢃ2VꢄꢂuSꢅ

SWN

SHDN

INPUT

V

IN

D1

L1

2.7V TO 5.5V

6.8ꢀH

SWP

L2

6.8ꢀH

GND

C1

D2

C4

1ꢀF

LT3582

4.7ꢀF

C2

10ꢀF

V

NEG

CAPP

–5V

V

OUTN

100mA

V

POS

12V

SDA

SCL

CA

V

OUTP

2

I C

38mA (V = 2.7)

IN

C3

4.7ꢀF

V

INTERFACE

PP

58mA (V = 3.6)

IN

95mA (V = 5.5)

IN

RAMPP RAMPN

3582512 TA04a

C5

22nF

C6

22nF

REG0/OTP0 = B0h D1-D2: DIODES INC. B0540WS-7

REG1/OTP1 = 4Ch L1-L2: COILCRAFT LPS4018-682ML

REG2/OTP2 = 0Bh C1: 4.7ꢀF, 6.3V, X5R, 0805

C2: 10ꢀF, 6.3V, X5R, 0805

C3: 4.7ꢀF, 16V, X5R, 0805

C4: 1ꢀF, 16V, X5R, 0603

C5-C6: 22nF, 0603

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTNVꢅrVGND

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTPVꢅrVGND

180

160

140

120

100

80

95

85

75

65

55

45

35

100

90

80

70

60

50

40

30

20

10

0

95

85

75

65

55

45

35

V

= 3.6V

V

= 3.6V

IN

60

40

20

0

100

0.1

1

10

0.1

1

10

100

LOAD CURRENT (mA)

3582512 TA04c

3582512 TA04b

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTPVꢅrV2_OUTN

95

85

75

65

55

45

35

200

180

160

140

120

100

80

V

= 3.6V

IN

60

40

20

0

100

0.1

1

10

LOAD CURRENT (mA)

3582512 TA04d

3582512fb

25

LT3582/LT3582-5/LT3582-12

PACKAGE DESCRIPTION

UDVPꢁckꢁni

±6-LiꢁdVPpꢁeꢅlcVQFNV(3ooV×V3oo)

(Reference LTC DWG # 05-08-1691)

0.70 p0.05

3.50 p 0.05

2.10 p 0.05

1.45 p 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 p0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 s 45o CHAMFER

R = 0.115

TYP

0.75 p 0.05

3.00 p 0.10

(4 SIDES)

15 16

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

1

2

1.45 p 0.10

(4-SIDES)

(UD16) QFN 0904

0.200 REF

0.25 p 0.05

0.00 – 0.05

0.50 BSC

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3582512fb

26

LT3582/LT3582-5/LT3582-12

REVISION HISTORY ^{(RivlelrꢂVhleꢅrfyVbinlꢂeVꢁꢅVRivVB)}

RE2

DATE

DE CRꢄPTꢄON

PAGEVNUMBER

B

11/09 Revised Title and Add text to Description

Revised Pin Conﬁguration

1

2

11

2

Added Text to I C Interface Section

Revised Typical Application Drawings

22, 23, 24

3582512fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LT3582/LT3582-5/LT3582-12

TYPICAL APPLICATION

TlꢂyVAMOLEDVPrwifV SuupyVleV0.8ooV(Mꢁx)VThlꢂ

EꢀﬁVcliꢂcyVꢁꢂdVPrwifVLree,VLrꢁdVꢀfroV2_OUTPVꢅrV2_OUTN

90

80

70

60

50

40

30

350

300

250

200

150

100

50

V

= 3.3V

SWN

SHDN

IN

INPUT

V

IN

2.7V TO 4.2V

L1

D1

SWP

1.5ꢀH

L2

1.5ꢀH

GND

C1

10ꢀF

D2

LT3582

C4

10ꢀF

C2

10ꢀF

V

CAPP

NEG

–5V

V

OUTN

90mA

V

POS

SDA

SCL

CA

4.6V

V

OUTP

2

I C

INTERFACE

100mA

V

PP

C3

10ꢀF

0

100

RAMPP RAMPN

3582512 TA06a

0.1

1

10

C5

10nF

C6

10nF

LOAD CURRENT (mA)

3582512 TA06b

REG0/OTP0 = 1Ch D1-D2: PANASONIC M21D3800L LOW V SCHOTTKY

F

REG1/OTP1 = 4Ch L1-L2: TDK MLP3216S1R5L

REG2/OTP2 = 07h C1-C4: TAIYO YUDEN JMK212BJ106MK, 6.3V, X5R 0805

C5-C6: 0402 X5R

RELATED PARTS

PART

DE CRꢄPTꢄON

COMMENT

V : 1.2V to 15V, V

LT1944/LT1944-1(Dual) Dual Output 350mA I , Constant Off-Time,

= 34V, I = 20ꢀA, I <1ꢀA, MS10

Q SD

SW

IN

OUT(MAX)

High Efﬁciency Step-Up DC/DC Converter

LT1945(Dual)

Dual Output, Pos/Neg, 350mA I , Constant Off-Time, V : 1.2V to 15V, V

=

34V, I = 20ꢀA, I <1ꢀA, MS10

Q SD

SW

IN

High Efﬁciency Step-Up DC/DC Converter

LT3463/LT3463A

Dual Output, Boost/Inverter, 250mA I , Constant

V : 2.4V to 15V, V

IN

40V, I = 40ꢀA, I <1ꢀA, DFN

Q SD

SW

Off-Time, High Efﬁciency Step-Up DC/DC Converter

with Integrated Schottkys

LT3471

Dual Output, Boost/Inverter, 1.3A I , 1.2MHz,

V : 2.4V to 16V, V

=

40V, I = 2.5mA, I <1ꢀA, DFN

Q SD

SW

IN

OUT(MAX)

High Efﬁciency Boost-Inverting DC/DC Converter

LT3472

Dual Output, Boost/Inverter, 0.35A I , 1.2MHz, High

V : 2.2V to 16V, V

34V, I = 2.8mA, I <1ꢀA, DFN

Q SD

SW

IN

Efﬁciency Boost-Inverting DC/DC Converter

LT3477

42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver

V : 2.5V to 25V, V

= 40V, I = Analog/PWM, I <1ꢀA,

Q SD

IN

QFN, TSSOP-20E

LT3494/LT3494A

180/350mA (I ), Low Noise High Efﬁciency Step-Up V : 2.3V to 16V, V

= 40V, I = 65ꢀA, I <1ꢀA,

Q SD

SW

IN

DC/DC Converter

2mm × 3mm DFN

LT3495/LT3495B/

LT3495-1/LT3495B-1

650/350mA (I ), Low Noise High Efﬁciency Step-Up V : 2.5V to 16V, V

= 40V, I = 60ꢀA, I <1ꢀA,

Q SD

SW

IN

DC/DC Converter

2mm × 3mm DFN

LT1930/LT1930A

LT1931/LT1931A

LT3467/LT3467A

LT1618

1A (I ), 1.2/2.2MHz, High Efﬁciency Step-Up

V : 2.6V to 16V, V

= 34V, I = 4.2/5.5mA, I <1ꢀA,

Q SD

SW

IN

DC/DC Converter

ThinSOT™

1A (I ), 1.2/2.2MHz, High Efﬁciency Inverting DC/DC V : 2.6V to 16V, V

= 34V, I = 4.2/5.5mA, I <1ꢀA, ThinSOT

Q SD

SW

IN

Converter

1.1A (I ), 1.3/2.1MHz, High Efﬁciency Step-Up DC/DC V : 2.4V to 16V, V

= 40V, I = 1.2mA, I <1ꢀA, ThinSOT

Q SD

SW

IN

Converter with Soft-Start

1.5A (I ), 1.4MHz, High Efﬁciency Step-Up

V : 1.6V to 18V, V

IN

= 35V, I = 1.8mA, I <1ꢀA, MS10, DFN

Q SD

SW

DC/DC Converter

LT1946/LT1946A

1.5A (I ), 1.2/2.7MHz, High Efﬁciency Step-Up DC/DC V : 2.6V to 16V, V

= 34V, I = 3.2mA, I <1ꢀA, MS8E

Q SD

SW

IN

Converter

ThinSOT is a trademark of Linear Technology Corporation.

3582512fb

LT 0110 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3582-5_15
厂家：	Linear
描述：	Boost and Single Inductor Inverting DC/DC Converters with Optional I2C Programing and OTP
文件：	总28页 (文件大小：326K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3582-5_15 [Linear]

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