LT3640EUFDPBF [Linear]
Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer; 双通道单片式降压型稳压器具有上电复位和看门狗定时器
| 型号： | LT3640EUFDPBF |
| 厂家： | 
Linear |
| 描述： | Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer |
| 文件： | 总24页 (文件大小：566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electrical Specifications Subject to Change
LT3640
Dual Monolithic Buck
Regulator with Power-On
Reset and Watchdog Timer
FEATURES
DESCRIPTION
The LT®3640 is a dual channel, current mode monolithic
buck switching regulator with a power-on reset and a
watchdog timer. Both regulators are synchronized to a
single oscillator with an adjustable frequency (350kHz to
2.5MHz). At light loads, both regulators operate in low
ripple Burst Mode® to maintain high efficiency and low
output ripple.
n
High Voltage Buck Regulator:
4V to 36V Operating Range
1.3A Output Current
n
OVLO Protects Input to 55V
n
Low Voltage Synchronous Buck Regulator:
2.5V to 5.5V Input Voltage Range
1A Output Current
n
Synchronizable, Adjustable 350kHz to 2.5MHz
The high voltage channel is a nonsynchronous buck with
an internal 2.4A top switch that operates from an input
of 4V to 36V; a 38V OVLO protects the device to 55V. The
low voltage channel operates from an input of 2.5V to
5.5V. Internal synchronous power switches provide high
efficiency without the need of external Schottky diode.
Bothchannelshavecycle-by-cyclecurrentlimit,providing
protection against shorted outputs.
Switching Frequency
Programmable Power-On Reset Timer
n
n
Programmable Window Mode Watchdog Timer
n
Quiescent Current: 275μA
n
Short-Circuit Robust
n
Programmable Soft-Start
n
Low Shutdown Current: I < 1μA
Q
n
Available in Thermally Enhanced 28-Lead
The power-on reset and watchdog timeout periods are
both adjustable using external capacitors. The window
mode watchdog timer flags when the μP pulses group
too close together or too far apart.
(4mm × 5mm) QFN and 28-Lead TSSOP Packages
APPLICATIONS
n
Industrial Power Supplies
Automotive Electronic Control Units
The LT3640 is available in a 28-pin 4mm × 5mm QFN
package and 28-pin TSSOP package. Both packages have
an exposed pad for low thermal resistance.
n
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
2MHz 3.3V/0.8A and 1.8V/0.8A Step Down Regulators
HV Channel Efficiency,
2MHz, VOUT1 = 3.3V
LV Channel Efficiency,
2MHz, VOUT2 = 1.8V
0.22μF
V
IN
5V TO 34V
10μF
3.3μH
80.6k
90
85
80
75
70
90
85
80
75
70
V
OUT1
EN/UVLO
V
SW
BST SW1
IN
3.3V/0.8A
V
IN2
= 3.3V
SYNC
PGOOD
WDE
22μF
DA
FB1
V
IN
= 12V
49.9k
10μF
V
OUT1
100k
100k
μP
LT3640
V
IN2
RST1
RST2
WDO
WDI
EN2
1μH
V
OUT2
SW2
1.8V/0.8A
100k
47μF
CWDT
CPOR
FB2
RT GND SS2 SS1
49.9k
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1
1nF
1.5nF
1.5nF
32.4k
V
CURRENT (A)
V
OUT2
CURRENT (A)
OUT1
1nF
3640 TA01b
3640 TA01c
3640 TA01a
3640p
1
LT3640
(Note 1)
ABSOLUTE MAXIMUM RATINGS
V , EN/UVLO Voltage (Note 7).................................55V
SW2 Voltage ................................–0.3V to (V + 0.3V)
IN
IN2
WDE Voltage.............................................................30V
BST Above SW, SW1 Voltage....................... –0.3V to 6V
SW1 Above SW Voltage............................... –0.3V to 6V
DA Current..................................................................2A
Operating Junction Temperature Range (Note 2)
LT3640E................................................. –40°C to 125°C
LT3640I.................................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature, FE Only (Soldering, 10 sec) .... 300°C
V
, SYNC, EN2, PGOOD, WDI,
IN2
WDO, RST1, RST2, Voltages ....................... –0.3V to 6V
SS1, SS2, FB1, FB2, RT, CWDT,
CPOR Voltages……….............................. –0.3V to 2.5V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
SS2
EN2
GND
SW2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FB2
PGOOD
EN/UVLO
SYNC
SS1
3
28 27 26 25 24 23
4
SYNC
SS1
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
SW2
5
V
IN2
V
IN2
6
GND
FB1
FB1
GND
7
V
RT
IN
RT
V
29
GND
IN
29
8
BST
SW
RST2
RST1
WDO
RST2
RST1
WDO
CWDT
BST
SW
SW1
DA
9
10
11
12
13
14
SW1
DA
CWDT
CPOR
WDE
9
10 11 12 13 14
UFD PACKAGE
NC
GND
GND
WDI
28-LEAD (4mm s 5mm) PLASTIC QFN
= 34°C/W
FE PACKAGE
θ
28-LEAD PLASTIC TSSOP
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
θ
= 30°C/W
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3640EFE#PBF
LT3640IFE#PBF
TAPE AND REEL
PART MARKING*
LT3640FE
LT3640FE
3640
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3640EFE#TRPBF
LT3640IFE#TRPBF
LT3640EUFD#TRPBF
LT3640IUFD#TRPBF
28-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
28-Lead Plastic TSSOP
LT3640EUFD#PBF
LT3640IUFD#PBF
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
3640
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3640p
2
LT3640
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
3.6
MAX
4
UNITS
l
l
l
l
V
IN
V
IN
V
IN
V
IN
Undervoltage Lockout Threshold
Undervoltage Release Threshold
Overvoltage Lockout Threshold
Overvoltage Release Threshold
V
V
V
V
3.8
4.2
38
35
34
36.5
35.5
37
Quiescent Current from V
EN/UVLO = 0.3V
Not Switching
0.1
275
1
375
μA
μA
IN
EN/UVLO Threshold Voltage
EN/UVLO High Bias Current
EN/UVLO Low Bias Current
SYNC Input Frequency
1.2
1.26
2
1.3
V
μA
EN/UVLO = Threshold + 60mV
EN/UVLO = Threshold – 60mV
0.1
μA
0.35
0.4
2.5
1
MHz
V
SYNC Threshold Voltage
Switching Frequency
0.8
l
l
RT = 32.4k
RT = 182k
1.75
450
2
500
2.35
550
MHz
kHz
l
FB1 Voltage
1.24
1.265
30
1.29
100
V
nA
FB1 Bias Current
FB1 Line Regulation
SW1 Minimum Off-Time
FB1 = 1.265V
5V < V < 30V
0.001
70
%/V
ns
IN
SW1 V
I
= 800mA
SW1
400
0.1
mV
μA
CESAT
SW1 Leakage Current
SW1 Current Limit
1
l
l
FB1 = 1V (Note 3)
FB1 = 0.1V
2.2
1.1
2.8
1.8
3.3
A
A
DA Current limit
FB1 = 1V (Note 4)
FB1 = 0.1V
1.35
0.8
1.7
A
A
BST Pin Current
I
= 800mA
30
2
50
2.7
130
90
mA
V
SW1
Minimum BST-SW Voltage
ΔFB1 to Start LV Channel
ΔFB1 Hysteresis to Stop LV Channel
80
30
100
50
mV
mV
V
l
l
V
V
Minimum Operating Voltage
Maximum Operating Voltage
2.3
2.5
5.5
1.5
612
100
IN2
IN2
V
EN2 Threshold Voltage
FB2 Voltage
0.3
1
V
l
588
600
0
mV
nA
%/V
ns
FB2 Bias Current
FB2 = 0.6V
FB2 Line Regulation
SW2 Minimum Off-Time
SW2 PMOS Current Limit
SW2 NMOS Current Limit
2.5V < V < 5.5V
0.01
70
IN2
l
l
(Note 5)
(Note 5)
1.5
0.9
1.9
1.1
275
200
40
2.2
1.3
A
A
SW2 PMOS R
SW2 NMOS R
I
I
= 0.5A (Note 6)
= 0.5A (Note 6)
mΩ
mΩ
mV
mV
mV
DS(ON)
DS(ON)
SW2
SW2
ΔFB2 to Enable PGOOD
ΔFB2 Hysteresis to Disable PGOOD
PGOOD Voltage
20
20
80
80
40
FB2 = 0.6V, I
= 1mA
200
320
PGOOD
3640p
3
LT3640
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
1.9
5
MAX
2.5
30
UNITS
μA
mV
mV
%
SS1, SS2 Charge Current
SS1 = 0.5V, SS2 = 0.5V
SS1 = 0.6V
1.4
SS1 to FB1 Offset Voltage
SS2 to FB2 Offset Voltage
SS2 = 0.3V
5
30
l
l
RST1 Threshold as Percentage of V
RST2 Threshold as Percentage of V
Undervoltage to RST Assert Time
RST1, RST2, WDO Pull-Up Current
RST1, RST2, WDO Output Voltage
90
89
92
92
20
15
150
9.5
16
32
2
94
FB
94
%
FB
μs
RST1, RST2, WDO = 0V
5
30
250
11
μA
mV
ms
ms
ms
ms
μA
V
I
, I
, I
= 2mA
RST1 RST2 WDO
l
RST1, RST2 Timeout Period (t
)
CPOR = 220pF
CWDT = 820pF
CWDT = 820pF
CWDT = 820pF
WDI = 1.2V
8
14
RST
Watchdog Start Delay Time (t
Watchdog Upper Boundary (t
Watchdog Lower Boundary (t
WDI Pull-Up Current
)
DLY
18
l
l
)
27
35
WDU
)
1.68
2.2
WDL
2
WDI Voltage Threshold
0.55
300
300
0.85
1.15
0.9
WDI Low Minimum Pulse Width
WDI High Minimum Pulse Width
WDE Pull-Down Current
WDE Threshold
ns
ns
WDE = 2V
1
μA
V
l
0.5
0.7
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation
to static test. Slope compensation reduces current limit at higher duty
cycle.
Note 4: The oscillator cycle is extended when DA current exceeds its limit.
Note 2: The LT3640E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3640I is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range.
DA current limit is flat over duty cycle.
Note 5: If the SW2 NMOS current exceeds its limit at the start of an
oscillator cycle, the PMOS will not be turned on in the cycle.
Note 6: The QFN switch R
is guaranteed by correlation to wafer level
DS(ON)
measurement.
Note 7: Absolute maximum voltage at V and RUN/SS pin is 55V for
IN
nonrepetitive one second transients, and 36V for continuous operation.
3640p
4
LT3640
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
HV Channel Efficiency
(2MHz, VOUT1 = 5V)
LV Channel Efficiency
(2MHz, VOUT2 = 1.2V)
HV Channel Efficiency
(2MHz, VOUT1 = 3.3V)
90
85
80
75
70
90
85
80
75
70
90
85
80
75
70
V
= 12V
IN
V
= 12V
IN
V
= 24V
IN
V
= 16V
IN
V
= 3.3V
V
= 16V
= 24V
IN2
IN
V
= 5V
IN2
V
IN
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
V
CURRENT (A)
V
CURRENT (A)
V
OUT2
CURRENT (A)
OUT1
OUT1
3640 G01
3640 G02
3640 G03
LV Channel Efficiency
(2MHz, VOUT2 = 1.8V)
Quiescent Current vs VIN
Quiescent Current vs Temperature
0.35
0.30
350
300
90
85
80
75
70
V
= 3.3V
IN2
0.25
250
V
= 5V
IN2
0.20
0.15
0.10
0.05
200
150
100
50
0.00
0
20
30
40
50
100
150
0
10
–50
0
0
0.2
0.4
0.6
0.8
1.0
V
CURRENT (A)
V
VOLTAGE (V)
IN
TEMPERATURE (°C)
OUT2
3640 G05
3640 G06
3640 G04
FB1 Voltage vs SS1
FB1 Voltage vs Temperature
FB2 Voltage vs Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.70
0.65
0.60
0.55
0.50
0.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
REGULATION
REGULATION
RST1 THRESHOLD
RST2 THRESHOLD
0
1.0
1.5
2.0
50
100
150
0.5
–50
0
50
100
150
–50
0
SS1 VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3640 G08
3640 G09
3640 G07
3640p
5
LT3640
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency
vs Temperature
HV Channel Current Limit
vs Duty Cycle
FB2 Voltage vs SS2
0.52
0.51
0.50
0.49
0.48
2.5
2.0
1.5
1.0
0.5
0.0
700
600
500
400
300
200
100
0
0
40
60
80
100
0
400
6000
800
1000
–50
0
50
100
150
20
200
TEMPERATURE (°C)
DUTY CYCLE (%)
SS2 VOLTAGE (mV)
3640 G11
3640 G12
3640 G10
LV Channel Peak Current Limit
vs Duty Cycle
LV Channel Switch Voltage
Drop vs Current (VIN2 = 3.3V)
VOUT1 Minimum Load to Run at
Full Frequency (VOUT1 = 3.3V)
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
450
400
350
300
250
200
150
100
50
2.0
1.5
1.0
0.5
0.0
2.5MHz
2MHz
PMOS
NMOS
0
0
5
10
V
15
20
25
30
0.5
1
1.5
0
0
40
60
80
100
20
VOLTAGE (V)
SW2 CURRENT (A)
DUTY CYCLE (%)
IN
3640 G15
3640 G14
3640 G13
HV Channel Switching Frequency
(VOUT1 = 3.3V)
LV Channel Switching Frequency
(VOUT2 = 1.8V)
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
V
= 3.3V
V
= 12V
IN2
IN
V
= 16V
V
= 5V
IN
IN2
V
= 24V
IN
0
0.4
CURRENT (A)
OUT2
0.6
0.8
1.0
0.2
0
0.4
0.6
0.8
1.0
1.2
0.2
V
V
CURRENT (A)
OUT1
3640 G17
3640 G16
3640p
6
LT3640
T = 25°C, unless otherwise noted.
A
TYPICAL PERFORMANCE CHARACTERISTICS
Watchdog Upper Boundary
Period vs CWDT
Full Frequency Waveforms
PFM Operation Waveforms
180
160
140
120
100
80
SW1
10V/DIV
SW1
10V/DIV
I
L1
I
L1
0.5A/DIV
0.5A/DIV
SW2
5V/DIV
SW2
5V/DIV
60
40
I
L2
I
L2
20
0.5A/DIV
0.5A/DIV
0
3640 G19
3640 G18
0
1000
2000
3000
4000
5000
200ns/DIV
200ns/DIV
C
CAPACITANCE (pF)
WDT
V
V
= 12V
OUT1
V = V
IN2 OUT1
V
V
= 12V
OUT1
V
OUT2
= V
IN1
IN1
IN2 OUT1
3640 G20
= 3.3V/25mA
V
= 1.8V/30mA
= 3.3V/0.5A
V
= 1.8V/0.5A
OUT2
Watchdog Upper Boundary
Period vs Temperature
RST/WDO Pull-Up Current
35
30
20
15
10
5
25
20
15
10
5
0
0
50
100
150
–50
0
1
1.5
2
0
0.5
TEMPERATURE (°C)
RST/WDO VOLTAGE (V)
3640 G21
3640 G22
3640p
7
LT3640
PIN FUNCTIONS (FE/QFN)
FB2(Pin1/Pin26):Thelowvoltageconverterregulatesthe
FB2 pin to 600mV. Connect the feedback resistor divider
tap to this pin to set output voltage.
WDE (Pin 13/Pin 10): Watchdog Enable Pin.
WDI (Pin 14/Pin 11): The WDI pin receives watchdog
signals from a microprocessor.
PGOOD (Pin 2/Pin 27): Open-drain logic output that starts
to sink current when FB2 is in regulation.
GND (Pins 15, 16, 23, 26, Exposed Pad 29/Pins 12, 13,
20, 23, Exposed Pad 29): Ground. These pins must be
soldered to PCB ground.
EN/UVLO (Pin 3/Pin 28): Pull this pin below 0.3V to shut
down the LT3640. The 1.26V threshold can function as an
accurateundervoltagelockout,preventingtheLT3640from
NC (Pin 17/Pin 14): Not Connected.
DA (Pin 18/Pin 15): The DA pin is used to sense the catch
diodecurrentforcurrentlimitandprotection.Connectthis
pin to catch diode anode.
operating until V voltage has reached the programmed
IN
level.
SYNC (Pin 4/Pin 1): Driving the SYNC pin with an external
clock signal synchronizes both converters to the applied
frequency. The lowest external clock frequency should be
20% higher than the internal oscillator frequency.
SW1 (Pin 19/Pin 16): Output of the High Voltage Internal
Power Switch. Connect this pin to the inductor and catch
diode cathode.
SW (Pin 20/Pin 17): The SW pin is used to charge the
SS1 (Pin 5/Pin 2): The SS1 pin sets the FB1 voltage ex-
ternally between 0V and 1.265V, providing soft-start and
tracking. Tie this pin 1.5V or higher to use the internal
1.265Vreference. Acapacitortogroundatthispinsetsthe
ramp time to regulated output voltage for the high voltage
converter. Use a resistor divider to track another supply.
boost capacitor. Connect this pin to the boost capacitor.
BST(Pin21/Pin18):TheBSTpinisusedtoprovideadrive
voltage, higher than V pin voltage, to the high voltage
IN
channel internal power switch. Connect an external boost
diode to this pin.
FB1(Pin6/Pin3):Thehighvoltageconverterregulatesthe
FB1 pin to 1.265V. Connect the feedback resistor divider
tap to this pin to set output voltage.
V
(Pin 22/Pin 19): The V pin supplies current to
IN
IN
the LT3640’s internal circuitry and to the high voltage
channel internal power switch. This pin must be locally
bypassed.
RT (Pin 7/Pin 4): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the internal oscillator
frequency.
V
(Pin 24/Pin 21): The V pin supplies current to the
IN2
IN2
internal power MOSFET of the low voltage converter and
to the LT3640’s internal circuitry when V is above 3V.
RST2 (Pin 8/Pin 5): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB2 goes above 550mV.
IN2
SW2 (Pin 25/Pin 22): Switch Node of the Low Voltage
Converter. Connect this pin to an inductor.
RST1 (Pin 9/Pin 6): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB1 goes above 1.165V.
EN2 (Pin 27/Pin 24): Low Voltage Converter Enable Pin.
Pull this pin below 0.3V to shut down the low voltage
converter. Pull this pin above 1.5V to enable the low volt-
age converter.
WDO(Pin10/Pin7):Open-drainlogicoutputthatremains
asserted for the period set by the CPOR pin capacitor if
WDE is enabled and WDI pin is not driven by an appropri-
ate signal.
SS2 (Pin 28/Pin 25): The SS2 pin sets the FB2 voltage
externally between 0V and 0.6V, providing soft-start and
tracking. Tie this pin 0.8V or higher to use the internal
0.6V reference. A capacitor to ground at this pin sets the
ramp time to regulated output voltage for the low voltage
converter. Use a resistor divider to track another supply.
CWDT (Pin 11/Pin 8): Connect a capacitor to ground at
this pin to set watchdog timer.
CPOR (Pin 12/Pin 9): Connect a capacitor to ground at this
pin to set the power-on reset timer and WDO output timer.
3640p
8
LT3640
BLOCK DIAGRAM
C
IN
V
IN
2μA
D
BST
BST
SW
EN/
UVLO
100k
C
BST
+
–
ENABLE
–
+
Q1
R
Q
A4
A3
S
5.5V
DRIVER
+
–
V
REF
A1
A2
1.265V
L1
V
OUT1
C
2μA
SW1
DA
g
D1
m1
SS1
VC1
+
–
+
–
+
RAMP
GENERATOR
OUT1
OSCILLATOR
3
R2
FB1
V
OUT1
+
–
R1
RT
SYNC
+
–
A8
V
IN2
+
–
A5
3
C
IN2
2μA
g
m2
+
–
S
L2
SS2
FB2
V
OUT2
C
SW2
+
LOGIC
CIRCUIT
VC2
A7
R
Q
–
+
R4
OUT2
V
OUT2
+
–
V
REF
50mV
R3
–
+
600mV
A6
+
–
PGOOD
A9
EN2
2μA
2μA
CWDT
CPOR
WATCHDOG
TIMER
POR TIMER
RST1
RST2
WDE
WDI
WDO
3640 BD
3640p
9
LT3640
TIMING DIAGRAMS
Power-On Reset Timing
FB
t
t
RST
UV
RST
Watchdog Timing
WDI
WDO
t < t
WDU
t
t
WDU
DLY
t < t
t
t
< t < t
t
RST
WDL RST
WDL
WDU
3640 TD
OPERATION
The LT3640 is a dual channel, constant-frequency, current
mode monolithic buck switching regulator with power-on
resetandwatchdogtimer.Bothchannelsaresynchronized
toasingleoscillatorwithfrequencysetbyRT.Operationcan
be best understood by referring to the Block Diagram.
An active clamp (not shown) on the VC1 node provides
peak current limit. A DA pin current comparator extends
the oscillator cycle until the catch diode current is below
the valley current limit. Both the peak and valley current
limits help to control the inductor current in fault condi-
tions such as shorted output with high V . Both current
IN
Buck Regulators
limits are reduced when the voltage at the FB1 pin is below
0.2V. This current foldback helps to control the inductor
current during start-up and overload.
The high voltage channel is a nonsynchronous buck
regulator that operates from the V pin. The start of each
IN
oscillator cycle sets an SR latch and turns on the internal
The NPN power switch driver operates from either the V
IN
NPN power switch. An amplifier and comparator monitor
pin or the BST pin. An external capacitor and diode are
used to generate a voltage between the BST and SW pins.
Duringthepower-upoftheLT3640,aninternal5mAcurrent
source charges the external BST capacitor. The regulator
starts switching when the (BST-SW) voltage reaches the
2V threshold. The internal NPN power switch can be fully
saturated for efficient operation when the (BST-SW) volt-
age is between 2.3V and 5.5V.
thecurrentflowingbetweentheV andSW1pins, turning
IN
theswitchoffwhenthiscurrentreachesaleveldetermined
by the voltage at VC1 node. An error amplifier measures
the output voltage through an external resistor divider tied
to the FB1 pin and servos the VC1 node. The reference
of the error amplifier is determined by the lower of the
internalreferenceandthevoltageattheSS1pin.Iftheerror
amplifier’s output increases, more current is delivered to
the output; if it decreases, less current is delivered.
The low voltage channel is a synchronous buck regulator
that operates from the V pin. It starts switching only
IN2
3640p
10
LT3640
OPERATION
when the V pin voltage is above 2.3V, the EN2 pin is
to ground. Any overvoltage or undervoltage condition on
IN2
pulled high and the FB1 pin voltage is above 1.165V. The
internal top power MOSFET is turned on each cycle at the
beginning of each oscillator cycle, and turned off when
the current flowing through the top MOSFET reaches a
level determined by the voltage at the VC2 node. An error
amplifier measures the output voltage through an external
resistor divider tied to the FB2 pin and servos the VC2
node. The reference of the error amplifier is determined by
the lower of the internal 600mV reference and the voltage
at the SS2 pin.
the V pin triggers an internal latch that discharges the
IN
SS1 pin to below 100mV before it is released. If the EN2
pin goes low, the V voltage falls below 2.2V or the FB1
IN2
pin goes below 1.165V, the SS2 pin will be discharged to
below 100mV before it is released.
To optimize efficiency, the LT3640 switches to low ripple
Burst Mode operation in light load situations. Between
switching pulses, control-circuitry current is minimized.
A power good comparator with 40mV of hysteresis trips
when the low voltage channel is enabled and the FB2 pin is
above550mV. ThePGOODpinisanopen-drainoutputthat
is pulled low when both the outputs are in regulation.
WhilethetopMOSFETisoff,thebottomMOSFETisturned
on in an oscillator cycle until the inductor current starts
to reverse. If the inductor current is higher than the valley
current limit at the beginning of an oscillator cycle, the top
MOSFET will not turn on in this cycle, limiting inductor
current in shorted output fault.
Power-On Reset and Watchdog Timer
The LT3640 includes one power-on reset timer for each
buck regulator and one common watchdog timer. Power-
on reset and watchdog timers are both adjustable using
external capacitors. Operation can be best understood by
referring to the Timing Diagram.
Aninternalregulatorprovidespowertothecontrolcircuitry.
The regulator draws most power from the V pin and a
IN2
small portion of power from the V pin when the V pin
IN
IN2
voltage is higher than 3V. If the voltage at V pin is lower
IN2
The RST1, RST2 and WDO pins are all open-drain outputs
withweakinternalpull-upstoabout2V.TheRST1andRST2
than 3V, the regulator draws all power from the V pin.
IN
The EN/UVLO pin is used to put the LT3640 in shutdown,
reducing the input current to less than 1μA. The accurate
1.26V threshold of the EN/UVLO pin provides a program-
pins are pulled low when the LT3640 is enabled and V is
IN
above 3.6V. Once the FB1 pin rises above 1.165V, the high
voltagechannelresettimerisstartedandRST1isreleased
aftertheresettimeoutperiod.Thelowvoltagechannelreset
timer is started once the FB2 pin rises above 550mV, and
releases RST2 after the reset timeout period.
mableV undervoltagelockoutthroughanexternalresistor
IN
divider tied to the EN/UVLO pin. A 2μA hysteresis current
on the EN/UVLO pin prevents switching noise from shut-
ting down the LT3640.
The watchdog circuit monitors a μP’s activity. As soon
as both RST1 and RST2 are released, a delay timer is
started. Thewatchdogtimerisstartedafterthedelaytimer
times out. The LT3640 implements windowed watchdog
function for higher system reliability. The watchdog timer
detects falling edges on the WDI pin. If the falling edges
are grouped too close together or too far apart, the WDO
pin is pulled down and the reset timer is started. When the
reset timer times out, WDO is released and the watchdog
timer is again started after the delay period.
The LT3640 has an overvoltage protection feature which
disables switching action in both channels when the V
IN
pin voltage goes above 36V. When switching is disabled,
the LT3640 can sustain V voltages up to 55V for one
IN
second.
Internal 2μA current sources charge the SS1 pin and
the SS2 pin up to about 2V. Soft-start or output voltage
tracking of the two channels can be independently imple-
mented with capacitors from the SS1 pin and the SS2 pin
3640p
11
LT3640
APPLICATIONS INFORMATION
Setting the Output Voltages
off for a minimum of ~70ns. The minimum and maximum
duty cycles are:
The internal reference voltage is 1.265V for the high volt-
age channel, and 600mV for the low voltage channel. The
output voltages are set by resistor dividers according to
the following formulas:
DC
DC
= f • t
S ON(MIN)
MIN
= 1 – f • t
OFF(MIN)
MAX
S
where f is the switching frequency, t
is the mini-
S
ON(MIN)
istheminimumswitch
⎛
⎞
VOUT1
1.265V
mumswitchon-time, andt
OFF(MIN)
R2 = R1•
− 1
⎜
⎟
off-time. These equations illustrate how duty cycle range
increases when switching frequency decreases.
⎝
⎠
⎛
⎞
VOUT2
0.6V
R4 = R3 •
− 1
The internal oscillator of the LT3640 can be synchronized
to an external 350kHz to 2.5MHz positive clock signal on
⎜
⎟
⎝
⎠
Use 1% resistors in the resistor dividers. To avoid noise
problems, R1 should be 100k or less, and R3 should
be 50k or less. Reference designators refer to the Block
Diagram.
the SYNC pin. The R value should be chosen such that
T
the internal oscillator’s frequency is 20% lower than the
lowest SYNC clock frequency (refer to Table 1). To avoid
erratic operation, the LT3640 ignores the SYNC signal
until the FB1 pin voltage is above 1.165V. When applying
a SYNC signal, the rising edges reset the LT3640’s internal
clock and initiate a switch cycle. The amplitude of the
SYNC signal must be at least 2V. The SYNC pulse width
must be at least 40ns.
Switching Frequency
The LT3640 uses a constant-frequency PWM architecture
thatcanbeprogrammedtoswitchfrom350kHzto2.2MHz
by using a resistor tied from the RT pin to ground. Table
1 shows the necessary R value for a desired switching
T
V Voltage Range
IN
frequency.
The LT3640’s minimum operating voltage is 3.6V. A higher
minimumoperatingvoltagecanbeaccuratelyprogrammed
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz)
R (k)
T
witharesistordividerbetweentheV pinandtheEN/UVLO
IN
0.35
0.5
1
267
182
pin. The EN/UVLO threshold is 1.26V. When the LT3640
is enabled, a 2μA current flows out of the EN/UVLO pin
generatinghysteresistopreventtheswitchingactionfrom
falselydisablingtheLT3640.Choosethedividerresistances
for appropriate hysteresis voltage.
82.5
32.4
27.4
2
2.2
The high voltage nonsynchronous channel operates from
Selection of the operating frequency is mainly a trade-off
between efficiency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The disadvantage is lower
efficiency.
the V pin. The minimum V voltage to regulate output
IN
IN
voltage is:
⎛
⎞
VOUT1 + VD
DCMAX
V
=
− VD + VCE
IN(MIN)
⎜
⎟
⎝
⎠
The high switching frequency also decreases the duty
cycle range. The reason is that the LT3640 switches have
finite minimum on- and off-times independent of the
switching frequency. The top switch in the high voltage
channel can turn on for a minimum of ~60ns and turn off
for a minimum of ~70ns. The top switch in the low voltage
channel can turn on for a minimum of ~110ns and turn
WhereV istheforwardvoltagedropofthecatchdiode,V
D
CE
is the voltage drop of the internal NPN power switch, and
DC
is the maximum duty cycle (refer to the Switching
MAX
Frequencysection).IfV isbelowthecalculatedminimum
IN
voltage, output will lose regulation.
3640p
12
LT3640
APPLICATIONS INFORMATION
The maximum V should not exceed the absolute maxi-
calculated minimum voltage, the output will fall out of
regulation.
IN
mum rating. For fixed frequency operation, the maximum
V is:
IN
The maximum V for fixed frequency operation is:
IN2
⎛
⎞
VOUT1 + VD
DCMIN
VOUT2
DCMIN
V
=
− VD + VCE
IN(MAX)
V
≈
⎜
⎟
IN2(MAX)
⎝
⎠
Notethatthehighvoltagebuckwillstillregulateataninput
voltage that exceeds V (up to 36V). However, the
Where DC
is the minimum duty cycle (refer to the
MIN
IN(MAX)
Switching Frequency section). For voltage that exceeds
(up to 5.5V), the low voltage channel exhi-
switching frequency will be lowered to satisfy the equa-
V
IN2(MAX)
tion (Figure 1).
bits pulse-skipping behavior, and the output ripple will
increase.
Oncetheinputvoltagereaches36V,aninternalovervoltage
lockout(OVLO)circuitistriggeredtodisableswitchingac-
tion (Figure 2). Without switching, the LT3640 can sustain
Inductor Selection
V voltage transients up to 55V for one second.
IN
Inductorselectioninvolvesinductance,saturationcurrent,
series resistance (DCR) and magnetic loss. The inductor
currentrippledeterminestheinductance.Areasonablecur-
rent ripple is around 30% of the maximum load current:
V
Voltage Range
IN2
The low voltage synchronous channel operates from
the V pin. The V pin can be connected to either an
IN2
IN2
ΔI = 0.3 • I
L
OUT(MAX)
independent voltage supply or the high voltage channel
output for a two-stage power regulator.
where I
is the maximum load current. To guaran-
OUT(MAX)
tee sufficient output current, peak inductor current must
In either configuration, if the high voltage channel is over-
loadedandpulledoutofregulation,thelowvoltagechannel
will be disabled. The SS2 pin will be discharged as well.
be lower than the switch current limit (I ). The peak
LIM
inductor current is:
ΔIL
2
IL(PEAK) = IOUT(MAX)
where I
+
The minimum V voltage to regulate output voltage is:
IN2
VOUT2
DCMAX
V
≈
is the peak inductor current. For the high
L(PEAK)
IN2(MIN)
voltage channel, the top switch current limit is at least
2.4A at low duty cycles and decreases linearly to 1.8A at
DC = 0.8. Be sure to pick an inductor ripple current that
Where DC
is the maximum duty cycle (refer to
MAX
the Switching Frequency section). If V is below the
IN2
providessufficientmaximumloadcurrentI
.Once
OUT(MAX)
I
L1
2A/DIV
SW1
10V/DIV
I
L1
0.5A/DIV
V
IN
20V/DIV
55V , 40V, 15V
PK
3640 F01
200ns/DIV
SET = 2MHz
3640 F02
10μs/DIV
V
V
= 30V
R
T
IN
OUT1
= 3.3V/0.2A
Figure 2. VIN Overvoltage Lockout
Figure 1. Lower Switching Frequency Occurs in High
Voltage Channel When Required On-Time Is Below 50ns
3640p
13
LT3640
APPLICATIONS INFORMATION
the ripple current is determined, the inductance for the
high voltage channel is:
Of course, such a simple design guide will not always
result in the optimum inductors for the applications. A
larger value inductor provides a slightly higher maximum
load current and will reduce the output voltage ripple. A
largervalueinductoralsoresultsinhigherefficiencyinthe
condition of same DCR and same magnetic loss. However,
for a same series of inductors, a larger value inductor has
higher DCR. The trade-off between inductance and DCR
is not always obvious. Use experiments to find optimum
inductors.
⎛
⎞
VOUT1 + VD
1−
⎜
⎟
V
⎝
⎠
IN
L1≈ (VOUT1 + VD) •
ΔIL1 • fS
The largest inductor current ripple occurs at the highest
V . To guarantee current capacity, use V
in the
IN
IN(MAX)
above formula.
Low inductance may result in discontinuous mode opera-
tion, which is okay, but reduces maximum load current.
For details of maximum output current and discontinuous
modeoperation,seetheLinearTechnologyApplicationNote
44. For duty cycles greater than 50%, there is a minimum
inductance required to avoid subharmonic oscillations.
See the Linear Technology Application Note 19.
For the low voltage channel, the top MOSFET current limit
is at least 1.5A at low duty cycle and decreases linearly
to 1.2A at DC = 0.8. Pick an inductor ripple current (ΔI )
L2
following the same principle as the high voltage channel.
The inductance for the low voltage channel is:
⎛
⎞
VOUT2
1−
⎜
⎟
V
⎝
⎠
IN2
L2 ≈ (VOUT2) •
Input Capacitors
ΔIL2 • fS
Bypass the V and V pins of the LT3640 with a ce-
IN
IN2
For robust operation in fault conditions, the inductor
saturation current should be higher than the upper limit
of the corresponding top switch current limit. For the high
voltage channel, the inductor saturation current should be
at least 3.5A. For the low voltage channel, the inductor
saturation current should be at least 2.5A.
ramic capacitor of X7R or X5R type. Y5V types have poor
performance over temperature and applied voltage, and
should not be used.
Buck converters draw pulse current from the input sup-
ply. The input capacitor is required to reduce the resulting
voltage ripple:
To keep the efficiency high, the inductor series resistance
(DCR) should be as small as possible (must be < 0.1Ω),
and the core material should be intended for the chosen
operation frequency. High efficiency converters generally
cannot afford the core loss found in low cost powdered
iron cores; instead use ferrite, molypermalloy or Kool Mμ
cores. Table 2 lists several vendors and suitable inductor
series.
⎛
⎞
VOUT
IL
ΔV ≈ VOUT • 1−
•
IN
⎜
⎟
V
(V • CIN • fS)
⎝
⎠
IN
IN
+ESRCIN •IL
where C is the input capacitance, ESR is the series
IN
CIN
resistance (ESR) of the input capacitor, and I is the induc-
L
tor current. The input voltage ripple ΔV usually should
IN
not exceed 100mV. The above equation can be used to
estimate the input capacitance for both channels. The
input capacitors need to be placed close to the LT3640
(see the PCB Layout section).
Table 2. Inductor Vendors
PART SERIES
VENDOR
LQH55D
Murata
www.murata.com
SLF7045
SLF10145
TDK
Asecondprecautionregardingtheceramicinputcapacitor
concernsthemaximuminputvoltageratingoftheLT3640.
A ceramic input capacitor combined with trace or cable
inductanceformsaunderdampedtankcircuit.IftheLT3640
circuit is plugged into a live supply, the input voltage can
3640p
www.componenttdk.com
D62CB, D63CB
D75C, D75F
TOKO
www.toko.com
CR54, CDRH74
CDRH6D38, CR75
Sumida
www.sumida.com
14
LT3640
APPLICATIONS INFORMATION
ring to twice its nominal value, possibly exceeding the
LT3640’svoltagerating.Thissituationcanbeeasilyavoided
(see the Linear Technology Application Note 80).
Table 3. Capacitor Vendors
PART SERIES
VENDOR
Ceramic, Polymer, Tantalum Panasonic
www.panasonic.com
Kemet
www.kemet.com
Ceramic, Polymer, Tantalum Sanyo
www.sanyovideo.com
Output Capacitors and Output Ripple
Ceramic, Tantalum
Theoutputcapacitorhastwoessentialfunctions.Insteady
state, it determines the output voltage ripple. In transient,
it stores energy in order to satisfy transient loads and
stabilize the control loop. Ceramic capacitors have low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
Ceramic
Murata
www.murata.com
Ceramic, Tantalum
Ceramic
AVX
www.avxcorp.com
Taiyo Yuden
www.taiyo-yuden.com
100
VOUT • fS
COUT
=
Catch Diode
where f is in MHz, and C
is the recommended output
OUT
S
The high voltage channel requires an external catch diode
toconductcurrentduringswitchoff-time.Averageforward
current in normal operation can be calculated from:
capacitance in μF. Use X5R or X7R types. This choice will
provide low output ripple and good transient response.
The control loop is usually easier to be stabilized by a
bigger value of output capacitor. This equation applies
for both channels.
IOUT (V − VOUT
)
IN
ID(AVG)
where I
=
V
IN
In the case where V is connected to the high voltage
IN2
is the output load current. The only reason to
OUT
channel output, the high voltage channel output capaci-
consider a diode with a larger current rating than neces-
sary for nominal operation is for the worst-case condition
of overloaded output. The diode current will then increase
to the typical peak switch current. Peak reverse voltage
is equal to the regulator input voltage. Use a diode with a
reverse voltage rating greater than the input voltage. Table
4 lists several Schottky diodes and their manufacturers.
tor can be combined with the low voltage channel input
capacitor.TherequiredV inputcapacitorvalueisusually
IN2
smallerthanthehighvoltageoutputcapacitor.Ifthebigger
output capacitor can be placed close to the V pin, an
IN2
input capacitor is not necessary for the V pin.
IN2
When choosing a capacitor, look carefully through the
data sheet to find out what the actual capacitance is under
operating conditions (applied voltage and temperature).
A physically larger capacitor or one with a higher voltage
rating may be required. High performance tantalum or
electrolyticcapacitorscanbeusedfortheoutputcapacitor.
Low ESR is important, so choose one that is intended for
use in switching regulators. Table 3 lists several capacitor
vendors.
Table 4. Diode Vendors
V
(V)
I
V AT 1A V AT 2A
F F
(MV)
R
AVE
PART NUMBER
(A)
(MV)
On Semiconductor
MBRM120E
MBRM140
20
40
1
1
530
595
Diodes Inc.
B120
20
30
20
30
40
1
1
2
2
2
500
500
B130
B220
500
500
500
B230
DFLS240L
International Rectifier
10BQ030
20BQ030
30
30
1
2
420
470
470
3640p
15
LT3640
APPLICATIONS INFORMATION
BST and SW Pin Considerations
very close to the minimum input voltage to regulate the
output voltage for most of the load range.
The high voltage channel requires an external capacitor
between the BST and SW pins and an external boost diode
from a voltage source to the BST pin. In most cases, a
0.22μF capacitor will work well. The (BST-SW) voltage
cannot exceed 5.5V, and must be more than 2.3V for best
efficiency.Connecttheboostdiodetoanyvoltagebetween
Soft-Start
The LT3640 has a soft-start pin for each channel. The
feedback pin voltage is regulated to the lower of the cor-
responding SS pin and the internal references, which is
1.265Vforthehighvoltagechannel,and600mVforthelow
voltage channel. A capacitor from the SS pin to ground is
charged by an internal 2μA current source resulting in an
output ramping linearly from 0V to the regulated voltage.
The duration of the ramp is:
2.5V and 5.5V. The V pin is the best choice if the low
IN2
voltage channel is used.
The high voltage channel will not start until the (BST-SW)
voltage is 2V or above. When the LT3640 is enabled, an
internal~5mAcurrentsourcefromV flowsoutoftheBST
IN
pin. The SW pin is disconnected from the SW1 pin, and is
pulled down by an internal current source to ground. The
external boost capacitor can be charged up regardless of
theoutput.Whenthe(BST-SW)voltagereaches2V,theSW
pinisconnectedtotheSW1pin,andthehighvoltagechan-
nel starts switching. However, the internal bipolar power
switchcannotbefullysaturateduntilthe(BST-SW)voltage
is further charged to above 2.3V. To start up a traditional
nonsynchronous buck regulator with very light load, the
input voltage needs to be a couple of volts higher than
the minimum running input voltage if the input voltage is
ramping up slowly. The LT3640’s unique boost capacitor
chargingschemesolvesthisstart-upissue.Figure3shows
that the minimum input voltage to start the high voltage
channel nonsynchronous buck regulator of the LT3640 is
1.265V
2µA
tSS1 = CSS1
tSS2 = CSS2
where t
•
600mV
2µA
•
is the ramping time for the SS1 pin, t
the ramping time for the SS2 pin, C
from the SS1 pin to ground, and C
from the SS2 pin to ground.
is
SS1
SS2
is the capacitance
is the capacitance
SS1
SS2
At power-up, a latch is set to discharge the SS1 pin.
After the SS1 pin is discharged to below 100mV, the
latch is reset. The internal 2μA current source starts to
charge the SS1 pin when the (BST-SW) voltage is charge
to above 2V.
5
5
START
START
4
4
RUN
RUN
3
2
1
0
3
2
1
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
V
CURRENT (A)
V
CURRENT (A)
OUT
OUT
3640 F03a
3640 F03b
(3b) FS = 500kHz
Figure 3. High Voltage Channel Minimum Input Voltage for VOUT1 = 3.3V
(3a) FS = 2MHz
3640p
16
LT3640
APPLICATIONS INFORMATION
In the event of V undervoltage lockout, V overvoltage
IN
IN
EN
lockout or the EN/UVLO pin being driven below 1.26V, the
2V/DIV
soft-start latch is set, triggering a start-up sequence.
V
OUT1
2V/DIV
A latch is set to discharge the SS2 pin at power-up. After
V
OUT2
1V/DIV
the FB1 pin reaches 1.165V, the V voltage is above 2.3V,
IN2
the EN2 pin is enabled, and the SS2 pin is below 100mV,
the latch is reset. The internal 2μA current source starts
to charge the SS2 pin.
PGOOD
2V/DIV
3640 F04
500μs/DIV
V
= 12V
IN
T
In the event of V out of regulation, the V pin falling
FB1
IN2
R SET = 2MHz
below 2.2V, or the EN pin going low, the SS2 discharging
Figure 4. Soft-Start of LT3640
latch is set, triggering a start-up sequence.
The SS pins can also be pulled up by external current
sources or resistors for output tracking. The external pull-
up current should not exceed 100μA for either SS pin.
Figure 4 shows the soft-start for a 3.3V and 1.8V
application.
SW1
10V/DIV
I
L1
Shorted-Output Protection
0.5A/DIV
If an inductor is chosen that will not saturate excessively,
the LT3640 will tolerate a shorted output. For the high
voltage channel, the DA current comparator extends the
internal oscillator period until the catch diode current is
below its limit. Both the top switch and the DA comparator
have current foldback to help limit load current when the
output is shorted to ground. The DA current limit is 1.35A
when the FB1 voltage is above 0.2V, and is 0.8A when the
FB1 voltage is below 0.2V. Figure 5 shows the high voltage
channel operation under shorted output.
3640 F05
1μs/DIV
V
V
= 30V
IN
OUT1
= SHORT
Figure 5. The High Voltage Channel Reduces Frequency
to Protect Against Shorted Output With 30V Input
Because of the low V voltage, the low voltage channel
SW2
2V/DIV
IN2
does not have current foldback. The low voltage channel
does not extend the internal oscillator in shorted output
condition allowing the high voltage channel to operate in
constantfrequency.IfthebottomMOSFETcurrentexceeds
1.1A at the start of a clock cycle, the top MOSFET is kept
off in this cycle (similar to pulse-skipping operation).
The inductor valley current is kept below 1.1A to ensure
robustness in shorted output condition (Figure 6).
I
L2
1A/DIV
3640 F06
1μs/DIV
V
V
= 5V
OUT2
IN2
= SHORT
Figure 6. The Low Voltage Channel Operates in
Pulse-Skipping Mode to Protect Against Shorted Output
3640p
17
LT3640
APPLICATIONS INFORMATION
Reverse Protection
SW1
10V/DIV
In battery charging applications or in battery back-up
systems, the output will be held high when the input to the
LT3640 is absent. If the V pin is floated and the LT3640 is
I
L1
0.5A/DIV
IN
SW2
5V/DIV
enabled,theLT3640’sinternalcircuitrywillpullitsquiescent
current through the SW1 pin or the SW2 pin. This is fine if
the system can tolerate a few mA in this state. If the LT3640
is disabled, the SW1 pin and the SW2 pin current will drop
I
L2
0.5A/DIV
3640 F08a
2μs/DIV
toessentiallyzero.However,iftheV pinisgroundedwhile
IN
V
V
= 12V
V
V
= V
OUT2
IN
OUT1
IN2 OUT1
= 3.3V/25mA
= 1.8V/30mA
the high voltage channel output is held high, an external
diode is required at the V pin to prevent current being
IN
(8a)
pulled out of the V pin. If the V pin is grounded while
IN
IN2
the low voltage channel output is held high, an external
SW1
10V/DIV
diode is required at the V pin to prevent current being
IN2
pulled out of the V pin (Figure 7).
IN2
I
L1
0.5A/DIV
0.1μF
SW2
5V/DIV
IN
V
SW BST SW1
OUT1
OUT2
IN
I
L2
0.5A/DIV
+
–
DA
FB1
3640 F08b
2μs/DIV
EN/UVLO
LT3640
V
V
= 12V
OUT1
V
V
= V
OUT2
IN
IN2 OUT1
= 3.3V/25mA
= 1.8V/30mA
SW2
FB2
(8b)
IN2
V
IN2
+
–
SW1
10V/DIV
GND
I
L1
3640 F07
0.5A/DIV
Figure 7. Diodes Prevent Shorted Inputs from
Discharging a Battery Tied to the Outputs
SW2
5V/DIV
I
L2
PFM Operation
0.5A/DIV
3640 F08c
2μs/DIV
To improve efficiency at light loads, the LT3640 auto-
matically switches to pulse frequency modulation (PFM)
operation which minimizes the switching loss and keeps
the output voltage ripples small.
V
V
= 12V
OUT1
V
V
= V
OUT2
IN
IN2 OUT1
= 3.3V/0mA
= 1.8V/30mA
(8c)
Figure 8. PFM Operation
Because the two channels of the LT3640 may have differ-
ent loads, the two channels can have different switching
frequency (Figure 8).
The threshold of power-on comparator is 1.15V for the high
voltage channel, and 550mV for the low voltage channel.
Power-On Reset Timer
Both RST1 and RST2 are open-drain outputs with weak
internal pull-ups (100k to ~2V). The DC characteristics of
the RST1 and RST2 pull-down strength are shown in the
Typical Performance Characteristics section. The weak
3640p
EachchanneloftheLT3640hasapower-oncomparator.Both
comparators are enabled when the LT3640 is powered up
andstartsmonitoringtheircorrespondingfeedbackvoltages.
18
LT3640
APPLICATIONS INFORMATION
pull-ups eliminate the need for external pull-ups when
the rise time of these pins is not critical. The open-drain
configuration allows wired-OR connections.
The accuracy of the watchdog timer will be limited by
the accuracy and temperature coefficient of the capacitor
WDT
C
. Extra parasitic capacitance on the CWDT pin, such
as probe capacitance, can affect the watchdog timer.
The two power-on reset timers share one oscillator. The
power-on reset timeout period, t
(64 cycles on the
RST
CPOR pin), which is the same for the two channels, can
CWDT
be programmed by connecting a capacitor, C , between
the CPOR pin and ground:
WD STARTS
POR
CPOR
64 CYCLES 64 CYCLES
⎛ ⎞
⎝ F⎠
s
⎜ ⎟
tRST = CPOR • 37 • 106
FB2
FB1
RST1
RST2
For example, using a capacitor value of 8.2nF gives a
303ms reset timeout period. The accuracy of t will be
3640 F09a
20ms/DIV
RST
limited by the accuracy and temperature coefficient of the
capacitor CPOR. Extra parasitic capacitance on the CPOR
(9a)
pin, such as probe capacitance, can affect t
.
RST
Watchdog
CWDT
CPOR
The WDE pin is the enable pin for the watchdog. As soon
as both RST1 and RST2 are released, the watchdog starts
a delay period, t , during which the input signal at the
DLY
WDI pin is ignored for higher reliability. After the delay
period, the watchdog starts detecting falling edges on the
WDI pin. If the time between any two WDI falling edges is
WDI
WDO
3640 F09b
1ms/DIV
shorterthanthewatchdoglowerboundary,t
,orlonger
WDL
, the WDO pin
than the watchdog upper boundary, t
(9b)
WDU
is pulled down for a period of t , which is the same as
RST
the power-on reset timeout period. When the WDO pin is
released, the watchdog again starts the delay period.
CWDT
CPOR
The WDO is open-drain output with weak internal pull-up,
similar to the RST pins.
The delay period corresponding to 33 cycles on CWDT, the
watchdog lower boundary (4 cycles on CWDT), and the
watchdog upper boundary (64 cycles on CWDT) are all
WDI
WDO
related and set by a capacitor, C
pin and ground:
, between the CWDT
WDT
3640 F09c
50ms/DIV
(9c)
⎛
⎜
⎞
⎟
33
⎝ 64⎠
tDLY = tWDU
•
Figure 9. Power-On Reset and Watchdog Timing
tWDU
16
tWDL
=
⎛ ⎞
⎝ F⎠
s
tWDU = CWDT • 37 • 106
⎜ ⎟
3640p
19
LT3640
APPLICATIONS INFORMATION
on the same side of the circuit board as the LT3640, and
their connections should be made on that layer. Place a
local, unbroken ground plane below these components.
The BST and SW nodes should be as small as possible.
Figure 9a shows the power-on reset timing. Having FB1
or FB2 high starts the CPOR oscillator. After t , the cor-
RST
responding RST is released. When both RST1 and RST2
are released, the CWDT oscillator starts. Figure 9b shows
The boost capacitor (C ) should be as close to the BST
thewatchdogwaveformwiththeWDIperiodbetweent
BST
WDL
and SW pins as possible.
andt
.TheWDIfallingedgeresetstheCWDToscillator.
WDU
The CPOR oscillator is disabled and WDO remains high.
The input loop of the low voltage channel is formed by
Figure 9c shows the watchdog waveform with the WDI
the V pin, the input capacitor (C ) and the ground.
IN2
IN2
period longer than t
. WDO is asserted for a period of
WDU
Place C close to the V and the GND pin to minimize
IN2
IN2
t
when the watchdog upper boundary, t
, expires.
RST
WDU
this loop. Place a local, unbroken ground plane below
this input loop.
PCB Layout
Keep the FB1 and FB2 nodes small so that the ground
traces will shield them from the switching nodes. The
Exposed Pad on the bottom of the package must be sol-
dered to the ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3640 to additional ground planes within the circuit
board and on the bottom side.
For proper operation and minimum EMI, care must be
taken during the printed circuit board (PCB) layout. Figure
10 shows the recommended component placement with
trace, ground plane and via locations. The input loop of
the high voltage channel, which is formed by the V
IN
and SW1 pins, the external catch diode (D1), the input
capacitor (C ) and the ground, should be as small as
IN
possible. These external components should be placed
C
OUT2
L2
C
C
IN2
IN
C
BST
L1
C
OUT1
3640 F10
Figure 10. Recommended PCB Layout, FE28 Package
3640p
20
LT3640
TYPICAL APPLICATIONS
2MHz 3.3V/1.3A and 1.2V/1A Buck Regulators
V
0.22μF
IN
D2
5V TO 34V
4.7μF
100k
301k
L1
3.3μH
V
OUT1
3.3V/1.3A
EN/UVLO
V
SW
BST
SW1
IN
10μF
80.6k
49.9k
D1
DA
FB1
SYN
WDE
EN2
V
IN2
2.5V TO 5.5V
PGOOD
LT3640
V
IN2
4.7μF
L2
1μH
RST1
RST2
WDO
V
OUT2
1.8V/1A
SW2
47μF
100k
WDI
FB2
SS1
CWDT CPOR
RT
GND SS2
49.9k
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: DIODES B240A
1nF
1.5nF
32.4k
1.5nF
1nF
D2: CENTRAL SEMI CMDSH-4E
3640 TA02
2MHz 5V/0.8A and 1.2V/1A Buck Regulators
V
0.22μF
D2
IN
7V TO 34V
4.7μF
100k
453k
L1
V
OUT1
4.7μH
5V/0.8A
EN/UVLO
V
SW
BST
SW1
IN
10μF
301k
100k
D1
DA
SYN
WDE
WDI
FB1
EN2
LT3640
WDI
V
IN2
OUT1
10μF
100k
L2
1μH
PGOOD
WDO
100k
100k
V
OUT2
1.2V/1A
SW2
100k
47μF
49.9k
49.9k
RST1
RST2
CWDT CPOR
FB2
SS1
RT
GND SS2
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: DIODES B240A
D2: CENTRAL SEMI CMDSH-4E
1nF
1.5nF
32.4k
1.5nF
1nF
3640 TA03
2MHz 2.5V/0.8A and 0.6V/1A Buck Regulators
0.22μF
D2
V
IN
L1
3.6V TO 25V
3.3μH
V
OUT1
2.5V/0.8A
4.7μF
EN/UVLO
V
SW
BST
SW1
IN
22μF
100k
100k
D1
DA
FB1
SYN
EN2
WDE
PGOOD
LT3640
V
IN2
L2
1μH
RST1
RST2
WDO
V
OUT2
0.6V/1A
SW2
FB2
100μF
WDI
CWDT CPOR
RT
GND SS2
32.4k
SS1
L1: VISHAY IHLP-2020
L2: VISHAY IHLP-1616
D1: ON SEMI MBRS230
1nF
1.5nF
1.5nF
1nF
D2: CENTRAL SEMI CMDSH2-3
3640 TA04
3640p
21
LT3640
PACKAGE DESCRIPTION
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 0.10
2.74
(.108)
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
4.50 0.10
SEE NOTE 4
6.40
(.252)
BSC
2.74
(.108)
0.45 0.05
1.05 0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
3640p
22
LT3640
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 0.05
4.50 0.05
3.10 0.05
2.50 REF
2.65 0.05
3.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.50 REF
4.10 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 0.05
4.00 0.10
(2 SIDES)
27
28
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 0.10
(2 SIDES)
3.50 REF
3.65 0.10
2.65 0.10
(UFD28) QFN 0506 REV B
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3640p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3640
TYPICAL APPLICATION
2MHz 3.3V/0.8A and 0.8V/1.2A Buck Regulators
0.1μF
V
IN
4V TO 34V
4.7μH
V
OUT1
3.3V/0.8A
4.7μF
EN/UVLO
V
SW
BST
SW1
IN
22μF
80.6k
49.9k
DA
SYN
FB1
WDE
EN2
PGOOD
LT3640
V
IN2
RST1
RST2
WDO
1μH
V
OUT2
0.8V/1.2A
SW2
68μF
16.5k
49.9k
WDI
FB2
SS1
CWDT CPOR
RT
GND SS2
1nF
1.5nF
32.4k
1.5nF
1nF
3640 TA05
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
V : 3.6V to 36V, V
LT1933
LT1936
LT1940
500mA (I ), 500kHz Step-Down Switching Regulator in SOT-23
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OUT(MIN) Q SD
OUT
IN
ThinSOTTM Package
36V, 1.4A (I ), 500kHz, High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V
= 1.2V, I = 1.9mA, I < 1μA,
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OUT(MIN)
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MS8E Package
Dual 25V, 1.4A (I ), 1.1MHz, High Efficiency Step-Down DC/DC
Converter
V : 3.6V to 25V, V
= 1.2V, I = 3.8mA, I < 30μA,
Q SD
OUT
IN
TSSOP16E Package
LT1976/LT1967 60V, 1.2A (I ), 200kHz/500kHz, High Efficiency Step-Down
V : 3.3V to 60V, V
= 1.2V, I = 100μA, I < 1μA,
Q SD
OUT
IN
OUT(MIN)
DC/DC Converters with Burst Mode Operation
TSSOP16E Package
LT3434/LT3435 60V, 2.4A (I ), 200kHz/500kHz, High Efficiency Step-Down
V : 3.3V to 60V, V
= 1.2V, I = 100μA, I < 1μA,
Q SD
OUT
IN
OUT(MIN)
DC/DC Converters with Burst Mode Operation
TSSOP16 Package
LT3437
LT3480
LT3481
LT3493
LT3505
LT3508
LT3680
LT3684
LT3685
LT3693
60V, 400mA (I ), Micropower Step-Down DC/DC Converter with V : 3.3V to 60V, V
= 1.25V, I = 100μA, I < 1μA,
Q SD
OUT
IN
OUT(MIN)
Burst Mode Operation
3mm
×
3mm DFN10 and TSSOP16E Packages
V : 3.6V to 38V, V = 0.78V, I = 70μA, I < 1μA,
IN OUT(MIN)
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High
OUT
Q
SD
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
3mm
×
3mm DFN10 and MSOP10E Packages
34V with Transient Protection to 36V, 2A (I ), 2.8MHz, High
V : 3.6V to 34V, V
= 1.26V, I = 50μA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
3mm
×
3mm DFN10 and MSOP10E Packages
36V, 1.4A (I ), 750kHz High Efficiency Step-Down
V : 3.6V to 36V, V
= 0.8V, I = 1.9mA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converter
2mm
×
3mm DFN6 Package
36V with Transient Protection to 40V, 1.4A (I ), 3MHz,
V : 3.6V to 34V, V
= 0.78V, I = 2mA, I = 2μA,
OUT
IN
OUT(MIN)
Q
SD
High Efficiency Step-Down DC/DC Converter
3mm
×
3mm DFN8 and MSOP8E Packages
36V with Transient Protection to 40V, Dual 1.4A (I ), 3MHz,
V : 3.7V to 37V, V
= 0.8V, I = 4.6mA, I = 1μA,
OUT
IN
OUT(MIN)
Q
SD
High Efficiency Step-Down DC/DC Converter
4mm
×
4mm QFN24 and TSSOP16E Packages
36V, 3.5A, 2.4MHz, Low Quiescent Current (<75μA) Step-Down
DC/DC Converter
V : 3.6V to 36V, V
= 0.8V, I = 75μA, I < 1μA,
IN
OUT(MIN)
Q
SD
3mm × 3mm DFN10, MS10E Package
34V with Transient Protection to 36V, 2A (I ), 2.8MHz,
V : 3.6V to 34V, V = 1.26V, I = 850μA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
High Efficiency Step-Down DC/DC Converter
3mm
×
3mm DFN10 and MSOP10E Packages
36V with Transient Protection to 60V, Dual 2A (I ), 2.4MHz,
V : 3.6V to 38V, V
= 0.78V, I = 70μA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
High Efficiency Step-Down DC/DC Converter
3mm
×
3mm DFN10 and MSOP10E Packages
36V, 3.5A, 2.4MHz, Step-Down DC/DC Converter
V : 3.6V to 36V, V
= 0.8V, I = 1.3mA, I < 1μA,
IN
OUT(MIN)
Q
SD
3mm × 3mm DFN10, MS10E Package
3640p
LT 0110 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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