LT3686AEMSE#TRPBF [Linear]
LT3686A - 37V/1.2A Step-Down Regulator in 3mm x 3mm DFN and MSE; Package: MSOP; Pins: 12; Temperature Range: -40°C to 85°C;
| 型号： | LT3686AEMSE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3686A - 37V/1.2A Step-Down Regulator in 3mm x 3mm DFN and MSE; Package: MSOP; Pins: 12; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总30页 (文件大小：556K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3686A
37V/1.2A Step-Down
Regulator in 3mm × 3mm DFN
and MSE
FeAtures
Description
The LT®3686A is a current mode PWM step-down DC/DC
converter with an internal power switch. The wide input
range of 3.6V to 37V makes the LT3686A suitable for
regulatingpowerfromawidevarietyofsources, including
24V industrial supplies and automotive batteries. Its high
maximum frequency allows the use of tiny inductors and
capacitors, resulting in a very small solution. Operating
frequencyabovetheAMbandavoidsinterferingwithradio
reception, making the LT3686A particularly suitable for
automotive applications.
■
Wide Input Range:
Operation from 3.6V to 37V
Overvoltage Lockout Protects Circuit Through
60V Transients
■
Low Minimum On-Time:
Converts 16V to 3.3V
1.2A Output Current
at 2MHz
IN
OUT
■
■
■
■
■
■
■
■
■
■
Adjustable Frequency: 300kHz to 2.5MHz
Constant Switching Frequency at Light Loads
Can Be Synchronized to External Clock
Tracking and Soft-Start
Cycle-by-cycle current limit, thermal shutdown and DA
current sense provide protection against fault conditions.
Soft-start and frequency foldback eliminate input current
surgeduringstart-up.Anoptionalinternalregulatedactive
load at the output via the BD pin keeps the LT3686A at
full switching frequency at light loads, resulting in low,
predictable output ripple above the audio and AM bands.
Internal compensation and an internal boost diode reduce
external component count.
Precision UVLO
Short-Circuit Robust
I in Shutdown <1µA
Q
Internally Compensated
Thermally Enhanced MSOP and 3mm × 3mm DFN
Packages
ApplicAtions
■
Automotive Systems
The LT3686A offers external synchronization capability,
whereas the LT3686 does not.
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
■
Battery-Powered Equipment
■
Wall Transformer Regulation
Distributed Supply Regulation
■
typicAl ApplicAtion
3.3V Step-Down Converter
12VIN Efficiency (2MHz)
90
80
V
IN
V
BD
IN
6V TO 37V
3.3V
OUT
2.2µF
EN/UVLO
BOOST
0.22µF
6.8µH
70
60
50
40
30
20
10
0
5V
OUT
2MHz
LT3686A
V
3.3V
1.2A
SW
SYNC/MODE
OUT
MBRM140
31.6k
SS
RT
DA
FB
10nF
GND
10k
22µF
31.6k
3686A TA01a
0
400
600
800 1000 1200
LOAD CURRENT (mA)
200
(V 6V TO 16V AT 2MHz)
IN
3686A TA01b
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1
LT3686A
Absolute MAxiMuM rAtinGs
(Note 1)
SYNC/MODE Voltage...................................................6V
Operating Junction Temperature Range (Note 2)
LT3686AE........................................... –40°C to 125°C
LT3686AI............................................ –40°C to 125°C
LT3686AH .......................................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (MSE Package Only,
Input Voltage (V ) (Note 7)......................................60V
IN
BOOST Voltage .........................................................55V
BOOST Pin Above SW Pin.........................................25V
FB Voltage...................................................................6V
EN/UVLO Voltage (Note 7) ........................................60V
BD Voltage ................................................................25V
RT Voltage...................................................................6V
SS Voltage ...............................................................2.5V
Soldering, 10 Sec) ................................................ 300°C
pin conFiGurAtion
TOP VIEW
TOP VIEW
1
2
3
4
5
6
GND
12 SW
11 SW
10 DA
V
1
2
3
4
5
10 SW
IN
V
IN
BD
FB
SS
RT
9
8
7
6
DA
BD
FB
SS
RT
13
GND
11
GND
BOOST
9
8
7
BOOST
SYNC/MODE
EN/UVLO
SYNC/MODE
EN/UVLO
MSE PACKAGE
DD PACKAGE
12-LEAD PLASTIC MSOP
10-LEAD (3mm × 3mm) PLASTIC DFN
= 40°C/W,
= 10°C/W
JC
JA
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
= 43°C/W
JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
orDer inForMAtion
LEAD FREE FINISH
LT3686AEDD#PBF
LT3686AIDD#PBF
LT3686AEMSE#PBF
LT3686AIMSE#PBF
LT3686AHMSE#PBF
TAPE AND REEL
PART MARKING*
LFRK
PACKAGE DESCRIPTION
10-Lead Plastic DFN
10-Lead Plastic DFN
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic MSOP
TEMPERATURE RANGE
LT3686AEDD#TRPBF
LT3686AIDD#TRPBF
LT3686AEMSE#TRPBF
LT3686AIMSE#TRPBF
LT3686AHMSE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
LFRK
3686A
3686A
3686A
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
*For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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2
LT3686A
electricAl chArActeristics
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VEN/UVLO ≥ 1.34V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Quiescent Current at Shutdown
V
V
< 0.4V
= 1V
0.1
10
1
15
µA
µA
EN/UVLO
EN/UVLO
Quiescent Current
Not Switching, SYNC/MODE ≤ 0.4V
Not Switching, SYNC/MODE ≥ 0.8V
1.1
1.2
1.3
1.4
mA
mA
Internal Undervoltage Lockout
Overvoltage Lockout
3.4
38
3.6
39
V
V
●
●
37
Feedback Voltage
V
= 3.6V ↔ 37V
0.790
0.785
0.8
0.8
0.810
0.815
V
V
IN
FB Pin Bias Current
Switching Frequency
60
100
nA
I
< 1.2A
0.3
1.9
2.5
2.3
MHz
MHz
DA
T
R = 15.4kΩ, IDA < 1.2A
2.1
100
150
680
Minimum On Time
Minimum Off Time
SYNC/MODE > 0.8V, BD < 6V
110
200
ns
ns
Switch V
I
= 1.2A
SW
mV
CESAT
Switch Current Limit
(Note 3)
1.9
1.85
2.3
2.3
2.6
2.65
A
A
●
Switch Active Current
SW = 10V (Note 4)
SW = 0V (Note 5)
400
20
600
30
µA
µA
BOOST Pin Current
I
I
= 1.2A
= 1.2A
20
2.2
40
mA
V
SW
SW
Minimum Boost Voltage Above Switch
Max BD Pin Active Load Current
BD Pin Voltage to Disable Active Load
DA Pin Current to Stop OSC
SYNC/MODE High
2.4
7
SYNC/MODE > 0.8V, BD < 6V
30
6
mA
V
●
●
●
●
6.5
1.7
1.2
0.8
A
V
SYNC/MODE Low
0.4
0.2
V
SYNC/MODE Bias Current
SS Threshold
µA
V
0.9
2
SS Source Current
V
= 1V
1.3
2.7
µA
SS
EN/UVLO Bias Current
V
V
= 10V
= 0V
40
1
µA
µA
EN/UVLO
EN/UVLO
●
EN/UVLO Threshold to Turn Off
EN/UVLO Hysteresis Current
Boost Diode Forward Drop
1.22
1.8
1.28
2.4
1.34
3
V
µA
V
I
BD
to I
= 200mA
0.85
BOOST
Note 3: Current limit guaranteed by design and/or correlation to static test.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Slope compensation reduces current limit at higher duty cycle.
Note 4: Current flows into pin.
Note 5: Current flows out of pin.
Note 2: The LT3686AE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3686AI is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3686AH is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes; operating lifetime is derated for junction
temperatures greater than 125°C. (Note 6)
Note 6: This IC includes overtemperature protection that is intended to protect
the device during momentary overload conditions. Junction temperature will
exceed the maximum operating junction temperature when overtemperature
protection is active. Continuous operation above the specified maximum
operating junction temperature may impair device reliability. See High
Temperature Considerations section. Also see Operation section.
Note 7: Absolute Maximum Voltage at V and EN/UVLO pins is 60V for
IN
nonrepetitive one second transients, and 55V for continuous operation.
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3
LT3686A
typicAl perForMAnce chArActeristics
TA = 25°C unless otherwise noted.
5VOUT Efficiency
3.3VOUT Maximum Load Current
3.3VOUT Efficiency (2MHz)
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
TYPICAL
MODE/SYNC > 0.8V
MODE/SYNC > 0.8V
MINIMUM
MODE/SYNC < 0.4V
MODE/SYNC < 0.4V
0.6
0.4
V
V
= 12V
= 3.3V
V
V
= 12V
= 5V
OUT
IN
OUT
IN
V
= 3.3V
OUT
L = 6.8µH
f = 2MHz
L = 10µH
f = 2MHz
L = 6.8µH
f = 2MHz
0.2
0
0
400
600
800 1000 1200
0
400
600
800 1000 1200
0
10
20
(V)
30
40
200
200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
V
IN
3686A G01
3686A G02
3686A G03
Internal Undervoltage Lockout
(UVLO)
Switch Voltage Drop
5VOUT Maximum Load Current
900
800
700
600
2.0
1.8
1.6
1.4
1.2
1.0
0.8
4.0
3.5
3.0
2.5
2.0
TYPICAL
MINIMUM
500
400
300
200
100
0
0.6
0.4
150°C
125°C
25°C
V
= 5V
OUT
L = 10µH
f = 2MHz
0.2
0
–50°C
0
500
1000
I
1500
(mA)
2000
2500
10
20
(V)
30
40
–50
0
50
100
150
V
TEMPERATURE (°C)
SW
IN
3686A G05
3686A G04
3686A G06
Overvoltage Lockout (OVLO)
VFB vs Temperature
40
39
38
37
36
35
820
810
800
790
780
–50
0
50
100
150
–50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
3686A G07
3686A G08
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4
LT3686A
typicAl perForMAnce chArActeristics
TA = 25°C unless otherwise noted.
Switching Frequency vs
Temperature
Soft-Start/Track vs Frequency
(1MHz)
Switching Frequency vs RT
1200
1000
800
600
400
200
0
300
250
200
150
100
50
2.20
2.15
2.10
2.05
2.00
1.95
1.90
R
= 15.4k
T
0
0
500
1000
1500
2000
2500
0
0.5
1
1.5
2
2.5
–50
0
50
100
150
SS (mV)
FREQUENCY (MHz)
TEMPERATURE (°C)
3686A G11
3686A G09
3686A G10
Switch Current Limit vs
Temperature
Soft-Start/Track vs VFB
EN/UVLO Pin Current
3.0
2.5
2.0
1.5
1.0
45
40
35
30
25
20
15
10
900
800
700
600
500
400
300
200
5
0
100
0
–50
0
50
100
150
0
10
20
30
40
50
0
200
400
600
800 1000 1200
TEMPERATURE (°C)
EN/UVLO (V)
SS (mV)
3686A G14
3686A G13
3686A G12
3.3VOUT Maximum VIN for Full
Frequency (2MHz)
5VOUT Maximum VIN for Full
Frequency (2MHz)
Current Limit vs Duty Cycle
3.0
25
20
15
10
5
35
30
25
20
15
10
5
MODE/SYNC > 0.8
MODE/SYNC > 0.8
MODE/SYNC < 0.4
2.5
2.0
1.5
1.0
0.5
0
SWITCH PEAK
DA VALLEY
MODE/SYNC < 0.4
V
= 3.3V
V
OUT
= 5V
OUT
L = 6.8µH
f = 2MHz
L = 10µH
f = 2MHz
0
0
0
25
50
75
100
0
500
1000
1500
0
500
1000
DUTY CYCLE (%)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3686A G15
3686A G16
3686A G17
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5
LT3686A
typicAl perForMAnce chArActeristics
TA = 25°C unless otherwise noted.
3.3VOUT Typical Minimum Input
Voltage
5VOUT Typical Minimum Input
Voltage
Continuous Mode Waveform
7
6
8
7
6
5
4
3
2
1
0
MODE/SYNC < 0.4
MODE/SYNC > 0.8
V
SW
MODE/SYNC < 0.4
MODE/SYNC > 0.8
2V/DIV
5
4
3
I
L
200mA/DIV
3686A G20
200ns/DIV
V
V
= 10V
IN
OUT
= 3.3V
2
1
0
L = 6.8µH
f = 2MHz
V
= 3.3V
V
= 5V
OUT
OUT
C
= 22µF
OUT
L = 15µH
f = 1MHz
L = 22µH
I
= 200mA
LOAD
f = 1MHz
MODE/SYNC = 0V
1
10
100
1000
1
10
100 1000
I
(mA)
I
(mA)
LOAD
LOAD
3686A G18
3686A G19
Fixed Frequency No Load
Waveform
Start-Up Shutdown Waveform
ILOAD = 5mA
Light Load Discontinuous Mode
Waveform
V
IN
1V/DIV
V
V
SW
SW
2V/DIV
2V/DIV
V
OUT
I
I
1V/DIV
L
L
200mA/DIV
200mA/DIV
3686A G21
3686A G23
3686A G22
200ns/DIV
200ms/DIV
200ns/DIV
V
V
= 10V
V
= 5V
V
V
= 10V
IN
OUT
OUT
IN
OUT
= 3.3V
L = 22µH
f = 1MHz
= 3.3V
L = 6.8µH
f = 2MHz
L = 6.8µH
f = 2MHz
I
= 5mA
LOAD
C
I
= 22µF
MODE/SYNC = 0V
C
I
= 22µF
OUT
OUT
= 25mA
= 0mA
LOAD
LOAD
MODE/SYNC = 0V
MODE/SYNC = 3.3V
Start-Up Shutdown Waveform
ILOAD = 5mA
Start-Up Shutdown Waveform
ILOAD = 500mA
Start-Up Shutdown Waveform
ILOAD = 500mA
V
V
V
IN
1V/DIV
IN
IN
1V/DIV
1V/DIV
V
V
V
OUT
1V/DIV
OUT
OUT
1V/DIV
1V/DIV
3686A G24
3686A G25
3686A G26
200ms/DIV
200ms/DIV
200ms/DIV
V
= 5V
V
= 5V
V
= 5V
OUT
OUT
OUT
L = 22µH
f = 1MHz
L = 22µH
f = 1MHz
L = 22µH
f = 1MHz
I
= 5mA
I
= 500mA
I
= 500mA
LOAD
LOAD
LOAD
MODE/SYNC = 1V
MODE/SYNC = 0V
MODE/SYNC = 1V
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6
LT3686A
pin Functions (DFN/MSE)
V (Pin1/2):TheV pinsuppliescurrenttotheLT3686A’s
EN/UVLO (Pin 6/7): The EN/UVLO pin is used to start
up the LT3686A. Pull the pin below 0.4V to shutdown the
LT3686A. The 1.28V threshold can function as an accurate
undervoltage lockout (UVLO), preventing the regulator
from operating until the input voltage has reached the
IN
IN
internal regulator and to the internal power switch. This
pin must be locally bypassed.
BD (Pin 2/3): When the SYNC/MODE Pin is driven with
clock pulses or tied greater than 0.8V, the LT3686A will
prevent pulse-skipping at light loads by regulating an
active load on the BD pin; see Applications Information
section Fixed Frequency at Light Load.
programmedlevel.DonotdrivetheEN/UVLOpinaboveV .
IN
SYNC/MODE (Pin 7/8): The SYNC/MODE pin is used
to synchronize the internal oscillator of the LT3686A to
an external signal. The SYNC signal can be driven by a
signal with pulse width of at least 200ns on and off time.
The SYNC/MODE Pin also acts as mode select for the BD
active load; when it is driven with pulses or tied above
0.8V,theLT3686Awillpreventpulseskippingatlightloads
by regulating an active load on the BD pin. To disable the
active load, tie SYNC/MODE to below 0.4V.
FB (Pin 3/4): The LT3686A regulates its feedback pin to
0.8V. Connect the feedback resistor divider tap to this pin.
Set the output voltage according to:
V
R1=R2 OUT –1
0.8V
A good value for R2 is 10k.
BOOST (Pin 8/9): The BOOST pin is used to provide a
drive voltage, higher than the input voltage, to the internal
bipolar NPN power switch.
SS(Pin4/5):ProvidesSoft-StartandTracking.Aninternal
2µA current source tied to a 2.5V reference supplies cur-
rent to this pin to charge an external capacitor to create a
voltage ramp at the pin. Feedback voltage and switching
frequency both track SS voltage. Feedback voltage stops
trackingat0.8V.SSisresetunderUVLO,OVLOandthermal
shutdown conditions. Float the pin if soft-start feature is
not being used.
DA (Pin 9/10): Connect catch diode (D1) anode to this
pin.
SW (Pin 10/11, 12): The SW pin is the output of the
internal power switch. Connect this pin to the inductor,
catch diode and boost capacitor.
GND (Exposed Pad Pin 11/Pin 1, Exposed Pad Pin 13):
The exposed pad GND pin is the only ground connection
for the device. The exposed pad should be soldered to a
large copper area to reduce thermal resistance.
RT (Pin 5/6): The RT pin is used to program the oscillator
frequency.SelectthevalueofR resistoraccordingtotable
T
1 in the applications section of the data sheet.
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7
LT3686A
block DiAGrAM
BOOST
V
V
IN
IN
R4
C2
INT REG
UVLO
OVLO
EN/ULVO
1.27V
OFF ON
R5
C3
L1
Q1
DRIVER
SW
V
OUT
C1
BD
FB
D1
R1
R2
ACTIVE
LOAD
–
+
+
gm
SS
R
S
V
C
Q
SLOPE
COMP
C4
Q
0.8V
DA
OSC
FREQUENCY FOLDBACK
GND
RT
R3
SYNC/MODE
3686A BD
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8
LT3686A
operAtion
The LT3686A is a current mode step-down regulator.
The EN/UVLO pin is used to place the LT3686A in shut-
down. The 1.28V threshold on the EN/UVLO pin can be
programmed by an external resistor divider (R4, R5) to
disable the LT3686A. When the EN/UVLO pin is driven
above 1.28V, an internal regulator provides power to the
control circuitry. This regulator includes both overvoltage
decreases, less current is delivered. An active clamp (not
shown) on the V node provides current limit.
C
The switch driver operates from either V or from the
IN
BOOST pin. An external capacitor and the internal boost
diode are used to generate a voltage at the BOOST pin that
is higher than the input supply. This allows the driver to
fully saturate the internal bipolar NPN power switch for
efficient operation.
and undervoltage lockout to prevent switching when V
is more than 37V or less than 3.6V.
IN
A comparator monitors the current flowing through the
catch diode via the DA pin and reduces the LT3686A’s
operating frequency when the DA pin current exceeds the
1.7A valley current limit. This helps to control the output
currentinfaultconditionssuchasshortedoutputwithhigh
input voltage. The DA comparator works in conjunction
withtheswitchpeakcurrentlimitcomparatortodetermine
the maximum deliverable current of the LT3686A.
Tracking soft-start is implemented by providing constant
current via the SS pin to an external soft-start capacitor
(C4) to generate a voltage ramp. FB voltage is regulated
to the voltage at the SS pin until it exceeds 0.8V; FB
is then regulated to the reference 0.8V. Soft-start also
reduces the oscillator frequency to avoid hitting current
limit during start-up. The SS capacitor is reset during
fault events such as overvoltage, undervoltage, thermal
shutdown and startup.
The SYNC/MODE pin doubles as mode select for the
BD active load circuit. The active load is enabled when
SYNC/MODE is driven with sync pulses or tied above
0.8V and disabled when SYNC/MODE is tied below 0.4V.
The LT3686A will prevent pulse skipping at light loads
by regulating the active load. The active load will assist
startup by guaranteeing a minimum load to charge the
boost capacitor. It also hastens the recharge of boost
capacitor when operating beyond maximum duty cycle.
An oscillator is programmed by resistor R . The oscillator
T
sets an RS flip-flop, turning on the internal 1.2A power
switch Q1. An amplifier and comparator monitor the cur-
rent flowing between the V and SW pins, turning the
IN
switch off when this current reaches a level determined by
the voltage at V . An error amplifier measures the output
C
voltage through an external resistor divider tied to the FB
pin and servos the V node. If the error amplifier’s output
C
The active load works only when the BD pin is less than 6V.
increases, more current is delivered to the output; if it
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9
LT3686A
ApplicAtions inForMAtion
FB Resistor Network
45
40
35
30
25
20
15
10
5
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
V
0.8V
⎛
⎞
OUT
R1=R2
–1
⎟
⎜
⎝
⎠
R2 should be 20k or less to avoid bias current errors.
Reference designators refer to the Block Diagram.
0
0
10
20
30
40
50
EN/UVLO (V)
Programmable Undervoltage Lockout
3686A F02
The EN/UVLO pin can be programmed by an external re-
Figure 2. EN/UVLO Pin Current
sistor divider between V and the EN/UVLO pin. Choose
IN
Input Voltage Range
the resistors according to:
The input voltage range for the LT3686A applications
depends on the output voltage and on the absolute maxi-
VIN
1.28V
R4 = R5
–1
mum ratings of the V and BOOST pins. The minimum
IN
input voltage is determined by either the LT3686A’s
minimum operating voltage of 3.6V, or by its maximum
duty cycle.
R4 also sets the hysteresis voltage for the programmable
UVLO:
ꢀ Hysteresisꢀ=ꢀR4ꢀ•ꢀ2.4µA
The duty cycle is the fraction of time that the internal
switch is on and is determined by the input and output
voltages:
Once V drops below the programmed voltage, the
IN
LT3686A will enter a low quiescent current state (Iq ≈
15µA). To shutdown the LT3686A completely (Iq < 1µA),
reduce EN/UVLO pin voltage to below 0.4V.
VOUT + VD
DC=
V – VSW + VD
IN
10000
1000
100
10
Where V is the forward voltage drop of the catch diode
D
(~0.4V) and V is the voltage drop of the internal switch
SW
(~0.67V at maximum load). This leads to a minimum input
voltage of:
VOUT + VD
DCMAX
V
=
– VD + VSW
IN(MIN)
1
DC
can be adjusted with frequency.
MAX
0.1
Theboostcapacitorischargedwiththeenergystoredinthe
inductor,thecircuitwillrelyonsomeminimumloadcurrent
to sustain the charge across the boost capacitor.
0
1
2
3
4
5
6
7
8
EN/UVLO (V)
3686A F01
Figure 1. IQ vs VEN/UVLO (VIN = 10V)
3686afa
10
LT3686A
ApplicAtions inForMAtion
The maximum input voltage is determined by the absolute
When the required on time decreases below the typical
minimum on time of 100ns, instead of the switch pulse
widthbecomingnarrowertoaccommodatethelowerduty
cycle requirement, the switch pulse width remains fixed at
100ns. The inductor current ramps up to a value exceed-
ing the load current and the output ripple increases. The
part then remains off until the output voltage dips below
the programmed value before it begins switching again
(Figure 4).
maximum ratings of the V and BOOST pins. For fixed
IN
frequency operation, the maximum input voltage is de-
termined by the minimum duty cycle DC
:
MIN
VOUT + VD
DCMIN
V
=
– VD + VSW
IN(MAX)
DC
can be adjusted with frequency. Note that this is a
MIN
restrictionontheoperatinginputvoltageforfixedfrequency
operation;thecircuitwilltoleratetransientinputsuptothe
absolute maximum ratings of the V and BOOST pins.
V
SW
20V/DIV
IN
Minimum On Time
I
L
500mA/DIV
As the input voltage is increased, the LT3686A is required
to switch for shorter periods of time. Delays associated
with turning off the power switch dictate the minimum on
time of the part. The minimum on time for the LT3686A
is 100ns (Figure 3).
V
OUT
100mA/DIV
AC
3686A F04
2µs/DIV
V
V
= 35V
IN
OUT
= 3.3V
L = 6.8µH
C
= 22µF
= 300mA
OUT
OUT
I
Figure 4. Pulse Skip Occurs When Required On Time Is
Below 100ns
V
SW
10V/DIV
Provided that the load can tolerate the increased output
voltage ripple and that the components have been prop-
erly selected, operation while pulse skipping is safe and
will not damage the part. As the input voltage increases,
the inductor current ramps up quicker, the number of
skipped pulses increases, and the output voltage ripple
increases.
I
L
500mA/DIV
V
OUT
100mV/DIV
AC
3686A F03
500ns/DIV
V
V
= 18V
IN
OUT
= 3.3V
L = 6.8µH
C
= 22µF
= 1.2mA
OUT
I
LOAD
Inductor current may reach current limit when operating
in pulse skip mode with small valued inductors. In this
case, the LT3686A will periodically reduce its frequency
Figure 3. Continuous Mode Operation Near Minimum On Time
3686afa
11
LT3686A
ApplicAtions inForMAtion
to keep the inductor valley current to 1.7A (Figure 5). Peak
inductor current is therefore peak current plus minimum
switch delay:
Table 1. RT vs Frequency
FREQUENCY (MHz)
R (kΩ)
MIN SYNC FREQUENCY (MHz)
T
2.5
2.3
2.1
1.9
1.8
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
9.53
N/A
N/A
12.1
15.4
20.0
22.6
25.5
31.6
40.2
52.3
69.8
97.6
150
1.7A + (V – V )/Lꢀ•ꢀ100ns
IN
OUT
N/A
N/A
V
SW
10V/DIV
2.50
2.30
1.99
1.70
1.42
1.14
I
L
500mA/DIV
V
OUT
100mA/DIV
AC
3686A F05
2µs/DIV
V
V
= 35V
IN
OUT
= 3.3V
0.874
0.615
0.363
L = 6.8µH
C
= 22µF
= 1.2A
OUT
OUT
I
280
Figure 5. Pulse Skip with Large Load Current Will Be Limited by
the DA Valley Current Limit. Notice the Flat Inductor Valley
Current and Reduced Switching Frequency
300
250
The part is robust enough to survive prolonged opera-
tion under these conditions as long as the peak inductor
current does not exceed 2A. Inductor current saturation
and junction temperature may further limit performance
during this operating regime.
200
150
100
50
Frequency Selection
0
0
The maximum frequency that the LT3686A can be pro-
grammed to is 2.5MHz. The minimum frequency that the
LT3686A can be programmed to is 300kHz. The switching
frequency is programmed by tying a 1% resistor from the
RT pin to ground. Table 1 can be used to select the value
0.5
1
1.5
2
2.5
FREQUENCY (MHz)
3686A F06a
Figure 6a. Switching Frequency vs RT
40
35
30
of R . Minimum on-time and edge loss must be taken into
T
consideration when selecting the intended frequency of
operation. Higher switching frequency increases power
dissipation and lowers efficiency. Finite transistor band-
width limits the speed at which the power switch can be
turned on and off, effectively setting the minimum on-time
of the LT3686A. For a given output voltage, the minimum
on-time determines the maximum input voltage to remain
in continuous mode operation outlined in the Minimum On
Timesectionofthedatasheet.Finitetransitiontimeresults
inasmallamountofpowerdissipationeachtimethepower
switch turns on and off (edge loss). Edge loss increases
with frequency, switch current, and input voltage.
5V
OUT
25
20
15
10
5
12V
OUT
3.3V
OUT
0
0.25
0.75
1.25
1.75
2.25
FREQUENCY (MHz)
3686A F06b
Figure 6b. Suggested Inductance vs Frequency
3686afa
12
LT3686A
ApplicAtions inForMAtion
Usingasmallervalueinductorwillincreaseinductorcurrent
The SYNC/MODE pin is used to synchronize the internal
oscillator with an external square wave. The synchroniz-
ing clock signal to the LT3686A should be below 2.5MHz
with pulse width of at least 200ns on and off time, a low
state below 0.4V and a high state above 0.8V. The SYNC
frequency must be higher than the RT programmed fre-
quency; see Table 1.
ripple and reduce the V voltage at which the active load
IN
can keep the LT3686A at full switching frequency.
There are several graphs in the Typical Performance
Characteristics section of this data sheet that show the
maximum load current as a function of input voltage and
inductor value for several popular output voltages. Low
inductance may result in discontinuous mode opera-
tion, which is okay, but further reduces maximum load
current. For details of the maximum output current and
discontinuous mode operation, see Linear Technology
Application Note 44. Finally, for duty cycles greater than
The inductor value should be chosen based on the RT
frequency rather than the highest synchronization fre-
quency.
The SYNC/MODE pin doubles as mode select for the
BD active load circuit. The active load is enabled when
SYNC/MODE is driven with clock pulses or tied greater
than 0.8V and disabled when SYNC/MODE is tied below
0.4V. See Fixed Frequency at Light Load section.
50% (V /V > 0.5), there is a minimum inductance
OUT IN
required to avoid subharmonic oscillations. See Linear
Technology Application Note 19.
Catch Diode
Inductor Selection and Maximum Output Current
A low capacitance 1-2A Schottky diode is recommended
for the catch diode, D1. The diode must have a reverse
voltage rating equal to or greater than the maximum input
voltage. The MBRM140 is a good choice; it is rated for
1A continuous forward current and a maximum reverse
voltage of 40V.
A good first choice for the inductor value is:
4(VOUT + VD)
L=
f
where V is the voltage drop of the catch diode (~0.4V), L
D
is in μH, frequency is in MHz. With this value there will be
no subharmonic oscillation. The inductor’s RMS current
rating must be greater than the maximum load current
anditssaturationcurrentshouldbeabout30%higher.For
robust operation during fault conditions, the saturation
current should be above 2A. To keep efficiency high, the
series resistance (DCR) should be less than 0.1Ω. Table 2
lists several vendors and types that are suitable. For small
size, the inductor can be chosen according to:
Input Capacitor
Bypass the input of the LT3686A circuit with a 2.2μF or
higher value ceramic capacitor of X7R or X5R type. Y5V
types have poor performance over temperature and ap-
plied voltage and should not be used. A 2.2μF ceramic is
adequate to bypass the LT3686A and will easily handle
the ripple current. However, if the input power source has
high impedance, or there is significant inductance due to
long wires or cables, additional bulk capacitance may be
2(VOUT +VD)
L=
f
Table 2.
VENDOR
URL
PART SERIES
INDUCTANCE RATE(µH)
SIZE (mm)
Sumida
www.sumida.com
CDRH4D28
CDRH5D28
CDRH8D28
1.2 to 4.7
2.5 to 10
2.5 to 33
4.5 x 4.5
5.5 x 5.5
8.3 x 8.3
Toko
www.toko.com
A916CY
D585LC
2 to 12
1.1 to 39
6.3 x 6.2
8.1 x 8
Würth Elektronik
www.we-online.com
WE-TPC(M)
WE-PD2(M)
WE-PD(S)
1 to 10
2.2 to 22
1 to 27
4.8 x 4.8
5.2 x 5.8
7.3 x 7.3
3686afa
13
LT3686A
ApplicAtions inForMAtion
necessary. This can be provided with a low performance
electrolytic capacitor. Step-down regulators draw current
from the input supply in pulses with very fast rise and fall
times. The input capacitor is required to reduce the result-
ing voltage ripple at the LT3686A and to force this very
high frequency switching current into a tight local loop,
minimizing EMI. A 2.2μF capacitor is capable of this task,
but only if it is placed close to the LT3686A and the catch
diode (see the PCB Layout section). A second precaution
regarding the ceramic input capacitor concerns the maxi-
mum input voltage rating of the LT3686A. A ceramic input
capacitor combined with trace or cable inductance forms
a high quality (underdamped) tank circuit. If the LT3686A
circuit is plugged into a live supply, the input voltage can
ring to twice its nominal value, possibly exceeding the
LT3686A’s voltage rating. This situation is easily avoided;
see the Hot Plugging Safely section.
whereC
isinμFandfrequencyisinMHz.UseanX5Ror
OUT
X7Rtypeandkeepinmindthataceramiccapacitorbiased
withV willhavelessthanitsnominalcapacitance. This
OUT
choice will provide low output ripple and good transient
response. Transient performance can be improved with
a high value capacitor, but a phase lead capacitor across
the feedback resistor, R1, may be required to get the full
benefit (see the Compensation section).
For small size, the output capacitor can be chosen ac-
cording to:
83
COUT
=
VOUT • f
where C
is in μF and frequency is in MHz. However,
OUT
usinganoutputcapacitorthissmallresultsinanincreased
loop crossover frequency and increased sensitivity to
noise, requiring careful PCB design.
Output Capacitor
High performance electrolytic capacitors can be used for
the output capacitor. Low ESR is important, so choose
one that is intended for use in switching regulators. The
ESR should be specified by the supplier and should be
0.1Ω or less. Such a capacitor will be larger than a ceramic
capacitor and will have a larger capacitance, because the
capacitor must be large to achieve low ESR. Table 3 lists
several capacitor vendors.
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
theLT3686AtoproducetheDCoutput. Inthisroleitdeter-
mines the output ripple so low impedance at the switching
frequency is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LT3686A’scontrolloop. Ceramiccapacitorshaveverylow
equivalent series resistance (ESR) and provide the best
ripple performance. A good value is:
145
OUT • f
COUT
=
V
Table 3.
VENDOR
PHONE
URL
PART SERIES
COMMENTS
EEF Series
T494, T495
Panasonic
(714) 373-7366
www.panasonic.com
Ceramic
Polymer
Tantalum
Kemet
Sanyo
(864) 963-6300
(408) 794-9714
www.kemet.com
Ceramic
Tantalum
www.sanyovideo.com
Ceramic
Polymer
Tantalum
POSCAP
Murata
AVX
(404) 436-1300
(864) 963-6300
www.murata.com
www.avxcorp.com
Ceramic
Ceramic
Tantalum
TPS Series
Taiyo Yuden
www.taiyo-yuden.com
Ceramic
3686afa
14
LT3686A
ApplicAtions inForMAtion
Figure7showsthetransientresponseoftheLT3686Awith
several output capacitor choices. The output is 3.3V. The
loadcurrentissteppedfrom0.25Ato1Aandbackto0.25A,
and the oscilloscope traces show the output voltage. The
upper photo shows the recommended value. The second
photo shows the improved response (less voltage drop)
resulting from a larger output capacitor and a phase lead
capacitor. The last photo shows the response to a high
performanceelectrolyticcapacitor.Transientperformance
is improved due to the large output capacitance.
BOOST and BD Pin Considerations
Capacitor C3 and the internal boost diode are used to
generate a boost voltage that is higher than the input
voltage. In most cases a 0.22μF capacitor will work well.
Figure 8 shows two ways to arrange the boost circuit. The
BOOST pin must be at least 2.2V above the SW pin for
best efficiency. For outputs of 3V and above, the standard
circuit (Figure 8a) is best. For outputs less than 3V and
above 2.5V, place a discrete Schottky diode (such as the
SYNC/MODE < 0.4V
SYNC/MODE > 0.8V
V
OUT
32.4k
10k
I
I
L
L
500mA/DIV
500mA/DIV
22µF
FB
V
V
OUT
50mV/DIV
AC
OUT
50mV/DIV
AC
3686A F07a
3686A F07b
3686A F07c
3686A F07f
3686A F07i
20µs/DIV
20µs/DIV
20µs/DIV
20µs/DIV
20µs/DIV
20µs/DIV
V
OUT
47pF
32.4k
10k
I
I
L
L
500mA/DIV
500mA/DIV
22µF
×2
FB
V
V
OUT
50mV/DIV
AC
OUT
50mV/DIV
AC
3686A F07d
3686A F07e
V
OUT
32.4k
I
I
L
L
+
500mA/DIV
500mA/DIV
100µF
FB
10k
V
V
SANYO
4TPB100M
OUT
OUT
50mV/DIV
AC
50mV/DIV
AC
3686A F07g
3686A F07h
Figure 7. Transient Load Response of the LT3686A with Different Output Capacitors as the Load Current Is Stepped from 0.25A to
1A. VIN = 12V, VOUT = 3.3V, L = 6.8µH , Frequency = 2MHz
3686afa
15
LT3686A
ApplicAtions inForMAtion
BAT54)inparallelwiththeinternaldiodetoreduceV . The
the optimal boost capacitor for the chosen BD voltage.
The absence of BD voltage during startup will increase
minimum voltage to start and reduce efficiency. You must
also be sure that the maximum voltage rating of BOOST
D
following equations can be used to calculate and minimize
boost capacitance in μF:
0.065
pin is not exceeded. The BD pin can also be tied to V
CBOOST
=
IN
(V + VCATCH – VD −2.2)• f
(Figure 8c) but V will be limited to 25V and the active
BD
IN
load circuit is automatically disabled.
V is the forward drop of the boost diode, V
is the
D
CATCH
The minimum operating voltage of an LT3686A applica-
tion is limited by the undervoltage lockout (3.6V) and by
the maximum duty cycle as outlined above. For proper
start-up, the minimum input voltage is also limited by
the boost circuit. If the input voltage is ramped slowly, or
forward drop of the catch diode (D1), and frequency is in
MHz. A typical value of 0.22µF can be used for C
.
BOOST
For lower output voltages the BD pin can be tied to an
external voltage source with adequate local bypassing
(Figure 8b). The above equations still apply for calculating
BD
BOOST
LT3686A
V
V
V
V
V
SW
DA
OUT
OUT
OUT
IN
IN
GND
V
– V ≅ V
SW OUT
BOOST
8a
MAX V
≅ V + V
IN
BOOST
OUT
V
DD
BD
BOOST
LT3686A
V
V
SW
DA
IN
IN
GND
V
– V ≅ V
SW DD
BOOST
MAX V
≅ V + V
IN
8b
BOOST
DD
BD
BOOST
LT3686A
V
V
SW
DA
IN
IN
GND
V
– V ≅ V
IN
BOOST
SW
3686A F08
MAX V
≅ 2V
8c
BOOST
IN
Figure 8.
3686afa
16
LT3686A
ApplicAtions inForMAtion
the discharged output capacitor will present a load to the
switcher which will allow it to start. At light loads, the
inductorcurrentbecomesdiscontinuousandtheeffective
duty cycle can be very high. This reduces the minimum
the LT3686A is turned on with its EN/UVLO pin when the
output is already in regulation, then the boost capacitor
may not be fully charged. Because the boost capacitor is
charged with the energy stored in the inductor, the circuit
will rely on some minimum load current to get the boost
circuit running properly.
input voltage to approximately 400mV above V . At
OUT
higher load currents, the inductor current is continuous
and the duty cycle is limited by the maximum duty cycle,
requiring a higher input voltage to maintain regulation.
This minimum load will depend on the input and output
voltages, and on the arrangement of the boost circuit. The
minimum load generally goes to zero once the circuit has
started. Figure 9 shows plots of minimum load to start
and to run as a function of input voltage. In many cases
AstheLT3686Aentersdropout,theboostcapacitorvoltage
willbelimitedbyV ,whichisfixedbythemaximumduty
OUT
cycle. If the boost capacitor’s voltage during dropout falls
7
9
8
7
6
6
5
4
3
2
5
4
3
2
START
START
1
0
1
RUN
RUN
SUSTAIN
SUSTAIN
0
1
10
100
1000
1
10
100
1000
I
(mA)
I
(mA)
LOAD
LOAD
3686A F09a
3686A F09b
Figure 9a. Typical Minimum Input Voltage, VOUT = 3.3V,
f = 1MHz, L = 15µH, SYNC/MODE < 0.4V
Figure 9b. Typical Minimum Input Voltage, VOUT = 5V,
f = 1MHz, L = 22µH, SYNC/MODE < 0.4V
7
6
8
7
RUN
6
5
RUN
5
4
3
2
1
0
4
3
2
1
0
1
10
100
1000
1
10
100
1000
I
(mA)
I
(mA)
LOAD
LOAD
3686A F09c
3686A F09d
Figure 9c. Typical Minimum Input Voltage, VOUT = 3.3V,
f = 1MHz, L = 15µH, SYNC/MODE > 0.8V
Figure 9d. Typical Minimum Input Voltage, VOUT = 5V,
f = 1MHz, L = 22µH, SYNC/MODE > 0.8V
3686afa
17
LT3686A
ApplicAtions inForMAtion
below the minimum voltage to sustain boosted operation
(2.2V across the boost capacitor), the output voltage will
fall suddenly to:
into a fixed on time, fixed frequency, open loop current
source. Instead of controlling switch current, the internal
error amplifier servos the active load on the output via
the BD pin to maintain output voltage regulation. The
impact on efficiency is mitigated by pulling the minimum
current necessary to keep switching at full frequency. The
necessary BD load to maintain output regulation depends
V
OUT
= (V ꢀ–2.2)ꢀ•ꢀDC
IN MAX
Figure 9 shows the minimum V necessary to sustain
IN
boosted operation during dropout. Once V drops below
IN
the sustain voltage, V will need to reach the start voltage
on V , inductor size, and load current. As the necessary
IN
IN
again to refresh the boost capacitor. The programmable
BD load increases beyond its 40mA limit, pulse-skipping
mode will resume.
undervoltagelockout(UVLO)functioncanbeusedtoavoid
operating unless V is greater than the start voltage.
IN
TheBDactiveloadcircuitryisenabledwhenMODEtiedhigh
anddisabledwhenMODEistiedlow. Evenwhenactivated,
the active load will shutdown when BD voltage exceeds
Fixed Frequency at Light Load
TheLT3686Acontainsuniqueactiveloadcircuitrytoallow
for full frequency switching at very light loads. To enable
theactiveload,drivetheSYNC/MODEpinwithclockpulses
or a DC voltage greater than 0.8V.
either 6V or V in an effort to minimize power dissipation
IN
and intelligently react to external configurations.
To address the startup concerns delineated in the BOOST
and BD Pin Considerations section, the active load will
assist startup by pulling maximum current (40mA) to
charge the boost capacitor voltage in the absence of an
adequate load. An internal power good circuit will disable
Typical fixed frequency nonsynchronous buck regulators
skip pulses at light loads. With a fixed input voltage, as the
loadcurrentdecreasesindiscontinuousmode,theregula-
tor is required to switch for shorter periods of time. When
therequiredontimedecreasesbelowthetypicalminimum
on time, the regulator skips one or more pulses so the
effective average duty cycle is equal to the required duty
cycle. This likelihood of entering pulse-skipping is exacer-
bated by the tendency for minimum on time to increase at
very light loads. Pulse-skipping is undesirable because it
causesunpredictable,sub-harmonicoutputripplethatcan
interferewiththeoperationofothersensitivecomponents
such as AM receivers and audio equipment.
the BD active load when V reaches 0.7V. Figure 9 com-
FB
pares plots of minimum input voltage to start and run as
a function of load current. In many cases the discharged
output capacitor will present a load to the switcher which
will allow it to start. The plots show the worst-case situ-
ation where V is ramping very slowly.
IN
The active load also activates to hasten the recharge of
boost cap when operating beyond maximum duty cycle.
When not in use, the active load pulls no current.
The BD active load is designed to combat pulse-skipping
byprovidinganoperationalregimebetweenfullfrequency
discontinuous and pulse-skipping modes.
40
35
PULSE-SKIPPING
30
ACTIVE
The maximum V before pulse-skipping in discontinu-
IN
LOAD
25
20
15
10
5
ous mode is directly dependent on load current; as the
load decreases, so does the pulse-skipping boundary. An
artificial load on the output helps push the pulse-skipping
boundary higher. The LT3686A achieves this goal by
commanding the minimum load necessary to keep itself
at full switching frequency, hence the circuitry is called
an active load.
DCM
CCM
0
0
20
40
60
80
(mA)
100 120 140
I
OUT
3686A F10
As the LT3686A approaches minimum on time in dis-
continuous mode, its power switch transitions smoothly
Figure 10. Regions of Operation (5VOUT, 2MHz)
3686afa
18
LT3686A
ApplicAtions inForMAtion
Soft-Start
regulated to the voltage at the SS pin until it exceeds 0.8V,
FB is then regulated to the reference 0.8V. Soft-start also
reduces the oscillator frequency to avoid hitting current
limit during start-up. Figure 12 shows the start-up wave-
forms with and without the soft-start circuit.
The SS pin is used to soft-start the LT3686A, eliminating
input current surge during start-up. It can also be used to
track another voltage in the system (Figure 11).
An internal 2µA current source charges an external soft-
start capacitor to generate a voltage ramp. FB voltage is
V
OUT
2V/DIV
V
SS
500mV/DIV
3686A F11
1ms/DIV
Figure 11. LT3686A Configured to Track Voltage on SS Pin
V
SW
10V/DIV
SS
GND
I
L
500mA/DIV
V
OUT
2V/DIV
5µs/DIV
V
V
= 10V
IN
OUT
= 3.3V
L = 6.8µH
C
C
= 22µF
OUT
= 0
SS
V
SW
10V/DIV
SS
GND
I
L
1.2nF
500mA/DIV
V
OUT
2V/DIV
3686A F12
50µs/DIV
V
V
= 10V
OUT
L = 6.8µH
IN
= 3.3V
C
C
= 22µF
OUT
= 1.2nF
SS
Figure 12. To Soft Start the LT3686A, Add a Capacitor to the SS Pin
3686afa
19
LT3686A
ApplicAtions inForMAtion
Short and Reverse Protection
pull large currents from the output through the SW pin
and the V pin. Figure 14 shows a circuit that will run
IN
Iftheinductorischosensothatitwon’tsaturateexcessively,
the LT3686A will tolerate a shorted output. When operat-
ing in short-circuit condition, the LT3686A will reduce
its frequency until the valley current is 1.7A (Figure 13).
There is another situation to consider in systems where
the output will be held high when the input to the LT3686A
is absent. This may occur in battery charging applications
or in battery backup systems where a battery or some
other supply is diode OR-ed with the LT3686A’s output.
only when the input voltage is present and that protects
against a shorted or reversed input.
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT3686A circuits. However, these
capacitors can cause problems if the LT3686A is plugged
into a live supply (see Linear Technology Application
Note 88 for a complete discussion). The low loss ceramic
capacitor combined with stray inductance in series with
the power source forms an underdamped tank circuit,
If the V pin is allowed to float and the EN/UVLO pin is
IN
held high (either by a logic signal or because it is tied to
V ), then the LT3686A’s internal circuitry will pull its
IN
quiescent current through its SW pin. This is fine if your
system can tolerate a few mA in this state. If you ground
theEN/UVLOpin,theSWpincurrentwilldroptoessentially
and the voltage at the V pin of the LT3686A can ring
IN
to twice the nominal input voltage, possibly exceeding
the LT3686A’s rating and damaging the part. If the input
supply is poorly controlled or the user will be plugging
zero. However, if the V pin is grounded while the output
IN
is held high, then parasitic diodes inside the LT3686A can
LT3686A
V
V
IN
SW
V
BD
IN
20V/DIV
BOOST
EN/UVLO
SYNC/MODE
SS
SW
V
OUT
I
L
500mA/DIV
DA
FB
RT
3686A F13
2µs/DIV
GND
V
= 35V
IN
L = 6.8µH
= 22µF
C
OUT
3686A F14
R
= 17.4k
T
V
= 0V
OUT
Figure 14. Input Diode Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output; it Also
Protects the Circuit from a Reversed Input. The LT3686A
Runs Only When the Input is Present
Figure 13. The LT3686A Reduces its Frequency from
2MHz to 160kHz to Protect Against Shorted Output
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20
LT3686A
ApplicAtions inForMAtion
the LT3686A into an energized supply, the input network
should be designed to prevent this overshoot. Figure 15
shows the waveforms that result when an LT3686A
circuit is connected to a 24V supply through six feet of
24-gauge twisted pair. The first plot is the response with
a 2.2μF ceramic capacitor at the input. The input voltage
rings as high as 35V and the input current peaks at 20A.
One method of damping the tank circuit is to add another
capacitor with a series resistor to the circuit. In Figure 15b
an aluminum electrolytic capacitor has been added. This
capacitor’s high equivalent series resistance damps the
circuit and eliminates the voltage overshoot. The extra
capacitor improves low frequency ripple filtering and
can slightly improve the efficiency of the circuit, though
it is likely to be the largest component in the circuit. An
alternative solution is shown in Figure 15c. A 1Ω resistor
is added in series with the input to eliminate the voltage
overshoot (it also reduces the peak input current). A 0.1μF
capacitorimproveshighfrequencyfiltering.Thissolutionis
smaller and less expensive than the electrolytic capacitor.
For high input voltages its impact on efficiency is minor,
reducing efficiency one percent for a 5V output at full load
operating from 24V.
CLOSING SWITCH
SIMULATES HOT PLUG
I
IN
V
IN
DANGER!
LT3686A
2.2µF
V
IN
20V/DIV
RINGING V MAY EXCEED
IN
+
ABSOLUTE MAXIMUM
RATING OF THE LT3686A
I
IN
5A/DIV
LOW
STRAY
IMPEDANCE
ENERGIZED
24V SUPPLY
INDUCTANCE
20µs/DIV
DUE TO 6 FEET
(2 METERS) OF
TWISTED PAIR
(15a)
V
LT3686A
2.2µF
IN
20V/DIV
+
+
+
10µF
35V
AI.EI.
I
IN
5A/DIV
(15b)
20µs/DIV
1Ω
V
LT3686A
2.2µF
IN
20V/DIV
0.1µF
I
IN
5A/DIV
3686A F15
20µs/DIV
(15c)
Figure 15. A Well Chosen Input Network Prevents Input Voltage Overshoot and Ensures Reliable Operation
When the LT3686A Is Connected to a Live Supply
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21
LT3686A
ApplicAtions inForMAtion
Frequency Compensation
theloopcrossoveroccursabovetheR C zero.Thissimple
C C
model works well as long as the value of the inductor is
not too high and the loop crossover frequency is much
lower than the switching frequency. With a larger ceramic
capacitor (very low ESR), crossover may be lower and a
phaseleadcapacitor(CPL)acrossthefeedbackdividermay
improve the phase margin and transient response. Large
electrolytic capacitors may have an ESR large enough to
create an additional zero, and the phase lead may not be
necessary. If the output capacitor is different than the rec-
ommendedcapacitor,stabilityshouldbecheckedacrossall
operatingconditions, includingloadcurrent, inputvoltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load.
The LT3686A uses current mode control to regulate the
output. This simplifies loop compensation. In particular,
the LT3686A does not require the ESR of the output ca-
pacitor for stability allowing the use of ceramic capacitors
to achieve low output ripple and small circuit size. Figure
16 shows an equivalent circuit for the LT3686A control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output cur-
rent proportional to the voltage at the V node. Note that
C
the output capacitor integrates this current, and that the
capacitor on the V node (C ) integrates the error ampli-
C
C
fier output current, resulting in two poles in the loop. R
C
provides a zero. With the recommended output capacitor,
CURRENT MODE
POWER STAGE
LT3686A
–
+
1V
g
m
=
2A/V
OUT
R1
C
PL
–
+
FB
g
=
V
m
C
ESR
C1
200µA/V
R
C1
C
800mV
ERROR
+
160k
AMPLIFIER
C
C
1M
100pF
R2
GND
3686A F16
Figure 16. Model for Loop Response
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22
LT3686A
ApplicAtions inForMAtion
PCB Layout
High Temperature Considerations
ForproperoperationandminimumEMI,caremustbetaken
during printed circuit board layout. Figure 17 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
The die temperature of the LT3686A must be lower than
the maximum rating of 125°C (150°C for LT3686AH). For
high ambient temperatures, care should be taken in the
layout of the circuit to ensure good heat sinking of the
LT3686A. The maximum load current should be derated
as the ambient temperature approaches the maximum
allowed junction temperature. The die temperature is
calculated by multiplying the LT3686A power dissipa-
tion by the thermal resistance from junction to ambient.
Power dissipation within the LT3686A can be estimated
by calculating the total power loss from an efficiency
measurement and subtracting the catch diode loss. The
resultingtemperatureriseatfullloadisnearlyindependent
ofinputvoltage.Thermalresistancedependsonthelayout
of the circuit board, but 43°C/W is typical for the (3mm
× 3mm) DFN package.
flow in the LT3686A’s V and SW pins, the catch diode
IN
(D1) and the input capacitor (C2). The loop formed by
these components should be as small as possible and tied
to system ground in only one place. These components,
along with the inductor and output capacitor, should be
placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
unbroken ground plane below these components, and tie
thisgroundplanetosystemgroundatonelocation, ideally
at the ground terminal of the output capacitor C1. The SW
and BOOST nodes should be as small as possible. Finally,
keep the FB node small so that the ground pin and ground
traceswillshielditfromtheSWandBOOSTnodes.Include
vias near the exposed GND pad of the LT3686A to help
remove heat from the LT3686A to the ground plane.
C1
OUT
C2
SW
D1
V
IN
BD
DA
BST
FB
SS
SYNC/
MODE
RT
UVLO
3686A F17
Figure 17. PCB Layout
3686afa
23
LT3686A
ApplicAtions inForMAtion
Outputs Greater Than 19V
0.22µF
Note that for outputs above 19V, the input voltage range
will be limited by the maximum rating of the BOOST pin.
The sum of input and output voltages cannot exceed the
BOOSTpin’s55Vrating. The25Vcircuit(Figure18)shows
how to overcome this limitation using an additional Zener
diode.
15V
V
IN
30V TO 36V
2.2µ
V
LT3686A
BD
IN
BOOST
EN/UVLO
0.22µF
SYNC/MODE
V
SW
OUT
100µH
500mA
SS
RT
DA
FB
100n
301k
GND
Other Linear Technology Publications
10µF
61.9k
10k
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for Buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
3686A F18
Figure 18. 25V Step-Down Converter
3686afa
24
LT3686A
typicAl ApplicAtions
0.8V Step-Down Converter
V
IN
V
BD
IN
3.6V TO 25V
2.2µF
1nF
EN/UVLO
BOOST
0.22µF
2.2µH
LT3686A
V
0.8V
1.2A
SW
SYNC/MODE
OUT
SS
RT
DA
FB
GND
61.9k
100µF
3686A TA02a
3.3V Step-Down Converter
V
IN
V
BD
IN
5V TO 37V
2.2µF
EN/UVLO
BOOST
0.22µF
6.8µH
LT3686A
V
3.3V
1.2A
SW
SYNC/MODE
OUT
SS
RT
DA
FB
31.6k
1nF
GND
61.9k
10k
22µF
3686A TA02b
1.8V Step-Down Converter
V
IN
V
BD
IN
3.6V TO 25V
2.2µF
1nF
EN/UVLO
BOOST
0.22µF
3.3µH
LT3686A
V
1.8V
1.2A
SW
SYNC/MODE
OUT
SS
RT
DA
FB
12.4k
GND
61.9k
10k
47µF
3686A TA02c
3686afa
25
LT3686A
typicAl ApplicAtions
3.3V Step-Down Converter with Programmed UVLO
V
IN
V
BD
IN
7.5V TO 37V
BOOST
500k
100k
0.22µF
6.8µH
2.2µF
LT3686A
EN/UVLO
V
3.3V
1.2A
SW
OUT
DA
FB
31.6k
SYNC/MODE
SS
RT
22µF
10k
1nF
GND
61.9k
3686A TA02d
2.5V Step-Down Converter
V
IN
V
BD
IN
3.6V TO 25V
2.2µF
1nF
EN/UVLO
BOOST
0.22µF
4.7µH
LT3686A
V
2.5V
1.2A
SW
SYNC/MODE
OUT
SS
RT
DA
FB
21.5k
GND
61.9k
10k
33µF
3686A TA02e
5V Step-Down Converter
V
IN
V
BD
IN
7V TO 37V
2.2µF
1nF
EN/UVLO
BOOST
0.22µF
10µH
LT3686A
V
SW
SYNC/MODE
OUT
5V
1.2A
SS
RT
DA
FB
52.3k
GND
61.9k
10k
15µF
3686A TA02f
3686afa
26
LT3686A
pAckAGe Description
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev D)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ± 0.102
(.112 ± .004)
2.845 ± 0.102
(.112 ± .004)
0.889 ± 0.127
(.035 ± .005)
1
6
0.35
REF
5.23
(.206)
MIN
1.651 ± 0.102
(.065 ± .004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
12
4.039 ± 0.102
7
NO MEASUREMENT PURPOSE
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
(.159 ± .004)
TYP
(NOTE 3)
0.406 ± 0.076
RECOMMENDED SOLDER PAD LAYOUT
(.016 ± .003)
12 11 10 9 8 7
REF
DETAIL “A”
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0° – 6° TYP
4.90 ± 0.152
(.193 ± .006)
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
1
2 3 4 5 6
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MSE12) 0910 REV D
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3686afa
27
LT3686A
pAckAGe Description
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
0.40 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DD) DFN REV C 0310
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3686afa
28
LT3686A
revision history
REV
DATE DESCRIPTION
PAGE NUMBER
A
5/11 Revised MSOP in Features, Pin Configuration, Order Information and Package Description sections
1, 2, 27
Updated Electrical Characteristics section
Updated value for EN/UVLO pin in Pin Functions section
Updated values in Operation section
3
7
9
Revised equation in Programmable Undervoltage Lockout section, Table 1 and minor text edit to Minimum On
Time in Applications Information section
10, 12, 13
3686afa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
tionthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
29
LT3686A
typicAl ApplicAtion
5V Step-Down Converter
V
IN
7V TO 37V
V
BD
IN
2.2µF
1nF
EN/UVLO
BOOST
0.22µF
10µH
LT3686A
V
SW
SYNC/MODE
OUT
5V
1.2A
SS
RT
DA
FB
52.3k
GND
61.9k
10k
15µF
3686A TA02f
relAteD pArts
PART NUMBER DESCRIPTION
COMMENTS
LT3686
LT3689
37V, 55V with Transient Protection 1.2A, 2.5MHz, High
Efficiency Step-Down DC/DC Converter
V : 3.6V to 37V, Transient to 55V, V
= 0.8V, I = 1.1mA, I <1µA,
Q SD
IN
OUT(MIN)
10-Pin 3mm × 3mm DFN Package
36V, 60V Transient Protection, 800mA, 2.2MHz, High
Efficiency MicroPower Step-Down DC/DC Converter
with POR Reset and Watchdog Timer
V : 3.6V to 36V Transient to 60V, V
= 0.8V, I = 75µA, I <1µA,
Q SD
IN
OUT(MIN)
16-Pin 3mm × 3mm QFN Package
LT3682
LT3970
LT3990
LT3480
36V, 60V
, 1A, 2.2MHz, High Efficiency MicroPower
V : 3.6V to 36V, V
= 0.8V, I = 75µA, I <1µA, 12-Pin 3mm × 3mm
MAX
IN
OUT(MIN) Q SD
Step-Down DC/DC Converter
DFN Package
40V, 350mA (I ), 2.2MHz, High Efficiency Step-Down V : 4.2V to 40V, V
DC/DC Converter with Only 2.5µA of Quiescent Current 2mm × 3mm DFN, 10-Pin MSOP Packages
= 1.21V, I = 2.5µA, I <1µA, 10-Pin
Q SD
OUT
IN
OUT(MIN)
60V, 350mA (I ), 2.2MHz, High Efficiency Step-Down V : 4.2V to 60V, V = 1.21V, I = 2.5µA, I <1µA, 10-Pin
DC/DC Converter with Only 2.5µA of Quiescent Current 3mm × 3mm DFN, 16-Pin MSOPE Packages
OUT
IN
OUT(MIN)
Q
SD
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, V : 3.6V to 38V, V
= 0.78V, I = 70µA, I <1µA, 10-Pin
Q SD
OUT
IN
OUT(MIN)
High Efficiency Step-Down DC/DC Converter with
3mm × 3mm DFN, 10-Pin MSOP Packages
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, V : 3.6V to 38V, V = 0.78V, I = 70µA, I <1µA, 10-Pin
OUT IN OUT(MIN)
Burst Mode® Operation
LT3685
LT3505
LT3437
Q
SD
High Efficiency Step-Down DC/DC Converter
3mm × 3mm DFN, 10-Pin MSOP Packages
36V with Transient Protection to 40V, 1.4A (I ), 3MHz, V : 3.6V to 34V, V
High Efficiency Step-Down DC/DC Converter
= 0.78V, I = 2mA, I = 2µA, 8-Pin
OUT
IN
OUT(MIN)
Q
SD
3mm × 3mm DFN, 8-Pin MSOP Packages
60V, 400mA (I ), MicroPower Step-Down DC/DC
Converter with Burst Mode Operation
V : 3.3V to 60V, V = 1.25V, I = 100µA, I <1µA, 10-Pin
OUT
IN
OUT(MIN)
Q
SD
3mm × 3mm DFN, 16-Pin TSSOP Packages
LT1976/LT1977 60V, 1.2A (I ), 200/500kHz, High Efficiency
V : 3.3V to 60V, V = 1.2V, I = 100µA, I <1µA, 16-Pin TSSOP
OUT
IN
OUT(MIN)
Q
SD
Step-Down DC/DC Converter with Burst Mode Operation Package
3686afa
LT 0511 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
30
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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