LT3692AIUH#PBF_技术文档

LT3692A

Monolithic Dual Tracking

3.5A Step-Down Switching Regulator

FeaTures

DescripTion

The LT^®3692A is a dual current mode PWM step-down

DC/DCconverterwithtwointernal3.8Aswitches.Independent

n

Wide Input Range:

– Operation from 3V to 36V

– OVLO Protects Circuit Through 60V Transients

Independent Supply, Shutdown, Soft-Start, UVLO,

Programmable Current Limit and Programmable

Power Good for Each 3.5A Regulator

Die Temperature Monitor

Adjustable/Synchronizable Fixed Frequency

Operation from 250kHz to 2MHz with Synchronized

Clock Output

input voltage, shutdown, feedback, soft-start, UVLO current

limitandcomparatorpinsforeachchannelsimplifycomplex

power supply tracking and sequencing requirements.

n

To optimize efficiency and component size, both convert-

ers have a programmable maximum current limit and are

synchronized to either a common external clock input, or

aresistorsettablefixed250kHzto2MHzinternaloscillator.

A frequency divider is provided for channel 1 to further

optimize component size. At all frequencies, a 180° phase

relationshipbetweenchannelsismaintained,reducingvolt-

age ripple and component size. A clock output is available

for synchronizing multiple regulators.

n

Independent Synchronized Switching Frequencies

Optimize Component Size

n

Antiphase Switching

Outputs Can Be Paralleled

Flexible Output Voltage Tracking

Minimum input to output voltage ratios are improved by

allowingtheswitchtostayonthroughmultipleclockcycles

onlyswitchingoffwhentheboostcapacitorneedsrecharg-

ing. Independent channel operation can be programmed

using the SHDN pin. Disabling both converters reduces

the total quiescent current to <10µA.

Low Dropout: 95% Maximum Duty Cycle

5mm × 5mm QFN Package

FMEA Compliant 38-Pin Exposed Pad TSSOP Package

applicaTions

n

Automotive Supplies

n

Distributed Supply Regulation

The LT3692A is an improved version of the LT3692 with

reduced minimum on-time.

L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Independent Synchronized Switching Frequencies

Extend Full Frequency Input Range

Typical applicaTion

3.3V and 1.2V 2-Stage Dual Step-Down Multi-Frequency Converter

V

OUT1

V

IN1

5.5V TO 36V

CH1:

550kHz

4.7µF

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

0.1µF

SW1

IND1

SW2

IND2

CH2:

2.2MHz

0.22µF

4.7µH

0.5µH

V

1.2V

1A

V

OUT2

OUT1

3.3V

LT3692A

V

OUT1

V

OUT2

FB2

3692A TA01b

2.5A

V

IN

= 30V

47µF

8.06k

24.9k

FB1

4.02k

100p

47µF

2.2MHz

550kHz

100k

CMPI1

CMPI2 FB1

CMPO2

8.06k

CMPO1

PG

SS1

SS2

ILIM1

ILIM2

V

C2

C1

RT/SYNC CLKOUT

DIV

CLKOUT

2.2MHz

220pF

0.1µF

33pF 680pF

13k

T

J

22pF

GND

10nF

40.2k

33.2k

100k

68.1k 102k

3692a TA01a

3692a TA01c

3692afc

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For more information www.linear.com/3692A

LT3692A

absoluTe MaxiMuM raTings ^{(Note 1)}

V

, SHDN1/2, CMPO1/2.......................................40V

V

, T .............................................................. 100µA

C1/2 J

IN1/2

V

Transient (Note 2)...........................................60V

Operating Junction Temperature Range (Note 3)

SW1/2....................................................................V

BST1/2 ......................................................................60V

BST1/2 Pin Above SW1/2..........................................25V

LT3692AEUH ..................................... –40°C to 125°C

LT3692AIUH ...................................... –40°C to 125°C

LT3692AHUH..................................... –40°C to 150°C

LT3692AEFE ...................................... –40°C to 125°C

LT3692AIFE ....................................... –40°C to 125°C

LT3692AHFE...................................... –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

IN1/2

IND1/2, V

.........................................................40V

OUT1/2

FB1/2, CMPI1/2, SS1/2................................................5V

RT/SYNC .....................................................................5V

DIV, ILIM1/2.............................................................3.0V

pin conFiguraTion

TOP VIEW

1

2

SW1

NC

38

37

36

35

34

33

32

31

30

29

28

NC

IND1

NC

TOP VIEW

3

V

IN1

4

SHDN1

SS1

V

OUT1

NC

5

32 31 30 29 28 27 26 25

6

I

BST1

CMPO1

CMPI1

FB1

LIM1

BST1

CMPO1

CMPI1

FB1

1

2

3

4

5

6

7

8

24 ILIM1

7

V

C1

23

22

21

20

19

18

V

C1

8

NC

RT/SYNC

CLKOUT

9

RT/SYNC

CLKOUT

33

GND

10

11

12

13

14

15

16

17

18

19

39

GND

NC

FB2

T

J

T

J

FB2

CMPI2

CMPO2

BST2

DIV

V

27 DIV

CMPI2

CMPO2

BST2

NC

C2

17 ILIM2

V

I

26

25

24

23

22

21

20

C2

9

10 11 12 13 14 15 16

UH PACKAGE

LIM2

SS2

SHDN2

V

OUT2

NC

V

IN2

32-LEAD (5mm × 5mm) PLASTIC QFN

NC

θ

JA

= 23°C/W, θ = 1.5°C/W

IND2

NC

JC(PAD)

EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB

*DO NOT CONNECT

SW2

FE PACKAGE

38-LEAD PLASTIC TSSOP

θ

= 17.5°C/W, θ

= 3°C/W

JA

JC(PAD)

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

3692afc

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For more information www.linear.com/3692A

LT3692A

orDer inForMaTion

LEAD FREE FINISH

LT3692AEUH#PBF

LT3692AIUH#PBF

LT3692AHUH#PBF

LT3692AEFE#PBF

LT3692AIFE#PBF

LT3692AHFE#PBF

TAPE AND REEL

PART MARKING*

3692A

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

–40°C to 150°C

LT3692AEUH#TRPBF

LT3692AIUH#TRPBF

LT3692AHUH#TRPBF

LT3692AEFE#TRPBF

LT3692AIFE#TRPBF

LT3692AHFE#TRPBF

32-Lead (5mm × 5mm) Plastic QFN

38-Lead Plastic TSSOP

3692A

3692AFE

38-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_VIN1/2= 15V unless otherwise specified. (Note 3)

PARAMETER

CONDITIONS

MIN

1.24

–1

TYP

1.32

0

MAX

1.4

1

UNITS

V

l

SHDN Voltage Threshold Ch 1/2

SHDN Input Current Ch 1/2

V

SHDN

= 1.35V

µA

V

Undervoltage Lockout (Note 4)

2.5

36

2.8

39

6

3.1

43

IN1

Overvoltage Lockout Ch 1/2 (Note 5)

V

IN

l

Shutdown Current

Quiescent Current

V

SHDN

V

SHDN

V

SHDN

V

SHDN

V

VC1/2

V

VIN1/2

V

VC1/2

V

VC1/2

= 0V

13

µA

mA

µA

mV

nA

IN1

IN2

IN1

IN2

= 0V

0

2

= 2V

3

4

5

= 2V

400

790

780

–13

0

630

806

0

1000

822

830

13

l

Feedback Voltage Ch 1/2

= 1V

Feedback Voltage Regulation

Feedback Voltage Offset Ch 1 to Ch 2

Feedback Bias Current Ch 1/2

= 3V to 35V, V

= 1V

= 0.5V to 1.4V

VC1/2

= 1V

85

200

T Output Voltage (Note 6)

J

T = 25°C, I = 25µA, Temperature = 25°C

250

1.23

–380

mV

V

mV

J

TJ

I

= 25µA, Temperature = 125°C

TJ

= 25µA, Temperature = –40°C

l

T Error

Temperature = 25°C to 125°C

–100

300

17

0

100

500

33

mV

µMho

µA

J

Error Amp g Ch 1/2

V

VC1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

FB1/2

= 1V, I = 10µA

VC1/2

400

25

m

Error Amp Source Current Ch 1/2

Error Amp Sink Current Ch 1/2

Error Amp High Clamp Ch 1/2

= 0.7V, V

= 1V

VC1/2

=0.9V, V

= 0.7V

= 0V

20

28

36

µA

VC1/2

1.7

0.7

1.9

0.9

2.1

1.08

V

Error Amp Switching Threshold Ch 1/2

V

3692afc

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LT3692A

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_VIN1/2= 15V unless otherwise specified. (Note 3)

PARAMETER

CONDITIONS

MIN

9.5

TYP

12

MAX

14.5

2.4

2

UNITS

µA

l

Soft-Start Source Current Ch 1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

VC1/2

V

FB1/2

= 2V, V

= 2V

= 0.07V

SS1/2

Soft-Start V Ch 1/2

1.9

2.15

1.4

160

0

V

OH

Soft-Start Sink Current Ch 1/2

= 0.7V, V

= 0V

= 2V

0.7

mA

mV

µA

SS1/2

Soft-Start V Ch 1/2

120

–12

150

70

200

12

OL

l

Soft-Start to Feedback Offset Ch 1/2

Soft-Start Sink Current Ch 1/2 POR

Soft-Start POR Threshold

= 1V, V

= 2V, V

= 0.4V

SS1/2

= 0.14V (Note 7)

400

100

115

0

600

140

150

100

500

760

94

mV

nA

Soft-Start SW Disable Ch 1/2

CMPI Bias Current Ch 1/2

CMPO Leakage Ch 1/2

V

= 0V (Note 7)

95

FB1/2

= 0.8V

–100

CMPI1/2

= 0.8V, V

Rising

= 40V,

70

nA

CMPO1/2

l

CMPI Threshold Ch 1/2

700

86

720

90

mV

%

CMPI Threshold Ch 1/2 of V

CMPI Hysteresis Ch 1/2

Rising (Note 8)

FB1/2

35

60

85

mV

µA

CMPO Sink Current Ch 1/2

RT/SYNC Reference Current

= 0.6V, V

= 0.2V,

200

300

CMPO1/2

l

V

= 0.36V (E- and I-Grade)

= 0.36V (H-Grade)

11.3

11.2

12

12.7

13

µA

RT/SYNC

Minimum Switching Frequency

Switching Frequency

R

=0Ω

50

110

1

150

1075

3.0

kHz

MHz

Deg

µA

V

RT/SYNC

= 28k

=100k

925

2.25

Maximum Switching Frequency

Switching Phase Angle Ch 1 ≥ Ch 2

DIV Reference Current

2.5

185

12

l

V

= 1V

10.7

0.44

0.89

1.39

13.3

0.56

1.06

1.56

DIV

CH1 DIV 2 Threshold

R

= 0V

0.5

1.0

1.5

0.25

2

RT/SYNC

CH1 DIV 4 Threshold

V

CH1 DIV 8 Threshold

V

CLKOUT V

V

OL

OH

V

CLKOUT to SW1ON Delay ( t

CLKOUT to SW2ON Delay ( t

)

CLKOUT Rising

CLKOUT Falling

60

ns

DCLKOSW1

30

ns

DCLKOSW2

RT/SYNC to CLKOUT Delay ( t

SYNC Frequency Range

)

V

= 0V to 2V Rising Edge

= 2V to 0V Falling Edge

300

150

ns

DRTSYNCH

RT/SYNC

)

ns

DRTSYNCL

250

2000

kHz

Deg

ns

SYNC Phase Angle Ch 1 to Ch 2

Minimum Switch On-Time Ch 1/2

Minimum Switch Off-Time Ch 1/2

SYNC Frequency = 250kHz

180

140

200

ns

3692afc

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LT3692A

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_VIN1/2= 15V unless otherwise specified. (Note 3)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Minimum Boost for 100% DC Ch 1/2 (Note 9)

1.6

2.2

2.6

V

IND + V

Current Ch 1/2

V

= 0V

= 5V

1.5

0.5

5

µA

OUT

VOUT1/2

l

ILIM1/2 Reference Current

IND to V Maximum Current Ch 1/2

V

= 0V

10

12

16

µA

ILIM

V

= 0V, V

= 0.5V, V

= 1.5V, V

= 1V (Note 10)

= 5V (Note 10)

0.8

1.25

1.4

1.8

2

2.2

2.6

4.6

2.6

3.0

3.6

3.8

5.8

A

OUT

ILIM1/2

VOUT

= 1V (Note 10)

= 5V (Note 10)

= 1V (Note 10)

= 5V (Note 10)

VOUT

1.8

l

3.7

l

Switch Leakage Current Ch 1/2

Switch Saturation Voltage Ch 1/2

V

= 0V

1

10

µA

SW1/2

I

= 500mA, V

= 3A, V

= 18V

100

300

mV

SW1/2

BST1/2

= 18V

Boost Current Ch 1/2

I

= 500mA, V

= 8V

7

35

13

55

40

85

mA

SW1/2

BST1/2

= 3A, V

= 8V

BST1/2

Minimum Boost Voltage Ch1/2 (Note 11)

I

= 3A, V

= 8V

1.6

2.2

3.0

V

SW1/2

BST1/2

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: The T output voltage represents the temperature at the center

of the die while dissipating quiescent power. Due to switch power

J

dissipation and temperature gradients across the die, the T output

J

voltage measurement does not guarantee that absolute maximum junction

temperature will not be exceeded.

Note 2: Absolute Maximum Voltage at V

and SHDN1/2 pins is 60V for

IN1/2

nonrepetitive 1 second transients and 40V for continuous operation.

Note 7: An internal power on reset (POR) latch is set on the positive

transition of the SHDN1/2 pin through its threshold, thermal shutdown or

overvoltage lockout. The output of the latch activates current sources on

each SS pin which typically sink 400µA and discharge the SS capacitor.

The latch is reset when both SS pins are driven below the soft-start POR

threshold or the SHDN pin is taken below its threshold.

Note 8: The threshold is expressed as a percentage of the feedback

reference voltage for the channel.

Note 9: To enhance dropout operation, the output switch will be turned off

for the minimum off-time only when the voltage across the boost capacitor

drops below the minimum boost for 100% duty cycle threshold.

Note 3: The LT3692AEUH/LT3692AEFE is guaranteed to meet performance

specifications from 0°C to 125°C junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LT3692AIUH/LT3692AIFE is guaranteed over the full –40°C to 125°C

operating junction temperature range. The LT3692AHUH/LT3692AHFE is

guaranteed over the full –40°C to 150°C operating junction temperature

range. High junction temperatures degrade operating lifetimes. Operating

lifetime is derated at junction temperatures greater than 125°C.

Note 4: V undervoltage lockout is defined as the voltage which the V

IN

pin must exceed for operation. The threshold guarantees that internal bias

lines are regulated and switching frequency is constant. Actual minimum

input voltage to maintain a regulated output will depend upon output

voltage and load current. See the Applications Information section.

Note 10: The IND to V

current flowing from the IND pin to the V

maximum current is defined as the value of

OUT

pin which resets the switch

OUT

latch when the V pin is at its high clamp.

C

Note 11: This is the minimum voltage across the boost capacitor needed

to guarantee full saturation of the internal power switch.

Note 5: V overvoltage lockout is defined as the voltage when exceeded

IN

halts converter operation. See the Applications Information section.

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For more information www.linear.com/3692A

LT3692A

Typical perForMance characTerisTics

V_INOvervoltage Threshold

vs Temperature

V_IN1Quiescent Current

vs SHDN1 Voltage

Shutdown Threshold and Minimum

Input Voltage vs Temperature

3.5

3.0

41.0

40.5

40.0

6000

5000

4000

3000

2000

1000

0

MINIMUM

INPUT VOLTAGE

2.5

39.5

39.0

38.5

38.0

37.5

37.0

36.5

36.0

2.0

1.5

1.0

0.5

150°C

125°C

25°C

–50°C

SHUTDOWN

THRESHOLD VOLTAGE

0

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

–25

0

150

–50

25 50 75 100 125

TEMPERATURE (°C)

1

1.2

0

0.2 0.4 0.6 0.8

VOLTAGE (V)

1.4

3692A G02

3692A G01

3692A G03

Shutdown Quiescent Current

vs Temperature

FB Voltage and CH1-CH2 FB

Offset vs Temperature

T_JOutput Voltage vs Temperature

820

815

810

805

800

8

1.50

1.25

1.00

0.75

0.50

0.25

0

10

9

8

7

6

5

4

3

2

1

0

V

= V

= 0V

SHDN2

SHDN1

6

4

I

Q1

2

OFFSET

0

R

= 30k

–2

–4

–6

–8

TJ

CH2

CH1

TO GND

–0.25

–0.50

R

TJ

= 30k TO –1V

I

Q2

25 50

TEMPERATURE (°C)

75 100

–50 –25

0

125 150

125

100

150

–50

50

50 75

–25

0

25

75

–50 –25

0

25

100 125 150

TEMPERATURE (°C)

3692A G04

3692A G05

3692A G06

Error Amplifier Transconductance

vs Temperature

Soft-Start-to-Feedback Offset

vs Temperature

Comparator Thresholds

vs Temperature

750

740

730

720

710

700

690

680

670

660

650

425

420

415

410

405

400

395

390

385

380

375

370

4

V

= 0.4V

SS

3

2

RISING

THRESHOLD

1

0

–1

–2

–3

–4

FALLING

THRESHOLD

–50

50

100 125

150

–25

0

25

75

50 75

TEMPERATURE (°C)

–50

10 30 50 70 90 110 130 150

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

–30 –10

TEMPERATURE (°C)

3692A G09

3692A G07

3692A G08

3692afc

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For more information www.linear.com/3692A

LT3692A

Typical perForMance characTerisTics

Comparator Sink Current

vs Temperature

Switching Frequency

vs Temperature

Switching Phase vs Temperature

1800

1600

1400

1200

1000

800

600

400

200

0

195

193

191

400

350

300

250

200

150

100

50

SINK CURRENT AT V

CMPO

= 0.4V

R

= 44.2k

= 28.0k

RT/SYNC

189

187

185

183

181

179

177

175

R

= 13.0k

= 0k

RT/SYNC

R

RT/SYNC

0

50 75

25

TEMPERATURE (°C)

–50 –25

50 75

TEMPERATURE (°C)

–50 –25

0

100 125 150

0

25

100 125

150

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

3692A G11

3692A G12

3692A G10

CLKOUT-to-SW1 Delay

vs Temperature

RT/SYNC-to-CLKOUT and SW1

Delay vs Temperature

Synchronization Duty Cycles

vs Temperature

160

150

140

130

120

110

100

90

100

90

80

70

60

50

40

30

20

10

0

450

400

350

300

250

200

150

100

50

RT/SYNC FREQUENCY = 1MHz

SW1

MAXIMUM RT/SYNC DUTY CYCLE

CLKOUT

MINIMUM RT/SYNC DUTY CYCLE

80

70

60

0

–50 –25

125

150

–50

50

100 125

150

0

25 50 75 100

TEMPERATURE (°C)

–25

0

25

75

50 75

–50 –25

0

25

100 125 150

TEMPERATURE (°C)

3692A G13

3692A G15

3695A G14

DIV Voltage Threshold

vs Temperature

Switch Saturation Voltage

vs Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

300

250

200

150

100

50

÷8

÷4

÷2

I

= 3A

SW

I

= 1A

SW

I

= 500mA

SW

0

50 75

25

TEMPERATURE (°C)

–50 –25

0

100 125 150

75 100

–50 –25

0

25 50

125 150

TEMPERATURE (°C)

3695A G16

3692A G17

3692afc

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LT3692A

Typical perForMance characTerisTics

Switch Peak Current

vs Temperature

Minimum Boost Voltage

vs Temperature

Boost Current vs Temperature

100

90

80

70

60

50

40

30

20

10

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

I

= 3A

SW

V

= 1.5V

ILIM

3A

V

= 0.5V

ILIM

V

= 0V

ILIM

1A

0.5A

–50

50

100 125

–50

50

100 125

150

–25

0

25

75

150

–25

0

25

75

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

TEMPERATURE (°C)

3692A G18

3692A G19

3692A G20

CLKOUT Frequency

vs RT/SYNC Resistance

5.0V Efficiency and Power Loss

3.3V Efficiency and Power Loss

90

85

80

75

70

65

60

3.0

2500

2250

2000

1750

90

85

80

75

70

65

60

3.0

2.5

2.0

1.5

1.0

0.5

0

EFFICIENCY

2.5

2.0

1.5

1.0

0.5

0

EFFICIENCY

1500

1250

POWER LOSS

1000

750

V

F

= 12V

SW

CH1 = 5V

V

= 12V

IN

500

= 1MHz

FREQ = 1MHz

CH1 = 3.3V

CH2 = 0V

250

0

CH2 = 0V

0

3.5

0

10 20 30 40 50 60 70 80

RT/SYNC RESISTANCE (kΩ)

0.5 1.0 1.5 2.0 2.5 3.0

4

2

2.5

0

0.5

1

1.5

3

3.5

4

OUTPUT CURRENT (A)

3692A G21

3692A G22

3692A G23

2.5V Efficiency and Power Loss

1.8V Efficiency and Power Loss

85

80

75

70

65

60

55

3.0

2.5

2.0

1.5

1.0

0.5

0

90

85

80

75

70

65

60

3.0

2.5

2.0

1.5

1.0

0.5

0

EFFICIENCY

POWER LOSS

V

F

= 12V

SW

CH1 = 2.5V

V

F

= 12V

SW

CH1 = 1.8V

IN

= 1MHz

CH2 = 0V

2.0 2.5

0

0.5 1.0 1.5

3.0 3.5

4

0

2.0

3.0 3.5

0.5 1.0 1.5

2.5

4

OUTPUT CURRENT (A)

3692A G24

3692A G25

3692afc

8

For more information www.linear.com/3692A

LT3692A

pin FuncTions

BST1/BST2: The BST pin provides a higher than V base

ILIM1/ILIM2: The voltage present at the ILIM pin deter-

mines the peak inductor current for the channel. The ILIM

pin is driven by an internal current source with a typical

value of 12µA. A resistor from the ILIM pin to ground sets

theILIMvoltage. Themaximumcurrentlimitrangeis4.8A

to2AwhentheILIMvoltagesare1.5Vand0Vrespectively.

IN

drive to the power NPN to ensure a low switch drop. If the

voltage between the BST pin and the V pin is less than

IN

the voltage required to fully turn on the power NPN, the

power switch is turned off to recharge the BST capacitor.

CMPI1/CMPI2: The CMPI pin is an input to a compara-

tor with a threshold of 720mV and 60mV of hysteresis.

Connecting the CMPI pin to the FB pin will generate a

power good signal when the output is within 90% of its

regulated value.

IND1/IND2: The IND pin is the input to the internal sense

resistor that measures current flowing in the inductor.

When the current in the resistor exceeds the current dic-

tated by the V pin, the SW latch is held in reset, disabling

C

the output switch. Bias current flows out of the IND pin.

CMPO1/CMPO2: The CMPO pin is an open-collector

output that sinks current when the CMPI pin falls below

its threshold. For a typical input voltage above 2.8V, its

RT/SYNC: The voltage present at the RT/SYNC pin deter-

mines the constant switching frequency. The RT/SYNC

pin is driven by an internal current source with a typical

value of 12µA which allows a single resistor from the RT/

SYNCpintogroundtosettheRT/SYNCvoltageandresult-

ing switching frequency. Minimum switching frequency

outputstateremainstrue,althoughduringshutdown,V

IN1

undervoltagelockoutorthermalshutdown,itscurrentsink

capability is reduced. The COMPO pins can be left open

circuit or tied together to form a single power good signal.

is typically 110kHz when V

is 0V and maximum

RT/SYNC

DIV:ThevoltagepresentattheDIVpindeterminestheratio

of channel 1 frequency to the master clock frequency set

by the RT/SYNC pin. The DIV pin is driven by an internal

current source with a typical value of 12µA which allows

a single resistor from the DIV pin to ground to set the

DIV voltage and resulting channel 1 frequency divider.

Ratios of 1, 2, 4 and 8 are available. See the Applications

Information section for more information.

switching frequency is typically 2.5MHz when V

is above 950mV.

RT/SYNC

Driving the RT/SYNC pin with an external clock signal will

synchronize the switch to the applied frequency. Synchro-

nization occurs on the rising edge of the clock signal after

theclocksignalisdetected.Eachrisingclockedgeinitiates

an oscillator ramp reset. A gain control loop servos the

oscillator charging current to maintain constant oscillator

amplitude. Hence, the slope compensation and channel

phase relationship remain unchanged. If the clock signal

is removed, the oscillator reverts to resistor mode after

thesynchronizationdetectioncircuitrytimesout.Theclock

source impedance should be set such that the current out

oftheRT/SYNCpininresistormodegeneratesafrequency

roughly equivalent to the synchronization frequency. See

theApplicationsInformationsectionformoreinformation.

DNC: Do Not Connect.

GND: The exposed pad pin is the only ground connec-

tion for the device. The exposed pad should be soldered

to a large copper area to reduce thermal resistance. The

GND pin is common to both channels and also serves as

small-signal ground. For ideal operation all small-signal

ground paths should connect to the GND pin at a single

point avoiding any high current ground returns.

FB1/FB2: The FB pin is the negative input to the error am-

plifier. The output switches to regulate this pin to 806mV

with respect to the exposed ground pad. Bias current

flows out of the FB pin.

3692afc

9

For more information www.linear.com/3692A

LT3692A

pin FuncTions

SHDN1/SHDN2: The shutdown pin is used to control each

channel’s operation. In addition to controlling channel 1,

the SHDN1 pin also activates control circuitry for both

channels and must be present for channel 2 to operate.

When SHDN1 is below its threshold, switching on both

channels is halted. Further reducing the SHDN1 voltage

to 0.6V reduces the quiescent current to a typical value

of 6µA Independent channel UVLO can be programmed

by connecting the SHDN pin to an input voltage divider.

See the Applications Information section for more infor-

mation. If the shutdown features are not used, the SHDN

SW1/SW2: The SW pin is the emitter of the internal power

NPN. At switch off, the inductor will drive this pin below

ground with a high dV/dt. An external Schottky catch

diode to ground, close to the SW pin and respective V

IN

decoupling capacitor’s ground, must be used to prevent

this pin from excessive negative voltages.

T : The T pin outputs a voltage proportional to junction

J

temperature. The pin is 250mV for 25°C and has a slope

of 10mV/°C. See the Applications Information section for

more information.

V

V : The V pin is the output of the error amplifier

C

pin should be tied to V .

C1/ C2

IN

and the input to the peak switch current comparator. It is

normally used for frequency compensation, but can also

be used as a current clamp or control loop override. If

SS1/SS2: Current flowing out the SS pin into an external

capacitor defines the rise time of the output voltage. When

theSSpinislowerthanthe0.806Vreference,thefeedback

is regulated to the SS voltage. When the SS pin exceeds

the reference voltage, the output will regulate the FB pin

voltage to 0.806V and the SS pin will continue to rise until

the error amplifier drives V above the maximum switch

C

current level, a voltage clamp activates. This indicates that

the output is overloaded and current is pulled from the SS

pin reducing the regulation point.

its clamp voltage. During an output overload, the V pin is

C

V

: The V pin powers the internal control circuitry for

IN1

driven above the maximum switch current level activating

IN1

bothchannelsandismonitoredbyovervoltage/undervolt-

its voltage clamp. When the V clamp is activated, the SS

C

age lockout comparators. The V pin is also connected

pinisdischargeduntiltheoutputreachesaregulationpoint

that the maximum output current can maintain. When the

overload condition is removed, the output soft starts from

that voltage. In the case of a SHDN or thermal shutdown

event, a power on reset latch ensures the capacitors on

bothchannelsarefullydischargedbeforeeitherisreleased.

Connecting both SS pins together ensures the outputs

track together.

IN1

to the collector of channel 1’s on-chip power NPN switch.

The V pin has high dI/dt edges and must be decoupled

IN1

to ground close to the pin of the device.

V

: The V pin powers the output stage for channel 2

IN2

and is monitored by overvoltage/undervoltage lockout

comparators. V voltage must be greater than typically

IN1

2.8V for V operation. The V pin is also the collector

IN2

of channel 2’s on-chip power NPN switch. The V pin

CLKOUT: The CLKOUT pin generates a square wave of 0V

to 2.5V which is synchronized to the internal oscillator. If

the switching frequency is set by an external resistor the

resultant clock duty cycle will be 50%. If the RT/SYNC pin

isdrivenbyanexternalclocksource,theresultantCLKOUT

duty cycle will mirror the external source.

IN2

has high dI/dt edges and must be decoupled to ground

close to the pin of the device.

V

: The V

pin is the output to the internal

OUT1/ OUT2

OUT

sense resistor that measures current flowing in the induc-

tor. When the current in the resistor exceeds the current

dictatedbytheV pin,theSWlatchisheldinresetdisabling

C

the output switch. Bias current flows out of the V

pin.

OUT

3692afc

10

For more information www.linear.com/3692A

LT3692A

block DiagraM

V

IN1

V

IN1

1.32V

+

–

+

–

SHDN1

39V

CHANNEL 1

BST1

SW1

IND1

DROPOUT

THERMAL

SHUTDOWN

ENHANCEMENT

PRE

S

R

DRIVER

CIRCUITRY

–

+

Q

2.5V

PRE

12µA

S

R

Q

–

+

–

SS1

V

OUT1

90mV

V

C1

R1

R2

FB1

2.5V

CMPI1

12µA

CMPO1

+

–

ILIM1

0.806V

0.72V

+

–

SLOPE

R

LIM

2.5V

COMPENSATION

12µA

RT/SYNC

DIV

T

J

INTERNAL

REGULATOR

AND

2.5V

CLK1

V

+

–

IN1

R3

CLKOUT

GND

MASTER CLOCK

2.8V

OSCILLATOR

AND AGC

REFERENCES

CLK2 TO CHANNEL 2

R

DIV

3692a F01

Figure 1. LT3692A Block Diagram

applicaTions inForMaTion

TheLT3692Aisadualchannel,constantfrequency,current

mode buck converter with internal 3.8A switches. Each

channelcanbeindependentlycontrolledwiththeexception

Once the internal reference reaches its regulation point,

the internal oscillator will start generating a master clock

signal for the two regulators at a frequency determined by

thevoltagepresentattheRT/SYNCpin.Thechannel 1clock

is then divided by 1, 2, 4 or 8 depending on the voltage

presentattheDIVpin. Channel2’sclockrunsatthemaster

clock frequency with a 180° phase shift from channel 1.

that V must be above the typically 2.8V undervoltage

IN1

lockoutthresholdtopowerthecommoninternalregulator,

oscillator and thermometer circuitry.

If the SHDN1 pin is taken below its 1.32V threshold switch-

ing on both channels will be disabled. Further reducing the

SHDN1 below a typical value of 0.6V will place the LT3692A

in a low quiescent current mode. In this mode the LT3692A

Alternatively, if a synchronization signal is detected by

the LT3692A the RT/SYNC pin, the master clock will be

generated at the incoming frequency on the rising edge

of the synchronization pulse with channel 1 in phase with

the synchronization signal. Frequency division and phase

remainsthesameastheinternallygeneratedmasterclock.

typically draws 6µA from V and <1µA from V . When

IN1

IN2

the SHDN pin is driven above 1.32V, the internal bias circuits

turn on generating an internal regulated voltage, 0.806V ,

FB

12µART/SYNC, DIVandILIMcurrentreferences, andaPOR

In addition, the internal slope compensation will be au-

signal which sets the soft-start latch.

tomatically adjusted to prevent subharmonic oscillation

3692afc

11

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

during synchronization. In either mode of oscillator op-

eration, a square wave with the master clock frequency,

synchronized to channel 1 is present at the CLKOUT pin.

in the inductor. The cycle is repeated with the start of each

clock cycle. However, if the internal sense resistor voltage

exceedsthepredeterminedlevelatthestartofaclockcycle,

the flip-flop will not be set resulting in a further decrease

in inductor current. Since the output current is controlled

The two regulators are constant frequency, current mode

step-down converters. Current mode regulators are con-

trolled by an internal clock and two feedback loops that

control the duty cycle of the power switch. In addition to

thenormalerroramplifier,thereisacurrentsenseamplifier

that monitors switch current on a cycle-by-cycle basis.

This technique means that the error amplifier commands

current to be delivered to the output rather than voltage.

A voltage fed system will have low phase shift up to the

resonant frequency of the inductor and output capacitor,

then an abrupt 180° shift will occur. The current fed sys-

tem will have 90° phase shift at a much lower frequency,

but will not have the additional 90° shift until well beyond

the LC resonant frequency. This makes it much easier to

frequency compensate the feedback loop and also gives

much quicker transient response.

by the V voltage, output regulation is achieved by the

C

error amplifier continually adjusting the V pin voltage.

C

The error amplifier is a transconductance amplifier that

compares the FB voltage to the lowest voltage present at

eithertheSSpinoraninternal806mVreference. Compen-

sationoftheloopiseasilyachievedwithasimplecapacitor

or series resistor/capacitor from the V pin to ground.

C

The regulators’ maximum output current occurs when

the V pin is driven to its maximum clamp value by the

C

error amplifier. The value of the typical maximum switch

current can be programmed from 4.8A to 2A by placing

a resistor from the ILIM pin to ground.

Since the SS pin is driven by a constant current source, a

singlecapacitoronthesoft-startpinwillgeneratecontrolled

linear ramp on the output voltage.

The Block Diagram in Figure 1 shows only one of the

switching regulators whose operation will be discussed

below. The additional regulator will operate in a similar

manner with the exception that its clock will be 180° out-

of-phase with the other regulator.

If the current demanded by the output exceeds the maxi-

mum current dictated by the V pin clamp, the SS pin

C

will be discharged, lowering the regulation point until the

outputvoltagecanbesupportedbythemaximumcurrent.

Once the overload condition is removed, the regulator will

soft-start from the overload regulation point.

When, during power-up, an internal POR signal sets

the soft-start latch, both SS pins will be discharged to

ground to ensure proper start-up operation. When the SS

Shutdowncontrol, V overvoltage,orthermalshutdown

pin voltage drops below 100mV, the V pin is driven low

IN

C

will set the soft-start latch, resulting in a complete soft-

start sequence.

disabling switching and the soft-start latch is reset. Once

the latch is reset the soft-start capacitor starts to charge

with a typical value of 12µA.

The switch driver operates from either the V or BST volt-

IN

age. An external diode and capacitor are used to generate a

As the voltage rises above 115mV on the SS pin, the V

C

drive voltage higher than V to saturate the output NPN and

pin will be driven high by the error amplifier. When the

IN

maintain high efficiency. If the BST capacitor voltage is suf-

ficient, the switch is allowed to operate to 100% duty cycle.

If the boost capacitor discharges towards a level insufficient

to drive the output NPN, a BST pin comparator forces a mini-

mumcycleofftime,allowingtheboostcapacitortorecharge.

voltageontheV pinexceeds0.9V,theclockset-pulsesets

C

the driver flip-flop, which turns on the internal power NPN

switch. This causes current from V , through the NPN

IN

switch, inductor and internal sense resistor to increase.

When the voltage drop across the internal sense resistor

exceeds a predetermined level set by the voltage on the

A comparator with a threshold of 720mV and 60mV of

hysteresis is provided for detecting error conditions. The

CMPO output is an open-collector NPN that is off when

the CMPI pin is above the threshold allowing a resistor

to pull the CMPO pin to a desired voltage.

3692afc

V pin, the flip-flop is reset and the internal NPN switch

C

is turned off. Once the switch is turned off the inductor

will drive the voltage at the SW pin low until the external

Schottky diode starts to conduct, decreasing the current

12

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

The voltage present at the T pin is proportional to the

for frequencies between 150kHz and 2250kHz. A 0V to

2.5V square wave with the same frequency as the master

oscillator and in phase with channel 1 is output via the

CLKOUT pin. The CLKOUT signal can be used to synchro-

nize multiple switching regulators.

J

junction temperature of the LT3692A. The T pin will be

J

250mV for a die temperature of 25°C and will have a slope

of 10mV/°C.

Choosing the Output Voltage

Toalleviatedutycyclerestrictionsduetominimumswitch-

on times, channel 1’s switching frequency can be divided

fromthemasterclockby1,2,4or8determinedbyresistor

The output voltage is programmed with a resistor divider

between the output and the FB pin. Choose the 1% resis-

tors according to:

R

in Figure 1. Channel 2’s switching frequency is not

DIV

affected by the DIV pin. The DIV pin is driven by a 12µA











V_OUT

0.806

R1= R2 •

– 1



currentsource. SettingresistorR setsthevoltagepres-

DIV

ent at the DIV pin which determines the divisor as shown

in Table 1. The DIV pin doesn’t have any input hysteresis

near the ratio thresholds.

R2 should be 10k or less to avoid bias current errors. Ref-

erence designators refer to the Block Diagram in Figure 1.

Table 1. Channel 1 Divisor vs V_DIV

Choosing the Switching Frequency

DIV VOLTAGE

< 0.5V

FREQUENCY RATIO

R

DIV

The LT3692A switching frequency is set by resistor R3 in

Figure 1. The RT/SYNC pin is driven by a 12µA current

source. Setting resistor R3 sets the voltage present at

the RT/SYNC pin which determines the master oscillator

frequency as illustrated in Figure 2. The R3 resistance

(in kΩ) may be calculated from the desired switching

frequency (in kHz) by the equation:

V

DIV

1

2

4

8

0

0.5V < V < 1.0V

61.9k

102k

150k

DIV

1.0V < V < 1.5V

DIV

1.5V < V

DIV

The switching frequency is typically set as high as pos-

sibletoreduceoverallsolutionsize. TheLT3692Aemploys

techniques to enhance dropout at high frequencies but

efficiency and maximum input voltage decrease due to

switching losses and minimum switch-on times.

2

R3 = 1.86E-6 • F

+ 2.81E-2 • F –1.76

SW

2500

2250

2000

1750

The maximum recommended frequency can be approxi-

mated by the equation:

V_OUT+ V_D

1

Frequency (Hz) =

•

1500

1250

V – V + V_Dt_ON(MIN)

IN

SW

1000

750

whereV istheforwardvoltagedropofthecatchdiode(D1

D

Figure 2), V is the voltage drop of the internal switch,

SW

500

and t

in the minimum on-time of the switch.

250

ON(MIN)

0

10 20 30 40 50 60 70 80

RT/SYNC RESISTANCE (kΩ)

3692a F02

Figure 2. Switching Frequency vs RT/SYNC Resistance

3692afc

13

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

Table 2. Efficiency and Size Comparisons for Different R_RT/SYNCValues, 3.3V Output

EFFICIENCY

VIN1/2

†

FREQUENCY

250kHz

RT/SYNC

5.90k

V

= 12V

V

L*

C*

C + L (Area)

IN(MAX)

2

88%

39V

12µH

5.6µH

3.3µH

1.5µH

1µH

120µF

60µF

30µF

22µF

15µF

59.8mm

2

500kHz

13.0k

87%

84%

82%

78%

39V

26V

18V

12V

54.6mm

2

1000kHz

1500kHz

2250kHz

28.0k

51.9mm

2

44.2k

46.9mm

2

69.8k

19.1mm

†

V

is defined as the highest typical input voltage that maintains constant output voltage ripple.

IN(MAX)

* Inductor and capacitor values chosen for stability and constant ripple current.

Forcing switch-off for a minimum time will only occur at the

end of a clock cycle when the boost capacitor needs to be

recharged.Thisoperationhasthesameeffectasloweringthe

clock frequency for a fixed off time, resulting in a higher duty

cycle and lower minimum input voltage. The resultant duty

cycle depends on the charging times of the boost capacitor

and can be approximated by the following equation:

The following example along with the data in Table 2

illustrates the trade-offs of switch frequency selection for

a single input voltage system.

Example.

V

= 25V, V

= 3.3V, I

= 2.5A, t

= 140ns,

IN

OUT

ON(MIN)

V = 0.6V, V = 0.4V:

D

SW

3.3+ 0.6

25 – 0.4+ 0.6 140ns

1

Max Frequency =

•

~ 1.1MHz

DC_MAX

=

1

1+

B

RT/SYNC ~ 31.6kΩ (Figure 2 )

where B is 3A divided by the typical boost current from

the Electrical Characteristics table.

Input Voltage Range

This leads to a minimum input voltage of:

Once the switching frequency has been determined, the

input voltage range of the regulator can be determined. The

minimuminputvoltageisdeterminedbyeithertheLT3692A’s

minimumoperatingvoltageof~2.8V,orbyitsmaximumduty

cycle. The duty cycle is the fraction of time that the internal

switchisonduringaclockcycle. Unlikemostfixedfrequency

regulators, the LT3692A will not switch off at the end of each

clock cycle if there is sufficient voltage across the boost

capacitor (C3 in Figure 1) to fully saturate the output switch.

V_OUT+ V_D

DC_MAX

V

=

– V_D+ V_SW

IN(MIN)

where V is the voltage drop of the internal switch.

SW

Figure 4 shows a typical graph of minimum input voltage

vs load current for the 3.3V output shown in Figure 15.

6

V

= 3.3V

OUT

t

P

5

4

3

2

1

0

START-UP

SW1

SW2

RUNNING

t /2

P

t

P

t /2

P

t

P

CLKOUT

0

1000 1500 2000 2500 3000 3500

500

3692a F03

t

DCLKOSW1

CURRENT (mA)

t

DCLKOSW2

3692a F04

Figure 4. Minimum Input Voltage vs Load Current

Figure 3. Timing Diagram RT/SYNC = 28.0k, t_P= 1µs, V_DIV= 0V

3692afc

14

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

In cases where multiple input voltages are present, or the

IN OUT

The maximum input voltage is determined by the absolute

V /V

ratio for channel 1 is significantly different than

maximum ratings of the V and BST pins and by the

IN

channel2, channel1’sfrequencycanbedividedbyafactor

of 2, 4 or 8 from the programmed value by setting the DIV

pin resistor to the appropriate value. Dividing channel 1’s

frequency will increase the maximum input voltage by the

same ratio. Channel 1’s external components will have to

be chosen according to the resulting frequency.

frequency and minimum duty cycle. The minimum duty

cycle is defined as:

DC

= t

• Frequency

ON(MIN)

MIN

Maximum input voltage as:

V_OUT+ V_D

DC_MIN

V

=

– V_D+ V_SW

IN(MAX)

Example:

V

= 3.3V, I

= 1A, frequency = 1MHz, temperature

OUT

Note that the LT3692A will regulate if the input voltage is

taken above the calculated maximum voltage as long as

= 25°C, V = 0.1V, B = 50 (from boost characteristics

SW

specification), V = 0.4V, t

= 140ns. V = 0.75V.

D

ON(MIN)

DIV

maximum ratings of the V and BST pins are not violated.

IN

However operation in this region of input voltage will

exhibit pulse-skipping behavior.

DC_MIN1= t_ON(MIN1)• Frequency/2 = 0.07

3.3 + 0.4

Example:

V

=

– 0.4 + 0.1= >39V

IN1(MAX)

0.07

V

= 3.3V, I

= 1A, frequency = 1MHz, temperature

OUT

= 25°C, V = 0.1V, B = 50 (from boost characteristics

SW

Inductor Selection and Maximum Output Current

specification), V = 0.4V, t

= 140ns:

D

ON(MIN)

A good first choice for the LT3692A inductor value is:

1

DC_MAX

=

= 98%

V_OUT

f

1

L =

1+

50

where f is frequency in MHz and L is in µH.

3.3 + 0.4

0.98

V

=

– 0.4 + 0.1= 3.48V

IN(MIN)

With this value the maximum load current will be ~3.5A,

independent of input voltage. The inductor’s RMS cur-

rent rating must be greater than your maximum load

current and its saturation current should be higher than

the maximum peak switch current, and will reduce the

output voltage ripple.

DC_MIN= t_ON(MIN)•Frequency = 0.14

3.3 + 0.4

V

=

– 0.4 + 0.1= 26.1V

IN(MAX)

0.14

If the maximum load for a single channel is lower than

2.5A, then you can decrease the value of the inductor and

operate with higher ripple current, or you can adjust the

maximum switch current for the channel via the ILIM pin.

Thisallowsyoutouseaphysicallysmallerinductor, orone

with a lower DCR resulting in higher efficiency.

2 • t

P

SW1

SW2

1/(2 • t )

t

P

t /2

P

t

P

The peak inductor and switch current is:

CLKOUT

∆I_L

2

I_SW(PK)= I_L(PK)= I_OUT

+

3692a F05

t

DCLKOSW1

t

DCLKOSW2

To maintain output regulation, this peak current must be

less than the LT3692A’s switch current limit, ILIM. ILIM

Figure 5. Timing Diagram RT/SYNC = 28.0k,

t_P= 1µs, V_DIV= 0.75V

3692afc

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can be set between 2A and 4.8A for each channel via a

resistor from the ILIM pin to ground. The ILIM pin is

driven by a 12µA current source. Setting resistor R

sets the voltage present at the ILIM pin which determines

the maximum switch current as illustrated in Figure 6. A

capacitor from the ILIM pin to ground, or a resistor divider

from the output, can be used to limit the peak current dur-

ing start-up. If a capacitor is used it must be discharged

before power-up to ensure proper operation (see 3.3V and

2.5V Dual Step-Down Converter in Typical Applications).

WhentheLT3692A’sinputsuppliesareoperatedatdifferent

input voltages, an input capacitor sized for that channel

should be placed as close as possible to the respective

LIM

V pins.

IN

A caution regarding the use of ceramic capacitors at the

input. A ceramic input capacitor can combine with stray

inductance to form a resonant tank circuit. If power is

applied quickly (for example by plugging the circuit into

a live power source) this tank can ring, doubling the input

voltage and damaging the LT3692A. The solution is to

either clamp the input voltage or dampen the tank circuit

by adding a lossy capacitor in parallel with the ceramic

capacitor. For details, see Application Note 88.

Referring to Figure 6, as the peak current limit is reduced,

slope compensation further reduces the peak current with

increasing duty cycle.

When the ILIM pin is used to reduce the peak switch cur-

rent, the equation for inductor choice becomes:

Output Capacitor Selection

Typicallystep-downregulatorsareeasilycompensatedwith

an output crossover frequency that is 1/10 of the switch-

ing frequency. This means that the time that the output

capacitor must supply the output load during a transient

step is ~2 or 3 switching periods. With an allowable 1%

drop in output voltage during the step, a good starting

value for the output capacitor can be expressed by:

50 • V_OUT

f •R_ILIM

L =

for R_ILIM> 24.9kΩ

where f is frequency in MHz, L in µH and R in kΩ.

4.5

4.0

3.5

Max Load Step

Frequency • 0.01• V_OUT

C_VOUT

=

3.0

2.5

2.0

1.5

Example:

V

= 3.3V, Frequency = 1MHz, Max Load Step = 2A.

2

OUT

C_VOUT

=

= 60µF

1.0

1E6• 0.01• 3.3V

0

30

50 60 70 80 90 100

10 20

40

ILIM PIN RESISTOR (kΩ)

The calculated value is only a suggested starting value.

Increasethevalueiftransientresponseneedsimprovement

or reduce the capacitance if size is a priority. The output

capacitor filters the inductor current to generate an output

with low voltage ripple. It also stores energy in order to

satisfytransientloadsandtostabilizetheLT3692A’scontrol

loop. The switching frequency of the LT3692A determines

the value of output capacitance required. Also, the current

mode control loop doesn’t require the presence of output

capacitor series resistance (ESR). For these reasons, you

are free to use ceramic capacitors to achieve very low

output ripple and small circuit size.

3692a F06

Figure 6. Peak Switch Current vs ILIM Resistor

Input Capacitor Selection

Bypass the inputs of the LT3692A circuit with a 4.7µF or

higher ceramic capacitor of X7R or X5R type. A lower

value or a less expensive Y5V type can be used if there

is additional bypassing provided by bulk electrolytic or

tantalum capacitors.

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Youcanalsouseelectrolyticcapacitors. TheESRsofmost

aluminum electrolytics are too large to deliver low output

ripple. Tantalum and newer, lower ESR organic electrolytic

capacitors intended for power supply use, are suitable

and the manufacturers will specify the ESR. The choice of

capacitor value will be based on the ESR required for low

ripple. Because the volume of the capacitor determines

its ESR, both the size and the value will be larger than a

ceramic capacitor that would give you similar ripple per-

formance. One benefit is that the larger capacitance may

give better transient response for large changes in load

current. Table 3 lists several capacitor vendors.

BST Pin Considerations

The capacitor and diode tied to the BST pin generate a

voltage that is higher than the input voltage. In most cases

a0.47µFcapacitorandasmallSchottkydiode(suchasthe

CMDSH-4E)willworkwell.Toensureoptimalperformance

at duty cycles greater than 80%, use a 0.5A Schottky

diode (such as a PMEG4005). Almost any type of film or

ceramic capacitor is suitable, but the ESR should be <1Ω

to ensure it can be fully recharged during the off time of

the switch. The capacitor value can be approximated by:

I_OUT(MAX)• V_OUT

C_BST

=

5 • V

V

OUT

– 2 • f

(

)

IN

Table 3

VENDOR

Taiyo Yuden

AVX

TYPE

SERIES

where I

is the maximum load current.

OUT(MAX)

Ceramic X5R, X7R

Figure 7 shows four ways to arrange the boost circuit. The

BST pin must be more than 3V above the SW pin for full

efficiency. Generally, for outputs of 3.3V and higher the

standard circuit (Figure 7a) is the best. For lower output

voltages the boost diode can be tied to the input (Fig-

ure 7b). The circuit in Figure 7a is more efficient because

the BST pin current comes from a lower voltage source.

Figure 7c shows the boost voltage source from available

DC sources that are greater than 3V. The highest efficiency

is attained by choosing the lowest boost voltage above 3V.

For example, if you are generating 3.3V and 1.8V and the

3.3V is on whenever the 1.8V is on, the 1.8V boost diode

can be connected to the 3.3V output. In any case, you

must also be sure that the maximum voltage at the BST

pin is less than the maximum specified in the Absolute

Maximum Ratings section.

Ceramic X5R, X7R

Tantalum

Kemet

Tantalum

TA Organic

AL Organic

T491, T494, T495

T520

A700

Sanyo

Panasonic

TDK

TA/AL Organic

AL Organic

POSCAP

SP CAP

Ceramic X5R, X7R

Catch Diode

The diode D1 conducts current only during switch-off

time. Use a Schottky diode to limit forward voltage drop to

increase efficiency. The Schottky diode must have a peak

reverse voltage that is equal to regulator input voltage and

sized for average forward current in normal operation.

Average forward current can be calculated from:

I_OUT

V

IN

The boost circuit can also run directly from a DC voltage

that is higher than the input voltage by more than 3V, as

in Figure 7d. The diode is used to prevent damage to the

I_D(AVG)

=

• V – V

(

IN

OUT

)

Withashortedcondition, diodecurrentwillincreasetothe

typical value determined by the peak switch current limit

of the LT3692A set by the ILIM pin. This is safe for short

periods of time, but it would be prudent to check with the

diode manufacturer if continuous operation under these

conditions can be tolerated.

LT3692A in case V is held low while V is present. The

X

IN

circuit saves several components (both BST pins can be

tied to D2). However, efficiency may be lower and dissipa-

tion in the LT3692A may be higher. Also, if V is absent,

X

the LT3692A will still attempt to regulate the output, but

will do so with very low efficiency and high dissipation

because the switch will not be able to saturate, dropping

1.5V to 2V in conduction.

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D2

C3

D2

V

BST

V

SW

V

IN

SW

IN

LT3692A

IND

OUT

IND

OUT

V

< 3V

OUT

V

OUT

GND

V

– V = V

V

– V = V

BST SW IN

BST(MAX)

BST

SW

OUT

= V + V

= 2 • V

IN

BST(MAX)

IN

OUT

D2

(7a)

(7b)

D2

V

= LOWEST V

IN

X

V

> V + 3V

IN

X

OR V

> 3V

OUT

C3

BST

V

SW

V

IN

SW

IN

LT3692A

IND

OUT

IND

OUT

V

< 3V

V

< 3V

OUT

V

OUT

GND

V

– V = V

V

– V = V

BST SW X

BST

SW

X

3692a F07

= V + V

= V

X

BST(MAX)

IN

X

BST(MAX)

= 3V

= V + 3V

IN

X(MIN)

(7c)

(7d)

Figure 7. BST Pin Considerations

The minimum input voltage of an LT3692A application is

limited by the minimum operating voltage (typically 2.8V)

and by the maximum duty cycle as outlined above. For

proper start-up, the minimum input voltage is also limited

by the boost circuit. If the input voltage is ramped slowly,

or the LT3692A is turned on with its SS pin when the

output is already in regulation, then the boost capacitor

may not be fully charged. Because the boost capacitor is

charged with the energy stored in the inductor, the circuit

will rely on some minimum load current to get the boost

circuit running properly. This minimum load will depend

on input and output voltages, and on the arrangement of

the boost circuit. The Typical Performance Characteristics

section shows plots of the minimum load current to start

and to run as a function of input voltage for 3.3V outputs.

Inmanycasesthedischargedoutputcapacitorwillpresent

a load to the switcher which will allow it to start. The plots

Outputs Greater Than 6V

For outputs greater than 6V, add a resistor of 1k to 2.5k

across the inductor to damp the discontinuous ringing of

the SW node, preventing unintended SW current. The 12V

output circuit in the Typical Applications section shows

the location of this resistor.

Frequency Compensation

The LT3692A uses current mode control to regulate the

output.Thissimplifiesloopcompensation.Inparticular,the

LT3692A does not require the ESR of the output capacitor

for stability so you are free to use ceramic capacitors to

achieve low output ripple and small circuit size. Frequency

compensation is provided by the components tied to the

V pin. Generally a capacitor and a resistor in series to

C

ground determine loop gain. In addition, there is a lower

value capacitor in parallel. This capacitor is not part of

the loop compensation but is used to filter noise at the

switching frequency.

show the worst-case situation where V is ramping very

IN

slowly.UseaSchottkydiodefortheloweststart-upvoltage.

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Loop compensation determines the stability and transient

performance.Designingthecompensationnetworkisabit

complicatedandthebestvaluesdependontheapplication

and in particular the type of output capacitor. A practical

approach is to start with one of the circuits in this data

sheet that is similar to your application and tune the com-

pensation network to optimize the performance. Stability

should then be checked across all operating conditions,

including load current, input voltage and temperature.

Synchronization

The RT/SYNC pin can also be used to synchronize the

regulatorstoanexternalclocksource.DrivingtheRT/SYNC

resistor with a clock source triggers the synchronization

detection circuitry. Once synchronization is detected, the

rising edge of SW1 will be synchronized to the rising edge

of the RT/SYNC signal and the rising edge of SW2 syn-

chronized to the falling edge of the RT/SYNC signal (see

Figures 10 and 11). During synchronization, a 0V to 2.4V

square wave with the same frequency and duty cycle as

the synchronization signal is output via the CLKOUT pin

with a typical propagation delay of 250ns. In addition, an

internal AGC loop will adjust slope compensation to avoid

subharmonic oscillation. If the synchronization signal is

halted, thesynchronizationdetectioncircuitrywilltimeout

in typically 10µs at which time the LT3692A reverts to the

free-runningfrequencybasedontheRT/SYNCpinvoltage.

The LT1375 data sheet contains a more thorough discus-

sion of loop compensation and describes how to test the

stability using a transient load.

Figure8showsanequivalentcircuitfortheLT3692Acontrol

loop. The error amp is a transconductance amplifier with

finite output impedance. The power section, consisting of

the modulator, power switch and inductor, is modeled as

a transconductance amplifier generating an output cur-

rent proportional to the voltage at the V pin. Note that

The synchronizing clock signal input to the LT3692A must

have a frequency between 200kHz and 2MHz, a duty cycle

between 20% and 80%, a low state below 0.5V and a high

state above 1.6V. Synchronization signals outside of these

parameters will cause erratic switching behavior. If the

RT/SYNC pin is held above 1.6V at any time, switching

will be disabled.

C

the output capacitor integrates this current, and that the

capacitor on the V pin (C ) integrates the error amplifier

C

output current, resulting in two poles in the loop. In most

cases a zero is required and comes from either the output

capacitor ESR or from a resistor in series with C .

C

This simple model works well as long as the value of the

inductor is not too high and the loop crossover frequency

is much lower than the switching frequency. A phase lead

If the synchronization signal is not present during regu-

lator start-up (for example, the synchronization circuitry

is powered from the regulator output) the RT/SYNC pin

must remain below 1V until the synchronization circuitry

is active for proper start-up operation.

capacitor (C ) across the feedback divider may improve

PL

the transient response.

LT3692A

CURRENT MODE

POWER STAGE

m

OUTPUT

g

= 4.8mho

C

R1

R2

ESR

PL

g

= 400µmho

m

FB

–

+

V

C

C1

3.6M

R

C

CERAMIC

ERROR

AMP

TANTALUM

OR

POLYMER

0.806V

C

F

C

3692a F08

Figure 8. Model for Loop Response

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Ifthesynchronizationsignalpowersupinanundetermined

Ifthesynchronizationsignalpowersupinalowimpedance

state (V , V , Hi-Z), connect the synchronization clock

state (V ), connect a resistor between the RT/SYNC pin

OL OH

OL

to the LT3692A as shown in Figure 9. The circuit as shown

will isolate the synchronization signal when the output

voltageisbelow90%oftheregulatedoutput.TheLT3692A

will start up with a switching frequency determined by the

resistor from the RT/SYNC pin to ground.

and the synchronizing clock. The equivalent resistance

seen from the RT/SYNC pin to ground will set the start-

up frequency.

If the synchronization signal powers up in a high imped-

ance state (Hi-Z), connect a resistor from the RT/SYNC

pin to ground. The equivalent resistance seen from the

RT/SYNC pin to ground will set the start-up frequency.

V

CC

OUT1

LT3692A

SYNCHRONIZATION

CIRCUITRY

PG1

RT/SYNC

CLK

3692a F09

Figure 9. Synchronous Signal Powered from Regulator’s Output

t

P

t

P

SW1

SW2

SW1

SW2

t /2

P

t

P

t

P

t /2

P

t

P

t

P

PON

CLKOUT

t

DCLKOSW1

t

DCLKOSW1

DCLKOSW2

PON

DCLKOSW2

t /2

t

P

t

P

RT/SYNC

DRTSYNCH

RT/SYNC

3692a F11

3692a F10

t

DRTSYNCH

DRTSYNC

Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50%

Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%

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Reducing Input Ripple Voltage

Shutdown and Undervoltage/Overvoltage Lockout

Synchronizing the switches to the rising and falling edges

ofthesynchronizationsignalprovidestheuniqueabilityto

Typically, undervoltage lockout (UVLO) is used in situa-

tions where the input supply is current limited, or has a

relatively high source resistance. A switching regulator

draws constant power from the source, so source cur-

rent increases as source voltage drops. This looks like a

negative resistance load to the source and can cause the

sourcetocurrentlimitorlatchlowunderlowsourcevoltage

conditions. UVLO prevents the regulator from operating

at source voltages where these problems might occur.

reduceinputripplecurrentsinsystemswhereV andV

IN1

IN2

are connected to the same supply. Decreasing the input

current ripple reduces the required input capacitance. For

example, the input ripple voltage shown in Figure 12 for

a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V

regulator is decreased from a peak of 472mV to 160mV

as shown in Figure 13 by driving the LT3692A with a 71%

duty cycle synchronization signal.

Overvoltagelockout(OVLO)istypicallyusedtoshutdown

the switching regulator during potentially harmful input

voltage transients.

SW1

SW2

The overvoltage lockout threshold is typically 39V. Each

channel of the LT3692A is forced into shutdown when its

input voltage exceeds 39V, and will survive voltages as

high as 60V. When the input voltage drops back below

39V, theLT3692AgoesthroughaPORcycleandtheoutput

soft-starts from its existing level to its regulation point.

INPUT

RIPPLE V

RT/SYNC

3692a F12

Additionally, an internal comparator will force both chan-

Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase

nels into shutdown below the minimum V

of 2.8V.

IN1

This feature can be used to prevent excessive discharge

of battery-operated systems. In addition to the V un-

IN1

SW1

SW2

dervoltage lockout, both channels will be disabled when

SHDN1 is less than 1.32V.

Programmable UVLO may be implemented using an input

voltage divider and one of the internal comparators (see

the Typical Applications section).

INPUT

RIPPLE V

RT/SYNC

When the SHDN pin is taken above 1.32V, its respective

channelisallowedtooperate.WhentheSHDNpinisdriven

below 1.32V, its channel is disabled. Taking SHDN1 below

0.6V will place the LT3692A in a low quiescent current

mode. A graph of quiescent current vs SHDN1 voltage

can be found in the Typical Performance Characteristics

section. There is no hysteresis on the SHDN pins.

3692a F13

Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase

KeeptheconnectionsfromanyseriesresistorstotheSHDN

pins short and make sure that the interplane or surface

capacitance to switching nodes is minimized.

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Soft-Start

a soft-start recovery. The typical time before the SS pin

takes control is:

The output of the LT3692A regulates to the lowest voltage

presentateithertheSSpinoraninternal0.806Vreference.

A capacitor from the SS pin to ground is charged by an

internal 12µA current source resulting in a linear output

ramp from 0V to the regulated output whose duration is

given by:

C_SS• 1.2V

1.4mA

t_SS(CONTROL)

=

Open-Collector Comparators

The CMPO pin is the open-collector output of an internal

comparator. The comparator compares the CMPI pin volt-

age to 90% of the reference voltage (0.72V) with 60mV

of hysteresis.

C_SS• 0.806V

t_RAMP

=

12µA

At power-up, a reset signal sets the soft-start latch and

discharges both SS pins to approximately 0V to ensure

proper start-up. When both SS pins are fully discharged

the latch is reset and the internal 12µA current source

starts to charge the SS pin.

The CMPO pin has a typical sink capability of 300µA when

theCMPIpinisbelowthethresholdandcanwithstand40V

when the threshold is exceeded. The CMPO pin is active

(sink capability is reduced in shutdown and undervoltage

lockout mode) as long as the V pin voltage exceeds

IN1

When the SS pin voltage is below 115mV, the V pin is

C

typically 2.8V.

pulled low which disables switching. This allows the SS

The comparators can be used to monitor input and output

voltages as well as die temperature. See the Typical Ap-

plications circuit collection for examples.

pin to be used as an individual shutdown for each channel.

As the SS pin voltage rises above 90mV, the V pin is re-

C

leased and the output is regulated to the SS voltage. When

the SS pin voltage exceeds the internal 0.806V reference,

theoutputisregulatedtothereference. TheSSpinvoltage

will continue to rise until it is clamped at typically 2.15V.

Output Tracking/Sequencing

Complexoutputtrackingandsequencingbetweenchannels

can be implemented using the LT3692A’s SS and CMPO

pins. Figure 14 shows several configurations for output

tracking/sequencing for a 3.3V and 1.8V application.

IntheeventofaV undervoltagelockout,thesoft-startlatch

IN1

issetforbothchannels,triggeringafullstart-upsequence.If

a channel’s SHDN pin is driven below 1.32V, its overvoltage

lockout is enabled, or the internal die temperature for its

power switch exceeds its maximum rating during normal

operation, the soft-start latch is set for that channel.

Independent soft-start for each channel is shown in Fig-

ure 16a. The output ramp time for each channel is set by

thesoft-startcapacitorasdescribedinthesoft-startsection.

Ratiometric tracking is achieved in Figure 14b by con-

necting both SS pins together. In this configuration, the

SS pin source current is doubled (24µA) which must be

taken into account when calculating the output rise time.

Inaddition,iftheloadexceedsthemaximumoutputswitch

current, the output will start to drop causing the V pin

C

clamp to be activated. As long as the V pin is clamped,

C

the SS pin will be discharged. As a result, the output will

be regulated to the highest voltage that the maximum

output current can support. For example, if a 6V output is

loaded by 1Ω the SS pin will drop to 0.64V, regulating the

output at 4.8V (4.8A • 1Ω). Once the overload condition

is removed, the output will soft start from the temporary

voltage level to the normal regulation point.

By connecting a feedback network from V

to the SS2

OUT1

voltage, absolute

pin with the same ratio that sets V

OUT2

tracking shown in Figure 14c is implemented. The mini-

mum value of the top feedback resistor (R1) should be set

such that the SS pin can be driven all the way to ground

with 1.4mA of sink current when V

is at its regulated

OUT1

voltage. In addition, a small V

voltage offset will be

OUT2

Since the SS pin is clamped at typically 2.15V and has to

discharge to 0.806V before taking control of regulation,

momentary overload conditions will be tolerated without

present due to the SS2 12µA source current. This offset

can be corrected for by slightly reducing the value of R2.

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Figure 14d illustrates output sequencing. When V

is

For example, assume a maximum input of 36V:

OUT1

within 10% of its regulated voltage, CMPO1 releases the

V = 36V, V

= 3.3V at 2A and V

= 1.2V at 1A.

IN

OUT1

OUT2

SS2 soft-start pin allowing V

to soft-start. In this case

OUT2

V_OUT+ V_D

1

CMPO1 will be pulled up to 2V by the SS pin. If a greater

voltage is needed for CMPO1 logic, a pull-up resistor to

Frequency (Hz) =

•

V – V + V_Dt_ON(MIN)

IN

SW

V

can be used. This will decrease the soft-start ramp

OUT1

V – V

• V

OUT

time and increase tolerance to momentary shorts.

(

)

IN

OUT

L =

V • f

IN

If precise output ramp up and down is required, drive the

SS pins as shown in Figure 14e. The minimum value of

resistor (R3) should be set such that the SS pin can be

driven all the way to ground with 1.4mA of sink current

during power-up and fault conditions.

Single Step-Down:

1.2 + 0.6

35V – 0.4 + 0.6 140ns

1

Frequency (Hz) =

•

≅ 350kHz

36V – 3.3 • 3.3

36V • 350kHz

(

)

Application Optimization

L1=

L2 =

≥ 8.5µH

≥ 3.3µH

In multiple channel applications requiring large V to

IN

V

ratios, the maximum frequency and resulting in-

OUT

36V – 1.2 • 1.2

36V • 350kHz

(

)

ductor size is determined by the channel with the largest

ratio. The LT3692A’s multi-frequency operation allows the

user to minimize component size for each channel while

maintaining constant frequency operation. The circuit in

Figure 15 illustrates this approach. A 2-stage step-down

approach coupled with multi-frequency operation will

further reduce external component size by allowing an

2-Stage Step-Down:

3.3 + 0.6

36V – 0.4 + 0.6 140ns

1

Frequency (Hz) =

•

≅ 750kHz

36V – 3.3 • 3.3

(

)

L1=

L2 =

≥ 4.0µH

≥ 1.0µH

increase in frequency for the channel with the lower V

to V

IN

36V • 750kHz

ratio. The drawback to this approach is that the

OUT

outputpowercapabilityforthefirststageisdeterminedby

the output power drawn from the second stage. The dual

step-down application in Figure 16 steps down the input

3.3 – 1.2 • 1.2

3.3 • 750kHz

(

)

2-Stage Step-Down Multi-Frequency:

= 100k, FREQ1 = 550kHz, FREQ2 = 2200kHz.

voltage (V ) to the highest output voltage then uses that

IN1

voltage to power the second output (V ). V

must be

IN2

OUT1

R

DIV

able to provide enough current for its output plus V

OUT2

36V – 3.3 • 3.3

36V • 550kHz

(

)

maximumload. NotethattheV

voltagemustbeabove

OUT1

L1=

≥ 5.4µH

V ’s minimum input voltage as specified in the Electrical

IN2

Characteristics (typically 2.8V) when the second channel

starts to switch. Delaying channel 2 can be accomplished

by either independent soft-start capacitors or sequencing

with the CMP01 output.

3.3 – 1.2 • 1.2

3.3 • 2200KHz

(

)

L2 =

≥ 0.47µH

In addition, R

= 33.2k reduces the peak current limit

ILIM2

on channel 2 to 2A, which reduces inductor size and catch

diode requirements.

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Independent Start-Up

Ratiometric Start-Up

Absolute Start-Up

V

OUT1

0.5V/DIV

V

OUT1

0.5V/DIV

PG1

PG2

PG1

PG2

PG1

V

OUT2

0.5V/DIV

PG2

5ms/DIV

10ms/DIV

LT3692A

V

OUT1

V

OUT1

V

OUT1

R1 R3

R2

R1 R3

FB1

CMPI1

FB1

CMPI1

FB1

CMPI1

R2

2.5V

CMPO1

12µA

SS1

12µA

SS1

12µA

SS1

PG1

0.72V

+

–

0.72V

+

–

0.72V

+

–

0.1µF

R4 R6

0.1µF

V

OUT2

R4 R6

R5

R4 R6

R5

FB2

CMPI2

R5

2.5V

CMPO2

PG2

12µA

SS2

12µA

SS2

12µA

SS2

0.72V

+

–

0.72V

+

–

0.72V

+

–

R8

0.22µF

R7

(14a)

(14b)

(14c)

Output Sequencing

Controlled Power Up and Down

V

OUT1

V

OUT1

0.5V/DIV

PG1/PG2

V

OUT2

V

OUT2

0.5V/DIV

PG1

PG2

SS1/2

10ms/DIV

LT3692A

V

OUT1

V

OUT1

R1

R2

R1 R3

FB1

CMPI1

FB1

CMPI1

R2

2.5V

CMPO1

12µA

SS1

12µA

SS1

PG1

0.72V

+

–

0.72V

+

–

R5

+

0.1µF

–

V

OUT2

V

OUT2

R4 R6

R5

R4 R6

R5

FB2

CMPI2

FB2

CMPI2

2.5V

CMPO2

PG2

12µA

SS2

12µA

SS2

0.72V

+

–

0.72V

+

–

3692a F14

0.22µF

(14d)

(14e)

Figure 14. SS Pin Configurations

3692afc

24

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

V

IN1

5.5V TO 36V

4.7µF

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

SW1

IND1

SW2

IND2

4.7µH

0.47µF

V

OUT2

OUT1

1.2V

LT3692A

3.3V

V

OUT1

V

OUT2

FB2

2A

600kHz

100k

PG2

3A

100µF

8.06k

47µF

100pF 4.02k

24.9k

300kHz

FB1

8.06k

×3

100k

CMPI1

CMPI2

PG1

CMPO1

SS1

CMPO2

SS2

ILIM1

ILIM2

ILIM1

V

C2

C1

CLOCKOUT

600kHz

RT/SYNC CLKOUT

DIV

0.1µF

820pF

680pF

T

J

GND

33pF

0.1µF

49.9k

7.50k

15.8k 61.9k

10nF

13.0k

3692a F15

Figure 15. 3.3V and 1.2V Dual Step-Down Multi-Frequency Converter

V

IN1

5.5V TO 36V

4.7µF

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

0.1µF

SW1

IND1

SW2

IND2

0.22µF

4.7µH

0.5µH

V

1.2V

1A

V

LT3692A

OUT2

OUT1

3.3V

2.5A

V

OUT1

V

OUT2

FB2

47µF

8.06k

24.9k

FB1

4.02k

100pF

8.06k

47µF

2.2MHz

550kHz

100k

CMPI1

CMPI2 FB1

CMPO2

CMPO1

PG

SS1

SS2

ILIM1

ILIM2

V

C2

C1

CLKOUT

2.2MHz

RT/SYNC CLKOUT

DIV

33pF

220pF

0.1µF

680pF

13k

22pF

T

J

GND

10nF

40.2k

33.2k

100k

68.1k 102k

3692a F16

Figure 16. 3.3V and 1.2V 2-Stage Dual Step-Down Multi-Frequency Converter

3692afc

25

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

Shorted and Reverse Input Protection

LT3692A

GND

V

SW

Iftheinductorischosensothatitwon’tsaturateexcessively,

an LT3692A step-down regulator will tolerate a shorted

output. There is another situation to consider in systems

where the output will be held high when the input to the

LT3692A is absent. This may occur in battery charging

applicationsorinbatteryback-upsystemswhereabattery

or some other supply is diode OR-ed with the LT3692A’s

IN

(18a)

LT3692A

V

SW

IN

output. If the V

pin is allowed to float and the SHDN

IN1/2

pin is held high (either by a logic signal or because it is

GND

tied to V ), then the LT3692A’s internal circuitry will pull

IN

itsquiescentcurrentthroughitsSWpin. Thisisfineifyour

system can tolerate a few mA in this state. If you ground

the SHDN pin, the SW pin current will drop to essentially

(18b)

zero. However, if the V pin is grounded while the output

IN

LT3692A

GND

V

SW

IN

is held high, then parasitic diodes inside the LT3692A can

pull large currents from the output through the SW pin

and the V

pin. Figure 17 shows a circuit that will run

IN1/2

only when the input voltage is present and that protects

3692a F18

(18c)

against a shorted or reversed input.

Figure 18. Subtracting the Current When the Switch Is On (18a)

from the Current When the Switch Is Off (18b) Reveals the Path of

the High Frequency Switching Current (18c). Keep this Loop Small.

The Voltage on the SW and BST Traces Will Also Be Switched; Keep

These Traces as Short as Possible. Finally, Make Sure the Circuit

Is Shielded with a Local Ground Plane

PARASITIC DIODE

D4

V

SW

IN

V

IN1/2

OUT1/2

LT3692A

3692a F17

Figure 17. Diode D4 Prevents a Shorted Input from Discharging a

Backup Battery Tied to the Output

3692afc

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For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

PCB Layout

Place additional vias near the catch diodes. Adding more

copper to the top and bottom layers and tying this copper

to the internal planes with vias can further reduce thermal

resistance. The topside metal and component outlines

in Figure 19 illustrate proper component placement and

trace routing.

For proper operation and minimum EMI, care must be

taken during printed circuit board (PCB) layout. Figure 18

shows the high di/dt paths in the buck regulator circuit.

Notethatlargeswitchedcurrentsflowinthepowerswitch,

the catch diode and the input capacitor. The loop formed

by these components should be as small as possible.

TheLT3692A’spowerful3.8Aswitchesallowtheconverter

to source large output currents. Depending on the con-

verter’s operating conditions, the resulting internal power

dissipation can raise the junction temperature beyond

its maximum rating. Operating conditions include input

voltages, output voltages, switching frequencies, output

currents, and the ambient environmental temperature,

etc. An estimation of the junction temperature rise above

ambient temperature helps determine whether a given

design may exceed the maximum junction ratings for

specific operating conditions. However, temperature rise

depends on PCB design and the proximity to other heat

sources. The final converter design must be evaluated

on the bench.

These components, along with the inductor and output

capacitor, should be placed on the same side of the cir-

cuit board and their connections should be made on that

layer. Place a local, unbroken ground plane below these

components, and tie this ground plane to system ground

at one location, ideally at the ground terminal of the out-

put capacitor C2. Route all small signal analog returns

to the ground connection at the bottom of the package.

Additionally, the SW and BST traces should be kept as

short as possible.

Thermal Considerations

ThePCBmustalsoprovideheatsinkingtokeeptheLT3692A

cool. The exposed metal on the bottom of the package

must be soldered to a ground plane. This ground should

be tied to other copper layers below with thermal vias;

theselayerswillspreadtheheatdissipatedbytheLT3692A.

An estimation of the junction temperature rise begins by

determining which circuit components dissipate power.

In order to simplify the power loss estimation, only the

inductors,catchdiodes,andtheLT3692Awillbeconsidered

3692a F19

DC1403A TSSOP LAYOUT

QFN LAYOUT

Figure 19. PCB Top Layer and Component Placement for TSSOP and QFN Packages

3692afc

27

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

as heat sources. After the operating conditions have been

determined, the individual power losses are calculated by:

Note that the larger TSSOP package demonstrates better

thermal performance than the compact QFN package on

the LT3692A demo circuit boards. For LT3692A applica-

tions that favor thermal performance, the TSSOP package

is the preferred package option.





V_OUT

V

IN

Power_D1,2= 1−

•I_OUT• V_FD









Power_IND1,2= R_IND•I_OUT2

Table 4. LT3692A Operating Conditions

V_OUT

V

IN

V

F

V

I

V

I

IN

SW

OUT1

OUT2

Power_CH1,2= 0.1•

•I_OUT2+ 2•10^–3

(V)

30

12

24

12

(kHz)

300/600

1000

500

(V)

(A)

(V)

(A)

1.2

3.3

5

2

2.5

2

3.3

2

2.5

2

I_OUT• V_OUT• V_BOOST

•V_IN+

+

40• V

IN

500

5

3













V_IN

I_OUT

0.3

V_IN•I_OUT•F_SW•10⁻⁶•

+

Table 5. LT3692A Power Loss Contributions

3

PD1

(W)

PD2

(W)

PL1

(W)

PL2

(W)

PCH1

(W)

PCH2

(W)

0.86

0.82

0.71

0.79

0.80

0.82

0.78

0.98

0.24

0.25

0.24

0.54

0.24

0.25

0.24

0.54

0.38

0.62

0.54

0.81

0.72

0.62

0.48

0.59

where:

F_SW= SwitchingFrequency inkHz

R_IND= Inductor Resistance

Table 6. Estimated System Power Loss and IC Temperature Rise

(W) TSSOP (°C) QFN (°C)

CALCULATED MEASURED CALCULATED MEASURED CALCULATED MEASURED

V_FD= CatchDiodeForward VoltageDrop

V_BOOST= SwitchBoost Voltage

P

LOSS

T

RISE

3.2

3.4

3.0

4.2

3.2

3.5

3.1

4.7

41.9

44.3

38.5

55.4

44.9

48.8

35.3

52.0

45.8

49

42.2

61.2

49.1

54.8

42.3

63

For the LT3692A demo board (see Figure 19) using the

TSSOP package, the estimated junction temperature rise

above ambient temperature is found by:

The power loss and temperature rise equations provided

in the Thermal Considerations section serve as a good

starting point for estimating the junction temperature

rise. However, the LT3692A is a very versatile converter.

The combination of independent input voltages, output

voltages, output currents, switching frequencies, and

package selections for the LT3692A dictate that no power

loss estimation scheme can accommodate every possible

operating condition. As such, it is absolutely necessary to

evaluate a converter’s performance at the bench.

T_RISETSSOP≈ 10• (Power_D1+ Power_D2)+

12.3• (Power_IND1+ Power_IND2)+ 17.5•

Power_CH1+ Power_CH2

(

)

The estimated junction temperature rise above ambient

for the LT3692A QFN layout (see Figure 19) is:

T_RISEQFN≈ 8.5• (Power_D1+ Power_D2)+

13• (Power_IND1+ Power_IND2)+ 23•

Power_CH1+ Power_CH2

(

)

Thepowerdissipationintheotherpowercomponentssuch

as boost diodes, input and output capacitors, inductor

core loss, and trace resistances cause additional copper

heating and can further increase what the IC sees as am-

bient temperature. See the LT1767 data sheet’s Thermal

Considerations section.

Forexample,thetypicalapplicationcircuitslistedinTable4

are used to calculate the individual power loss contribu-

tions in Table 5. Table 6 shows the estimated power loss

andjunctiontemperatureriseaboveambienttemperature.

3692afc

28

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

Die Temperature and Thermal Shutdown

Generating a Negative Regulated Voltage

The LT3692A T pin outputs a voltage proportional to the

The simple charge pump circuit in Figure 21 uses the

CLKOUT pin output to generate a negative voltage, elimi-

nating the need for an external regulated supply. Surface

mount capacitors and dual-package Schottky diodes

minimize the board area needed to implement the nega-

tive voltage supply.

J

internal junction temperature. The T pin typically outputs

J

250mV for 25°C and has a slope of 10mV/°C. Without the

aidofexternalcircuitry,theT pinoutputisvalidfrom20°C

J

to150°C(200mVto1.5V)withamaximumloadof100µA.

Full Temperature Range Measurement

30k

To extend the operating temperature range of the T out-

J

T

J

put below 20°C, connect a resistor from the T pin to a

J

LT3692A

CLKOUT

GND

330pF

D4

negative supply as shown in Figure 20. The negative rail

voltage and T pin resistor may be calculated using the

J

0.1µF

D3

following equations:

3692 F21

D3, D4: ZETEX BAT54S

2• TEMP(MIN)°C

V_NEG

≤

Figure 21. Circuit to Generate the Negative Voltage Rail to

Extend the T_JPin Operating Range

100

V_NEG

33µA

R1≤

As a safeguard, the LT3692A has an additional thermal

shutdownthresholdsetatatypicalvalueof163°Cforeach

channel. Each time the threshold is exceeded, a power-on

sequence for that channel will be initiated. The sequence

will then repeat until the thermal overload is removed.

where:

TEMP(MIN)°C is the minimum temperature where a

valid T pin output is required.

J

V

NEG

= Regulated negative voltage supply.

It should be noted that the T pin voltage represents

J

For example:

a steady-state temperature and should not be used to

guarantee that maximum junction temperatures are

not exceeded. Instantaneous power along with thermal

gradients and time constants may cause portions of the

die to exceed maximum ratings and thermal shutdown

thresholds. Be sure to calculate die temperature rise for

steady state (>1Min) as well as impulse conditions.

TEMP(MIN)°C = –40°C

V

NEG

V

NEG

≤ –0.8V

= –1, R1 ≤ |V |/33µA = 30.2kΩ

NEG

LT3692A

R1

T

J

V

NEG

GND

+

3692 F20

Figure 20. Circuit to Extend the T_JPin Operating Range

3692afc

29

For more information www.linear.com/3692A

LT3692A

applicaTions inForMaTion

CLKOUT Capacitive Loading

A minor drawback to generating a negative rail from the

CLKOUT pin is that the charge pump adds capacitance to

the CLKOUT pin, resulting in an output synchronization

clock signal phase delay. Figures 22 and 23 show the im-

pact of capacitive loading on the CLKOUT signal rise and

fall times. Note that a typical 10:1 150MHz oscilloscope

probe contributes significant capacitance to the CLKOUT

node, necessitating a low capacitance probe for accurate

measurements.ApplicationsrequiringCLKOUTtogenerate

the negative supply voltage and provide the synchroniza-

tion clock to other regulators may benefit from buffering

CLKOUT prior to the charge pump circuitry.

CHARGE PUMP

SCOPE PROBE: 15pF

SYNCHRONIZED LT3692A

RT/SYNC PIN

500mV/DIV

FET PROBE: 2pF

3692a F22

40ns/DIV

FREQUENCY: 1.000MHz

Figure 22. CLKOUT Rise Time

Other Linear Technology Publications

SCOPE PROBE: 15pF

Application Notes 19, 35 and 44 contain more detailed

descriptions and design information for buck regulators

and other switching regulators. The LT1376 data sheet

has a more extensive discussion of output ripple, loop

compensation and stability testing. Design Note 100

shows how to generate a dual (+ and –) output supply

using a buck regulator.

CHARGE PUMP

SYNCHRONIZED

LT3692A RT/SYNC PIN

500mV/DIV

FET PROBE: 2pF

3692a F23

20ns/DIV

FREQUENCY: 1.000MHz

Figure 23. CLKOUT Fall Time

3692afc

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For more information www.linear.com/3692A

LT3692A

Typical applicaTions

3692afc

31

For more information www.linear.com/3692A

LT3692A

Typical applicaTions

3.3V and 1.8V 2-Stage Dual Step-Down Multi-Frequency Converter

V

IN

5.5V TO 36V

4.7µF

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

SW1

IND1

SW2

IND2

8.2µH

24.9k

1µH

0.47µF

0.22µF

V

OUT2

LT3692A

V

OUT1

1.8V

V

OUT1

V

3.3V 2.5A

400kHz

OUT2

1A

1600kHz

47µF

100µF

100pF

8.06k

10k

100pF

8.06k

FB1

FB2

100k

PG

CMPI1

CMPI2

CMPO1

SS1

CMPO2

SS2

ILIM1

ILIM2

0.1µF

V

C2

C1

CLOCKOUT

1600kHz

RT/SYNC CLKOUT

DIV

470pF

330pF

T

J

GND

0.1µF

33pF

100k

16.5k

47.5k 102k

10nF

36.5k

40.2k

3692a TA03

3692afc

32

For more information www.linear.com/3692A

LT3692A

Typical applicaTions

12V to 3.3V and 2.5V Converter with Start-Up Current Limiting

V

IN

12V

4.7µF

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

SW1

IND1

SW2

IND2

2.2µH

24.9k

0.22µF

100pF

V

OUT1

2.5V

OUT2

LT3692A

3.3V

3A

V

OUT1

V

OUT2

FB2

3A

100pF 16.9k

47µF

FB1

1MHz

8.06k

CMPI1

CMPI2

CMPO2

SS2

CMPO1

SS1

ILIM1

ILIM2

V

C2

C1

CLOCKOUT

1MHz

RT/SYNC CLKOUT

DIV

33pF

330pF

24.9k

0.1µF

330pF

T

J

GND

33pF

120k

0.1µF

21.0k

28.0k

10nF

0.1µF

120k

3692a TA04

3692afc

33

For more information www.linear.com/3692A

LT3692A

Typical applicaTions

3.3V/5A Single Output with UVLO/OVLO and Power Good

V

IN

5.5V TO 18V

60V TRANSIENT

4.7µF

×2

13k

174k

7.15k

37.4k

V

IN2

IN1

SHDN1

SHDN2

BST1

CMPI2

0.22µF

CMPO2

SW1

IND1

3.3µH

51.1k

ILIM1

V

OUT

LT3692A

3.3V

ILIM2

SS1

V

OUT1

OUT2

5A

47µF

×2

V

2MHz EFFECTIVE RIPPLE

SS2

BST2

0.22µF

V

C1

SW2

IND2

820pF

V

C2

33pF

CLOCKOUT

1MHz

24.9k

CLKOUT

RT/SYNC

T

J

FB1

CMPI1

FB2

8.06k

100k

Q1

2N3904

DIV

CMPO1

PG

GND

0.1µF

10nF

3692a TA05

20k 28k

3692afc

34

For more information www.linear.com/3692A

LT3692A

Typical applicaTions

Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter

V

IN2

V

IN1

5V

12V

2A MAX

4.7µF

13k

47.5k

2.2µF

V

IN2

IN1

SHDN1

SHDN2

BST1

CMPO1

CMPO2

0.22µF

SW1

IND1

2.2µH

SS1

LT3692A

V

3.3V

4A

OUT

0.1µF

SS2

V

OUT1

OUT2

47µF

×2

ILIM1

ILIM2

V

BST2

0.22µF

V

C1

SW2

IND2

2.2µH

V

C2

64.9k

36.5k

33pF

680pF

CLOCKOUT

2MHz

24.9k

CLKOUT

FB1

CMPI1

FB2

RT/SYNC

DIV

8.06k

T

CMPI2

J

GND

3692a TA06

21.0k 61.9k 61.9k

10nF

3692afc

35

For more information www.linear.com/3692A

LT3692A

Typical applicaTions

5V and 1.8V Dual 2-Stage Converter

V

IN1

6V TO 36V

4.7µF

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

SW1

IND1

SW2

IND2

4.7µH

1µH

0.22µF

V

OUT2

OUT1

5V

LT3692A

1.8V

1A

V

OUT1

V

OUT2

FB2

1A

22µF

42.2k

47µF

10k

100pF

8.06k

FB1

2MHz

1MHz

FB1

CMPI1

CMPI2

100k

8.06k

PG

CMPO1

SS1

CMPO2

SS2

ILIM1

ILIM2

ILIM1

V

C2

C1

CLOCKOUT

2MHz

RT/SYNC CLKOUT

DIV

680pF

33pF

0.1µF

T

J

GND

0.1µF

330pF

39.2k

49.9k

10k

61.9k 61.9k

10nF

3692a TA07

3692afc

36

For more information www.linear.com/3692A

LT3692A

Typical applicaTions

3692afc

37

For more information www.linear.com/3692A

LT3692A

Typical applicaTions

5V, 3.3V, 2.5V, 1.8V Synchronized Quad Output

V

5V

1A

OUT1

2.2µF

SV

PV

IN

IN2

PV

DDR

IN

3.3µH

270k

V

3.3V

2A

OUT2

V

PGOOD

SW

FB

IN1

7V TO 36V

100µF

4.7µF

×2

LT3612

RUN

MODE

RT

ITH

TRACK/SS

PGND

60.4k

SGND

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

SW1

IND1

SW2

IND2

6.8µH

FB1

2.2µF

0.22µF

47µF

SV

PV

IN

IN2

PV

LT3692A

DDR

IN

V

OUT1

V

3.3µH

V

2.5V

2A

OUT2

OUT3

PGOOD

SW

FB

100pF 42.2k

47µF

FB1

FB2

LT3612

191k

RUN

MODE

RT

CMPI1

CMPI2

100k

8.06k

ITH

100°C

TEMP FLAG

CMPO2

SS2

TRACK/SS

PGND

CMPO1

SS1

60.4k

SS1

SGND

ILIM1

ILIM2

ILIM1

V

C1

CLOCKOUT

600kHz

V

C2

C1

RT/SYNC CLKOUT

DIV

0.1µF

330pF

T

J

2.2µF

GND

28k

33pF

SV

IN

PV

IN2

PV

73.2k

DDR

IN

3.3µH

V

1.8V

2A

0.1µF

OUT4

60.4k

24.9k

16k

R14

49.9k

PGOOD

SW

FB

LT3612

121k

RUN

MODE

RT

ITH

TRACK/SS

PGND

60.4k

SGND

0.1µF

3692 TA09

3692afc

38

For more information www.linear.com/3692A

LT3692A

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1772 Rev C)

Exposed Pad Variation AA

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

4.50 REF

2.74 REF

SEE NOTE 4

6.40

2.74

REF (.252)

(.108)

0.315 0.05

BSC

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

FE38 (AA) TSSOP REV C 0910

(.0067 – .0106)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3692afc

39

For more information www.linear.com/3692A

LT3692A

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 0.05

5.50 0.05

4.10 0.05

3.45 0.05

3.50 REF

(4 SIDES)

3.45 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 0.05

5.00 0.10

(4 SIDES)

31 32

0.40 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 0.10

3.50 REF

(4-SIDES)

3.45 0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3692afc

40

For more information www.linear.com/3692A

LT3692A

revision hisTory

REV

DATE

9/11

4/12

DESCRIPTION

PAGE NUMBER

A

Added H-grade

2 to 4

B

Clarified the synchronization maximum frequency and Typical Application.

Clarified the Electrical Characteristics table.

Clarified the DIV Voltage Threshold vs Temperature graph.

Replaced 90mV with 100mV.

1

4

7

12

Clarified Table 1.

13

Replaced DIV resistor values in the applications schematics.

25, 31, 32

C

3/13

Added V Quiescent Current vs SHDN1 Voltage Graph

6

IN1

Clarified SHDN1/2 Pin Function Description

10

11

21

Clarified SHDN pin operation in Applications Information operation in general description

Clarified SHDN pin operation description in Applications Information

3692afc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

41

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/3692A

LT3692A

Typical applicaTion

FMEA Fault Tolerant 3.3V/2A and 5V/2A Dual Converter

V

IN1

6V TO 36V

(60V TRANSIENT)

4.7µF

100k

V

IN1

V

IN2

SHDN2

SHDN1

BST1

SHDN2

BST2

SW1

IND1

SW2

IND2

6.8µH

4.22k

5.6µH

0.22µF

47µF

0.22µF

V

3.3V

2A

OUT1

5V

OUT2

LT3692A

V

OUT1

V

OUT2

FB2

2A

2.49k

100µF

500kHz

FB1

500kHz

806Ω

249k

PG2

CMPI1

CMPI2

806Ω

PG1

CMPO1

SS1

CMPO2

SS2

ILIM2

ILIM1

ILIM2

V

C2

C1

CLOCKOUT

500kHz

RT/SYNC CLKOUT

DIV

T

33pF

820pF

10nF

J

680pF

15.4k

33pF

22nF

GND

12.7k

13.0k

10nF

49.9k

3692a TA10

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

= 3V to 36V, Transients to 60V, V

LT3692

LT3507

LT3508

LT3680

LT3693

LT3480

LT3980

LT3971

LT3991

36V with Transient Protection to 60V, Dual 3.5A, 2.5MHz, High Efficiency

Step-Down DC/DC Converter

V

= 0.8V,

OUT(MIN)

IN

I = 4mA, I <10µA, 5mm × 5mm QFN-32

Q

SD

36V, Triple 2.4A, 1.4A and 1.4A (I ), 2.5MHz, High Efficiency

Step-Down DC/DC Converter with LDO Controller

V

= 4V to 36V, V

= 0.8V, I = 7mA, I = 1µA,

OUT(MIN) Q SD

OUT

IN

5mm × 7mm QFN-38

36V with Transient Protection to 40V, Dual 1.4A (I ), 3MHz,

High Efficiency Step-Down DC/DC Converter

V

= 3.7V to 37V, V

= 0.8V, I = 4.6mA, I = 1µA,

OUT

IN

OUT(MIN) Q SD

4mm × 4mm QFN-24, TSSOP-16E

36V, 3A, 2.4MHz High Efficiency Micropower Step-Down DC/DC

Converter

V

IN

= 3.6V to 36V, V = 0.8V, I = 75µA, I < 1µA,

OUT(MIN)

Q

SD

3mm × 3mm DFN-10, MSOP-10E

36V, 3A, 2.4MHz High Efficiency Step-Down DC/DC Converter

V

= 3.6V to 36V, V

= 0.8V, I = 1.3mA, I < 1µA,

IN

OUT(MIN)

Q

SD

3mm × 3mm DFN-10, MSOP-10E

36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High Efficiency

V

Q

= 3.6V to 38V, Transients to 60V, V

= 0.78V,

OUT

IN

OUT(MIN)

Step-Down DC/DC Converter with Burst Mode^®Operation

I = 70µA, I < 1µA, 3mm × 3mm DFN-10, MSOP-10E

SD

58V with Transient Protection to 80V, 2A (I ), 2.4MHz, High Efficiency

Step-Down DC/DC Converter with Burst Mode Operation

V

Q

= 3.6V to 58V, Transients to 80V, V

= 0.79V,

OUT

IN

OUT(MIN)

I = 75µA, I < 1µA, 3mm × 4mm DFN-16, MSOP-16E

SD

38V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC Converter

V

= 4.2V to 38V, V

= 1.2V, I = 2.8µA, I < 1µA,

OUT

IN

OUT(MIN) Q SD

with Only 2.8µA of Quiescent Current

3mm × 3mm DFN-10, MSOP-10E

55V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC Converter

V

= 4.2V to 55V, V

= 1.2V, I = 2.8µA, I < 1µA,

OUT

IN

OUT(MIN) Q SD

with Only 2.8µA of Quiescent Current

3mm × 3mm DFN-10, MSOP-10E

3692afc

LT 0313 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

42

For more information www.linear.com/3692A

●

 LINEAR TECHNOLOGY CORPORATION 2011

(408)432-1900 FAX:(408)434-0507 www.linear.com/3692A


型号：	LT3692AIUH#PBF
厂家：	Linear
描述：	LT3692A - Monolithic Dual Tracking 3.5A Step-Down Switching Regulator; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 开关
文件：	总42页 (文件大小：724K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3692AIUH#PBF [Linear]

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