LT3752-1_15 [Linear]
Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller;
| 型号： | LT3752-1_15 |
| 厂家： | 
Linear |
| 描述： | Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller |
| 文件： | 总52页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3752/LT3752-1
Active Clamp Synchronous
Forward Controllers with Internal
Housekeeping Controller
FEATURES
DESCRIPTION
TheLT®3752/LT3752-1arecurrentmodePWMcontrollers
n
Input Voltage Range: LT3752: 6.5V to 100V,
LT3752-1:Limited Only by External Components
Internal Housekeeping DC/DC Controller
Programmable Volt-Second Clamp
High Efficiency Control: Active Clamp,
Synchronous Rectification, Programmable Delays
Short-Circuit (Hiccup Mode) Overcurrent Protection
Programmable Soft-Start/Stop
Programmable OVLO and UVLO with Hysteresis
Programmable Frequency (100kHz to 500kHz)
Synchronizable to an External Clock
optimized for an active clamp forward converter topology.
ADC/DChousekeepingcontrollerisincludedforimproved
efficiency and performance. The LT3752 allows operation
up to 100V input and the LT3752-1 is optimized for ap-
plications with input voltages greater than 100V.
n
n
n
n
n
n
n
n
Aprogrammablevolt-secondclampallowsprimaryswitch
duty cycles above 50% for high switch, transformer and
rectifier utilization. Active clamp control reduces switch
voltage stress and increases efficiency. A synchronous
output is available for controlling secondary side syn-
chronous rectification.
APPLICATIONS
The LT3752/LT3752-1 are available in a 38-lead plastic
TSSOP package with missing pins for high voltage
spacings.
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Offline and HV Car Battery Isolated Power Supplies
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48V Telecommunication Isolated Power Supplies
n
Industrial, Automotive and Military Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
18V to 72V, 12V/12.5A, 150W Active Clamp Isolated Forward Converter
V
OUT
V
IN
18V TO 72V
12V
6.8µH
12.5A
4:4
INTV
V
4.7µF
100V
CC
2.2µF
AUX
+
•
•
470µF
16V
•
•
×3
2.2µF
•
15nF
ZVN4525E6
0.15Ω
22µF
16V
×2
BSC077N12NS3
Si2325DS
FDMS86101
100nF
499Ω
10k
100Ω
100Ω
BSC077N12NS3
HOUT HI
AOUT
V
SENSE
OUT
IN
V
AUX
V
IN
OC
SENSEP
2.2µF
68pF
SYNC
I
100k
5.9k
GND
100k
100k
2k
UVLO_V
0.006Ω
SEC
LT8311
FB
PGOOD
SYNC
11.3k
I
SENSEN
SOUT
LT3752
•
•
220pF
OVLO
GND
560Ω
1.82k
INTV
CC
V
INTV
CC
AUX
220nF
499k
3.16k
13.7k
4.7nF
10k
100Ω
68pF
4.7µF
4.7µF
1µF
HFB
1.1k
3752 TA01
22nF
0.33µF
22.6k
49.9k
34k
31.6k
71.5k
2.8k
22nF
100k
100k
7.32k
1.2k
2.2nF
EFFICIENCY: 94% AT 48V /10A
IN OUT
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For more information www.linear.com/LT3752
LT3752/LT3752-1
TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Table of Contents .......................................... 2
Absolute Maximum Ratings.............................. 3
Order Information.......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics................................. 4
Pin Functions..............................................13
Block Diagram.............................................15
Timing Diagrams .........................................16
Operation...................................................19
Introduction ....................................................... 19
LT3752 Part Start-Up ......................................... 19
LT3752-1 Part Start-Up ...................................... 19
Applications Information ................................21
Programming System Input Undervoltage Lockout
(UVLO) Threshold and Hysteresis ......................21
Soft-Stop Shutdown...........................................21
Micropower Shutdown .......................................21
Programming System Input Overvoltage Lockout
(OVLO) Threshold...............................................21
LT3752-1 Micropower Start-Up from High System
Input Voltages ....................................................22
Programming Switching Frequency....................23
Synchronizing to an External Clock ....................23
FORWARD CONTROLLER.......................................27
Adaptive Leading Edge Blanking Plus
Programmable Extended Blanking......................27
Current Sensing and Programmable Slope
Compensation ....................................................28
Overcurrent: Hiccup Mode..................................28
Programming Maximum Duty Cycle Clamp: D
VSEC
(Volt-Second Clamp) ..........................................29
D
VSEC
Open Loop Control: No Opto-Coupler, Error
Amplifier or Reference........................................30
: Open Pin Detection Provides Safety.......30
R
IVSEC
Transformer Reset: Active Clamp Technique .....30
LO Side Active Clamp Topology (LT3752)...........32
HI Side Active Clamp Topology (LT3752-1).........33
Active Clamp Capacitor Value and
Voltage Ripple ....................................................33
Active Clamp MOSFET Selection ........................34
Programming Active Clamp Switch Timing: AOUT
to OUT (t ) and OUT to AOUT (t ) Delays.......35
AO
OA
Programming Synchronous Rectifier Timing:
SOUT to OUT (t ) and OUT to SOUT (t )
SO
OS
Delays.................................................................35
Soft-Start (SS1, SS2) .........................................36
Soft-Stop (SS1) ..................................................36
Hard-Stop (SS1, SS2).........................................37
OUT, AOUT, SOUT Pulse-Skipping Mode............37
AOUT Timeout....................................................38
Main Transformer Selection ...............................38
Primary-Side Power MOSFET Selection .............40
Synchronous Control (SOUT).............................40
Output Inductor Value......................................... 41
Output Capacitor Selection................................. 41
Input Capacitor Selection ................................... 41
PCB Layout / Thermal Guidelines ......................42
Typical Applications......................................44
Package Description .....................................50
Revision History ..........................................51
Typical Application .......................................52
Related Parts..............................................52
INTV Regulator Bypassing and Operation ......24
CC
HOUSEKEEPING CONTROLLER..............................24
Housekeeping: Operation....................................25
Housekeeping: Soft-Start/Shutdown..................25
Housekeeping: Programming Output Voltage.....25
Housekeeping: Programming Cycle-by-Cycle Peak
Inductor Current and Slope Compensation.........25
Housekeeping: Adaptive Leading Edge Blanking.26
Housekeeping: Overcurrent Hiccup Mode...........26
Housekeeping: Output Overvoltage and Power
Good ..................................................................26
Housekeeping: Transformer Turns Ratio and
Leakage Inductance............................................26
Housekeeping: Operating Without This Supply...27
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For more information www.linear.com/LT3752
LT3752/LT3752-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V (LT3752) ...........................................................100V
IN
1
2
PGND
NC
38
37
36
HFB
HCOMP
RT
UVLO_V , OVLO....................................................20V
SEC
V (LT3752-1) .................................................16V, 8mA
IN
3
HI
SENSE
INTV , SS2..............................................................16V
CC
4
FB
FB, SYNC ....................................................................6V
5
HOUT
AOUT
SOUT
34
32
30
28
26
24
COMP
SYNC
SS1
SS1, COMP, HCOMP, HFB, RT.....................................3V
6
I
, I
, OC, HI
................................0.35V
SENSEP SENSEN
SENSE
7
IVSEC..................................................................–250µA
Operating Junction Temperature Range (Notes 2, 3)
LT3752EFE, LT3752EFE-1 .................. –40°C to 125°C
LT3752IFE, LT3752IFE-1 .................... –40°C to 125°C
LT3752HFE, LT3752HFE-1 ................. –40°C to 150°C
LT3752MPFE, LT3752MPFE-1............ –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 Sec)..................300°C
8
IVSEC
9
UNLO_V
SEC
39
PGND
GND
10
11
12
13
14
15
16
17
18
19
OVLO
V
T
AO
IN
T
AS
INTV
T
CC
OS
T
BLNK
NC
OUT
OC
NC
SS2
22
21
20
I
GND
SENSEP
I
PGND
SENSEN
FE PACKAGE
VARIATION: FE38(31)
38-LEAD PLASTIC TSSOP
θ
JA
= 25°C/W
EXPOSED PAD (PIN 39) IS PGND AND GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LT3752FE
PACKAGE DESCRIPTION
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
LT3752EFE#PBF
LT3752EFE#TRPBF
LT3752IFE#TRPBF
LT3752HFE#TRPBF
LT3752MPFE#TRPBF
LT3752EFE-1#TRPBF
LT3752IFE-1#TRPBF
LT3752HFE-1#TRPBF
LT3752MPFE-1#TRPBF
LT3752IFE#PBF
LT3752FE
LT3752HFE#PBF
LT3752MPFE#PBF
LT3752EFE-1#PBF
LT3752IFE-1#PBF
LT3752HFE-1#PBF
LT3752MPFE-1#PBF
LT3752FE
LT3752FE
LT3752FE-1
LT3752FE-1
LT3752FE-1
LT3752FE-1
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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For more information www.linear.com/LT3752
LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
MIN
6.5
TYP
MAX
100
16
UNITS
l
l
l
Operational Input Voltage (LT3752)
Operational Input Voltage (LT3752-1)
V
V
10.5
V
V
V
V
V
V
V
V
(LT3752)
(LT3752)
5.8
5.5
0.3
9.5
7.6
1.9
170
4
6.4
V
IN(ON)
IN(OFF)
5.9
V
l
l
Hysteresis (LT3752)
0.1
0.5
V
IN(ON/OFF)
(LT3752-1)
10.4
V
IN(ON)
(LT3752-1)
V
IN(OFF)
l
l
l
Hysteresis (LT3752-1)
1.61
2.19
265
6.2
V
IN(ON/OFF)
Start-Up Current (LT3752-1)
(Notes 6, 7)
µA
mA
IN
IN
Quiescent Current (Housekeeping Controller
Only) (LT3752)
HCOMP = 1V (Housekeeping Not Switching),
HFB = 0.85V
l
V
Quiescent Current (Housekeeping Controller
HCOMP = 1V (Housekeeping Not Switching),
HFB = 0.85V
3
4.6
9.5
mA
mA
IN
Only) (LT3752-1)
V
IN
Quiescent Current (Housekeeping Controller +
HCOMP = 1V (Housekeeping Not Switching),
HFB = 1.35V, FB = 1.5V (Main Loop Not Switching)
7.5
Forward Controller)
l
l
UVLO_V Micropower Threshold (V
)
I < 20µA
VIN
0.2
0.4
20
0.6
40
V
µA
V
SEC
SD
V
IN
Shutdown Current (Micropower)
UVLO_V
= 0.2V
= 1V
SEC
UVLO_V
Threshold (V
)
1.180
1.250
165
0
1.320
220
SEC
SYS_UV
V
IN
Shutdown Current (After Soft-Stop)
UVLO_V
UVLO_V
UVLO_V
µA
µA
SEC
SEC
SEC
UVLO_V
UVLO_V
(ON) Current
(OFF) Current
= V
= V
+ 50mV
– 50mV
SEC
SYS_UV
SYS_UV
SEC
l
l
Hysteresis Current
4.0
5
25
6.0
µA
µA
With One-Shot Communication Current
OVLO (Rising) (No Switching, Reset SS1)
OVLO (Falling) (Restart SS1)
OVLO Hysteresis
(Note 15)
1.220
1.250
1.215
35
1.280
V
V
l
23
47
mV
OVLO Pin Current (Note 10)
OVLO = 0V
OVLO = 1.5V (SS1 = 2.7V)
OVLO = 1.5V (SS1 = 1.0V)
5
0.9
5
100
nA
mA
nA
100
Oscillator (Forward Controller: OUT, SOUT, AOUT)
Frequency: f
Frequency: f
Frequency: f
= 100kHz
= 300kHz
= 500kHz
R = 82.5k
94
100
300
500
106
321
530
kHz
kHz
kHz
OSC
OSC
OSC
T
l
R = 24.9k
T
279
470
R = 14k
T
f
Line Regulation
R = 24.9k
T
OSC
6.5V < V < 100V (LT3752)
0.05
0.05
0.1
0.1
%/V
%/V
IN
10.5V < V < 16V (LT3752-1)
IN
Frequency and D
Foldback Ratio (LT3752) (Fold) SS1 = V
Foldback Ratio (LT3752-1) (Fold) SS1 = V
+ 25mV, SS2 = 2.7V
4
2
VSEC
SSACT
Frequency and D
+ 25mV, SS2 = 2.7V
VSEC
SS1ACT
l
l
SYNC Input High Threshold
SYNC Input Low Threshold
SYNC Pin Current
(Note 4)
(Note 4)
1.2
1.025
75
1.8
V
V
0.6
1.0
6.6
SYNC = 6V
µA
SYNC Frequency/Programmed f
1.25
7.2
5
kHz/kHz
OSC
Linear Regulator (INTV ) (LT3752)
CC
INTV Regulation Voltage
7
V
V
CC
Dropout (V -INTV
)
CC
V
IN
= 6.5V, I = 10mA
INTVCC
0.8
4.75
IN
INTV UVLO(+)
(Start Switching)
V
CC
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For more information www.linear.com/LT3752
LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
INTV UVLO(–)
CONDITIONS
MIN
0.075
9.4
TYP
4.6
MAX
4.85
0.24
UNITS
(Stop Switching)
V
V
CC
INTV UVLO Hysteresis
0.15
CC
Linear Regulator (INTV ) (LT3752-1)
CC
INTV Regulation Voltage
10
0.6
7
10.4
V
V
V
V
V
CC
Dropout (V -INTV
)
CC
V
IN
= 8.75V, I
= 10mA
INTVCC
IN
INTV UVLO(+)
(Start Switching)
(Stop Switching)
7.4
7.2
0.3
CC
INTV UVLO(–)
6.8
0.2
CC
INTV UVLO Hysteresis
0.1
CC
Linear Regulator (INTV ) (LT3752/LT3752-1)
CC
INTV OVLO(+)
(Stop Switching)
(Start Switching)
15.9
15.4
0.38
16.5
16
17.2
16.7
0.67
V
V
V
CC
INTV OVLO(–)
CC
INTV OVLO Hysteresis
0.5
CC
INTV Current Limit
INTV = 0V
17
35
35
23
50
50
29
60
60
mA
mA
mA
CC
CC
l
l
INTV = 5.75V (LT3752)
CC
INTV = 8.75V (LT3752-1)
CC
Error Amplifier
FB Reference Voltage
FB Line Reg
l
1.220
1.250
1.275
V
6.5V < V < 100V (LT3752)
0.1
0.1
0.3
0.3
mV/V
mV/V
IN
10.5V < V < 16V (LT3752-1)
IN
FB Load Reg
COMP_SW – 0.1V < COMP < COMP_V – 0.1V
0.1
50
0.3
mV/V
nA
OH
FB Input Bias Current
Open-Loop Voltage Gain
Unity-Gain Bandwidth
COMP Source Current
COMP Sink Current
(Note 10)
200
85
dB
(Note 8)
2.5
11
MHz
mA
mA
V
FB = 1V, COMP = 1.75V (Note 10)
FB = 1.5V, COMP = 1.75V
FB = 1V
6
6.5
11.5
2.6
1.25
COMP Output High Clamp
COMP Switching Threshold
Current Sense (Main Loop)
V
I
Maximum Threshold
FB = 1V, OC = 0V
180
220
6.1
2
260
mV
V/V
µA
SENSEP
COMP Current Mode Gain
∆V /∆V
COMP ISENSEP
I
I
I
Input Current (D = 0%)
Input Current (D = 80%)
Input Current
(Note 10)
(Note 10)
SENSEP
SENSEP
SENSEN
33
µA
FB = 1.5V (COMP Open) (Note 10)
FB = 1V (COMP Open) (Note 10)
20
90
30
135
µA
µA
l
OC Overcurrent Threshold
OC Input Current
82.5
96
107.5
500
mV
nA
200
AOUT Driver (Active Clamp Switch Control) (LT3752 External PMOS; LT3752-1 External NMOS)
AOUT Rise Time
C = 1nF (Note 5), INTV = 12V
23
19
ns
ns
V
L
CC
AOUT Fall Time
C = 1nF (Note 5), INTV = 12V
L CC
AOUT Low Level
0.1
AOUT High Level
INTV = 12V
11.9
7.8
V
CC
AOUT High Level in Shutdown (LT3752)
UVLO_V
= 0V, INTV = 8V, I = 1mA Out
AOUT
V
SEC
CC
of the Pin
AOUT Low Level in Shutdown (LT3752-1)
UVLO_V
the Pin
= 0V, INTV = 12V, I = 1mA Into
AOUT
0.25
V
SEC
CC
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For more information www.linear.com/LT3752
LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AOUT Edge to OUT (Rise): (t
)
C
C
= 1nF, C
= 3.3nF, INTV = 12V
AO
SOUT
R
R
OUT CC
= 44.2k
168
253
218
328
268
403
ns
ns
TAO
TAO
= 73.2k (Note 11)
OUT (Fall) to AOUT Edge: (t
)
= 1nF, C = 3.3nF, INTV = 12V
OA
SOUT
R
R
OUT
CC
= 44.2k
= 73.2k (Note 12)
150
214
196
295
250
376
ns
ns
TAO
TAO
SOUT Driver (Synchronous Rectification Control)
SOUT Rise Time
C
C
= 1nF, INTV = 12V (Note 5)
21
19
ns
ns
V
OUT
CC
SOUT Fall Time
= 1nF, INTV = 12V (Note 5)
CC
OUT
SOUT Low Level
0.1
SOUT High Level
INTV = 12V
11.9
7.8
V
CC
SOUT High Level in Shutdown
UVLO_V
= 0V, INTV = 8V, I = 1mA Out
SOUT
V
SEC
CC
of the Pin
AOUT Edge to SOUT (Fall): (t
)
C
C
C
= C
= 1nF, INTV = 12V
AS
AOUT
SOUT CC
= 44.2k (Note 13)
= 73.2k
R
TAS
R
TAS
168
253
218
328
268
403
ns
ns
SOUT (Fall) to OUT (Rise): (t = t – t
)
AS
= 1nF, C
= 3.3nF, INTV = 12V
SO
OS
AO
SOUT
R
R
OUT CC
= 73.2k, R = 44.2k (Notes 11, 13)
= 44.2k, R = 73.2k
70
–70
110
–110
132
–132
ns
ns
TAO
TAO
TAS
TAS
OUT (Fall) to SOUT (Rise): (t
)
= 1nF, C
= 3.3nF, INTV = 12V
OUT CC
SOUT
R
R
= 14.7k
= 44.2k (Note 14)
52
102
68
133
84
164
ns
ns
TOS
TOS
OUT Driver (Main Power Switch Control)
OUT Rise Time
C
C
= 3.3nF, INTV = 12V (Note 5)
19
20
ns
ns
V
OUT
CC
OUT Fall Time
= 3.3nF, INTV = 12V (Note 5)
CC
OUT
OUT Low Level
0.1
OUT High Level
INTV = 12V
11.9
V
CC
OUT Low Level in Shutdown
UVLO_V
the Pin
= 0V, INTV = 8V, I = 1mA Into
OUT
0.25
V
SEC
CC
OUT (Volt-Sec) Max Duty Cycle Clamp
R = 24.9k, R
= 51.1k, FB = 1V, SS1 = 2.7V
T
IVSEC
D
VSEC
D
VSEC
D
VSEC
(1 • System Input (Min)) × 100
(2 • System Input (Min)) × 100
(4 • System Input (Min)) × 100
UVLO_V
UVLO_V
UVLO_V
= 1.25V
= 2.50V
= 5.00V
68.5
34.3
17.5
72.5
36.5
18.6
76.2
38.7
19.7
%
%
%
SEC
SEC
SEC
OUT Minimum ON Time
C
= 3.3nF, INTV = 12V (Note 9)
OUT
R
R
CC
= 14.7k
325
454
ns
ns
TBLNK
TBLNK
= 73.2k (Note 16)
SS1 Pin (Soft-Start: Frequency and D
) (Soft-Stop: COMP Pin, Frequency and D
)
VSEC
VSEC
SS1 Reset Threshold (V
)
150
1.25
11.5
10.5
mV
V
SS1(RTH)
SS1 Active Threshold (V
)
(Allow Switching)
SS1(ACT)
SS1 Charge Current (Soft-Start)
SS1 = 1.5V (Note 10)
7
16
µA
µA
SS1 Discharge Current (Soft-Stop)
SS1 = 1V, UVLO_V
SS1 = 1V
= V
– 50mV
SYS_UV
6.4
14.6
SEC
SS1 Discharge Current (Hard Stop)
OC > OC Threshold
0.9
0.9
0.9
mA
mA
mA
INTV < INTV UVLO(–)
CC
CC
OVLO > OVLO(+)
SS2 Pin (Soft-Start: Comp Pin)
SS2 Discharge Current
SS2 Charge Current
SS1 < V
SS1 > V
, SS2 = 2.5V
, SS2 = 1.5V
2.8
21
mA
µA
SS(ACT)
11
28
SS(ACT)
3752fb
6
For more information www.linear.com/LT3752
LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Error Amplifier (Housekeeping Controller)
HFB Reference Voltage
HFB Line Reg
0.90
1.000
1.10
V
6.5V < V < 100V (LT3752)
0.1
0.1
mV/V
mV/V
IN
10.5V < V < 16V (LT3752-1)
IN
HFB Load Reg
HCOMP V – 0.1V < HCOMP < HCOMP V
–
–6
mV/V
SW
OH
0.1V
HFB Input Bias Current
Transconductance
HFB = 1.1V (Note 10)
85
250
175
0.96
0.92
1.206
1.150
15
170
nA
µS
V/V
V
∆I
HCOMP
5µA
Voltage Gain
Power Good(+) (HFB Level)
Power Good(–) (HFB Level)
HFB OVLO(+)
V
(Disable HOUT Switching)
(Enable Housekeeping Operation)
HCOMP = 1.75V (Note 10)
HCOMP = 1.75V
V
HFB OVLO(–)
V
HCOMP Source Current
HCOMP Sink Current
11
13
19
23
µA
µA
V
18
HCOMP Output High Clamp
HCOMP Switching Threshold
Current Sense (Housekeeping Controller)
2.9
1.28
V
HI
Peak Current Threshold
HFB = 0.8V
69
79
86.5
mV
V/V
SENSE
HCOMP Current Mode Gain
9.1
∆V /∆V
HCOMP HISENSE
HI
SENSE
HI
SENSE
Input Current (D = 0%)
Input Current (D = 80%)
(Note 10)
2
52
µA
µA
HI
Overcurrent Threshold
84.6
98
105.4
mV
SENSE
HOUT Driver (Housekeeping Controller)
HOUT Rise Time
C = 1nF (Note 5), INTV = 12V
13
12
ns
ns
V
L
CC
HOUT Fall Time
C = 1nF (Note 5), INTV = 12V
L CC
HOUT Low Level
0.1
HOUT High Level
LT3752
LT3752-1
INTV = 12V
11.9
11.9
V
V
CC
HOUT Low Level in Shutdown
UVLO_V
= 0V, INTV = 12V, I = 1mA
HOUT
0.25
V
SEC
CC
Into the Pin
HOUT Maximum Duty Cycle
HCOMP = 2.7V, R = 24.9k
90
95
%
T
HOUT Minimum ON Time
C = 1nF (Note 9), INTV = 12V
350
ns
L
CC
Soft-Start (HSS) (Housekeeping Controller)
HSS (Internal) Ramp Time (t
)
HCOMP SW ≥ HCOMP V – 0.1V
2.2
4
ms
HSS
OH
Oscillator (Housekeeping Controller)
Frequency (f
Frequency (f
Frequency (f
) (f
Folded Back) (LT3752)
Folded Back) (LT3752-1)
HFB = 0.8V, R = 24.9k, SS1 = 0V
55
65
75
kHz
kHz
kHz
HOUT OSC
T
) (f
HOUT OSC
HFB = 0.8V, R = 24.9k, SS1 = 0V
119
279
141
300
163
321
T
l
) (Full-Scale f
HOUT
)
HFB = 1.15V, HCOMP = 2.7V
OSC
3752fb
7
For more information www.linear.com/LT3752
LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Guaranteed by correlation to static test.
Note 7: V start-up current is measured at V = V
– 0.25V and then
IN(ON)
IN
IN
scaled by 1.18× to correlate to worst-case V current required for part
IN
start-up at V = V
.
IN
IN(ON)
Note 2: The LT3752EFE/LT3752EFE-1 are guaranteed to meet performance
specifications from 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LT3752IFE/LT3752IFE-1 are guaranteed to meet performance
specifications from –40°C to 125°C junction temperature. The LT3752HFE/
LT3752HFE-1 are guaranteed to meet performance specifications from
–40°C to 150°C junction temperature. The LT3752MPFE/LT3752MPFE-1
are tested and guaranteed to meet performance specifications from –55°C
to 150°C junction temperature.
Note 3: For maximum operating ambient temperature, see the Thermal
Calculations section in the Applications Information section.
Note 4: SYNC minimum and maximum thresholds are guaranteed by
SYNC frequency range test using a clock input with guard banded SYNC
levels of 0.7V low level and 1.7V high level.
Note 8: Guaranteed by design.
Note 9: ON times are measured between rising and falling edges at 50% of
gate driver supply voltage.
Note 10: Current flows out of pin.
Note 11: Guaranteed by correlation to R = 73.2k test.
TAS
Note 12: t timing guaranteed by design based on correlation to
OA
measured t timing.
AO
Note 13: Guaranteed by correlation to R
Note 14: Guaranteed by correlation to R
Note 15: A 2µs one-shot of 20µA from the UVLO_V
communication between ICs to begin shutdown (useful when stacking
supplies for more power ( = inputs in parallel/outputs in series)). The
current is tested in a static test mode. The 2µs one-shot is guaranteed by
design.
= 44.2k test.
= 14.7k test.
TAO
TOS
pin allows
SEC
Note 5: Rise and fall times are measured between 10% and 90% of gate
driver supply voltage.
Note 16: Guaranteed by correlation to R
= 14.7k test.
TBLNK
3752fb
8
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
VIN Start-Up and Shutdown Current
VIN(ON), VIN(OFF) Thresholds
VIN Quiescent Current vs Junction
Temperature
vs Junction Temperature
vs Junction Temperature
220
200
180
160
140
120
100
80
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
8
7
LT3752-1 VIN_ON
LT3752/-1: HOUSEKEEPING + FORWARD
(NO SWITCHING)
6
5
4
3
2
1
0
LT3752-1 V START-UP CURRENT
IN
)
IN_ON
(V = V
IN
LT3752-1 VIN_OFF
LT3752: HOUSEKEEPING ONLY
(NO SWITCHING)
LT3752 VIN_ON
LT3752 VIN_OFF
60
LT3752-1: HOUSEKEEPING ONLY
(NO SWITCHING)
LT3752/LT3752-1 V SHUTDOWN CURRENT
IN
(V = 12V) UVLO_VSEC = 0.2V
IN
40
20
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G01
3752 G02
3752 G03
UVLO_VSEC Turn-On Threshold
vs Junction Temperature
UVLO_VSEC Hysteresis Current
vs Junction Temperature
HFB PGOOD Thresholds
vs Junction Temperature
1.275
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
6.0
5.5
5.0
4.5
4.0
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
HFB PGOOD (+) = ENABLE FORWARD
CONTROLLER CIRCUITRY
HFB PGOOD (–) = DISABLE FORWARD
CONTROLLER CIRCUITRY
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G04
3752 G05
3752 G06
HFB Reference Voltage
vs Junction Temperature
HFB OVLO Thresholds
vs Junction Temperature
1.30
1.25
1.20
1.15
1.10
1.05
1.00
1.100
1.075
HFB > OVLO (+) = DISABLE HOUT
SWITCHING
1.050
1.025
1.000
0.975
0.950
0.925
0.900
HFB < OVLO (–) = ENABLE HOUSEKEEPING
OPERATION
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G08
3752 G07
3752fb
9
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
HISENSE Overcurrent
(Hiccup Mode) Threshold
HISENSE Peak Current Threshold
vs Junction Temperature
HISENSE Pin Current vs Duty Cycle
vs Junction Temperature
60
50
40
30
20
10
0
110
105
100
95
85
84
83
82
81
80
79
78
77
76
75
90
T = 150°C
J
85
T = 25°C
J
T = –55°C
J
80
0
10 20 30 40 50 60 70 80 90 100
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
DUTY CYCLE (%)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G10
3752 G11
3752 G09
Housekeeping Internal Soft-Start
Time (HSS) vs Junction
Temperature
LT3752: INTVCC in Dropout at
VIN = 6.5V vs Current, Junction
Temperature
LT3752: INTVCC UVLO Thresholds
vs Junction Temperature
3.00
2.75
2.50
2.25
2.00
1.75
1.50
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
4.85
4.80
4.75
4.70
4.65
4.60
4.55
4.50
INTV > UVLO (+): ENABLE SWITCHING
CC
INTV < UVLO (–): DISABLE SWITCHING
CC
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
= 10mA
= 15mA
= 20mA
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G12
3752 G13
3752 G14
LT3752: INTVCC Regulation
Voltage vs Current, Junction
Temperature
LT3752-1: INTVCC in Dropout at
VIN = 8.75V vs Current, Junction
Temperature
7.00
6.95
6.90
6.85
6.80
6.75
6.70
6.65
6.60
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
V
= 12V
V
= 12V
IN
IN
I
I
I
I
= 0mA
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 20mA
= 30mA
= 10mA
= 15mA
= 20mA
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G15
3752 G16
3752fb
10
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
LT3752-1: INTVCC Regulation
LT3752-1: INTVCC UVLO Thresholds
vs Junction Temperature
Voltage vs Current, Junction
Temperature
SS1 Soft-Start/Soft-Stop Pin
Currents vs Junction Temperature
10.00
9.95
9.90
9.85
9.80
9.75
9.70
9.65
9.60
9.55
9.50
9.45
9.40
7.20
7.15
7.10
7.05
7.00
6.95
6.90
6.85
6.80
6.75
6.70
6.65
6.60
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
V
= 12V
IN
INTV > UVLO (+): ENABLE FORWARD
CC
CONVERTER SWITCHING
SS1 SOFT-START: CHARGE CURRENT* (–1)
SS1 SOFT-STOP: DISCHARGE CURRENT
INTV < UVLO (–): DISABLE FORWARD
CC
CONVERTER SWITCHING
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
= 10mA
= 20mA
= 30mA
9.0
8.5
8.0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G18
3752 G17
3752 G19
Switching Frequency
vs SS1 Pin Voltage
SS1 High, Active and Reset
SS2 Soft-Start Charge Current
vs Junction Temperature
Levels vs Junction Temperature
25
24
23
22
21
20
19
18
17
16
15
350
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
R = 24.9k
T
325
300
275
250
225
200
175
150
125
100
75
SS1 HIGH LEVEL
LT3752-1
f
(HOUT)
f
(OUT)
SS2 PIN CURRENT* (–1)
SS1 ACTIVE LEVEL
(ALLOW FORWARD CONVERTER SWITCHING)
f
LT3752
(HOUT)LT3752-1
f
(HOUT)
f
(OUT)
f
(HOUT)LT3752
50
25
0
SS1 RESET LEVEL (RESET SS1 LATCH)
f
(OUT)
–75 –50 –25
0
25 50 75 100 125 150 175
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
SS1 (V)
JUNCTION TEMPERATURE (°C)
3752 G21
3752 G22
3752 G20
Switching Frequency
vs Junction Temperature
FB Reference Voltage
vs Junction Temperature
325
320
315
310
305
300
295
290
285
280
275
1.30
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
R = 24.9k
T
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G23
3752 G24
3752fb
11
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
ISENSEP Maximum Threshold – VSLP
vs Duty Cycle (Programming Slope
Compensation)
OC Overcurrent
ISENSEP Maximum Threshold
vs COMP
(Hiccup Mode) Threshold
vs Junction Temperature
240
220
240
220
200
180
160
140
110
105
100
95
VSLP = I(I
) • R
SENSEP
ISLP
200
180
R
ISLP
= 0Ω
160
140
120
100
80
R
ISLP
= 1.5kΩ
OC THRESHOLD
90
R
ISLP
= 2kΩ
60
85
40
20
0
80
1.2 1.4 1.6
1.8
2
2.2 2.4 2.6
0
10 20 30 40 50 60 70 80 90 100
–75 –50 –25
0
25 50 75 100 125 150 175
COMP (V)
DUTY CYCLE (%)
JUNCTION TEMPERATURE (°C)
3752 G25
3752 G26
3752 G27
AOUT to OUT Delay (tAO) and OUT
to AOUT Delay (tOA) vs Junction
Temperature
AOUT to SOUT Delay (tAS
vs Junction Temperature
)
Extended Blanking Duration
vs Junction Temperature
340
320
300
280
260
240
220
200
180
160
140
340
320
300
280
260
240
220
200
180
160
140
220
200
180
160
140
120
100
80
t
AO
R
TBLNK
= 73.2k
R
TAS
= 73.2k
t
OA
R
= 73.2k
= 44.2k
TAO
t
t
R
TAS
= 44.2k
AO
R
TAO
OA
R
= 14.7k
TBLNK
60
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G30
3752 G29
3752 G28
SOUT (Fall) to OUT (Rise) Delay
(tSO = tAO – tAS) vs Junction
Temperature
OUT (Fall) to SOUT (Rise) Delay
(tOS) vs Junction Temperature
120
100
80
160
140
120
R
TAO
= 73.2k, R
= 44.2k
TAS
R
TOS
= 44.2k
60
40
20
100
80
60
40
20
0
R
TOS
= 14.7k
–20
–40
–60
–80
–100
–120
R
TOS
= 7.32k
R
= 44.2k, R
= 73.2k
TAO
0
TAS
–75 –50 –25
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
3752 G31
3752 G32
3752fb
12
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Required RIVSEC vs Switching
Frequency (for DVSEC × 100 = 72.5%,
UVLO_VSEC = 1.25V)
OUT Pin Rise/Fall Times
vs OUT Pin Load Capacitance
OUT Maximum Duty Cycle Clamp
(DVSEC) vs UVLO_VSEC
80
70
60
50
40
30
20
10
0
160
140
120
100
80
60
50
40
30
20
10
0
INTV = 12V
CC
V
R
R
= 12V
IN
T
(OVERDRIVEN FROM
= 24.9k (300kHz)
HOUSEKEEPING SUPPLY)
= 51.1k
IVSEC
60
40
20
0
0
1.25 2.5 3.75
5
6.25 7.5 8.75 10
100 150 200 250 300 350 400 450 500
0
1
2
3
4
5
6
7
8
9
10
UVLO_VSEC (V)
SWITCHING FREQUENCY (kHz)
OUT PIN LOAD CAPACITANCE (nF)
3752 G33
3752 G34
3752 G35
PIN FUNCTIONS
HFB (Pin 1): Housekeeping Supply Error Amplifier
50%.Resistordividerratioprogramsundervoltagelockout
(UVLO) threshold. A 5µA pin current hysteresis allows
programmingofUVLOhysteresis.Pinbelow0.4Vreduces
Inverting Input.
HCOMP (Pin 2): Housekeeping Supply Error Amplifier
Output and Compensation Pin.
V currents to microamps.
IN
OVLO (Pin 10): A resistor divider from system input
programs overvoltage lockout (OVLO) threshold. Fixed
hysteresis included.
RT (Pin 3): A resistor to ground programs switching
frequency.
FB (Pin 4): Error Amplifier Inverting Input.
T
(Pin 11): A resistor programs nonoverlap timing
AO
COMP (Pin 5): Error Amplifier Output. Allows various
compensation networks for nonisolated applications.
between AOUT rise and OUT rise control signals.
T
(Pin12):ResistorsatT andT definedelaybetween
AS
AO
AS
SYNC(Pin6):Allowssynchronizationofinternaloscillator
SOUT fall and OUT rise (= t – t ).
AO
AS
to an external clock. f
equal to f
allowed.
SYNC
OSC
T
(Pin 13): Resistor programs delay between OUT fall
OS
SS1 (Pin 7): Capacitor controls soft-start/stop of switch-
ing frequency and volt-second clamp. During soft-stop it
also controls the COMP pin.
and SOUT rise.
T
(Pin 14): Resistor programs extended blanking of
BLNK
I
and OC signals during MOSFET turn-on.
SENSEP
IVSEC (Pin 8): Resistor Programs OUT Pin Maximum
NC (Pins 15, 16, 37): No Connect Pins. These pins are not
connected inside the IC. These pins should be left open.
Duty Cycle Clamp (D
). This clamp moves inversely
VSEC
proportional to system input voltage to provide a volt-
second clamp.
SS2 (Pin 17): Capacitor controls soft-start of COMP pin.
AlternativelycanconnecttoOPTOtocommunicatestartof
switchingtosecondaryside. Ifunused, leavethepinopen.
UVLO_V
(Pin 9): A resistor divider from system in-
SEC
put allows switch maximum duty cycle to vary inversely
proportional with system input. This volt-second clamp
prevents transformer saturation for duty cycles above
GND(Pin18):AnalogSignalGround.Electricalconnection
exists inside the IC to the exposed pad (Pin 39).
3752fb
13
For more information www.linear.com/LT3752
LT3752/LT3752-1
PIN FUNCTIONS
PGND (Pins 19, 38, 39): The Power Grounds for the IC.
The package has an exposed pad (Pin 39) underneath the
ICwhichisthebestpathforheatoutofthepackage. Pin39
should be soldered to a continuous copper ground plane
under the device to reduce die temperature and increase
the power capability of the LT3752/LT3752-1.
INTV (Pin 26): A linear regulator supply generated from
CC
IN
V . LT3752 supplies 7V for AOUT, SOUT, OUT and HOUT
gate drivers. LT3752-1 supplies 10V for AOUT,SOUT, and
OUT gate drivers (HOUT supplied from V ). INTV must
IN
CC
be bypassed with a 4.7µF capacitor to power ground. Can
beexternallydrivenbythehousekeepingsupplytoremove
power from within the IC.
I
(Pin 20): Negative input for the current sense
SENSEN
comparator. Kelvin connect to the sense resistor in the
V (Pin28):InputSupplyPin. Bypasswith1µFtoground.
IN
source of the power MOSFET.
SOUT (Pin 30): Sync signal for secondary side synchro-
nous rectifier controller.
I
(Pin 21): Positive input for the current sense
SENSEP
comparator. Kelvin connect to the sense resistor in the
AOUT (Pin 32): Control signal for external active clamp
switch. (P-channel LT3752, N-channel LT3752-1).
source of the power MOSFET. A resistor in series with
I
programs slope compensation.
SENSEP
HOUT (Pin 34): Drives the gate of an N-channel MOSFET
used for the housekeeping supply. Active pull-off exists
in shutdown.
OC (Pin 22): An accurate 96mV threshold, independent
of duty cycle, for detection of primary side MOSFET over-
current and trigger of hiccup mode. Connect directly to
sense resistor in the source of the primary side MOSFET.
HI
(Pin 36): Current sense input for the house keep-
SENSE
ing supply. Connect to sense resistor in the source of the
Missing Pins 23, 25, 27, 29, 31, 33, 35: Pins removed
for high voltage spacings and improved reliability.
powerMOSFET.AresistorinserieswithHI
slope compensation.
programs
SENSE
OUT (Pin 24): Drives the gate of an N-channel MOSFET
between0VandINTV .Activepull-offexistsinshutdown.
CC
3752fb
14
For more information www.linear.com/LT3752
LT3752/LT3752-1
BLOCK DIAGRAM
HOUSEKEEPING CONTROLLER
9
1
2
UVLO_V
1.25V
HFB
HCOMP
SEC
–
+
+
–
79mV
CLAMP
1.25V
REF
0.4V
1.0V
–
+
SS1 > 1.25V
HARD STOP
5µA
20µA (1 SHOT)
1.25V
HSS
–
+
–
+
HISLP
SS1 < 150mV
HI
SENSE
HOUT
SOFT STOP
36
34
0.9mA
–
+
HICCUP
V
IN_ON
OVLO
1.25V (+)
1.215V (–)
+
–
V
10
IN_OFF
V
IN
98mV
–
+
EN
0.7A
R
Q
OUT
PGOOD
HISLP
S
+
–
UVLO_V
SEC
IVSEC
SYNC
V
8
6
IN
EN_SS1
28
26
–
+
1.25V
100k
INTV
CC
SS1 > 2.2V
OSC
RT
3
SS2
(INVERT LEVEL FOR LT3752-1)
17
ISLP
1.25V
+
–
ON
–
+
V
OFF
AOUT
SOUT
OUT
S
Q
FOLD
BACK
0.4A
32
30
24
SEC
CLAMP
R
ACTIVE CLAMP CONTROL
SS1
FG
SYNCHRONOUS CONTROL
CG
+
–
7
TIMING
LOGIC
0.4A
2A
150mV
HARD STOP
SS1 < 1.25V
S
OFF
CONTROL
ON
Q
R
MAIN SWITCH
INTV
INTV
CC_OV
CC_UV
Q
R
S
SOFT
START
SOFT
STOP
T > 170°C
J
HICCUP
BLANK
SS2
SS1
EN_SS1
+
+
–
–
OC
22
21
20
96mV
ISLP
I
I
SENSEP
+
–
1.25V
EA
SENSEN
(0→220)mV
FB
COMP
T
T
AS
T
OS
T GND
BLNK
PGND (19, 38)
AO
4
5
11
12
13
14
18
3752 BD
(+ EXPOSED (+ EXPOSED
PAD PIN 39) PAD PIN 39)
INTV
CC
PART
SYSTEM INPUT MAX
V
IN
PIN MAX
V
ON/OFF
IN
UVLO(+)/(REG)
AOUT PHASING
LT3752
LT3752-1
100V
100V
5.8V/5.5V
9.5V/7.6V
4.75V/7V
for External PMOS
for External NMOS
Limited Only by
External Components
16V, 8mA
(Internal V Clamp)
7V/10V
IN
3752fb
15
For more information www.linear.com/LT3752
LT3752/LT3752-1
TIMING DIAGRAMS
t
AOUT
OUT
OA
0V
0V
t
AO
V
/(1 – DUTY CYCLE)
IN
V
IN
SWP
0V
t
SO
SOUT
CG
t
OS
t
AS
0V
0V
0V
FG
V
/(1 – DUTY CYCLE)
OUT
FSW
0V
CSW
0V
T
OSC
(1/f
)
3752 F01
t
AO
t
OS
PROGRAMMED BY R , t PROGRAMMED BY R
TAO AS TAS
PROGRAMMED BY R , t = 0.9 • t , t = t – t
TOS OA
AO SO AO AS
Figure 1. LT3752 Timing Diagram
(LT3752-1 Inverts AOUT Phase for N-Channel Control)
CSW
V
V
OUT
IN
•
•
•
•
SWP
M1
FSW
M3
FG
LTXXXX
SYNC
CG
M4
OUT
LT3752
M2
AOUT
SOUT
OS
T
T
T
AO
AS
GND
–V
–V
OUT
IN
3752 F02
Figure 2. Timing Reference Circuit
3752fb
16
For more information www.linear.com/LT3752
LT3752/LT3752-1
TIMING DIAGRAMS
SYSTEM INPUT
(LT3752 V PIN)
SYSTEM INPUT (MIN)
+V
SYSTEM INPUT (MIN)
IN
HYST
0V
TRIGGER
SOFT STOP
UVLO_V
SEC
(RESISTOR DIVIDER
FROM SYSTEM INPUT)
1.25V
0V
7V (REG)
4.75V UVLO(+)
OPTIONAL
BOOTSTRAP
DIODE
INTV
CC
FROM V
HK
0V
PGOOD(+)
(96% OF FULL-SCALE V
)
V
HK
HK
(HOUSEKEEPING
SUPPLY OUTPUT)
SS1
SOFT
SS1
SOFT
COMPLETED SOFT-STOP
SHUTDOWN:
STARTS
STOPS
f
AND
SEC
f
,DV
OSC
DV
OSC
AND COMP
SEC
0.6V < UVLO_V
< 1.25V
SEC
0V
AND SS1 < 150mV
SS1
1.25V
150mV
0V
COMP
SWITCHING
THRESHOLD
1.25V
COMP
0V
SS2
SOFT
STARTS
COMP
SS2
0V
FULL-SCALE f
OSC
f
OSC
(SWITCHING
FREQUENCY)
FULL-SCALE f /4.6
OSC
AOUT, OUT, SOUT
SWITCHING
HOUT
0Hz
3752 F03
SWITCHING
Figure 3. LT3752 Start-Up and Shutdown Timing Diagram
3752fb
17
For more information www.linear.com/LT3752
LT3752/LT3752-1
TIMING DIAGRAMS
SYSTEM INPUT
SYSTEM INPUT (MIN)
+V
SYSTEM INPUT (MIN)
HYST
0V
TRIGGER
SOFT STOP
UVLO_V
PIN
SEC
(RESISTOR DIVIDER
1.25V
FROM SYSTEM INPUT)
0V
V
16V CLAMP
LT3752-1 V PIN
IN
(RESISTOR FROM
SYSTEM INPUT)
IN(ON)
V
IN(OFF)
BOOTSTRAP DIODE FROM V
HK
0V
10V (REG)
INTV
CC
OPTIONAL
BOOTSTRAP
DIODE
7V UVLO(+)
FROM V
HK
0V
PGOOD(+)
V
HK
(96% OF FULL-SCALE V
)
HK
(HOUSEKEEPING
SUPPLY OUTPUT)
SS1
SOFT
SS1
SOFT
COMPLETED SOFT-STOP
SHUTDOWN:
STOPS
STARTS
f
,DV
OSC
AND COMP
SEC
f
AND
SEC
0.6V < UVLO_V
< 1.25V
OSC
DV
SEC
AND SS1 < 150mV
SS1
1.25V
150mV
COMP
COMP
SWITCHING
THRESHOLD
1.25V
SS2
SOFT
STARTS
COMP
SS2
FULL-SCALE f
OSC
f
OSC
(SWITCHING
FREQUENCY)
FULL-SCALE f /2.13
OSC
AOUT, OUT, SOUT
SWITCHING
HOUT
3752 F04
SWITCHING
Figure 4. LT3752-1 Start-Up and Shutdown Timing Diagram
3752fb
18
For more information www.linear.com/LT3752
LT3752/LT3752-1
OPERATION
Introduction
LT3752 Part Start-Up
LT3752 start-up is best described by referring to the Block
Diagram and to the start-up waveforms in Figure 3. For
part start-up, system input voltage must be high enough
The LT3752/LT3752-1 are primary side, current mode,
PWM controllers optimized for use in a synchronous
forward converter with active clamp reset. Combined with
an integrated housekeeping controller, each IC provides
a compact, versatile, and highly efficient solution. The
to drive the UVLO_V
pin above 1.25V and the V pin
SEC
IN
must be greater than 6.5V. An internal linear regulator is
activated and provides a 7V INTV supply for all gate
LT3752 allows V pin operation between 6.5V and 100V.
CC
IN
drivers. The housekeeping controller starts up before the
forward controller. An internal soft-start (HSS) ramps
the housekeeping HCOMP pin to allow switching at the
gate driver output HOUT to drive an external N-channel
MOSFET. The housekeeping controller output voltage
For applications with system input voltages greater than
100V, the LT3752-1 allows RC start-up from input voltage
levels limited only by external components. The LT3752
and LT3752-1 based forward converters are targeted for
power levels up to 400W and are not intended for battery
chargerapplications.Forhigherpowerlevelstheconverter
V
is regulated when the HFB pin reaches 1.0V. V can
HK
HK
be used to override INTV to reduce power in the part,
CC
outputs can be stacked in series. Connecting UVLO_V
SEC
increase efficiency and to optimize the INTV level. Dur-
CC
pins, OVLO pins, SS1 pins and SS2 pins together allows
blocks to react simultaneously to all fault modes and
conditions.
ing start-up the housekeeping controller switches at the
programmed switching frequency (f ) folded back by
OSC
1/4.6. The SS1 pin of the forward controller is allowed to
Each IC contains an accurate programmable volt-second
clamp. When set above the natural duty cycle of the con-
verter, it provides a duty cycle guardrail to limit primary
switch reset voltage and prevent transformer saturation
during load transients. The accuracy and excellent line
start charging when V reaches 96% of its target value
HK
(PGOOD). When SS1 reaches 1.25V, the SS2 pin begins
to charge, controlling COMP pin rise and the soft-start of
output inductor peak current. The SS1 pin independently
soft starts switching frequency and a volt-second clamp.
As SS1 charges towards 2.6V the switching frequencies
of both controllers remain equal, synchronized and soft
regulation of the volt-second clamp provides V
regu-
OUT
lation for open-loop conditions such as no opto-coupler,
reference or error amplifier on the secondary side.
started towards full-scale f
.
OSC
For applications not requiring isolation but requiring high
step-down ratios, each IC contains a voltage error ampli-
fier to allow a very simple nonisolated, fully regulated
synchronous forward converter.
If secondary side control already exists for soft starting
the converter output voltage then the SS2 pin can still be
used to control initial inductor peak current rise. Simply
programming the primary side SS2 soft-start faster than
the secondary side allows the secondary side to take over.
If SS2 is not needed for soft-start control, its pull-down
strength and voltage rating also allow it to drive the input
The integrated housekeeping controller reduces the com-
plexity and size of the main power transformer by avoid-
ing the need for extra windings to create bias supplies.
Secondary side ICs no longer require start-up circuitry
and can operate even when output voltage is 0V.
of an opto-coupler connected to INTV . This allows
CC
the option of communicating to the secondary side that
switching has begun.
A range of protection features include programmable
overcurrent (OC) hiccup mode, programmable system
input undervoltage lockout (UVLO), programmable
system input overvoltage lockout (OVLO) and built-in
thermal shutdown. Programmable slope compensation
and switching frequency allow the use of a wide range of
output inductor values and transformer sizes.
LT3752-1 Part Start-Up
TheLT3752-1start-upofhousekeepingsupplyandforward
converter are similar to the LT3752 except for a small
changeinarchitectureandV pinlevel. LT3752-1start-up
is best described by referring to the Block Diagram and to
IN
3752fb
19
For more information www.linear.com/LT3752
LT3752/LT3752-1
OPERATION
the start-up waveforms in Figure 4. The LT3752-1 starts
and avoids the need for an auxiliary winding in the main
up by using a high valued resistor from system input to
transformer. The part’s low start-up current at the V pin
IN
charge up the input capacitor at the V pin. If system
allowstheuseofalargestart-upresistortominimizepower
IN
input is already high enough to generate UVLO_V
lossfromsysteminput.TheV capacitorvaluerequiredfor
SEC
IN
above 1.25V, then the part turns on once V pin charges
proper start-up is minimized by providing a large V
-
IN
IN(ON)
past V
(9.5V). If system input is not high enough
V
hysteresis, a low V I and a fast start-up time for
IN(ON)
to generate UVLO_V
IN(OFF) IN Q
above 1.25V, the V pin charges
the housekeeping controller. In contrast to the LT3752, the
LT3752-1 housekeeping gate driver (HOUT) runs from the
SEC
IN
towards system input until it reaches an internal 16V, 8mA
clamp. The part turns on when system input becomes
V pin instead of INTV . This avoids having to use cur-
IN
CC
high enough to generate UVLO_V
above 1.25V. As the
rentfromtheV pintochargetheINTV capacitorduring
SEC
IN CC
supply current of the part discharges the V capacitor a
initialstart-up.Thismeanstheregulated10VINTV onthe
IN
CC
bootstrap supply must be generated to prevent V pin
LT3752-1 does not wake up until the housekeeping supply
is valid. Start-up from this point is similar to the LT3752.
The housekeeping supply and forward converter switch
together with a soft-started frequency and volt-second
clamp.Theforwardconverterpeakinductorcurrentisalso
soft started similar to the LT3752.
IN
from falling below V
(7.6V).
IN(OFF)
TheLT3752-1usesthehousekeepingcontrollertoprovide
thebootstrapbiastotheV pinduringRCstart-upinstead
IN
ofwaitingfortheforwardconvertertoalsostart.Thismeth-
od is more efficient, requires a smaller V input capacitor
IN
3752fb
20
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
Programming System Input Undervoltage Lockout
(UVLO) Threshold and Hysteresis
used to pull down the UVLO_V pin below 1.25V but not
SEC
below the micropower shutdown threshold of 0.6V(max).
Typical V quiescent current after soft-stop is 165µA.
IN
The LT3752/LT3752-1 have an accurate 1.25V shutdown
threshold at the UVLO_V
pin. This threshold can be
SEC
Micropower Shutdown
used in conjunction with an external resistor divider to
If a micropower shutdown is required using an external
control signal, an open-drain transistor can be directly
definethefallingundervoltagelockoutthreshold(UVLO(–))
for the converter’s system input voltage (V ) (Figure 5).
S
connected to the UVLO_V
pin. The LT3752/LT3752-1
A pin hysteresis current of 5µA allows programming of
SEC
haveamicropowershutdownthresholdoftypically0.4Vat
the UVLO(+) threshold.
the UVLO_V
pin. V quiescent current in micropower
SEC
IN
V (UVLO(–)) [begin SOFT-STOP then shut down]
S
shutdown is 20µA.
R1
R2+R3
=1.25 1+
Programming System Input Overvoltage Lockout
(OVLO) Threshold
V (UVLO(+)) [begin SOFT-START]
TheLT3752/LT3752-1haveanaccurate1.25Vovervoltage
shutdown threshold at the OVLO pin. This threshold can
be used in conjunction with an external resistor divider to
define the rising overvoltage lockout threshold (OVLO(+))
S
= V (UVLO(–)) + (5µA • R1)
S
It is important to note that the part enters soft-stop when
the UVLO_V
pin falls back below 1.25V. During soft-
SEC
for the converter’s system input voltage (V ) (Figure 6).
S
stop the converter continues to switch as it folds back
switching frequency, volt-second clamp and COMP pin
voltage. See Soft-Stop in the Applications Information
section. When the SS2 pin is finally discharged below its
150mV reset threshold both the housekeeping supply and
forward converter are shut down.
When OVLO(+) is reached, the part stops switching im-
mediately and a hard stop discharges the SS1 and SS2
pins. The falling threshold OVLO(–) is fixed internally at
1.215V and allows the part to restart in soft-start mode.
A single resistor divider can be used from system input
supply (V ) to define both the undervoltage and overvolt-
S
age thresholds for the system. Minimum value for R3 is
1k. If OVLO is unused, place a 10k resistor from OVLO
pin to ground.
SYSTEM
INPUT (V )
S
LT3752/LT3752-1
R1
UVLO_V
SEC
–
+
V OVLO(+) [stop switching; HARD STOP]
S
5µA
R2
R3
TO
OVLO PIN
R1+R2
1.250V
=1.25 1+
R3
V OVLO(–) [begin SOFT-START]
S
3752 F05
1.215
1.25
= VS OVLO + •
(
)
Figure 5. Programming Undervoltage Lockout (UVLO)
Soft-Stop Shutdown
Soft-stop shutdown (similar to system undervoltage) can
be commanded by an external control signal. A MOSFET
with a diode (or diodes) in series with the drain should be
3752fb
21
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
SYSTEM
INPUT (V )
VHK (HOUSEKEEPING SUPPLY OUTPUT)
LT3752-1
SYSTEM
INPUT (V )
LT3752/LT3752-1
S
S
R
START
C
16V
8mA
V
R1
R2
R3
IN
TO
UVLO_V
PIN
1.250V(+)
+
SEC
1.215V(–)
START
OVLO
+
–
OVLO
–
1.250V
3752 F06
GND
Figure 6. Programming Overvoltage Lockout (OVLO)
3752 F07
LT3752-1 Micropower Start-Up from High System
Input Voltages
Figure 7. Micropower Start-Up from High System Input
The start-up capacitor can be calculated as:
The LT3752-1 starts up from system input voltage levels
limited only by external components (Figure 7). The low
start-up current of the LT3752-1 allows a large start-up
tHSS(MAX)
CSTART(MIN) = IHKEEP +IDRIVE (MAX),•
(
)
VDROOP(MIN)
resistor (R
) to be connected from system input volt-
IN
START
age (V ) to the V pin.
S
where:
Whensysteminputvoltageisapplied,thestart-upcapacitor
(C ) begins charging at the V pin. Once the V pin
I
I
f
= Housekeeping I (not switching)
Q
HKEEP
START
IN
IN
= (f /2.13) • Q )
DRIVE
OSC
G
exceeds9.5V(andUVLO_V >1.25V)thehousekeeping
SEC
= full-scale controller switching frequency
OSC
controller will start to switch and V supply current will
IN
START
begin to discharge C
. The C
capacitor value
Q = gate charge (V = V )(HOUT MOSFET)
START
G
GS
IN
should be chosen high enough to prevent the V pin
IN
t
= housekeeping output voltage soft-start time
HSS
from falling below 7.6V before the housekeeping supply
V
= 16V(clamp) – V
or V
DROOP
IN(OFF) IN(ONOFFHYST)
can provide a bootstrap bias to the V pin. The LT3752-1
IN
The start-up resistor can be calculated as:
start-up architecture minimizes the value of C
by
START
activating only the house keeping controller for provid-
VS(MAX) – V
IN(ON)(MAX)
RSTART(MAX)
=
ing drive back to the V pin. The forward controller only
IN
ISTART(MAX) •k
operates once the housekeeping supply is established. (If
a bootstrap diode is used from the housekeeping supply
where:
back to INTV , this only uses current from system input
CC
and not from the V pin).
V
V
= Maximum system input voltage
IN
S(MAX)
= Maximum V pin turn on threshold
IN(ON)(MAX)
IN
I
= Maximum V I for part start-up
IN Q
START(MAX)
k > 1.0 reduces R
and V charge-up time
IN
START
3752fb
22
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
Worst-case values should be used to calculate the C
where,
X = (10 /f ) – 365
START
and R
required to guarantee start-up and to turn on
9
START
in the time required.
OSC
7
7
Y = (300kHz – f )/10 (f
< 300kHz)
> 300kHz)
OSC
OSC
OSC
Example: (LT3752-1)
Y = (f
– 300kHz)/10 (f
OSC
For V
= 75V, V
= 10.4V
Example: For f
= 200kHz,
S(MIN)
IN(ON)(MAX)
OSC
I
= 265µA, I
= 4.6mA
= 150kHz
= 1.61V
START(MAX)
HKEEP(MAX)
R = 8.39 • 4635 • (1 + 0.01) = 39.28k (choose 39.2k)
T
Q = 8nC (at V = 10V), f
G
IN
OSC
The LT3752/LT3752-1 include frequency foldback at start-
up (see Figures 3 and 4). In order to make sure that a
SYNC input does not override frequency foldback during
start-up,theSYNCfunctionisignoreduntilSS1pinreaches
2.2V. Both the housekeeping and forward controllers run
synchronized to each other and in phase, with or without
the SYNC input.
t
= 4ms, V
HSS(MAX)
DROOP(MIN)
4ms
1.61V
CSTART(MIN) = 4.6mA+71kHz •8nC •
(
)
=12.8µF Choose 14.7µF
(
)
75V –10.4V
265µA •k
RSTART(MAX)
=
= 243k for k =1.0
(
)
Table 1. RT vs Switching Frequency (fOSC
)
SWITCHING FREQUENCY (kHz)
R (kΩ)
T
100
150
200
250
300
350
400
450
500
82.5
53.6
39.2
30.9
24.9
21
The R
value should be chosen with higher k
START(MAX)
values until the charge-up time for C
is acceptable.
START
In most cases, C
will be charged to the 16V clamp
START
on the LT3752-1 V pin before system input reaches its
IN
UVLO(+) threshold (Figure 4). This will allow an extra
5.6V for V
in the C
equation, allowing a smaller
DROOP
START
18.2
15.8
14
C
value and hence a faster start-up time.
START
The trade-off of lower R
tion, given by:
is greater power dissipa-
START
2
Synchronizing to an External Clock
P
= (V – V ) /R
RSTART
S
IN
START
for R
= 200k, V
= 150V, V = 10V (back
The LT3752 / LT3752-1 internal oscillator can be synchro-
nized to an external clock at the SYNC pin. SYNC pin high
level should exceed 1.8V for at least 100ns and SYNC
pin low level should fall below 0.6V for at least 100ns.
The SYNC pin frequency should be set equal to or higher
than the typical frequency programmed by the RT pin.
START
S(MAX) IN
driven from housekeeping supply)
2
P
= (150 – 10) /200k = 98mW.
RSTART
Programming Switching Frequency
The switching frequency for the housekeeping supply
and the main forward converter are programmed using a
resistor, R , connected from analog ground (Pin 18) to the
RT pin. Table 1 shows typical f
The value for R is given by:
An f
/f
ratio of x (1.0 < x < 1.25) will reduce the
SYNC OSC
externally programmed slope compensation by a factor
of 1.2x. If required, the external resistor R can be
T
ISLP
vs R resistor values.
OSC
T
reprogrammed higher by a factor of 1.2x. (see Current
Sensing and Programmable Slope Compensation).
T
R = 8.39 • X • (1 + Y)
T
3752fb
23
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
be externally overdriven by the housekeeping supply to
improve efficiency, remove power dissipation from within
the IC and provide more than 35mA output current ca-
pability. Any overdrive level should exceed the regulated
The part injection locks the internal oscillator to every ris-
ing edge of the SYNC pin. If the SYNC input is removed
at any time during normal operation the part will simply
changeswitchingfrequencybacktotheoscillatorfrequency
INTV level but not exceed 16V.
programmedbytheR resistor. Thisinjectionlockmethod
CC
T
avoids the possible issues from a PLL method which can
potentially cause a large drop in frequency if SYNC input
is removed.
In the case of a short-circuit fault from INTV to ground,
CC
eachICreducestheINTV outputcurrentlimittotypically
CC
23mA. The INTV regulator has an undervoltage lockout
CC
rising threshold, UVLO(+), which prevents gate driver
During soft-start the SYNC input is ignored until SS1 ex-
ceeds 2.2V. During soft-stop the SYNC input is completely
ignored. If the SYNC input is to be used, recall that the
switching until INTV reaches 4.75V (7V for LT3752-1)
CC
andmaintainsswitchinguntilINTV fallsbelowaUVLO(–)
CC
threshold of 4.6V (6.8V for LT3752-1).
programmabledutycycleclampD
isdependentonthe
VSEC
switchingfrequencyofthepart(seesectionProgramming
Duty Cycle Clamp). R should be reprogrammed by
For V levels close to or below the INTV regulated level,
IN
CC
IVSEC
ratio of x.
the INTV linear regulator may enter dropout. The result-
CC
1/x for an f
/f
SYNC OSC
ing lower INTV level will still allow gate driver switching
CC
as long as INTV remains above INTV UVLO(–) levels.
CC
CC
INTV Regulator Bypassing and Operation
CC
See the Typical Performance Characteristics section for
INTV performance vs V and load current.
The INTV pin is the output of an internal linear regula-
CC
CC
IN
tor driven from V and provides the supply for onboard
IN
gate drivers. The LT3752 INTV provides a regulated 7V
CC
HOUSEKEEPING CONTROLLER
supply for gate drivers AOUT, SOUT, OUT and HOUT. The
The LT3752/LT3752-1 include an internal constant fre-
quency, current mode, PWM controller for creating a
housekeepingsupply(seetheBlockDiagramandFigure8).
Connected as a flyback converter with multiple outputs,
the housekeeping supply is able to efficiently provide bias
to both primary and secondary ICs. It eliminates the need
to generate bias supplies from auxiliary windings in the
main forward transformer, reducing the complexity, size
and cost of the transformer.
LT3752-1INTV providesaregulated10Vsupplyforgate
CC
drivers AOUT, SOUT and OUT. INTV should be bypassed
CC
with a 4.7µF low ESR, X7R or X5R ceramic capacitor to
power ground to ensure stability and to provide enough
charge for the gate drivers.
The INTV regulator has a minimum 35mA output cur-
CC
rent limit. This current limit should be considered when
choosingtheswitchingfrequencyandcapacitanceloading
on each gate driver. Average current load on the INTV
CC
pin for a single gate driver driving an external MOSFET
V
V
AUX
*
IN
•
is given as :
•
V
IN
I
= f • Q
OSC G
INTVCC
INTV
INTV
HOUT
CC
CC
INTV
where:
CC
LTC3752/LT3752-1
•
R
HISLP
HCOMP
GND
HI
SENSE
f
= controller switching frequency
OSC
HFB
Q = gate charge (V = INTV )
G
GS
CC
R
HSENSE
While the INTV 50mA output current limit is sufficient
CC
R2
R1
VHK
for LT3752/LT3752-1 applications, efficiency and internal
*OPTIONAL ISOLATED SUPPLY FOR SECONDARY SIDE
power dissipation should also be considered. INTV can
3752 F08
CC
Figure 8. Housekeeping Supply
3752fb
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LT3752/LT3752-1
APPLICATIONS INFORMATION
Integrating the housekeeping controller saves cost and
space and allows switching frequency to be inherently
synchronized to the main forward converter.
to achieve regulation. The housekeeping controller is shut
down and the internal soft-start capacitor is discharged
for any of the following conditions (typical values):
The housekeeping supply can be used to overdrive the
(1) UVLO_V
< 1.25V
SEC
INTV pin to take power outside of the part, improve
(and SS1 < 0.15V)
:Soft-Stop Shutdown
:Micropower Shutdown
:System Input OVLO
CC
efficiency, provide more drive current and optimize the
(2) UVLO_V < 0.4V
SEC
INTV level. It can also be used as a bootstrap bias to
CC
(3) OVLO > 1.250V
(4) HI > 98mV
(5) INTV < X, > 16.5V :INTV UVLO, OVLO
the V pin as described in the section LT3752-1 Part
IN
:Housekeeping Overcurrent
SENSE
Start-Up. The housekeeping supply also allows bias to
any secondary side IC before the main forward converter
starts switching. This removes the need for external start-
up circuitry on the secondary side. Alternative methods
involve powering secondary side ICs directly from the
output voltage of the forward converter. This can cause
issues depending on the minimum and maximum allowed
input voltages for each IC.
CC
CC
(6) T > 170°C
:Thermal Shutdown
:V Pin UVLO
IN
J
(7) V < Y
IN
(X = 4.6V, Y = 5.5V for LT3752)
(X = 6.8V, Y = 7.6V for LT3752-1)
Housekeeping: Programming Output Voltage
The output voltage, V , of the housekeeping controller
Housekeeping: Operation
HK
is programmed using a resistor divider between V and
HK
The LT3752/LT3752-1 housekeeping controller opera-
tion is best described by referring to the Block Diagram
and Figure 8. The housekeeping controller uses a 0.7A
gate driver at HOUT to control an external N-channel
MOSFET.Whencurrentintheprimarywindingoftheflyback
transformer exceeds a level commanded by HCOMP and
the HFB pin (Figure 8) using the equation:
R1
R2
VHK =1V • 1+
The HFB pin bias current is typically 85nA.
sensed at the HI
pin, the duty cycle of the HOUT is
SENSE
Housekeeping: Programming Cycle-by-Cycle Peak
Inductor Current and Slope Compensation
terminated. Stored energy in the transformer is delivered
to the output during the off time of HOUT. The housekeep-
ing output voltage is programmed using a resistor divider
to the HFB pin. A transconductance amplifier monitors
the error signal between HFB pin and a 1.0V reference to
control HCOMP level and hence peak switch current. A
simple RC network from HCOMP pin to ground provides
compensation. Overcurrentprotectionexistsfortheexter-
The housekeeping controller limits cycle-by-cycle peak
current in the external switch and primary winding of
the flyback transformer by sensing voltage at a resistor
(R
)connectedinthesourceoftheexternalN-chan-
HISENSE
nel MOSFET (Figure 8). This sense voltage is compared to
asensethresholdattheHI pin,controlledbyHCOMP
SENSE
nal switch when 98mV is sensed at the HI
pin. This
SENSE
with an upper limit of 79mV. Since there is only one sense
line from the positive terminal of the sense resistor, any
parasitic resistance in ground side will increase its effec-
tive value and reduce available peak switch current. For
operation in continuous mode and above 50% duty cycle,
required slope compensation can be programmed by
causes a low power hiccup mode (repeated retry cycles’
of shutdown followed by soft-start) until the overcurrent
condition is removed.
Housekeeping: Soft-Start/Shutdown
Duringstart-upoftheLT3752/LT3752-1,thehousekeeping
controller has a built-in soft-start of approximately 2.2ms.
The time will vary depending on the HCOMP level needed
adding a resistor R
in series with the HI
pin. A
HISLP
SENSE
ramped current always flows out of the HI
pin. The
SENSE
current starts from 2µA at 0% duty cycle and ramps to
52µAat100%dutycycle.Minimizecapacitanceonthispin.
3752fb
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For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
hiccup mode over current level in the switch and primary
winding is given by:
For a desired peak switch current, the value for R
HISENSE
should be calculated using a 30% derated 79mV sense
thresholdwiththeeffectsofslopecompensationincluded:
98mV –∆VHSLP
ILP(OVERCURRENT)
=
52.5mV –∆VHSLP
RHSENSE
RHSENSE
where:
=
ILP(PEAK)
where:
∆V
= (2µA + D • (62.5µA) • R
)
HSLP
HISLP
∆V
= (2µA + D • (62.5µA) • R
)
D = switch duty cycle
HSLP
HISLP
I
= cycle-by-cycle peak current in primary
R
R
= slope compensation programming resistor
LP(PEAK)
winding
HISLP
= current sense resistor
HSENSE
D = switch duty cycle
= slope compensation programming resistor
Housekeeping: Output Overvoltage and Power Good
R
HISLP
The housekeeping controller monitors its supplies’ ris-
If operating in continuous mode above 50% duty cycle,
a good starting value for R is 499Ω which gives a
ing output voltage V via the HFB pin and determines
HK
HISLP
power good (PGOOD(+)) when V reaches 96% of its
HK
26mV total drop in current comparator threshold at 80%
programmed value. 10µs after confirmation of PGOOD,
the circuitry for the LT3752/LT3752-1 forward controller
is activated.
duty cycle. An f /f ratio of x (1.0V < x < 1.25) will
SYNC OSC
reducetheexternallyprogrammedslopecompensationby
a factor of 1.2x. If required, the external resistor R
can be reprogrammed higher by a factor of 1.2x.
HISLP
The SS1 pin is allowed to begin charging and eventually
allows the forward converter to start switching. If V
HK
Housekeeping: Adaptive Leading Edge Blanking
falls below 92% of its programmed level (PGOOD(–)),
the SS1 pin is discharged and forward controller circuitry
is disabled.
Blanking of the HI
signal on the leading edge of
SENSE
HOUT is adaptive to allow a wide range of MOSFETs. The
blanking occurs from the start of HOUT rise and waits
until HOUT has reached within 1V of its maximum level
Tolimithousekeepingoutputovervoltage,V ,thehouse-
HK
keeping controller overrides it’s own regulation loop and
immediately stops switching if its output voltage exceeds
20% of its programmed value. This is especially impor-
tant when using the housekeeping supply to bias other
ICs. The forward controller is still allowed to switch. The
housekeepingcontrollerreturnstonormalregulationloop
(INTV for LT3752, V for LT3752-1) before adding an
CC
IN
additional fixed 100ns of blanking.
Housekeeping: Overcurrent Hiccup Mode
To protect the housekeeping controller during a short-
to-ground fault on the housekeeping output voltage, a
control when it’s output voltage, V , falls to less than
HK
15% above it’s programmed value.
98mV fixed overcurrent threshold exists at the HI
SENSE
pin to discharge the internal soft-start capacitor and enter
a hiccup (retry) mode. This hiccup mode significantly
reduces the average power in the external components
compared to continued cycle-by-cycle switching at the
Housekeeping: Transformer Turns Ratio and Leakage
Inductance
The external resistor divider used to set the output voltage
of the housekeeping supply provides a relative freedom
in selecting the transformer turns ratio to suit a given
79mV threshold. Having already calculated the R
HSENSE
resistor for peak cycle-by-cycle current, the typical
3752fb
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For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
application. Simple integer turns ratios can be used which
allowoff-the-shelftransformers(seeexamplecircuitsinthe
Typical Applications section). Turns ratios can be chosen
on the basis of desired duty cycle. However, the input and
output levels, turns ratio and flyback leakage spike must
be considered for the breakdown rating of the MOSFET.
Transformer leakage inductance causes a voltage spike to
occur after the switch turns off. In some cases a snubber
circuit will be required to limit this spike.
be used in a fully regulated forward converter application.
In addition, they can still operate if damage occurs to
the feedback path—no secondary side error amplifier or
opto-coupler—by using an accurate, programmable volt-
secondclamptoregulatedutycycleinverselyproportional
to transformer input voltage.
Adaptive Leading Edge Blanking Plus Programmable
Extended Blanking
The LT3752/LT3752-1 provide a 2A gate driver at the
OUT pin to control an external N-channel MOSFET for
main power delivery in the forward converter (Figure 10).
During gate rise time and sometime thereafter, noise can
be generated in the current sensing resistor connected
to the source of the MOSFET. This noise can potentially
cause a false trip of sensing comparators resulting in
early switch turn off and in some cases re-soft-start of
the system. To prevent this, LT3752/LT3752-1 provide
Housekeeping: Operating Without This Supply
The housekeeping supply is highly recommended for
providing local bias voltages for both the primary and
secondary sides (to improve efficiency, simplify the main
transformer design and ensure all ICs are activated even
for V
= 0V). The LT3752 (not LT3752-1) housekeeping
OUT
supply components can be omitted (not populated) if an
extra winding already exists from the main transformer
to create an auxiliary supply. Care must be taken that the
auxiliary supply (for either the primary side or secondary
side or both) does not affect proper operation. A resistor
divider (Figure 8) should now be connected directly from
adaptive leading edge blanking of both OC and I
SENSEP
signals to allow a wide range of MOSFET Q ratings. In
G
addition, a resistor R
connected from T
pin to
TBLNK
BLNK
analog ground (Pin 18) programs an extended blanking
duration (Figure 9).
INTV to supply the HFB pin with a ratio :
CC
R1/R2 = 3
(ADAPTIVE)
LEADING
EDGE
BLANKING
(PROGRAMMABLE)
EXTENDED
CURRENT
SENSE
DELAY
(Example : R1 = 10k, R2 = 3.32k).
BLANKING
This ratio ensures HFB >> 0.96V (typical PGOOD level to
enable SS1 and the forward converter).
(a) At INTV = 4.75V (UVLO(+)), HFB = 1.2V.
CC
7.32k ≤ R
≤ 249k
TBLNK
220ns
OUT
t
= 50ns + (2.2ns • R
)
BLNK
TBLNK
(b) At INTV = 7V (Regulated), HFB = 1.7V.
CC
k
(c) At INTV = 8V (Overdriven), HFB = 2V.
CC
3752 F09
Care should be taken not to exceed HFB = 3V.
Figure 9. Adaptive Leading Edge Blanking Plus
Programmable Extended Blanking
FORWARD CONTROLLER
The LT3752/LT3752-1 are primary side, current mode,
PWM controllers optimized for use in a synchronous
forward converter with active clamp reset. Each IC can
3752fb
27
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
connectedinthesourceoftheexternaln-channelMOSFET
(Figure 10).
Adaptive leading edge blanking occurs from the start of
OUT rise and completes when OUT reaches within 1V of
its maximum level (INTV for LT3752, V for LT3752-1).
CC
IN
V
V
OUT
IN
Anextendedblankingthenoccurswhichisprogrammable
•
•
using the R resistor given by:
TBLNK
V
IN
2.2ns
k
INTV
CC
M1
INTV
OUT
LTC3752/LT3752-1
OC
CC
tBLNK = 50ns+
•R
,
TBLNK
FROM
REGULATION
LOOP
7.32k < R
< 249k
I
COMP
TBLNK
SENSEP
R
ISLP
R
SENSE
Adaptive leading edge blanking minimizes the value re-
quiredforR .IncreasingR furtherthanrequired
increases M1 minimum on time (Figure 10).
I
SENSEN
TBLNK
TBLNK
GND
3752 F10
In addition, the critical volt-second clamp (D
) is not
VSEC
Figure 10. Current Sensing and Programmable
Slope Compensation
blanked. Therefore, if D
decreases far enough (in soft
VSEC
startfoldbackandatmaximuminputvoltage)M1mayturn
off before blanking has completed. Since OC and I
The sense voltage across R
is compared to a sense
SENSE
SENSEP
threshold at the I
pin, controlled by COMP pin level.
SENSEP
signals are only seen when M1 is on (and after blanking
Two sense inputs, I
and I
, are provided to
SENSEP
SENSEN
has completed), R value should be limited by:
TBLNK
allow a Kelvin connection to R
. For operation in con-
SENSE
(2.2ns/k)R
< T
– t
– 50ns
ADAPTIVE
TBLNK
VSEC(MIN)
tinuous mode and above 50% duty cycle, required slope
compensation can be programmed by adding a resistor,
where,
R
, in series with the I
pin. A ramped current
pin. The current starts from
ISLP
SENSEP
9
T
= 10 (D
/(fold.fosc))
VSEC(MIN)
VSEC (MAX)
always flows out of the I
SENSE
(Input
/Input
)
(MIN)
(MAX)
2µA at 0% duty cycle and linearly ramps to 33µA at 80%
duty cycle. A good starting value for R is 1.5kΩ which
gives a 41mV total drop in current comparator threshold
at 65% duty cycle.
fold = f
and D
foldback ratio (for OUT pin)
OSC
VSEC
ISLP
( = 4 for LT3752 , = 2 for LT3752-1)
t
= OUT pin rise time to INTV – 1V
ADAPTIVE
CC
The COMP pin commands an I
0mV and 220mV. The 220mV allows a large slope com-
pensation voltage drop to exist in R without effecting
threshold between
SENSEP
Example: For Figure 20 circuit,
D
= 0.77,
= 23ns
ADAPTIVE
VSEC(MAX)
= 17.4V/74V, fold = 4, t
Input
(MIN)/(MAX)
ISLP
and f
= 240kHz,
OSC
the programming of R
currents in M1. An f
to set maximum operational
SENSE
9
5
T
= 10 (0.77/(4 • 2.4 • 10 )) • 17.4/74 = 188ns
/f
ratio of x (1.0 < x < 1.25)
VSEC(MIN)
SYNC OSC
will reduce the externally programmed slope compensa-
(2.2ns/1k)R
< 188 – 23 – 50
TBLNK
tion by a factor of 1.2x. If required, the external resistor
R
TBLNK
< 52.5k (Actual Circuit Uses 34k)
R
can be reprogrammed higher by a factor of 1.2x.
ISLP
Current Sensing and Programmable Slope
Compensation
Overcurrent: Hiccup Mode
The LT3752/LT3752-1 use a precise 96mV sense thresh-
old at the OC pin to detect excessive peak switch current
(Figure 10). During an overload condition switching
The LT3752/LT3752-1 command cycle-by-cycle peak
current in the external switch and primary winding of the
forward transformer by sensing voltage across a resistor
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For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
t
stops immediately and the SS1/SS2 pins are rapidly
discharged. The absence of switching reduces the sense
voltage at the OC pin, allowing SS1/SS2 pins to recharge
and eventually attempt switching again. The part exists
in this hiccup mode as long as the overcurrent condition
exists. This protects the converter and reduces power
dissipation in the components (see Hard Stop in the
Applications Information section). The 96mV peak switch
current threshold is independent of the voltage drop in
t
ON_VSEC
(PROGRAMMED
BY R
)
IVSEC
t
OUT
ON
DV
= t
/t
SEC ON_VSEC
D = t /t
ON
3752 F11
DV
= “DUTY CYCLE GUARDRAIL”
SEC
Figure 11. Volt-Second (DVSEC) Clamp
R
ISLP
used for slope compensation.
Output DC load current to trigger hiccup mode:
SYSTEM
INPUT
LOAD(OVERCURRENT)
R1
N
NP 96mV
UVLO_V
SEC
=
•
– 1/2 I
(
)
RIPPLE(P-P)
R2
R3
R
ISENSE
TO
OVLO
PIN
S
LT3752/LT3752-1
where:
N = forward transformer primary turns
IVSEC
R
RT
R
IVSEC
T
P
3752 F12
N = forward transformer secondary turns
S
Figure 12. Programming DVSEC
I
= Output inductor peak-to-peak ripple
RIPPLE(P-P)
current
A resistor R
from the IVSEC pin to analog ground
IVSEC
R
shouldbeprogrammedtoallowmaximumDCload
ISENSE
(Pin 18) programs D
.
VSEC
currentfortheapplicationplusenoughmarginduringload
transients to avoid overcurrent hiccup mode.
D
VSEC
(OUT pin duty cycle clamp)
RIVSEC fOSC
51.1k 300 UVLO_VSEC
1.25
Programming Maximum Duty Cycle Clamp: D
(Volt-Second Clamp)
VSEC
= 0.725 •
•
•
Unlike other converters which only provide a fixed maxi-
mum duty cycle clamp, the LT3752/LT3752-1 provide an
accurate programmable maximum duty cycle clamp
where:
R
f
= programming resistor at IVSEC pin
= switching frequency (kHz)
IVSEC
(D
) on the OUT pin which moves inversely with
VSEC
system input. D
OSC
provides a duty cycle guardrail to
VSEC
UVLO_V
= resistor divided system input voltage
SEC
limit the volt-seconds-on product over the entire natural
duty cycle range (Figures 11 and 12). This limits the
drain voltage required for complete transformer reset.
R
IVSEC
can program any D
required at minimum
VSEC
system input. D
will then follow natural duty cycle
VSEC
as V varies. Maximum programmable D
is typi-
IN
VSEC
3752fb
29
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
cally 0.75 but may be further limited by the transformer
design and voltage ratings of components connected to
the drain of the primary side power MOSFET (SWP). See
voltagecalculationsintheLOsideandHIsideactiveclamp
topologies sections.
secondaryside. D
controlstheoutputoftheconverter
VSEC
by controlling duty cycle inversely proportional to system
input. If D duty cycle guardrail is programmed X%
VSEC
above natural duty cycle, V
will only increase by X%
OUT
if a closed loop system breaks open. This volt-second
clamp is operational over a 10:1 system input voltage
If system input voltage falls below it's UVLO threshold
the part will enter soft-stop with continued switching.
The LT3752/LT3752-1 include an intelligent circuit which
range. See D
versus UVLO_V
pin voltage in the
VSEC
SEC
Typical Performance Characteristics section.
prevents D
from continuing to rise as system input
VSEC
R
IVSEC
: Open Pin Detection Provides Safety
voltagefalls(seeSoft-Stop).Withoutthis,toolargeaD
VSEC
The LT3752/LT3752-1 provide an open-detection safety
feature for the R pin. If the R resistor goes
open circuit the part immediately stops switching. This
prevents the part from running without the volt-second
clamp in place.
would require extremely high reset voltages on the SWP
node to properly reset the transformer. The UVLO_V
IVSEC
IVSEC
SEC
pin maximum operational level is the lesser of V – 2V
IN
or 12.5V.
The LT3752/LT3752-1 volt-second clamp architecture
is superior to an external RC network connected from
system input to trip an internal comparator threshold.
The RC method suffers from external capacitor error, part-
to-part mismatch between the RC time constant and the
IC’s switching period, the error of the internal comparator
threshold and the nonlinearity of charging at low input
Transformer Reset: Active Clamp Technique
The LT3752/LT3752-1 include a 0.4A gate driver at the
AOUT pin to allow the use of an active clamp transformer
resettechnique(Figures13, 17). Theactiveclampmethod
improves efficiency and reduces voltage stress on the
main power switch, M1. By switching in the active clamp
capacitor only when needed, the capacitor does not lose
itschargeduringM1on-time.Byallowingtheactiveclamp
voltages. The LT3752/LT3752-1 use the R
resistor to
IVSEC
define the charge current for an internal timer capacitor to
set an OUT pin maximum on-time, t . The voltage
ON(VSEC)
pin voltage (divided
capacitor, C , to store the average voltage required to
CL
across R
follows UVLO_V
IVSEC
SEC
reset the transformer, the main power switch sees lower
down from system input voltage). Hence, R
current
IVSEC
drain voltage.
varies linearly with input supply. The LT3752/LT3752-1
also trim out internal timing capacitor and comparator
thresholderrorstooptimizepart-to-partmatchingbetween
An imbalance of volt-seconds will cause magnetizing cur-
rent to walk upwards or downwards until the active clamp
capacitor is charged to the optimal voltage for proper
transformer reset. The voltage rating of the capacitor will
depend on whether the active clamp capacitor is actively
switched to ground (Figure 13) or actively switched to
t
and T.
ON(VSEC)
D
Open Loop Control: No Opto-Coupler, Error
VSEC
Amplifier or Reference
The accuracy of the programmable volt-second clamp
(D
) safely controls V
if open loop conditions exist
VSEC
OUT
suchasnoopto-coupler,erroramplifierorreferenceonthe
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For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
L
LEAK
CSW
FSW
V
IN
V
OUT
•
•
L
MAG
L
LEAK
SWP
C
CL
OUT
LT3752
AOUT
M1
LTXXXX
FG CG
C1
M2
M3
M4
V
D
R1
D1
–V
IN
–V
OUT
3752 F13
Figure 13. LO Side Active Clamp Topology
I
MAG
1A/DIV
SWP
50V/DIV
3752 F14
20µs/DIV
Figure 14. Active Clamp Reset: Magnetizing Current and M1 Drain Voltage
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
system input (Figure 17). In an active clamp reset topol-
ogy, volt-second balance requires:
LO SIDE ACTIVE CLAMP TOPOLOGY
V • D = (SWP – V ) • (1 – D)
IN
IN
where:
V = Transformer input supply
IN
D = (V /V ) • N = switch M1 duty cycle
OUT IN
V
= Output voltage (including the voltage drop
OUT
contribution of M4 catch diode during M1 off)
60
DUTY CYCLE (%)
80
20
30
40
50
70
N = Transformer turns ratio = N /N
P
S
3752 F15
SWP = M1 drain voltage
Figure 15. LO Side VCCL vs Duty Cycle
(Normalized to 50% Duty Cycle)
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LT3752/LT3752-1
APPLICATIONS INFORMATION
LO Side Active Clamp Topology (LT3752)
During load transients, duty cycle and hence V
may
CCL
increase. Replace D with D
in the equation above to
VSEC
The steady-state active clamp capacitor voltage, V
,
CCL
calculate transient V
values. See the previous section
ProgrammingDutyCycleClamp–D
CCL
required to reset the transformer in a LO side active clamp
.TheD
guard-
VSEC
VSEC
topology (Figure 13) can be approximated as the drain-to-
rail can be programmed as close as 5% higher than D but
mayrequirealargermargintoimprovetransientresponse.
source voltage (V ) of switch M1, given by:
DS
V
CCL
(LO side):
As shown in Figure 15, the maximum steady-state value
(a) Steady state: V
= SWP = V
for V
may occur at minimum or maximum input volt-
CCL
DS
CCL
age. HenceV shouldbecalculatedatbothinputvoltage
CCL
2
V
1
1–D
IN
levels and the largest of the two calculations used. M1
=
• V =
IN
V – V
•N
(
)
(
)
IN
OUT
drain should be rated for a voltage greater than the above
steady-state V calculation due to tolerances in duty
DS
(b) Transient:
cycle, load transients, voltage ripple on C and leakage
CL
inductance spikes. C should be rated higher due to the
CL
effect of voltage coefficient on capacitance value. A typical
2.5
2.3
2.0
1.8
1.5
1.3
1.0
0.8
choice for C is a good quality X7R capacitor. M2 should
CL
have a V rating greater than V since the bottom plate
HI SIDE ACTIVE CLAMP TOPOLOGY
DS
CCL
of C is –V
during M1 on and M2 off. For high input
CL
CCL
voltage applications, the limited V rating of available
DS
P-channel MOSFETs might require changing from a LO
side to HI side active clamp topology.
Forthelosideactiveclamptopologyinsteadystate,during
M1 on time, magnetizing current (I
) increases from a
MAG
negative value to a positive value (Figure 14). When M1
turnsoff,magnetizingcurrentchargesSWPuntilitreaches
CCL
0.5
20
40
50
60
70
30
80
DUTY CYCLE (%)
V
plus the voltage drop of the M2 body diode. At this
3752 F16
Figure 16. HI Side VCCL vs Duty Cycle
(Normalized to 50% Duty Cycle)
L
LEAK
FSW
CSW
V
IN
V
OUT
•
•
L
MAG
C
CL
C2
C1
T4
M2
V
D
•
•
L
LEAK
R1
D1
LTXXXX
FG CG
SWP
–V
M3
M1
M4
IN
AOUT
LT3752-1
OUT
–V
IN
–V
OUT
3752 F17
Figure 17. HI Side Active Clamp Topology
3752fb
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APPLICATIONS INFORMATION
moment the active clamp capacitor is passively switched
in to ground (due to the forward conduction of M2 body
diode) and the drain voltage increases at a slower rate
During load transients, duty cycle and hence V
may
CCL
increase. Replace D with D
in the equation above to
VSEC
values. D
calculate transient V
guardrail can be
CCL
VSEC
due to the loading of C . SWP above V causes I
programmedascloseas6%higherthanDbutmayrequire
a larger margin to improve transient response. See the
previous section Programming Duty Cycle Clamp–D
CL
IN
MAG
/dT
to reduce from a positive value towards zero (dV
SWP
= 0). As I
becomes negative it begins to discharge
.
MAG
VSEC
the SWP node. Switching in M2 before I
actively connects the bottom plate of C to ground and
reverses,
MAG
C
should be rated for a voltage higher than the above
CL
CL
steady-state calculation due to tolerances in duty cycle,
allows SWP to be discharged slowly. The resulting SWP
waveform during M1 off-time appears as a square wave
with a superimposed sinusoidal peak representing ripple
load transients, voltage ripple on C and the effect of
CL
voltage coefficient on capacitance value. A typical choice
for C is a good quality (X7R) capacitor. When using a
CL
voltage on C .
CL
gate drive transformer to provide control of the active
clamp switch (M2), the external components C1, C2, R1,
D1 and T4 are required. T4 size will increase for lower
programmed switching frequencies due to a minimum
volt-secondrequirement.Alternatively,asimplegatedriver
opto-coupler can be used as a switch to control M2, for a
smallersolutionsize.Theinputsupplycapacitorforthegate
drive opto-coupler is easily charged using the housekeep-
ing supply of the LT3752-1. Common component values
are shown in the Typical Applications section.
The switch M2 experiences near zero voltage switching
(ZVS) since only the body diode voltage drop appears
across it at switch turn on.
HI Side Active Clamp Topology (LT3752-1)
For high input voltage applications the V rating of avail-
DS
able P-channel MOSFETs might not be high enough to
be used as the active clamp switch in the LO side active
clamptopology(Figure13). AnN-channelapproachusing
the HI side active clamp topology (Figure 17) should be
used. This topology requires a gate drive transformer or
a simple gate drive opto-coupler to drive the N-channel
MOSFET (M2) for switching in the active clamp capacitor
Active Clamp Capacitor Value and Voltage Ripple
The active clamp capacitor value should be chosen based
on the amount of voltage ripple which can be tolerated
from SWP to V . The M1 drain voltage calculation is the
by components attached to SWP. Lower C values will
IN
CL
same as in the LO side active clamp case and M1 should
be rated in a similar manner. The voltage across the clamp
capacitor in the HI side architecture, however, is lower by
createlargervoltageripple(increaseddrainvoltageforthe
primary side power MOSFET) but will require less swing
in magnetizing current to move the active clamp capacitor
during duty cycle changes. Choosing too high a value for
the active clamp capacitor (beyond what is needed to keep
ripple voltage to an acceptable level) will require unneces-
sary additional flux swing during transient conditions. For
systems with flux swing detection, too high a value for the
active clamp capacitor will trigger the detection system
early and degrade transient response.
V since it is referenced to V .
IN
IN
The steady-state active clamp capacitor voltage V
to
CCL
reset the transformer in a HI side active clamp topology
can be approximated by:
V
CCL
(HI side):
(a) Steady state: V
= V
= V – V
CCL
RESET
DS
IN
D
1–D
N
=
• V = V • V
•
IN
IN
OUT
V – V
•N
(
IN
OUT
(b) Transient:
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AnotherfactortoconsideristheresonancebetweenC and
Active Clamp MOSFET Selection
CL
themagnetizinginductance(L
)ofthemaintransformer.
MAG
The selection of active clamp MOSFET is determined by
the maximum levels expected for the drain voltage and
drain current. The active clamp switch (M2) in a either a lo
side or hi side active clamp topology has the same BVdss
requirements as the main N-channel power MOSFET. The
current requirements are divided into two categories :
An RC snubber (R , C ) in parallel with C will dampen
S
S
CL
the sinusoidal ringing and limit the peak voltages at the
primary side MOSFET drain during input/load transients.
Check circuit performance to determine if the snubber
is required. Component values can be approximated as:
2
10
(1–D
2•π •f
OSC
)
MIN
(A) Drain Current
C (active clampcapacitance)=
•
CL
L
MAG
This is typically less than the main N-channel power
MOSFET because the active clamp MOSFET sees only
magnetizing current, estimated as :
where,
D
MIN
= (V /V
) • N /N
OUT IN(MAX) P S
Peak I
MAG
(steady state) = (1/2) • (N /N ) • (V
OSC
/
MAG
) • (1/f
P
S
OUT
and (if needed),
C (snubber capacitance) = 6 • C
L
)
where,
L
S
CL
R (snubber resistance) = (1/(1-D
)) • √(L
/C )
= main transformer’s magnetizing inductance
S
MAX
MAG CL
MAG
where,
Example (LT3752) : For V
=12V, N /N = 2, f
OSC
=
OUT
P
S
250kHz and L
= 100µH, Peak I
= 0.48A.
MAG
MAG
D
MAX
= ( V /V
) • N /N
OUT IN(MIN) P S
This value should be doubled for safety margin due to
variations in L , f and transient conditions.
Check the voltage ripple on SWP during steady-state
operation.
MAG OSC
(B) Body Diode Current
C
V
voltage ripple can be estimated as:
CL
2
2
The body diode will see reflected output current as a pulse
every time the main N-channel power MOSFET turns off.
This is due to residual energy stored in the transformer's
leakage inductance. The body diode of the active clamp
MOSFET should be rated to withstand a forward pulsed
current of:
= V
• (1-D) /(8 • C • L
• f
)
CCL(RIPPLE)
CCL
CL
MAG OSC
where,
D = (V /V ) • (N /N )
OUT IN
P
S
V
CCL
V
CCL
= V /(1-D) (Lo side active clamp topology)
IN
= D • V /(1-D) (Hi side active clamp topology)
IN
I
= (N /N ) (I
+ (I /2))
L(RIPPLE)(P-P)
D(MAX)
S
P
OUT(MAX)
Example : For V = 36V, V
= 12V, N /N = 2, V
CCL
=
IN
OUT
P
S
where,
108V (Lo side active clamp topology), C = 22nF, L
CL
MAG
2
I
= output inductor ripple current = (V
/
= 100µH, f
= 250kHz, V
= 108(0.33) /(8(22
L(RIPPLE)(P-P)
(L
OUT
OSC
CCL(RIPPLE)
–9
–4
4 2
• f )) • (1–(V /V )(N /N ))
• 10 )(10 )(2.5 • 10 ) ) = 10.7V
OUT OSC
OUT IN P S
I
= maximum output load current
Thetransformeristypicallychosentooperateatamaximum
flux density that is low enough to avoid excessive core
losses. This also allows enough headroom during input
and load transients to move the active clamp capacitor at
a fast enough rate to keep up with duty cycle changes.
OUT(MAX)
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Programming Active Clamp Switch Timing: AOUT to
Programming Synchronous Rectifier Timing: SOUT to
OUT (t ) and OUT to AOUT (t ) Delays
OUT (t ) and OUT to SOUT (t ) Delays
AO
OA
SO OS
Thetimingst andt representthedelaysbetweenAOUT
The LT3752/LT3752-1 include a 0.4A gate driver at the
SOUT pin to send a control signal via a pulse transformer
to the secondary side of the forward converter for syn-
chronous rectification (see Figures 1 and 2). For the
highest efficiency, M4 should be turned on whenever M1
is turned off. This suggests that SOUT should be a non-
overlapping signal with OUT with very small non-overlap
times. Inherent timing delays, however, which can vary
from application to application, can exist between OUT to
CSW and between SOUT to CG. Possible shoot-through
can occur if both M1 and M4 are on at the same time,
resulting in transformer and/or switch damage.
AO
OA
and OUT edges (Figures 1 and 2) and are programmed
by a single resistor, R , connected from analog ground
TAO
(Pin 18) to the T pin. Once t is programmed for the
AO
AO
reasons given below, t will be automatically generated.
OA
Front-end timing t (M2 off, M1 on)
AO
= AOUT(edge)-to-OUT(rising)
R
1k
TAO
= 50ns+3.8ns •
, 14.7k <RTAO < 125k
Inordertominimizeturn-ontransitionlossinM1thedrain
of M1 should be as low as possible before M1 turns on.
Front-end timing: t (M4 off, M1 on)
SO
To achieve this, AOUT should turn M2 off a delay of t
= SOUT(falling)-to-OUT(rising) delay
AO
beforeOUTturnsM1on.Thisallowsthemaintransformer’s
= t = t – t
AS
SO
AO
magnetizingcurrenttodischargeM1drainvoltagequickly
= 3.8ns • (R – R
)
TAO
TAS
towards V before M1 turns on.
IN
where:
As SWP falls below V , however, the rectifying diodes on
IN
t
AS
= 50ns + (3.8ns • R /1k) , 14.7k < R < 125k,
the secondary side are typically active and clamp the SWP
TAS
TAS
node close to V . If enough leakage inductance exists,
IN
t
AO
= 50ns + (3.8ns • R /1k), 14.7k < R
< 125k,
TAO
TAO
however, the clamping action on SWP by the secondary
side will be delayed—potentially allowing the drain of
M1 to be fully discharged to ground just before M1 turns
on. Even with this delay due to the leakage inductance,
t
is defined by resistors R and R connected from
TAS TAO
SO
analog ground (Pin 18) to their respective pins T and
AS
T . Each of these resistor defines a delay referenced
to the AOUT edge at the start of each cycle. R
AO
was
TAO
L
needs to be low enough to allow I
to be negative
MAG
MAG
already programmed based on requirements defined in
the previous section Programming AOUT to OUT Delay.
enough to slew SWP down to ground before M1 turns on.
If achievable, M1 will experience zero voltage switching
(ZVS) for highest efficiency. As will be seen in a later sec-
tion entitled Primary-Side Power MOSFET Selection, M1
transition loss is a significant contributor to M1 losses.
R
is then programmed as a delay from AOUT to SOUT
TAS
to fulfill the equation above for t . By choosing R less
SO
TAS
than or greater than R , the delay between SOUT falling
TAO
and OUT rising can be programmed as positive or nega-
Back-end timing t (M1 off, M2 on) is automatically
OA
tive. While a positive delay can always be programmed
generated
for t , the ability to program a negative delay allows for
SO
improved efficiency if OUT(rising)-to-CSW(rising) delay
= OUT(falling)-to-AOUT(edge) = 0.9 • t
AO
is larger than SOUT(falling)-to-CG(rising) delay.
t
should be checked to ensure M2 is not turned on until
OA
M1 and M3 are turned off.
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Back-end timing: t (M1 off, M4 on)
= OUT (falling)-to-SOUT (rising) delay
SS1 = 1.25V to 2.45V (soft-start f , D
). This is the
OS
OSC VSEC
SS1rangeforsoft-startingf andD
foldedbackfrom
OSC
VSEC
22% (50% for LT3752-1) to 100% of their programmed
= t = 35ns + (2.2ns • R /1k), 7.32k < R < 249k
TOS
OS
TOS
levels. Fold back of f
and D
reduces effective
OSC
VSEC
Thetimingresistor,R ,definestheOUT(falling)-to-SOUT
TOS
minimum duty cycle for the primary side MOSFET. This
allows inductor current to be controlled at low output
voltages during start-up.
(rising) delay. This pin allows programming of a positive
delay, for applications which might have a large inherent
delay from OUT fall to SW2 fall.
SS1 ramp rate is chosen slow enough to ensure f
and
OSC
D
foldback lasts long enough for the converter to take
VSEC
Soft-Start (SS1, SS2)
control of inductor current at low output voltages. In ad-
dition, slower SS1 ramp rate increases the non-switching
periodduringanoutputshorttogroundfault(overcurrent
hiccup mode) to reduce average power dissipation (see
Hard-Stop).
TheLT3752/LT3752-1useSS1andSS2pinsforsoftstarting
various parameters (Figures 3, 4 and 18). SS1 soft starts
internal oscillator frequency and D
(maximum duty
VSEC
cycle clamp). SS2 soft starts COMP pin voltage to control
outputinductorpeakcurrent.UsingseparateSS1andSS2
pins allows the soft-start ramp of oscillator frequency and
SS2 = 0V to 1.6V (soft-start COMP pin). This is the SS2
range for soft-starting COMP pin from approximately 1V
to 2.6V.
D
to be independent of COMP pin soft-start. Typically
VSEC
SS1capacitor(C )ischosenas0.47µF andSS2capaci-
SS1
tor (C ) is chosen as 0.1µF. Soft-start charge currents
SS2
SS2 ramp rate is chosen fast enough to allow a (slower)
soft-start control of COMP pin from a secondary side
opto-coupler controller.
are 11.5µA for SS1 and 21µA for SS2.
SS1 is allowed to start charging (soft-start) if all of the
following conditions exist (typical values) :
SS1 soft-start non-switching period (0V to 1.25V)
= 1.25V • C /11.5µA
SS1
(1) UVLO_V
> 1.25V: System input not in UVLO
SEC
SS1 soft-start f , D
period (1.25V to 2.45V)
VSEC
OSC
(2) OVLO < 1.215V: System input not in OVLO
(3) HFB > 0.96V: Housekeeping supply valid
(4) OC < 96mV: No over current condition
= 1.2V • C /11.5µA
SS1
SS2soft-startCOMPperiod(0Vto1.6V)=1.6V•C /21µA
SS2
Soft-Stop (SS1)
(5) X < INTV < 16V: INTV valid
CC
CC
The LT3752/LT3752-1 gradually discharge the SS1 pin
(soft-stop) when a system input UVLO occurs or when
an external soft-stop shutdown command occurs (0.4V <
(6) T < 165°C: Junction temperature valid
J
(7) V > Y: V pin valid
IN
IN
UVLO_V < 1.25V). During SS1 soft-stop the converter
(X = 4.75V, Y = 5.8V for LT3752)
(X = 7.0V, Y = 9.5V for LT3752-1)
SEC
continues to switch, folding back f , D
and COMP
OSC VSEC
pin voltage (Figures 3, 4 and 18). Soft-stop discharge
SS1 = 0V to 1.25V (no switching). This is the SS1 range
for no switching for the forward converter. SS2 = 0V.
current is 10.5µA for SS1. Soft-stop provides:
(1) Activecontrolofthesecondarywindingduringoutput
dischargeforcleanshutdowninself-drivenapplica-
tions.
SS1 > 1.25V allows SS2 to begin charging from 0V.
(2)Controlled discharge of the active clamp capacitor
tominimizemagnetizingcurrentswingduringrestart.
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SS1: 2.45V to 1.25V (soft-stop f , D
, COMP). This
(3) HFB < 0.92V: Housekeeping supply UVLO
(4) OC > 96mV: Over current condition
OSC VSEC
is the SS1 range for soft-stop folding back of:
(1)f andD
from100%to22%(50%forLT3752-1)
OSC
VSEC
(5) INTV < X(UVLO), > 16.5V (OVLO)
CC
of their programmed levels.
(6) T > 170°C: Thermal shutdown
J
(2)COMP pin (100% to 0% of commanded peak
current).
(7) V < Y: V pin UVLO
IN
IN
(X = 4.6V, Y = 5.5V for LT3752)
(X = 6.8V, Y = 7.6V for LT3752-1)
SS1soft-stopf
, D
, COMPperiod (2.45Vto1.25V)
OSC VSEC
= 1.2V • C /10.5µA
SS1
SS1 < 1.25V. Forward converter stops switching and SS2
pin is discharged to 0V using 2.8mA.
Switching stops immediately for any of the faults listed
above.WhenSS1dischargesbelow0.15Vitbeginscharg-
ing again if all faults have been removed. For an over cur-
rent fault triggered by OC > 96mV, the disable of switching
will cause the OC pin voltage to fall back below 96mV.
This will allow SS1 and SS2 to recharge and eventually
attempt switching again. If the over current condition still
exists, OC pin will exceed 96mV again and the discharge/
charge cycle of SS1 and SS2 will repeat in a hiccup mode.
The non-switching dead time period during hiccup mode
reduces the average power seen by the converter in an
over current fault condition. The dead time is dominated
by SS1 recharging from 0.15V to 1.25V.
SS1=1.25Vto0V:WhenSS1fallsbelow0.15Vtheinternal
SS1 latch is reset. If all faults are removed, SS1 begins
charging again. If faults still remain, SS1 discharges to 0V.
SS1 soft-stop non-switching period (1.25V to 0V)
= 1.25V • C /10.5µA
SS1
D
rises as system input voltage falls in order to
VSEC
provide a maximum duty cycle guardrail (volt-second
clamp). When system input falls below it's UVLO thresh-
old, however, this triggers a soft-stop with the converter
continuing to switch. It is important that D
no longer
VSEC
increases even though system input voltage may still be
falling. The LT3752/LT3752-1 achieve an upper clamp on
Non-switching period in over current (hiccup mode):
= 1.1V • C /11.5µA
SS1
D
by clamping the minimum level for the I
pin
VSEC
VSEC
to 1.25V. As SS1 pin discharges during soft-stop it folds
back D . As D falls below the natural duty cycle
OUT, AOUT, SOUT Pulse-Skipping Mode
VSEC
VSEC
During load steps, initial soft-start, end of soft-stop or
light load operation (if the forward converter is designed
tooperateinDCM),theloopmayrequirepulseskippingon
the OUT pin. This occurs when the COMP pin falls below
its switching threshold. If the COMP pin falls below it's
switching threshold while OUT is turned on, the LT3752/
LT3752-1 will immediately turn OUT off ; both AOUT and
SOUTwillcompletetheirnormalsignaltimingsreferenced
from the OUT falling edge. If the COMP pin remains below
it's switching threshold at the start of the next switching
cycle, the LT3752/LT3752-1 will skip the next OUT pulse
and therefore also skip AOUT and SOUT pulses. For AOUT
control, this prevents the active clamp capacitor from be-
of the converter, the converter loop follows D
. If the
VSEC
system input voltage rises (I
pin rises) during soft-
VSEC
stop the volt-second clamp circuit further reduces D
.
VSEC
The I.C. chooses the lowest D
commanded by either
VSEC
the I
pin or the SS1 soft-stop function.
VSEC
Hard-Stop (SS1, SS2)
Switching immediately stops and both SS1 and SS2 pins
are rapidly discharged (Figure 18. Hard-Stop) if any of the
following faults occur (typical values):
(1) UVLO_V
< 0.4V: Micropower shutdown
SEC
(2) OVLO > 1.250V: System input OVLO
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HARD STOP
(FAULTS)
SOFT-START
(WHEN ALL CONDITIONS SATISFIED)
SOFT-STOP
(0.4V < UVLO_V
< 1.25)
SEC
(1) UVLO_V
< 0.4V
(1) UVLO_V
> 1.25V
SEC
(1) EXTERNAL SOFT-STOP SHUTDOWN
(2) SYSTEM INPUT UVLO
SEC
(2) OVLO > 1.25V
(3) HFB < 0.92V
(4) OC > 96mV
(2) OVLO < 1.215V
(3) HFB > 0.96V
(4) OC < 96mV
(5) INTV < X, > 16.5V
(5) X < INTV < 16V
CC
CC
(6) T > 170°C
(6) T < 165°C
J
J
(7) V < Y
IN
(7) V > Y
IN
(X = 4.6V, Y = 5.5V: LT3752)
(X = 6.8V, Y = 7.6V: LT3752-1)
(X = 4.75V, Y = 5.8V: LT3752)
(Y = 7.0V, Y = 9.5V: LT3752-1)
HARD
STOP
SS1 SOFT STARTS
SS1 SOFT STOPS
f , D AND COMP
OSC VSEC
f
AND D
OSC
VSEC
2.6V
SS1 LATCH
RESET THRESHOLD
SS1
1.25V
0.15V
0V
0V
0V
2.6V
SS2 SOFT STARTS
COMP
SS2
0.25V
2.6V
COMP
RANGE
COMP 1.25V
SWITCHING THRESHOLD
COMP
1V
3752 F18
Figure 18. SS1, SS2 and COMP Pin Voltages During Faults, Soft-Start and Soft-Stop
ing accidentally discharged during missing OUT pulses
In order to ensure the active clamp switch controlled by
AOUTdoesnotstayontoolong,theLT3752/LT3752-1have
an internal 15µs timeout to turn off the AOUT signal. This
prevents the active clamp capacitor from being connected
across the transformer primary winding long enough to
create reverse saturation.
and/or causing reverse saturation of the transformer.
For SOUT control, this prevents the secondary side syn-
chronous rectifier controller from incorrectly switching
between forward FET and synchronous FET conduction.
The LT3752/LT3752-1 correctly re-establish the required
AOUT, SOUT control signals if the OUT signal is required
for the next cycle.
Main Transformer Selection
The LT3752/LT3752-1 simplify the design of the main
transformer and output inductor by removing the need for
any auxiliary windings. Any bootstrap supplies required
for the primary side or bias supplies required for the
secondary side can all be provided by the housekeeping
DC/DC controller included in the LT3752/LT3752-1. (see
Housekeeping Controller in the Applications Information
Section).
AOUT Timeout
During converter start-up in soft-start, the switching fre-
quency and maximum duty cycle clamp D
folded back. While this correctly reduces the effective
minimumontimeoftheOUTpin(toallowcontrolofinduc-
tor current for very low output voltages during start-up),
this means the AOUT pin on time duration can be large.
are both
VSEC
3752fb
38
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APPLICATIONS INFORMATION
The selection of the main transformer will depend on the
applications requirements : isolation voltage, power level,
maximumvolt-seconds,turnsratio,componentsize,power
losses and switching frequency.
density. After calculating N , the number of primary turns
S
(N ) can be calculated from,
P
N = N • D
V
/V
P
S
MAX IN(MIN) OUT
where,
Transformerconstructionusingtheplanarwindingtechnol-
ogy is typically chosen for minimizing leakage inductance
and reducing component height. Transformer core type is
usually a ferrite material for high frequency applications.
V
= minimum system input voltage
IN(MIN)
D
MAX
=maximumswitchdutycycleatV
(typically
IN(MIN)
chosen between 0.6 and 0.7)
At minimum input voltage the converter will run at a maxi-
mum duty cycle D . A higher transformer turns ratio
Find a family of transformers that meet both the isolation
and power level requirements of the application. The next
step is to find a transformer within that family which is
suitable for the application. The subsequent thought pro-
cess for the transformer design will include :
MAX
(N /N ) will create a higher D but it will also require
P
S
MAX
higher voltages at the drain of the primary side switch to
resetthetransformer(seeprevioussectionsLosideActive
ClampTopologyandHisideActiveClampTopology).D
(1)Secondary turns (N ), core losses, temperature
MAX
S
values are typically chosen between 0.6 and 0.7. Even for
rise, flux density, switching frequency
a given D
value, the loop must also provide protection
MAX
(2)Primary turns (N ), maximum duty cycle and reset
P
against duty cycles that may excessively exceed D
MAX
voltages
during transients or faults. While most converters only
(3)Copper losses
provide a fixed duty cycle clamp, the LT3752/LT3752-1
provideaprogrammablemaximumdutycycleclampD
that also moves inversely with input voltage.
VSEC
The expression for secondary turns (N ) is given by,
S
8
N = 10 V /(f
• A • B )
C M
S
OUT OSC
The resulting function is that of a programmable volt-
secondclamp.Thisallowstheusertochooseatransformer
where,
2
turns ratio for D
and then customize a maximum duty
MAX
A = cross-sectional area of the core in cm
C
cycle clamp D
above D
for safety. D
then
VSEC
MAX
VSEC
B = maximum AC flux density desired
M
follows the natural duty cycle of the converter as a safety
guardrail (see previous section Programming Duty Cycle
Clamp).
For flux density, choose a level which achieves an accept-
ablelevelofcoreloss/temperatureriseatagivenswitching
frequency. The transformer data sheet will provide curves
of core loss versus flux density at various switching fre-
quencies.Thedatasheetwillalsoprovidetemperaturerise
versus core loss. While choosing a value for BM to avoid
excessivecorelosseswillusuallyallowenoughheadroom
for flux swing during input / load transients, still make
sure to stay well below the saturation flux density of the
Afterdecidingontheparticulartransformerandturnsratio,
the copper losses can then be approximated by,
2
2
P
= D • I(Load)
(R
+ (N /N ) R
)
PRI
CU
(MAX)
SEC
S
P
where,
D = switch duty cycle (choose nominal 0.5)
I(Load) = maximum load current
transformer core. If needed, increasing N will reduce flux
S
(MAX)
3752fb
39
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
R
PRI
= primary winding resistance
perature is known. A final value for R
CONDUCTION
and therefore
DS(ON)
P
can be achieved from a few iterations.
R
= secondary winding resistance
SEC
(ii) P
= (Q • INTV • f
)
GATEDRIVER
G
CC OSC
If there is a large difference between the core losses and
the copper losses then the number of secondary turns
can be adjusted to achieve a more suitable balance. The
number of primary turns should then be recalculated to
maintain the desired turns ratio.
where,
Q = gate charge (V = INTV )
G
GS
CC
(iii) P
= P
+ P
(≈ 0 if ZVS)
TRANSITION
TURN_OFF
TURN_ON
(a) P
= (1/2)I
OSC
(N /N )(V /1-D)
OUT(MAX) S P IN
TURN_OFF
Primary-Side Power MOSFET Selection
(Q /I
) • f
GD GATE
Theselectionoftheprimary-sideN-channelpowerMOSFET
M1 is determined by the maximum levels expected for the
drain voltage and drain current. In addition, the power
losses due to conduction losses, gate driver losses and
transition losses will lead to a fine tuning of the MOSFET
selection. If power losses are high enough to cause an
unacceptabletemperatureriseintheMOSFETthenseveral
MOSFETs may be required to be connected in parallel.
where,
Q
GD
= gate to drain charge
I
= 2A source/sink for OUT pin gate driver
GATE
(b)P
=(1/2)I
(N /N )(V )(Q /I
)
TURN_ON
OSC
OUT(MAX)
S
P
DS
GD GATE
• f
where,
The maximum drain voltage expected for the MOSFET M1
follows from the equations previously stated in the active
clamp topology sections:
V
V
= M1 drain voltage at the beginning of M1 turn on
DS
typically sits between V and 0V (ZVS)
DS
IN
Duringprogrammabletimingt ,negativeI
discharges
2
AO
MAG
V
DS
(M1) = V /(V – (V
• N))
IN
IN
OUT
M1 drain SWP towards V (Figure 1). ZVS is achieved if
IN
The MOSFET should be selected with a BV
rating ap-
enough leakage inductance exists—to delay the second-
DSS
proximately 20% greater than the above steady state V
ary side from clamping M1 drain to V —and if enough
DS
IN
calculationduetotolerancesindutycycle, loadtransients,
energy is stored in L
to discharge SWP to 0V during
MAG
voltage ripple on C and leakage inductance spikes. A
thatdelay.(seeProgrammingActiveClampSwitchTiming:
CL
MOSFET with the lowest possible voltage rating for the
application should be selected to minimize switch on re-
sistance for improved efficiency. In addition, the MOSFET
should be selected with the lowest gate charge to further
minimize losses.
AOUT to OUT (t )).
AO
Synchronous Control (SOUT)
The LT3752 / LT3752-1 use the SOUT pin to communicate
synchronous control information to the secondary side
synchronous rectifier controller (Figure 19). The isolating
transformer(T
tiveload(R
to generate positive and negative signals required at the
SYNC input of the secondary side synchronous rectifier
controller. For the typical LT3752/LT3752-1 applications
operating with an LT8311, C
and T
MOSFET M1 losses at maximum output current can be
approximated as :
),couplingcapacitor(C
)andresis-
SYNC
SYNC
)allowthegroundreferencedSOUTsignal
SYNC
P
M1
= P
+ P
+ P
CONDUCTION
GATEDRIVER TRANSITION
(i) P
I
= (N /N ) • (V /V ) • (N /N •
P S OUT IN S P
DS(ON)
CONDUCTION
2
) • R
OUT(MAX)
is 220pF, R
is 560Ω
SYNC
SYNC
Note: The on resistance of the MOSFET, R
, in-
DS(ON)
DS(ON)
is typically a PULSE PE-68386NL.
SYNC
creases with the MOSFET’s junction temperature. R
should therefore be recalculated once junction tem-
3752fb
40
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
C
TheLT3752/LT3752-1allowverylarge∆I values(lowL
SYNC
L
OUT
220pF
T
values) without the worry of insufficient slope compensa-
SYNC
1
2
3
6
5
4
SOUT
(LT3752/LT3752-1)
SYNC
(SECONDARY SIDE
CONTROLLER)
•
•
•
•
tion—byallowingslopecompensationtobeprogrammed
R
SYNC
560Ω
with an external resistor in series with the I
pin (see
SENSEP
CurrentSensingandProgrammableSlopeCompensation).
3752 F19
Larger∆I willallowlowerL ,reducingcomponentsize,
L
OUT
Figure 19. SOUT Pulse Transformer
but will also cause higher output voltage ripple and core
losses. For LT3752/LT3752-1 applications, ∆I is typically
L
Typically choose C
between 220pF and 1nF. R
SYNC
SYNC
chosen to be 40% of I
.
OUT(MAX)
should then be chosen to obey :
Output Capacitor Selection
(1) SOUT
/100mA ≤ R
≤ √(L
/C
)
MAX
SYNC
MAG SYNC
The choice of output capacitor value is dependent on
output voltage ripple requirements given by :
where,
SOUT
= INTV
MAX
CC
∆V
≈ ∆I (ESR + (1/(8 • f
• C ))
OSC OUT
OUT
L
L
MAG
= T
magnetizing inductance
SYNC’S
where,
∆I = output inductor ripple current I
100mA = SOUT gate driver minimum source current
and
(2) R
L
L(RIPPLE)(P-P)
ESR = effective series resistance (of C
)
OUT
• C
≥ (–1) • Y/(ln (Z/SOUT
))
SYNC
SYNC
MAX
f
= switching frequency
= output capacitance
OSC
where,
C
OUT
Y = SYNC minimum pulse duration (50ns; LT8311)
Z = |SYNC level to achieve Y| ( 2V: LT8311)
This gives:
= ∆I /(8 • f
C
• ( ∆V – ∆I • ESR))
OUT L
OUT
L
OSC
Even though the LT3752/LT3752-1 INTV pin is allowed
CC
TypicallyC ismadeupofalowESRceramiccapacitor(s)
OUT
to be over driven by as much as 15.4V using the house-
to minimize ∆V . Additional bulk capacitance is added
OUT
keeping supply, SOUT
level should be designed to not
MAX
in the form of electrolytic capacitors to minimize output
cause T
output to exceed the maximum ratings of the
SYNC
voltage excursions during load steps.
LT8311’s SYNC pin.
Cost/Space reduction : If discontinuous conduction mode
(DCM) operation is acceptable at light load, the LT8311
has a preactive mode which controls the synchronous
Input Capacitor Selection
The active clamp forward converter demands pulses of
current from the input due to primary winding current and
magnetizing current. The input capacitor is required to
providehighfrequencyfilteringtoachieveaninputvoltage
as close as possible to a pure DC source with low ripple
voltage. For low impedance input sources and medium to
low voltage input levels, a simple ceramic capacitor with
low ESR should suffice. It should be rated to operate at a
worst case RMS input current of :
MOSFETs without T
, C
, R
or the LT3752/
SYNC SYNC
SYNC
LT3752-1 timing resistors R , R
(leave open).
TAS TOS
Output Inductor Value
The choice of output inductor value L
will depend on
OUT
theamountofallowableripplecurrent. Theinductorripple
current is given by:
I
L(RIPPLE)(P-P)
I
= (N /N ) I
/2
CIN(RMS)
S
P
OUT(MAX)
= ∆I = (V /(L
• f )) • (1 – (V /V )(N /N ))
OUT IN P S
L
OUT OUT OSC
3752fb
41
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
A small 1µF bypass capacitor should also be placed close
3.Thecurrentsenseresistorfortheforwardconvertermust
useshortKelvinconnectionstotheI andI
SENSEN
to the IC between V and GND.
IN
SENSEP
pins. The current sense resistor for the housekeeping
supply should have it’s ground connection as close as
possible to the power ground (PGND) pin 38.
Asinputvoltagelevelsincrease,anyuseofbulkcapacitance
to minimize input ripple can impact on solution size and
cost. Inaddition, inputswithhighersourceimpedancewill
cause an increase in voltage ripple. In these applications it
is recommended to include an LC input filter. The output
impedance of the input filter should remain below the
negativeinputimpedanceoftheDC/DCforwardconverter.
4. High dv/dt lines should be kept away from all timing
resistors, current sense inputs, HCOMP/COMP pins,
UVLO_VSEC/OVLO pins and both HFB and FB feedback
traces.
5. Gate driver traces (HOUT, AOUT, SOUT, OUT) should be
kept as short as possible.
PCB Layout / Thermal Guidelines
For proper operation, PCB layout must be given special
attention. Critical programming signals must be able to
co-exist with high dv/dt signals. Compact layout can be
achieved but not at the cost of poor thermal management.
The following guidelines should be followed to approach
optimal performance.
6. When working with high power components, multiple
parallel components are the best method for spread-
ing out power dissipation and minimizing temperature
rise. In particular, multiple copper layers connected
by vias should be used to sink heat away from each
power MOSFET.
1. Ensure that a local bypass capacitor is used (and placed
7. Keep high switching current PGND paths away from
signal ground. Also minimize trace lengths for those
high current switching paths to minimize parasitic
inductance.
as close as possible) between V and GND for the
IN
controller IC(s).
2. The critical programming resistors for timing (pins
T ,T ,T ,T ,IVSECandRT)mustuseshorttraces
AO AS OS BLNK
to each pin. Each resistor should also use a short trace
toconnecttoasinglegroundbusspecificallyconnected
to pin 18 of the IC (GND).
3752fb
42
For more information www.linear.com/LT3752
LT3752/LT3752-1
APPLICATIONS INFORMATION
V
OUT
12V
V
IN
18V TO 72V
T1
L1
12.5A
C1
T2
INTV
V
AUX
4:4
CC
6.8µH
+
C14
470µF
16V
4.7µF
100V
×3
•
•
R38
20k
D2
D3
•
•
C9
2.2µF
C10
2.2µF
D4
•
C8
C13
15nF
ZVN4525E6
M5
C24
2.2nF
250V
BSC077N12NS3
C7
100nF
22µF
16V
×2
FDMS86101
Si2325DS
D1
M4
M2
M3
R17
R18
0.15Ω
R16
10k
499Ω
R21
100Ω
R22
100Ω
BSC077N12NS3
M1
HOUT HI
AOUT
V
SENSE
OUT
OC
IN
V
V
IN
AUX
C11
2.2µF
R1
C28
68pF
SYNC
R30
R27
100k
I
SENSEP
100k
GND
R14
2k
100k
R15
0.006Ω
UVLO_V
SEC
LT8311
FB
PGOOD
R2
5.9k
R31
T3
SYNC
I
SENSEN
SOUT
11.3k
LT3752
•
•
C6 220pF
OVLO
GND
R13
560Ω
R3
1.82k
INTV
CC
V
INTV
AUX
CC
R28
3.16k
C17
220nF
R20
499k
R11
10k
R25
100Ω
C5
4.7µF
C16
1µF
R29
13.7k
C12
4.7µF
C18
68pF
PS2801-1
2.2nF
C19
4.7nF
HFB
R12
1.1k
R5
22.6k
R4
R7
R9
31.6k
R8
C3
R10
2.8k
C4
3752 F20a
34k
22nF
C2
0.33µF
R24
100k
R6
7.32k
R23
100k
R26
1k
22nF
49.9k
71.5k
T1: CHAMPS G45AH2-0404-04
T2: BH ELECTRONICS L00-3250
T3: PULSE PE-68386NL
L1: CHAMPS PQI2050-6R8
D1, D2, D3: BAS516
D4: CENTRAL SEMI CMMR1U-02
Efficiency vs Load Current
96
94
92
90
88
86
24V
48V
72V
IN
IN
IN
0
3
6
9
12
15
LOAD CURRENT (A)
3752 F20b
Figure 20. 18V to 72V, 12V/12.5A, 150W Active Clamp Isolated Forward Converter
3752fb
43
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL APPLICATIONS
18V to 72V, 12V/12.5A, 150W No-Opto, Active Clamp Isolated Forward Converter
V
OUT
V
IN
18V TO 72V
12V
T1
L1
12.5A
T2
C1
INTV
V
AUX
4:4
CC
6.8µH
+
C14
470µF
16V
4.7µF
100V
×3
•
•
R38
20k
D2
D3
•
•
C9
2.2µF
C10
2.2µF
D4
•
C8
15nF
C13
22µF
16V
×2
C24
2.2nF
250V
BSC077N12NS3
C7
100nF
FDMS86101
Si2325DS
D1
M5 ZVN4525E6
M4
M2
M3
R17
R18
0.15Ω
R16
10k
499Ω
R21
100Ω
R22
100Ω
BSC077N12NS3
M1
HOUT HI
AOUT
V
SENSE
OUT
OC
IN
V
V
IN
AUX
C11
2.2µF
R1
100k
SYNC
I
SENSEP
GND
R14
2k
R15
UVLO_V
SEC
LT8311
FB
0.006Ω
PGOOD
SYNC
R2
5.9k
T3
I
SENSEN
SOUT
LT3752
•
•
C6 220pF
OVLO
GND
R13
560Ω
R3
1.82k
V
AUX
INTV
INTV
CC
CC
R11
10k
C12
4.7µF
R20
499k
C5
4.7µF
HFB
R12
1.1k
R5
22.6k
R4
R7
R9
31.6k
R8
C3
22nF
C2
R10
2.8k
C4
2.2nF
34k
3752 TA02
R6
7.32k
22nF
49.9k
60.4k
0.33µF
T1: CHAMPS G45AH2-0404-04
T2: BH ELECTRONICS L00-3250
T3: PULSE PE-68386NL
L1: CHAMPS PQI2050-6R8
D1, D2, D3: BAS516
D4: CENTRAL SEMI CMMR1U-02
V
OUT vs Load Current (No-Opto)
Efficiency vs Load Current
14.0
96
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
94
92
90
88
86
V
V
V
V
V
= 70V
= 60V
= 48V
= 36V
= 20V
IN
IN
IN
IN
IN
24V
48V
72V
IN
IN
IN
0
2
4
6
8
10
12
0
3
6
9
12
15
LOAD CURRENT (A)
LOAD CURRENT (A)
3752 TA02a
3752 TA02b
3752fb
44
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W Active Clamp Isolated Forward Converter
T1
V
V
OUT
IN
31:5
150V TO
400V
12V
L1
16.7A
T2
R38
10k
C1
2.2µF
630V
R19
•
•
INTV
CC
V
AUX
INTV
C10
CC
R35
R16 4.2Ω
D4
15µH
+
C14
330µF
16V
C15
10nF
630V
402Ω
•
•
D3
FDMS86200
×3
374k
D2
C9
10µF
4.7µF
C8
47nF
630V
R36
374k
ACPL-W346
•
M4
D5
V
D1
C13
33µF
16V
×4
CC
RJK0653DPB
×2
C24
10nF
250V
M5
BSP300
V
M2
OUT
R38
ANODE
CATHODE
C21
0.22µF
C20
10µF
0.002
M3
R17
R18
0.15Ω
V
EE
499Ω
IPD60R1K4C6
R21
100Ω
R22
100Ω
C27
120pF
R34
IPD65R25OC6
M1
499k
HOUT
HI
SENSE
AOUT
V
OUT
OC
IN
V
AUX
V
IN
C11
2.2µF
C28
68pF
R30
R1
499k
SYNC
R27
100k
I
SENSEP
100k
GND
R14
2k
R15
0.022Ω
FB
UVLO_V
SEC
LT8311
PGOOD
SYNC
R2
5.76k
R31
11.3k
T3
I
SENSEN
SOUT
LT3752-1
•
•
C6 220pF
OVLO
GND
R13
560Ω
R3
2.94k
INTV
CC
V
INTV
CC
AUX
C12
R28
3.16k
C17
1µF
R20
432k
C18
100pF
R29
R11
10k
R25
100Ω
5.11k
C5
4.7µF
PS2801-1
4.7µF
C19
22nF
HFB
R12
806Ω
C16
1µF
C3
R5
40.2k
R4
R7
100k
R6
R9
78.7k
R8
R10
22k
3752 TA03
0.22µF
C2
R24
22k
R23
22k
R26
1.2k
95.3k
13k
124k
0.47µF
C4
3.3nF
2.2nF
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
Efficiency vs Load Current
96
95
94
93
92
91
90
89
88
87
86
85
V
V
V
V
= 150V
= 250V
= 350V
= 400V
IN
IN
IN
IN
0
2.5
5
7.5
10 12.5 15 17.5
LOAD CURRENT (A)
3752 TA03a
3752fb
45
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W No-Opto, Active Clamp Isolated Forward Converter
T1
V
V
OUT
IN
31:5
150V TO
400V
12V
L1
16.7A
C1
2.2µF
630V
T2
R38
10k
R19
•
•
INTV
CC
V
AUX
R16 4.2Ω
CC
R35
15µH
D4
+
C14
330µF
16V
C15
10nF
630V
402Ω
FDMS86200
×3
•
•
D3
INTV
374k
D2
C10
4.7µF
C9
10µF
C8
47nF
630V
D5
ACPL-W346
R36
374k
•
M4
V
D1
C13
33µF
16V
×4
CC
RJK0653DPB
×2
M5
BSP300
C24
10nF
250V
V
M2
OUT
R38
0.002
ANODE
CATHODE
C21
0.22µF
C20
10µF
M3
R17
R18
0.15Ω
V
EE
499Ω
IPD60R1K4C6
R21
100Ω
R22
100Ω
C27
120pF
R34
IPD65R25OC6
M1
499k
HOUT HI
AOUT
V
SENSE
OUT
IN
V
AUX
V
IN
C11
2.2µF
OC
SENSEP
R1
499k
SYNC
I
GND
R14
2k
R15
UVLO_V
OVLO
SEC
LT8311
FB
0.022Ω
PGOOD
SYNC
R2
5.76k
T3
I
SENSEN
SOUT
LT3752-1
•
•
C6 220pF
R13
560Ω
R3
2.94k
V
AUX
INTV
CC
INTV
CC
GND
R11
10k
C12
4.7µF
R20
432k
HFB
C5
4.7µF
R12
806Ω
C3
R5
40.2k
R4
R7
100k
R6
R9
78.7k
R8
R10
22k
C4
3752 TA04
2.2nF
0.22µF
C2
0.47µF
95.3k
13k
107k
3.3nF
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
VOUT vs Load Current (No-Opto)
Efficiency vs Load Current
14.0
96
95
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
94
93
92
91
90
89
88
87
86
85
V
V
V
V
= 150V
= 250V
= 350V
= 400V
V
V
V
V
= 150V
= 250V
= 350V
= 400V
IN
IN
IN
IN
IN
IN
IN
IN
0
2
4
6
8
10 12 14 16 18
0
2.5
5
7.5
10 12.5 15 17.5
LOAD CURRENT (A)
LOAD CURRENT (A)
3752 TA04a
3752 TA04b
3752fb
46
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W, Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
T1
V
V
OUT
IN
31:5
150V TO
400V
12V
L1
D3
16.7A
R19
T2
C15
10nF
630V
•
•
INTV
D5
V
AUX
C10
4.7µF
R35
CC
R38
10k
15µH
+
C14
330µF
16V
402Ω
D4
•
•
FDMS86200
×3
374k
D2
C1
C8
47nF
630V
C9
10µF
2.2µF
630V
R36
374k
•
C22
220nF
M4
C23 3.3nF
T4
C13
33µF
16V
×4
M2
RJK0653DPB
×2
M5
BSP300
C24
10nF
250V
D1
•
•
R38
R16
10k
C20
0.002
C21
470pF
M3
10µF
R17
R18
0.15Ω
R37
100Ω
499Ω
R21
100Ω
R22
100Ω
IPD60R1K4C6
C27
120pF
R34
IPD65R25OC6
M1
499k
HOUT HI
AOUT
V
SENSE
OUT
IN
V
AUX
V
IN
C11
2.2µF
OC
SENSEP
R1
499k
SYNC
R30
100k
R27
100k
C28
68pF
I
GND
R14
2k
R15
0.022Ω
UVLO_V
SEC
LT8311
FB
PGOOD
SYNC
R2
5.76k
T3
R31
I
SENSEN
SOUT
11.3k
LT3752-1
•
•
C6 220pF
OVLO
GND
R13
560Ω
R3
2.94k
INTV
CC
INTV
CC
V
AUX
R28
3.16k
C17
1µF
R20
432k
C18
100pF
R29
R25
100Ω
R11
10k
C12
5.11k
C5
4.7µF
4.7µF
PS2801-1
2.2nF
C19
22nF
HFB
R12
806k
C16
1µF
C3
R5
40.2k
R4
R7
100k
R6
R9
R10
3752 TA05
0.22µF
78.7k
R8
22k
R24
22k
C2
0.47µF
R23
22k
R26
1.2k
95.3k
13k
124k
C4
3.3nF
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
Efficiency vs Load Current
96
95
94
93
92
91
90
89
88
87
86
85
V
V
V
V
= 150V
= 250V
= 350V
= 400V
IN
IN
IN
IN
0
2.5
5
7.5
10 12.5 15 17.5
LOAD CURRENT (A)
3752 TA05a
3752fb
47
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A 200W, No-Opto, Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
T1
V
V
OUT
IN
31:5
150V TO
400V
12V
L1
D3
16.7A
R19
T2
R38
10k
C15
10nF
630V
•
•
INTV
D5
V
AUX
C10
4.7µF
R35
CC
D4
15µH
+
C14
330µF
16V
402Ω
FDMS86200
×3
•
•
374k
D2
C1
C8
47nF
630V
C9
10µF
2.2µF
630V
R36
374k
•
M4
C22
220nF
C23 3.3nF
T4
C13
33µF
16V
×4
M2
RJK0653DPB
×2
C24
10nF
250V
M5
BSP300
R38
D1
•
•
R16
10k
0.002Ω
C20
C21
470pF
M3
10µF
R17
R18
0.15Ω
R37
100Ω
499Ω
R21
100Ω
R22
100Ω
C27
120pF
IPD60R1K4C6
R34
IPD65R25OC6
499k
HOUT HI
AOUT
V
SENSE
OUT
M1
IN
V
V
AUX
IN
C11
2.2µF
OC
SENSEP
R1
499k
SYNC
I
GND
R14
2k
R15
UVLO_V
SEC
LT8311
FB
0.022Ω
PGOOD
SYNC
R2
5.76k
T3
I
SENSEN
SOUT
LT3752-1
•
•
C6 220pF
OVLO
GND
R13
R3
2.94k
560Ω
3752 TA06
V
INTV
CC
AUX
R11
10k
R20
432k
C12
4.7µF
2.2nF
HFB
C5
4.7µF
R12
806Ω
C3
R5
40.2k
R4
R7
100k
R6
R9
R10
22k
C4
3.3nF
0.22µF
C2
78.7k
R8
95.3k
13k
107k
0.47µF
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
VOUT vs Load Current (No-Opto)
Efficiency vs Load Current
14.0
96
95
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
94
93
92
91
90
89
88
87
86
85
V
V
V
V
= 150V
= 250V
= 350V
= 400V
V
V
V
V
= 150V
= 250V
= 350V
= 400V
IN
IN
IN
IN
IN
IN
IN
IN
0
2
4
6
8
10 12 14 16 18
0
2.5
5
7.5
10 12.5 15 17.5
LOAD CURRENT (A)
LOAD CURRENT (A)
3752 TA06a
3752 TA06b
3752fb
48
For more information www.linear.com/LT3752
LT3752/LT3752-1
TYPICAL APPLICATIONS
75V to 150V, 24V/14A 340W Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
T1
V
V
24V
14A
IN
OUT
10:6
75V TO
150V
L1
D3
R19
T2
C15
4.7nF
250V
•
•
INTV
D5
V
AUX
C10
4.7µF
R35
CC
R38
10k
15µH
+
C14
470µF
25V
1k
D4
•
•
102k
D2
C1
IPB072N15N3G
C8
15nF
250V
M2
IRFL214
C9
10µF
2.2µF
250V
R36
102k
•
C22
220nF
M4
C23 3.3nF
T4
C13
BSC047N08NS3
×2
M5
BSP300
C24
10nF
250V
22µF
25V
×4
D1
•
•
R38
R16
10k
C20
0.003Ω
C21
470pF
M3
10µF
R17
R18
0.15Ω
R37
100Ω
499Ω
R21
100Ω
R22
100Ω
C27
120pF
R34
IPB200N25N3
M1
698k
HOUT HI
AOUT
V
SENSE
OUT
IN
V
AUX
V
IN
C11
2.2µF
OC
SENSEP
R1
6.98k
C28
68pF
SYNC
R30
100k
R27
100k
I
GND
R14
2k
R15
0.0075Ω
UVLO_V
SEC
LT8311
FB
PGOOD
SYNC
R2
6.04k
T3
R31
I
SENSEN
SOUT
5.36k
LT3752-1
•
•
C6 220pF
OVLO
GND
R13
560Ω
R3
5.76k
INTV
CC
V
INTV
CC
AUX
C17
R28
3.16k
C18
100pF
R29
0.33µF
R25
100Ω
C12
4.7µF
5.11k
R11
10k
C5
4.7µF
R20
365k
PS2801-1
2.2nF
C19
22nF
HFB
R12
806Ω
C16
1µF
C3
R5
53k
R4
93.1k
R7
80.1k
R6
R9
R10
3752 TA07
0.22µF
C2
52.3k
R8
22k
R24
22k
R23
22k
R26
1.2k
10k
82.5k
0.47µF
C4
3.3nF
T1: CHAMPS LT80R2-12AC-1006
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
Efficiency vs Load Current
96
95
94
93
92
91
90
89
88
87
86
V
V
V
V
= 75V
IN
IN
IN
IN
= 100V
= 125V
= 150V
0
2.5
5
7.5
10
12.5
15
LOAD CURRENT (A)
3752 TA07a
3752fb
49
For more information www.linear.com/LT3752
LT3752/LT3752-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
Package Variation: FE38 (31)
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1665 Rev B)
Exposed Pad Variation AB
4.75 REF
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
REF
38
20
6.60 0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
REF (.252)
BSC
2.74
(.108)
0.315 0.05
1.05 0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED
19
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.50
(.0196)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.17 – 0.27
(.0067 – .0106)
TYP
FE38 (AB) TSSOP REV B 0910
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
3752fb
50
For more information www.linear.com/LT3752
LT3752/LT3752-1
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
06/14 Minor typographical changes throughout data sheet.
All
B
07/15 Changed Absolute Maximum SS2 rating to 16V.
Changed Absolute Maximum SS1 rating to 3V.
3
3
3
5
6
6
6
7
Changed Output Low Level in Shutdown conditions to INTV = 3V.
CC
Changed AOUT Rise and Fall Times.
Changed SOUT Rise and Fall Times.
Changed SS2 Discharge Current conditions to SS2 = 2.5V.
Changed SS2 Charge Current conditions to SS2 = 1.5V.
Changed HOUT Rise and Fall Times.
3752fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
51
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3752/LT3752-1
TYPICAL APPLICATION
75V to 150V, 24V/14A 340W No-Opto, Active Clamp Isolated Forward Converter
T1
L1, 15µH
D4
V
V
24V
14A
IN
OUT
10:6
75V TO
150V
D3
C15
4.7nF
250V
R19
1k
C8
R38
10k
T2
•
•
INTV
D5
V
AUX
C10
4.7µF
CC
R35
R36
+
C14
470µF
25V
•
•
D2
IPB072N15N3G
C1
2.2µF
250V
C9
10µF
C24
10nF
250V
15nF
•
M4
C22
220nF
C23 3.3nF
T4
250V
M2
IRFL214
BSC047N08NS3
×2
C13
M5
BSP300
R38
0.003Ω
22µF
25V
×4
D1
•
•
R16
10k
C20
C21
470pF
M3
10µF
R17
R18
0.15Ω
R37
100Ω
499Ω
R21
R22
100Ω
C27
120pF
100Ω
R34
IPB200N25N3
M1
698k
HOUT HI
AOUT
V
SENSE
OUT
IN
V
V
AUX
IN
C11
OC
SENSEP
R1
6.98k
SYNC
I
2.2µF
GND
R14
2k
R15
UVLO_V
SEC
LT8311
FB
0.0075Ω
PGOOD
SYNC
R2
6.04k
T3
I
SENSEN
SOUT
LT3752-1
•
•
C6 220pF
OVLO
GND
R13
R3
5.76k
560Ω
3752 TA08
INTV
INTV
C5
CC
CC
C12
4.7µF
R11
10k
R20
432k
2.2nF
HFB
R12
806Ω
4.7µF
R5
53k
R4
93.1k
R7
80.1k
R6
R9
C3
0.1µF
C2
R10
22k
C4
3.3nF
52.3k
R8
75k
10k
0.47µF
T1: CHAMPS LT80R2-12AC-1006
T2: WÜRTH 750817020
VOUT vs Load Current (No-Opto)
Efficiency vs Load Current
T3: PULSE PE-68386NL
28
96
95
94
93
92
91
90
89
88
87
86
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
27
26
25
24
23
22
21
20
D4: CENTRAL SEMI CMMR1U-02
V
V
V
V
= 75V
V
V
V
V
= 75V
IN
IN
IN
IN
IN
IN
IN
IN
= 100V
= 125V
= 150V
= 100V
= 125V
= 150V
0
2
4
6
8
10 12 14 16
0
2.5
5
7.5
10
12.5
15
LOAD CURRENT (A)
LOAD CURRENT (A)
3752 TA08a
3752 TA08b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT8311
Preactive Secondary Synchronous and
Opto Control for Forward Converters
Optimized for Use with Primary-Side LT3752/-1, LT3753 and LT8310 Controllers
LTC3765/LTC3766
Synchronous No-Opto Forward Controller
Chip Set with Active Clamp Reset
Direct Flux Limit, Supports Self Starting Secondary Forward Control
LTC3722/LTC3722-2
Synchronous Full Bridge Controllers
Adaptive or Manual Delay Control for Zero Voltage Switching, Adjustable
Synchronous Rectification Timing
LT3748
LT3798
100V Isolated Flyback Controller
5V ≤ V ≤ 100V, No Opto Flyback , MSOP-16 with High Voltage Spacing
IN
Off-Line Isolated No-Opto Flyback
Controller with Active PFC
V
IN
and V
Limited Only by External Components
OUT
3752fb
LT 0715 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
52
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT3752
●
●
LINEAR TECHNOLOGY CORPORATION 2014
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