LT3755-1 [Linear]
32-Channel 20mA LED Driver with Buck Controller 0.5μs Minimum LED On Time; 32通道20毫安LED驱动器，降压控制器0.5μs的最小LED导通时间
| 型号： | LT3755-1 |
| 厂家： | 
Linear |
| 描述： | 32-Channel 20mA LED Driver with Buck Controller 0.5μs Minimum LED On Time |
| 文件： | 总28页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3746
32-Channel 20mA LED
Driver with Buck Controller
FeaTures
DescripTion
The LT®3746integratesa32-channelLEDdriverwitha55V
buck controller. The LED driver lights up to 30mA/13V of
LEDs in series per channel, and the buck controller gener-
ates an adaptive bus voltage supplying the parallel LED
strings. Each channel has individual 6-bit dot correction
current adjustment and 12-bit grayscale PWM dimming.
Both dot correction and grayscale are accessible via a
serial data interface in TTL/CMOS logic.
n
6V to 55V Power Input Voltage Range
n
32 Independent LED Outputs up to 30mA/13V
n
6-Bit Dot Correction Current Adjustment
n
12-Bit Grayscale PWM Dimming
0.5µs Minimum LED On Time
n
n
Adaptive LED Bus Voltage for High Efficiency
n
Cascadable 30MHz Serial Data Interface
n
Full Diagnostic and Protection: Individual Open/Short
LED and Overtemperature Fault
The LT3746 performs full diagnostic and protection
against open/short LED and overtemperature fault. The
fault status is sent back through the serial data interface.
The 30MHz fully-buffered, skew-balanced, cascadable
serial data interface makes the chip extremely suitable
for large screen LCD dynamic backlighting and mono-,
multi-, full-color LED displays.
applicaTions
n
Large Screen Display LED Backlighting
n
Mono-, Multi-, Full-Color LED Displays
n
LED Billboards and Signboards
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
32-Channel LED Driver, 1MHz Buck, 3 LEDs 10mA to 30mA per Channel, 500Hz 12-Bit Dimming
V
IN
13V TO 42V
0.47µF
4.7µF
V
CAP
GATE
IN
EN/UVLO
EN
22µH
33mΩ
100k
V
CC
3V TO 5.5V
V
CC
80.6k
C1
10µF
SYNC
GND
2 × 47µF
RT
SS
ISP
ISN
LT3746
10k
46.4k
60.4k
10nF
FB
I
SET
LED00
LED01
T
SET
32.4k
LED02
.
.
.
2.048MHz CLOCK
PWMCK
LED29
LED30
LED31
SCKI
SDI
SCKO
SDO
TTL/CMOS
TTL/CMOS
LDI
LDO
3746 TA01
3746f
1
LT3746
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V
.......................................................................... 57V
IN
CAP......................................................... V – 8V to V
IN
IN
GATE..............................................................CAP to V
IN
56 55 54 53 52 51 50 49 48 47
LED00 to LED31, ISP, ISN.........................................13V
ISP.................................................ISN – 1V to ISN + 1V
EN/UVLO
LED15
LED14
LED13
LED12
LED11
LED10
LED09
LED08
1
2
3
4
5
6
7
8
9
46 SYNC
45 LED16
LED17
44
FB, RT, T , I ....................................................... 2V
SET SET
LED18
43
42 LED19
LED20
V ...............................................................–0.3V to 6V
CC
SCKI, SCKO, SDI, SDO, LDI, LDO, PWMCK, SYNC,
41
SS, EN/UVLO ............................................. –0.3V to V
Operating Junction Temperature Range
CC
40 LED21
39 LED22
38 LED23
37 LED24
36 LED25
35 LED26
34 LED27
33 LED28
32 LED29
31 LED30
30 LED31
29 GND
(Notes 2, 3)............................................–40°C to 125°C
Storage Temperature Range ..................–65°C to 125°C
57
GND
LED07 10
LED06 11
LED05 12
LED04 13
LED03 14
LED02 15
LED01 16
LED00 17
GND 18
19 20 21 22 23 24 25 26 27 28
UHH PACKAGE
56-LEAD (5mm × 9mm) PLASTIC QFN
T
= 125°C, θ = 32°C/W, θ = 2.0°C/W
JA JC
JMAX
EXPOSED PAD (PIN 57) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LT3746EUHH#PBF
LT3746IUHH#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3746EUHH#TRPBF
LT3746IUHH#TRPBF
3746
3746
56-Lead (5mm × 9mm) Plastic QFN
56-Lead (5mm × 9mm) Plastic QFN
–40°C to 125°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3746f
2
LT3746
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V,
VISP = VISN = 0V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
V
V
Operating Voltage
Supply Current
6
55
V
IN
IN
IN
I
V
= 0V
EN/UVLO
0.2
0.4
2
0.55
µA
mA
VIN
No Switching
V
V
V
Operating Voltage
3
5.5
V
CC
CC
CC
I
Supply Current (Note 4)
V
= 0V
EN/UVLO
0.1
3.3
10
1
3.8
µA
mA
mA
mA
VCC
LED Channel Off, 30MHz Data Off
LED Channel On, 30MHz Data Off
LED Channel On, 30MHz Data On
19
Undervoltage Lockout (UVLO)
UVLO Threshold
V
V
V
Rising
Falling
2.82
2.61
2.89
2.68
2.96
2.75
V
V
CC
CC
CC
EN/UVLO Shutdown Threshold
UVLO Threshold
I
<20µA
0.35
1.28
1.19
V
V
V
VCC
V
V
Rising
1.31
1.22
1.34
1.25
EN/UVLO
EN/UVLO
Falling
I
EN/UVLO Bias Current
V
= V
0.1
1
µA
EN/UVLO
EN/UVLO
CC
(V – V ) UVLO Threshold
(V – V ) Rising
4.6
4.1
4.9
4.4
5.2
4.7
V
V
IN
CAP
IN
CAP
(V – V ) Falling
IN
CAP
Soft Start (SS)
I
Soft Start Charge Current
Soft Start Discharge Current
Soft Start Reset Threshold
V
V
= 1V
SS
–16
–12
330
0.35
–8
µA
µA
V
SS
= V , V
= 1V
SS
CC EN/UVLO
V
SS(TH)
Oscillator
V
RT Pin Voltage
1.186
1.205
–80
1.224
V
RT
I
f
RT Pin Current Limit
Oscillator Frequency
V
= 0V
µA
RT
RT
R = 280k, V = 12V
196
490
1000
208
515
1050
220
540
1100
kHz
kHz
kHz
OSC
T
T
T
IN
IN
IN
R = 105k, V = 12V
R = 46.4k, V = 12V
f
Sync Frequency Range (Note 5)
R = 348k, V = 12V
200
1000
kHz
SYNC
T
IN
SYNC LOGIC
High Level Voltage
Low Level Voltage
V
= 12V, V = 3V to 5.5V
CC
IN
2.4
0
V
V
V
CC
0.6
Error Amplifiers and Loop Dynamics
l
V
FB Regulation Voltage
FB Input Bias Current
LED Regulation Voltage
Minimum GATE Off Time
Minimum GATE On Time
V
V
V
V
= V = 5V
1.186
0.44
1.210
–120
0.54
120
1.234
0.64
V
nA
V
FB
ISP
ISP
ISP
ISN
I
= V = 5V, V Regulated
ISN FB
FB
= V = 5V, V = 1V
ISN
FB
T
T
= 12V, V = V = 5V, V = 1V
ns
ns
OFF(MIN)
ON(MIN)
IN
ISP
ISN
FB
V
V
= 12V, (V – V ) = 60mV, V = 5V,
200
IN
FB
ISP
ISN
ISN
= 1V
Current Sense Amplifier
ISP/ISN Pin Common Mode
to ISN Dropout Voltage (V – V
l
l
V
V
V
= V
0
13
2
V
V
ISP
ISN
V
)
= 12V, V = V , V = 1V
1.7
46.5
–23
–48
IN
IN
ISN
IN
ISP
ISN FB
Current Limit Sense Threshold (V – V
)
= 1V
34
59
mV
µA
µA
ISP
ISN
FB
I
I
ISP Input Bias Current
ISN Input Bias Current
ISP
ISN
3746f
3
LT3746
The l denotes the specifications which apply over the full operating
elecTrical characTerisTics
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V,
VISP = VISN = 0V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Driver
V
CAP Bias Voltage (V – V
)
7V < V < 55V
6.54
6.77
22
7.00
V
mA
V
BIAS
CAP
IN
CAP
IN
I
CAP Bias Current Limit
(V – V ) = V
– 0.5V
BIAS
IN
CAP
GATE High Level (V – V
)
I
I
= –100mA
0.4
0.3
30
IN
GATE
GATE
GATE
GATE Low Level (V
GATE Rise Time
GATE Fall Time
– V
)
CAP
= 100mA
V
GATE
C
C
= 3.3nF to V , V = 12V
ns
ns
GATE
GATE
IN IN
= 3.3nF to V , V = 12V
30
IN IN
LED Driver
l
l
V
Trimmed I
Pin Voltage
SET
1.181
0
1.205
1.229
13
V
V
ISET
LEDxx Operating Voltage
LEDxx Leakage Current
V
= V = V
ISP ISN LEDxx
LED Channel Off, V = V = 5V,
V
0.2
µA
ISP
ISN
= 3V
LEDxx
I
LED Constant Sink Current
V
= V = 5V, V
= 0.5V
LED
ISP
ISN
LEDxx
REG = 0x00
7
15
23
10.5
20.5
30
14
26
37
mA
mA
mA
DC
REG = 0x20
DC
REG = 0x3F
DC
∆I
∆I
∆I
∆I
Current Mismatch Between Channels
Current Mismatch Between Devices
LED Current Line Regulation
V
= V = 5V, V
DC
= 0.5V,
= 0.5V,
= 0.5V,
8
15
20
0.7
2
%
LEDC
LEDD
LINE
ISP
ISN
LEDxx
REG = 0x20 (Note 6)
V
= V = 5V, V
LEDxx
–15
–0.2
–1
5
%
ISP
ISN
REG = 0x20 (Note 7)
DC
V
= V = 5V, V
LEDxx
0.2
0.7
%/V
%/V
ISP
ISN
REG = 0x20, V = 3V to 5.5V (Note 8)
DC
CC
LED Current Load Regulation
V
V
= V = 5V, REG = 0x20,
ISP ISN DC
LOAD
= 0.5V to 2.5V (Note 9)
LEDxx
V
V
Open LED Threshold
Short LED Threshold
Minimum LED On Time
V
V
V
V
= V = 5V, V
Falling
Rising
0.1
3.9
0.5
V
V
OPEN
SHT
ISP
ISP
ISP
CC
ISN
LEDxx
LEDxx
= V = 5V, V
3.65
4.15
ISN
T
= V = 5V, REG = 0x001
µs
LEDON
ISN
GS
PWMCK LOGIC
High Level Voltage
Low Level Voltage
= 3V to 5.5V
2.4
0
V
V
V
CC
0.6
Thermal Protection
l
I
T
T
Output Current
V
= 1V
19.0
19.8
510
20.6
µA
TSET
SET
SET
TSET
Over Temperature Threshold
T = 25°C
A
mV
Serial Data Interface
Single-Ended Input (Note 10)
High Level Voltage
Low Level Voltage
V
= 3V to 5.5V
CC
V
V
2.4
0
V
V
V
SIH
SIL
CC
0.6
I
Single-Ended Input Current
V
V
= 3V to 5.5V, SI = V or GND
–0.2
0.2
µA
SI
CC
CC
CC
Single-Ended Output (Note 10)
High Level Voltage
Low Level Voltage
= 3V to 5.5V
V
V
V
V
V
I
= –1mA
= 1mA
V
– 0.1
SOH
SOL
SO
SO
CC
I
0.1
3746f
4
LT3746
The l denotes the specifications which apply over the full operating
TiMing characTerisTics
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, VCC = 3V to 5.5V, VEN/UVLO = 1.5V, VFB = 1.5V,
VISP = VISN = 5V, VLEDxx = 0.5V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, CSCKO = CSDO = CLDO = 27pF to GND, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
30
UNITS
MHz
l
l
f
f
Data Shift Clock Frequency
PWMCK Clock Frequency
SCKI Pulse Duration
SCKI
25
MHz
PWMCK
l
l
t
t
SCKI = H (Figure 3)
SCKI = L (Figure 3)
16
16
ns
ns
WH-CKI
WL-CKI
l
l
t
t
PWMCK Pulse Duration
PWMCK = H (Figure 4)
PWMCK = L (Figure 4)
20
20
ns
ns
WH-PWM
WL-PWM
l
l
l
l
l
l
l
t
t
t
t
t
t
t
LDI Pulse Duration
LDI = H (Figure 3)
20
2
ns
ns
ns
ns
ns
ns
ns
ns
WH-LDI
SU-SDI
HD-SDI
SU-LDI
SDI-SCKI Setup Time
SDI – SCKI ↑ (Figure 3)
SCKI ↑ – SDI (Figure 3)
SCKI ↓ – LDI ↑ (Figure 3)
LDI ↓ – SCKI ↑ (Figure 3)
SCKI ↑ – SCKO ↑ (Figure 3)
SCKI ↓ – SCKO ↓ (Figure 3)
SCKI-SDI Hold Time
2
SCKI-LDI Setup Time
5
LDI-SCKI Hold Time
15
HD-LDI
PD-SCK↑
PD-SCK↓
SCKI-SCKO Propagation Delay (Rising)
SCKI-SCKO Propagation Delay (Falling)
SCK Duty Cycle Change
27
30
–3
44
50
∆t
t
∆t
= t
– t
PD-SCK↑ PD-SCK↓
PD-SCK
PD-SCK
l
l
l
SCKO-SDO Propagation Delay
LDI-LDO Propagation Delay (Rising)
LDI-LDO Propagation Delay (Falling)
LD Duty Cycle Change
2.2
4.5
27
30
–3
80
3
7
ns
ns
ns
ns
ns
ns
ns
SCKO ↑ – SDO (Figure 3)
LDI ↑ – LDO ↑ (Figure 3)
LDI ↓ – LDO ↓ (Figure 3)
PD-SD
44
50
t
t
PD-LD↑
PD-LD↓
∆t
t
∆t
= t
– t
PD-LD↑ PD-LD↓
PD-LD
PD-LD
PWMCK-LED Propagation Delay
SCKO/SDO/LDO Rise Time
PWMCK ↑ – I
(Figure 4)
PD-PWM
R-SO
LED
t
t
C
C
= 27pF, 10% to 90%
= 27pF, 90% to 10%
LOAD
LOAD
SCKO/SDO/LDO Fall Time
3
F-SO
Table 1. Test Parameter Equations
IOUTn – I
OUTavg(0−31) •100
IOUTavg(0−31)
∆ILEDC(%) =
(1)
IOUTavg – I
∆ILEDD(%) =
OUTcal •100
(2)
(3)
IOUTcal
Ê
ˆ
1.205V
RISET
I
OUTcal =1000 •
Á
˜
Ë
¯
IOUTn VCC=5.5V –IOUTn
100
2.5V
VCC=3.0V
∆ILINE(% / V) =
•
(4)
(5)
IOUTn
VCC=3.0V
IOUTn VOUTn=2.5V –IOUTn
100
2.0V
VOUTn=0.5V
∆ILOAD(% / V) =
•
IOUTn
VOUTn=0.5V
3746f
5
LT3746
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
SCKO/SDO/LDO loading capacitance, and PWMCK clock frequency; its
test condition is V = 3.3V, f = 30MHz, C = C = C = 27pF,
CC
SCKI
SCKO
SDO
LDO
f
= 409.6KHz.
PWMCK
Note 5: The SYNC frequency must be higher than the RT programmed
oscillator frequency, and is suggested to be around 20% higher.
Any SYNC frequency higher than the suggested value may introduce
sub-harmonic oscillation in the converter due to insufficient slope
compensation. See Application Information section.
Note 6: The Current Mismatch between Channels is calculated as
Equation 1 in Table 1.
Note 2: The LT3746E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3746I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: This IC includes thermal shutdown protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when thermal shutdown protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 7: The Current Mismatch between Devices is calculated as
Equations 2 and 3 in Table 1.
Note 8: The LED Current Line Regulation is calculated as Equation 4 in
Table 1.
Note 9: The LED Current Load Regulation is calculated as Equation 5 in
Table 1.
Note 10: The specifications of single-ended input SI apply to SCKI, SDI,
and LDI pins; the specifications of single-ended output SO apply to
SCKO, SDO, and LDO pins.
Note 4: The V supply current with LED channel on highly depends on
CC
the LED current setting and LEDxx pin voltage; its test condition is
R
V
= 60.4k, REG = 0x3F, REG = 0xFFF, V = V = 5V,
ISET
DC GS ISP ISN
= 0.5V. The V supply current with serial data interface on highly
LEDxx
CC
depends on V supply voltage, serial data interface clock frequency,
CC
3746f
6
LT3746
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
100Hz 8:1 GS Dimming
100Hz 4096:1 GS Dimming
500Hz 4096:1 GS Dimming
I
I
I
LED31
LED31
LED31
20mA/DIV
20mA/DIV
20mA/DIV
V
V
V
OUT
OUT
OUT
2V/DIV
2V/DIV
2V/DIV
V
V
V
LED31
LED31
LED31
2VDIV
2VDIV
2VDIV
V
V
PWMCK
5V/DIV
PWMCK
5V/DIV
V
PWMCK
5V/DIV
3746 G01
3746 G02
3746 G03
5ms/DIV
500ns/DIV
500ns/DIV
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
DC = 0×20,
31
DC = 0×20,
31
DC = 0×20,
31
31
31
GS = 0×200
GS = 0×001
GS = 0×001
31
200Hz Two-Level DC Dimming
200Hz Four-Level DC Dimming
Adaptive LED Bus Voltage I
I
LED31
I
LED31
V
OUT
20mA/DIV
20mA/DIV
0.2V/DIV
V
V
I
L
OUT
OUT
2V/DIV
2V/DIV
0.5A/DIV
V
V
LED31
LED31
I
2VDIV
2VDIV
LOAD
0.5A/DIV
V
V
SCKI
SCKI
5V/DIV
5V/DIV
(A)
(B)
(C)
(D)
(A) (B) (C)
1ms/DIV
(A) (B) (C)
3746 G04
3746 G05
3746 G06
0.5ms/DIV
2ms/DIV
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
(A) EN = 1, GS = 0×FF;
(A) EN = 0, GS = 0×FFF,
DC
00-31
GS
00-31
= 0×3F,
= 0×FFF
31
31
(B) EN = 1, DC = 0×3F;
31
(B) EN = 1, DC = 0×3F,
31
(C) EN = 1, DC = 0×00
(C) EN = 1, DC = 0×00
31
31
(D) EN = 1, DC = 0×20
31
Adaptive LED Bus Voltage II
Adaptive LED Bus Voltage III
Adaptive LED Bus Voltage IV
V
V
V
OUT
OUT
OUT
0.2V/DIV
0.2V/DIV
0.2V/DIV
I
I
L
L
I
L
0.5A/DIV
0.5A/DIV
0.5A/DIV
I
I
I
LOAD
LOAD
LOAD
0.5A/DIV
0.5A/DIV
0.5A/DIV
3746 G07
3746 G08
3746 G09
2ms/DIV
2ms/DIV
2ms/DIV
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
DC
00-31
GS
00-31
= 0×20,
= 0×800
DC
00-31
GS
08-11
GS
20-23
= 0×3F, GS
= 0×1FF, GS
= 0×7FF, GS
= 0×DFF, GS
= 0×3FF,
= 0×9FF,
28-31
DC
00-07
GS
08-15
DC
24-31
= 0×3F, GS
= 0×3FF, DC
= 0×7FF, DC = 0×1F, DC
16-23
= 0×2F,
= 0×BFF,
00-03
12-15
24-27
04-07
16-19
00-07
08-15
16-23
= 0×5FF, GS
= 0×BFF, GS
= 0×FFF
= 0×0F, GS
= 0×FFF
24-31
3746f
7
LT3746
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Buck Efficiency
Quiescent IVIN vs VIN
Shutdown IVIN vs VIN
100
95
90
85
80
75
70
5
4
3
2
1
0
0.43
24V , 12V
at 1MHz
OUT
IN
0.42
T = 125°C
T = 125°C
0.41
12V , 4V
at 500kHz
OUT
IN
T = 25°C
0.40
48V , 4V
at 200kHz
OUT
IN
T = –40°C
0.39
0.38
T = 25°C
30
65
60
T = –40°C
30
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
0
10
20
40
50
60
0
10
20
40
50
60
V
IN
(V)
V
IN
(V)
3746 G10
3746 G11
3746 G12
IVCC vs VCC – Channel Off, Data Off
IVCC vs VCC – Channel On, Data Off
IVCC vs VCC – Shutdown Mode
10
8
3.45
3.40
10.35
10.30
T = 125°C
T = 125°C
T = 25°C
3.35
3.30
3.25
3.20
3.15
3.10
3.05
10.25
10.20
10.15
10.10
10.05
10.00
9.95
T = 125°C
6
T = 25°C
4
T = –40°C
2
T = –40°C
T = –40°C
5.0
T = 25°C
3.5
0
3.0
4.0
4.5
(V)
5.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
3.0
3.5
4.0
V
CC
4.5
(V)
5.0
5.5
V
V
CC
CC
3746 G13
3746 G14
3746 G15
VCC UVLO Threshold vs
Temperature
EN/UVLO UVLO Threshold vs
Temperature
IVCC vs VCC – Channel On, Data On
27
25
23
21
19
17
15
2.90
2.85
2.80
2.75
2.70
2.65
2.60
1.32
1.30
1.28
1.26
1.24
1.22
1.20
+
UVLO
+
UVLO
T = 25°C
T = 125°C
–
UVLO
T = –40°C
–
UVLO
3.0
3.5
4.0
V
4.5
(V)
5.0
5.5
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
CC
3746 G16
3746 G17
3746 G18
3746f
8
LT3746
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
(VIN - VCAP) UVLO Threshold vs
Temperature
Oscillator Frequency fOSC vs
Temperature
Oscillator Frequency fOSC vs RT
4.90
4.80
1000
800
520
510
500
490
480
+
UVLO
4.70
4.60
4.50
4.40
600
400
200
0
–
UVLO
–50 –25
0
25
50
75 100 125
20
60 100 140 180 220 260 300
(kΩ)
–50 –25
0
25
50
75 100 125
JUNCTION TEMPERATURE (°C)
R
JUNCTION TEMPERATURE (°C)
T
3746 G19
3746 G20
3746 G21
LED Regulation Voltage vs
Load Current
Soft-Start Charge Current ISS vs
Temperature
FB Regulation Voltage vs
Load Current
1.208
1.206
1.204
1.202
1.200
1.198
0.52
0.51
–10.0
–10.2
–10.4
0.50
0.49
0.48
–10.6
–10.8
–11.0
0
200
400
600
800
1000
0
200
400
600
800
1000
–50 –25
0
25
50
75 100 125
LOAD CURRENT (mA)
LOAD CURRENT (mA)
JUNCTION TEMPERATURE (°C)
3746 G22
3746 G23
3746 G24
Current Sense Threshold
(VISP - VISN) vs VISN
CAP Bias Voltage (VIN - VCAP
vs VIN
)
CAP Bias Voltage (VIN - VCAP
vs ICAP
)
6.90
6.80
6.70
6.60
6.50
49
48
6.90
6.86
6.82
6.78
6.74
6.70
T = 25°C
T = 125°C
T = 25°C
T = –40°C
T = 125°C
T = –40°C
T = 25°C
47
46
45
6.40
6.30
6.20
T = 125°C
T = –40°C
0
4
8
12
(mA)
16
20
24
0
3
6
9
12
15
0
10
20
30
(V)
40
50
60
I
V
ISN
(V)
V
CAP
IN
3746 G27
3746 G25
3746 G26
3746f
9
LT3746
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
LED Current ILED vs
Dot Correction
VISET Pin Voltage vs Temperature
Nominal LED Current vs RISET
1.210
1.208
1.206
1.204
20
16
12
8
30
25
20
15
10
5
1.202
1.200
4
0
0
–50 –25
0
25
50
75
100 125
40
80 120 160 200 240 280 320
(kΩ)
4
16 22 28 34 40 46 52 58 64
DOT CORRECTION +1
JUNCTION TEMPERATURE (°C)
R
ISET
3746 G28
3746 G29
3746 G30
LED Current Variation ILED vs
Temperature
LED Current ILED vs LED Voltage
VLED
Short LED Threshold vs VISN
35
30
25
20
15
10
5
23
22
21
20
19
18
17
12
DC = 0×3F
9
6
3
0
DC = 0×20
DC = 0×00
0
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
–50 –25
0
25
50
75
100 125
0
4
8
12
16
V
JUNCTION TEMPERATURE (°C)
V
(V)
ISN
LED
3746 G31
3746 G32
3746 G33
LED Current Derating vs
Temperature
TSET Current vs ISET Current
TSET Threshold vs Temperature
20
16
12
8
700
650
600
550
500
450
400
350
35
30
25
20
15
10
5
OT = 0
OT = 1
4
0
0
0
4
8
12
(µA)
16
20
–50 –25
0
25
50
75
100 125
80 85 90 95 100 105 110 115 120
JUNCTION TEMPERATURE (°C)
I
JUNCTION TEMPERATURE (°C)
ISET
3746 G34
3746 G35
3746 G36
3746f
10
LT3746
pin FuncTions
EN/UVLO (Pin 1): Enable and Undervoltage Lockout
(UVLO) Pin. The pin can accept a digital input signal to
enable or disable the chip. Tie to 0.35V or lower to shut
downthechiportieto1.34Vorhigherfornormaloperation.
RT (Pin 47): Timing Resistor Pin. Programs the switching
frequency from 200kHz to 1MHz. See Table 2 for the rec-
ommended R values for common switching frequencies.
T
SS (Pin 48): Soft Start Pin. Placing a capacitor here pro-
grams soft start timing to limit inductor inrush current
during startup. The soft start cycle will not begin until all
This pin can also be connected to V through a resistor
IN
divider to program a power input UVLO threshold. If both
the enable and UVLO functions are not used, tie this pin
the V , EN/UVLO, and (V - V ) voltages are higher
CC
IN
CAP
to V pin.
CC
than their respective UVLO thresholds.
LED00 to LED31 (Pins 2-17, 30-45): LED Driver Output
FB (Pin 49): Feedback Pin. The pin is regulated to the
internal bang-gap reference 1.205V during startup and
precharging phases. Connect to a resistor divider from
the buck converter output to program the maximum LED
bus voltage. See more details in the Applications Informa-
tion section.
Pins. Connect the cathodes of LED strings to these pins.
GND (Pin 18, 20, 27, 29): Ground Pin.
SCKI (Pin 19): Serial Interface TTL/CMOS Logic Clock
Input Pin.
SDI (Pin 21): Serial Interface TTL/CMOS Logic Data
ISN (Pin 50): Negative Inductor Current Sense Pin. The
pin is connected to one terminal of the external inductor
current sensing resistor and the buck converter output
supplying parallel LED channels.
Input Pin.
LDI(Pin22):SerialInterfaceTTL/CMOSLogicLatchInput
Pin. An asynchronous input signal at this pin latches the
serial data in the shift registers into the proper registers
and the status information is ready to shift out with the
coming clock pulses. See more details in the Operation
section.
ISP (Pin 51): Positive Inductor Current Sense Pin. The pin
is connected to the inductor and the other terminal of the
external inductor current sensing resistor.
CAP (Pin 52): V Referenced Regulator Supply Capacitor
IN
Pin. The pin holds the negative terminal of an internal V
IN
V
(Pin23):LogicandControlSupplyPin.Thepinpowers
CC
referenced 6.8V linear regulator used to bias the gate driver
serial data interface and internal control circuitry. Must be
circuitry. Must be locally bypassed with a capacitor to V .
IN
locally bypassed with a capacitor to ground.
GATE (Pin 53): Gate Driver Pin. The pin drives an external
P-channelpowerMOSFETwithatypicalpeakcurrentof1A.
Connect this pin to the gate of the power MOSFET with a
short and wide PCB trace to minimize trace inductance.
PWMCK (Pin 24): Grayscale PWM Dimming TTL/CMOS
Logic Clock Pin. Individual PWM dimming signal is gener-
ated by counting this clock pulse from zero to the bits in
its 12-bit grayscale PWM register.
V
(Pin 54): Power Input Supply Pin. Must be locally
IN
LDO (Pin 25): Serial Interface TTL/CMOS Logic Latch
Output Pin.
bypassed with a capacitor to ground.
T
(Pin 55): Temperature Threshold Setting Pin. A
SET
SDO (Pin 26): Serial Interface TTL/CMOS Logic Data
Output Pin.
resistor to ground programs overtemperature threshold.
See more details in the Applications Information section.
SCKO (Pin 28): Serial Interface TTL/CMOS Logic Clock
I
(Pin 56): Nominal LED Current Setting Pin. A resistor
SET
Output Pin.
to ground programs the nominal LED current for all the
channels. See more details in the Applications Informa-
tion section.
SYNC (Pin 46): Switching Frequency Synchronization
Pin. Synchronizes the internal oscillator frequency to an
external clock applied to the SYNC pin. The SYNC pin is
Exposed Pad (Pin 57): Ground Pin. Must be soldered to a
continuouscoppergroundplanetoreducedietemperature
and to increase the power capability of the device.
TTL/CMOS logic compatible. Tie to ground or V if not
CC
used.
3746f
11
LT3746
block DiagraM
+
–
+
–
+
–
3746f
12
LT3746
operaTion
TheLT3746integratesasingleconstant-frequencycurrent-
mode nonsynchronous buck controller with thirty-two
linear current sinks. The buck controller generates an
adaptive output LED bus voltage to supply parallel LED
strings and the thirty-two linear current sinks regulate
and modulate individual LED strings. Its operation is best
understood by referring to the Block Diagram.
Serial Data Interface
The LT3746 has a 30MHz, fully-buffered, skew-balanced,
cascadableserialdatainterface.Theinterfaceusesanovel
6-wire (LDI, SCKI, SDI, LDO, SCKO, and SDO) topology
and can be connected to microcontrollers, digital signal
processors (DSPs), or field programmable gate arrays
(FPGAs).
Inaconventional4-wiretopologyshowninFigure1,theLDI
and SCKI signals need global routing while the SDI signal
only needs local routing between chips. Depending on the
number of chips in cascade and the size of system PCB
board,externalclock-treetypebufferswithcorresponding
driving capability are needed for both the LDI and SCKI
signals to minimize signal skews. The propagation delay
caused by the buffer insertion on the SCKI signal yields
the clock skew between the SCKI and SDI signals, which
usuallyrequiresthecustomerendtobalanceit. Sinceboth
the SDI and SDO signals require the same SCKI signal to
send and receive, the propagation delay between the SDI
and SDO signals limits the number of chips in cascade
and the series data interface clock frequency.
Start-Up
TheLT3746entersshutdownmodeanddrainsalmostzero
current when the EN/UVLO pin is lower than 0.35V. Once
the EN/UVLO pin is above 0.35V, the part starts to wake
up internal bias currents, generate various references,
and charge the capacitor C
voltage. This V referenced voltage regulator (V - V
towards 6.8V regulation
CAP
)
IN
IN CAP
will supply the internal gate driver circuitry driving an
external P-channel MOSFET in normal operation. The
LT3746 remains in undervoltage lockout (UVLO) mode
as long as any one of the EN/UVLO, V , and (V - V )
CC
IN
CAP
UVLO flags is high. Their UVLO thresholds are typically
1.31V, 2.89V, and 4.9V, respectively. After all the UVLO
flags are cleared, the buck controller starts to switch, and
the soft start SS pin is released and charged by a 12µA
currentsource, therebysmoothlyrampinguptheinductor
current and the output LED bus voltage.
The novel 6-wire topology eliminates the need for global
routing and buffer insertion for the LDI and SCKI signals.
Instead, it provides the LDO and SCKO signals along with
the SDO signal to drive the next chip. The skew inside the
chip among the LDI, SCKI, and SDI signals is balanced
internally.TheskewoutsidethechipamongtheLDO,SCKO,
and SDO signals can be easily balanced by parallel routing
these three signals between chips. The SDI signal is sent
withtheSCKIsignal,andtheSDOsignalisreceivedwiththe
SCKO signal. A slight duty cycle change between the SCKI
and SCKO signals may occur due to the process variation,
supplyvoltageandoperatingtemperature. Thisdutycycle
changeresultsfromthedifferenceinpropagationdelaysof
the positive and negative edges of the SCKI/SCKO signals
and will affect the maximum number of cascadable chips,
depending on the SCKI speed. In summary, the 6-wire
topology extends the maximum number of cascadable
chips, boosts the series data interface clock frequency,
eliminates the need for buffer insertion for global signals,
and offers an easy PCB layout. In a low-speed application
with a small number of cascaded chips, the 6-wire topol-
ogy can be simplified to the 4-wire topology by ignoring
the LDO and SCKO outputs.
Power-on-Reset (POR)
During start-up, an internal power-on-reset (POR) high
signal blocks the input signals to the serial data interface
andresetsalltheinternalregistersexceptthe386-bitshift
register. The 1-bit frame select (FS) register, 1-bit enable
LEDchannel(EN)register,individual12-bitgrayscale(GS)
registers,andindividual6-bitdotcorrection(DC)registers
are all reset to zero. Thus all the LED channels are turned
off initially with the default grayscale (0x000) and dot
correction(0x00)setting. Oncethepartcompletesitssoft
start (i.e., the SS pin voltage is higher than 1V) and the
output LED bus voltage is power good (i.e., within 5% of
its FB programmed regulation level), the POR signal goes
low to allow the input signals to the serial data interface.
Any fault triggering the soft start will generate another
POR high signal and reset internal registers again.
3746f
13
LT3746
operaTion
LT3746 6-WIRE TOPOLOGY
LDI CHIP 1 LDO LDI CHIP 2 LDO
LDO
SCKO
SDO
LDI CHIP N LDO
SCKI
SDI
SCKO
SDO
SCKI
SDI
SCKO
SDO
SCKI
SDI
SCKO
SDO
CONTROLLER
SDI
SCKI
LDI
CONVENTIONAL 4-WIRE TOPOLOGY
LDO
SCKO
SDO
LDI CHIP 1 LDO
LDI CHIP 2 LDO
LDI CHIP N LDO
SCKI
SDI
SCKO
SDO
SCKI
SDI
SCKO
SDO
SCKI
SDI
SCKO
SDO
CONTROLLER
SDI
3746 F01
Figure 1. LT3746 6-Wire Topology vs Conventional 4-Wire Topology
386 BITS
GS 31, 12 BITS
GS 0, 12 BITS
C1
C1
0
C0
C0
GS FRAME
DC 31, 6 BITS
DC 31, 6 BITS
x
x
x
x
x
x
DC 0, 6 BITS
DC 0, 6 BITS
x
x
x
x
x
x
DC FRAME
0
0
0
0
0
S31
0
0
0
0
0
S0
F0
STATUS FRAME
3746 F02
COMMAND REGISTER:
STATUS REGISTER:
C1: ENABLE LED CHANNELS - ENABLE = 1, DISABLE = 0
C0: FRAME SELECT - GS FRAME = 0, DC FRAME = 1
S0-S31: LED 0-31 FAULT - FAULT = 1, OK = 0
F0: OT - OVER TEMPERATURE = 1, OK = 0
Figure 2. Serial Data Frame Format
3746f
14
LT3746
operaTion
t
t
t
SU-LDI WH-LDI HD-LDI
LDI
t
WH-CKI
SCKI
SDI
1
378
385
386
1
384
385
386
1
t
SU-SDI
t
WL-CKI
t
HD-SDI
GS 31
MSB
DC 31
MSB
DC 0
LSB
GS 31
MSB
GS 0
LSB
C1
C0 = 1
C1
C0 = 0
DC 31
MSB
DC 0
LSB
GS 31
MSB
GS 0
LSB
GS 31
F0
C1
C0 = 0
SR[0]
SR[1]
LDO
C1
x
C0 = 1
C1
F0
MSB
DC 0
LSB + 1
GS 0
LSB + 1
GS 0
LSB
0
F0
C1
0
F0
t
PD-LD↓
t
PD-LD↑
t
PD-SCK↑
SCKO
1
378
385
386
1
384
385
386
t
PD-SCK↓
t
PD-SD
DC 31
MSB
DC 31
MSB
DC 31
MSB – 1
GS 31
MSB
DC 31
MSB
SDO/
SR[385]
0
F0
3746 F03
INPUT DATA
STATUS DATA
Figure 3. Serial Data Input and Output Timing Chart
C1/EN
t
WH-PWM
PWMCK
I(LED00)
I(LED01)
I(LED31)
PRECHG
1
2
3
3584
3585
4095
4096
1
2
t
PD-PWM
t
WL-PWM
REG = 0x002
REG = 0xFFF
REG = 0x000
TRACKING PHASE
PRECHARGING PHASE
3746 F04
Figure 4. Grayscale PWM Dimming and Precharging Signal Timing Chart
3746f
15
LT3746
operaTion
Figure2showstwoserialdatainputSDIframes(GSframe
andDCframe)andoneserialdataoutputSDOframe(status
frame). All the frames have the same 386-bit in length and
aretransmittedwiththeMSBfirstandtheLSBlast.TheSDI
frames are sent with the SCKI signal and the SDO frame is
received with the SCKO signal. The C0 bit (frame select)
determines any SDI frame to be either a GS frame (C0 = 0)
or a DC frame (C0 = 1), and the C1 bit (EN) enables (C1 = 1)
or disables (C1 = 0) all the LED channels. The status frame
SCKIandSCKOsignals.Therefore,adaisy-chaintypeloop
communication with simultaneous writing and reading
capability is implemented.
Figure 3 illustrates the timing relation among serial input
and serial output signals in more detail. One DC frame fol-
lowed by another GS frame is sent through the LDI, SCKI,
and SDI signals. At the same time, two status frames are
received through the LDO, SCKO, and SDO signals. The
rising edges of the SCKI signal shift a frame of 386-bit
dataattheSDIpinintothe386-bitshiftregisterSR[0:385].
After 386 clock cycles, all the 386-bit data sit in the right
placewaitingfortheLDIsignal.AnasynchronousLDIhigh
signal latches the 1-bit FS register, 1-bit EN register, and
individual 12-bit GS registers (when FS = 0) or 6-bit DC
registers(whenFS=1)foreachchannel. Atthesametime,
a frame of status information, including over temperature
flag and individual open/short LED fault flags, is parallel
loaded into the 386-bit shift register and will be shifted
out with the coming clock cycles.
reads back the T
pin resistor-programmable over-
SET
temperatureflagandindividualopen/shortLEDfaultflags,
as well as the individual 6-bit DC setting.
Inside the part, there are one 386-bit shift register
SR[0:385], one 1-bit frame select (FS) register, one 1-bit
enable LED channel (EN) register, thirty-two 12-bit gray-
scale (GS) registers, thirty-two 6-bit dot correction (DC)
registers,one1-bitovertemperature(OT)flagregister,and
thirty-two 1-bit LED fault flag registers. The input of the
386-bit shift register, i.e., the input of the first bit SR[0],
is connected to the SDI signal. The output of the 386-bit
shift register, i.e., the output of the last bit SR[385] is con-
nected to the SDO signal. The SCKI signal shifts the SDI
frame (GS or DC frame) in and the SCKO signal shift the
SDO frame (status frame) out of the 386-bit shift register
with their rising edges. The LDI high signal latches the SDI
frame (GS or DC frame) from the 386-bit shift register into
corresponding FS, EN, GS or DC registers, and loads the
SDO frame (status frame) from the OT and LED fault flag
registers to the 386-bit shift register at the same time.
The LDO signal is a buffered version of the LDI signal
with certain delay added to match the delay between the
Constant Current Sink
Each LED channel has a local constant current sink regu-
lating its own LED current independent of the LED bus
. The recommended LED pin voltage ranges
voltage V
OUT
from 0.5V to 2.5V. As shown in the Typical Performance
Characteristics I
vs V
curves, the LED current I
LED
LED
LED
LED
OUT
hasthebestloadregulationwhentheLEDpinvoltageV
sits between 0.5V to 2.5V. A lower LED bus voltage V
may not regulate all the LED channels across tempera-
ture, current, and manufacturing variation, while a higher
4096*T
PWMCK
PWM
PWM
PWM
1
2
3
V
= 4.4V
(1)
(2)
(3)
OUT
+
+
+
3.1V
3.5V
3.9V
PRECHG
–
–
–
+
+
+
4.4V
4.4V
4.0V
4.0V
1.3V
–
0.9V
–
0.5V
–
IDEAL V
OUT
OUT
3.6V
3.6V
LT3746 V
4.4V
CONSTANT V
OUT
3746 F05
t
t
2
t t
3 4
1
Figure 5. Adaptive-Tracking-plus-Precharging LED Bus Voltage Technique
3746f
16
LT3746
operaTion
LED bus voltage V
will force a higher LED pin voltage
Dual-Loop Analog OR Control
OUT
across the current sink, thereby dissipating more power
inside the part. See more details about the choice of the
LED bus voltage and the power dissipation calculation in
the Application Information section.
Theswitchingfrequencycanbeprogrammedfrom200kHz
to 1MHz with the resistor connected to the RT pin and it
can be synchronized to an external clock using the SYNC
pin. Each switching cycle starts with the gate driver
turning on the external P-channel MOSFET M1 and the
Dot Correction and Grayscale Digital-to-Analog
Conversion
inductor current is sampled through the sense resistor R
S
between the ISP and ISN pins. This current is amplified
and added to a slope compensation ramp signal, and the
resulting sum is fed into the positive terminal of the PWM
comparator. When this voltage exceeds the level at the
negative terminal of the PWM comparator, the gate driver
turnsoffM1. ThelevelatthenegativeterminalofthePWM
The resistor on the I
pin programs the nominal LED
SET
current(4mAto20mA)forallthechannels. IndividualLED
channel can be adjusted to a different current setting by
its own 6-bit dot correction register. The adjustable LED
current ranges from 0.5X to 1.5X of the nominal LED
current in 63 linear steps. See more details about setting
nominalLEDcurrentanddotcorrectionintheApplications
Information section.
comparator is set by either of two error amplifiers G
M1
and G . In this dual-loop analog OR control, the FB loop
M2
G
M1
regulates the FB pin voltage to 1.205V and the LED
loop G regulates the minimum active LED pin voltage
M2
In addition to the dot correction current adjustment,
individual LED channels can also be modulated by their
own grayscale PWM dimming signal. To achieve a better
performance, all the grayscale PWM dimming signals
are synchronized to the same frequency with no phase
shift between rising edges. Each constant current sink is
enabled or disabled when its grayscale PWM dimming
signal goes high or low. This periodic grayscale PWM
dimming signal is generated by its own 12-bit grayscale
register with a duty cycle from 0/4096 to 4095/4096 and
a period equal to 4096 PWMCK clock cycles.
(LED00 to LED31) to 0.5V. In the startup phase, the G
M2
is disabled and the output LED bus voltage is regulated
towards the feedback resistor programmed LED bus volt-
age. This FB programmed voltage defines the maximum
LED bus voltage and should be programmed high enough
to supply the worst case LED string across temperature,
current, and manufacturing variation.
Adaptive-Tracking-Plus-Precharging
Higher system efficiency and faster transient response
are two highly anticipated specifications in an indi-
vidually-modulated multi-channel LED driver chip.
The LT3746 uses a patent pending adaptive-tracking-
plus-precharging technique to achieve both of them
simultaneously.
The generation of the grayscale PWM dimming signal
is best understood by referring to Figure 4. After EN = 1
is set, the first rising edge of the PWMCK signal will in-
crease the internal 12-bit grayscale counter from zero to
one and turn on all the LED channels with grayscale value
not zero. Each following rising edge of the PWMCK signal
increases the grayscale counter by one. Any LED channel
will be turned off when its 12-bit grayscale register value
is equal to the value in the grayscale counter. To generate
a 100% duty cycle for all the grayscale PWM dimming
signals,thePWMCKsignalcanbepausedbeforecounting
to the value in any individual 12-bit grayscale registers.
Setting EN = 0 will reset the grayscale counter to zero and
turn off all the LED channels immediately.
Besides 32 internal grayscale PWM dimming signals,
the part also generates another internal precharging
signal PRECHG. As shown in Figure 4, the PRECHG
signal divides any grayscale PWM dimming cycle
into two phases: tracking phase when PRECHG = 0
and precharging phase when PRECHG = 1. During
each grayscale PWM dimming cycle – 4096 PWMCK
clock cycles, the PRECHG signal stays low for the first
3584 clock cycles (7/8 of the grayscale PWM dimming
3746f
17
LT3746
operaTion
period) and goes high for the rest 512 clock cycles (1/8 equalto0.5Vagain. Similarlyatthenexttimeinstantt ,
2
of the grayscale PWM dimming period). In the event of the output LED bus voltage is tracked down to 3.6V. In
all the LED channels being not active (i.e., either fault thismanner,theadaptive-trackingtechniqueeliminates
or off) before the 3585th PWMCK clock, the PRECHG unnecessarypowerdissipationacrossthecurrentsinks
signal will go high immediately.
and yields superior system efficiency when compared
to a constant 4.4V output voltage.
Tobetterexplaintheoperationoftheadaptive-tracking-
plus-precharging technique, a simplified application At a later time instant t when the PRECHG signal goes
3
system with 3-channel LED array is presented in high, theamplifierG isdisabledandgivesthecontrol
M2
Figure 5. Each channel consists of a single LED with back to the amplifier G . The amplifier GM1 regulates
M1
the forward voltage drop equal to 3.1V, 3.5V, and 3.9V, theoutputLEDbusvoltagetowardstheFBprogrammed
respectively. Three internal grayscale PWM dimming maximum value 4.4V to guarantee shorter minimum
signalsPWM1,PWM2,andPWM3areusedtomodulate LED on-time for the next grayscale PWM dimming
each LED channel.
cycle. Without the precharging phase, the output LED
bus voltage will stay at 3.6V before the next grayscale
PWMdimmingcycle,whenallthe3LEDchannelswillbe
turned on again. At that time the 3.6V LED bus voltage
is too low to keep all the LED channels in regulation,
and the minimum LED on time is greatly increased to
accommodatetheslowtransientresponseoftheswitch-
ing buck converter charging the output capacitor from
3.6V to 4.4V. This adaptive-tracking-plus-precharging
LED bus voltage technique simultaneously lowers the
powerdissipationintheLT3746andmaintainsashorter
minimum LED on-time.
AtthebeginningofeachgrayscalePWMdimmingcycle,
all three LED channels are turned on and the tracking
phase starts with PRECHG = 0. The amplifier G is
M2
enabled and takes the control from the amplifier G ,
M1
regulating the minimum active LED pin voltage to 0.5V.
WiththeV
equalto0.5V,theoutputLEDbusvoltage
LED3
istrackedto4.4V.Subsequently,atacertaintimeinstant
t when the third channel is turned off, the minimum
1
active LED pin voltage goes to V
, 0.9V. Then the
LED2
amplifier G tracks the output LED bus voltage down
M2
to 4V to maintain the minimum active LED pin voltage
3746f
18
LT3746
applicaTions inForMaTion
Globally, the LT3746 converts a higher input voltage to a
AnotherrestrictionontheminimuminputvoltageV
IN(MIN)
single lower LED bus voltage (V ) supplying 32 parallel
is the 2V minimum dropout voltage between the V and
OUT
IN
LED strings with the adaptive-tracking-plus-precharging
technique. Locally, the part regulates and modulates the
currentofeachstringtoanindependentdotcorrectionand
grayscale PWM dimming setting sent by TTL/CMOS logic
serial data interface. This Application Information section
serves as a guideline of selecting external components
(refer to the Block Diagram) and avoiding common pitfalls
for the typical application.
ISN pins, and thus the V
is calculated as:
IN(MIN)
VIN(MIN) =VOUT(MAX) + 2V
Choosing Switching Frequency
Selection of the switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
and gate charge losses. However, lower frequency opera-
tion requires larger inductor and capacitor values.
Programming Maximum V
OUT
The adaptive-tracking-plus-precharging technique regu-
Another restriction on the switching frequency comes
from the input and output voltage range caused by the
minimum switch on and switch off time. The highest
lates V
to its maximum value during the startup and
OUT
precharging phases, and adaptively lowers the voltage
to keep the minimum active LED pin voltage around 0.5V
during the tracking phase. Therefore, the maximum V
switching frequency f
be calculated as:
for a given application can
SW(MAX)
OUT
should be programmed high enough to keep all the LED
pin voltages higher than 0.5V to maintain LED current
regulation across temperature, current, and manufactur-
ing variation. As a starting point, the maximum LED bus
DMIN 1–D
tON(MIN) tOFF(MIN)
MAX
fSW(MAX) =MIN
,
voltage, V , can be calculated as:
OUT(MAX)
where the minimum duty cycle D
and the maximum
MIN
duty cycle D
are determined by:
MAX
VOUT(MAX) =0.5V +n• VF(MAX)
VOUT(MIN) + V
VOUT(MAX) + VD
where n is the number of LED per string and V
the maximum LED forward voltage rated at the highest
operating current and the lowest operating temperature.
is
DMIN
=
D and DMAX
IN(MAX) + VD
=
F(MAX)
V
VIN(MIN) + VD
t
istheminimumswitchontime(~200ns),t
OFF(MIN)
is the minimum switch off time (~120ns), V
minimum adaptive output voltage, V
muminputvoltage, andV isthecatchdiodeforwardvolt-
age (~0.5V). The calculation of f
ON(MIN)
The V
is programmed with a resistor divider
OUT(MAX)
is the
OUT(MIN)
between the output and the FB pin. The resistor values
are calculated as:
is the maxi-
IN(MAX)
D
simplifies to:
SW(MAX)
V
Ê
ˆ
R
FB2 =RFB1 OUT(MAX) -1
Á ˜
1.205V
Ë
¯
fSW(MAX)
=
V
OUT(MIN)+ V
D, 8.33•
IN(MAX)+ VD
VIN(MIN) – V
Toleranceofthefeedbackresistorswilladdadditionalerrors
totheoutputvoltage, so1%resistorvaluesshouldbeused.
The FB pin output bias current is typically 120nA, so use of
extremely high value feedback resistors could also cause
OUT(MAX)
MIN 5•
MHz
V
VIN(MIN)+ VD
Obviously,lowerfrequencyoperationaccommodatesboth
extremely high and low V to V ratios.
bias current errors. A typical value for R is 10k.
FB1
OUT
IN
V Power Input Supply Range
Besides these common considerations, the specific
application also plays an important role in switching fre-
quency choice. In a noise-sensitive system, the switching
IN
The power input supply for the LT3746 can range from 6V
to55V,coveringawidevarietyofindustrialpowersupplies.
3746f
19
LT3746
applicaTions inForMaTion
frequency is usually chosen to keep the switching noise
out of a sensitive frequency band.
from 0V to (V
– 2V) or 13V absolute maximum value,
IN
whichever is lower. The current sense amplifier not only
provides current information to form the current-mode
control,butalsoa46.5mVthreshold.The46.5mVthreshold
Switching Frequency Setting and Synchronization
across the R resistor imposes an accurate current limit
S
The LT3746 uses a constant switching frequency that can
be programmed from 200kHz to 1MHz with a resistor
to protect both P-channel MOSFET M1 and catch diode
D1, and also to prevent inductor current saturation. Good
Kelvin sensing is required for accurate current limit. The
from the RT pin to ground. Table 2 shows R values for
T
common switching frequencies.
R resistor value can be determined by:
S
Table 2. Switching Frequency fSW vs RT Value
∆ IL
f
(kHz)
R * (kΩ)
T
SW
IOUT(MAX) =IL(MAX)
–
200
280
182
2
300
400
500
600
700
800
900
1000
where the maximum inductor current I
is set by:
L(MAX)
133
105
46.5mV
IL(MAX)
=
84.5
71.5
60.4
53.6
46.4
RS
I
is the maximum output load current, and ∆I
OUT(MAX)
L
is the inductor peak-to-peak ripple current. Allowing ad-
equate margin for ripple current and external component
* Recommend 1% Standard Values
tolerances, R can be estimated as:
S
Synchronizing the LT3746 oscillator to an external fre-
quency can be achieved using the SYNC pin. The square
wave amplitude, compatible to TTL/CMOS logic, should
have valleys that are below 0.6V and peaks that are above
2.4V. The synchronization frequency also ranges from
35mV
RS =
IOUT(MAX)
Inductor Selection
200kHzto1MHz,inwhichtheR resistorshouldbechosen
T
The critical parameters for selection of an inductor are
inductance value, DC or RMS current, saturation current,
and DCR resistance. For a given input and output voltage,
the inductor value and switching frequency will determine
to set the internal switching frequency around 20% below
the synchronization frequency. In the case of 200kHz
synchronization frequency, R = 348k is recommended.
T
It is also important to note that when the synchroniza-
the peak-to-peak ripple current, ∆I . The ∆I value usually
L
L
tion frequency is much higher than the R programmed
T
ranges from 20% to 50% of the maximum output load
internal frequency, the internal slope compensation will
besignificantlyreduced, whichmaytriggersub-harmonic
oscillation at duty cycles greater than 50%.
current, I
. Lower values of ∆I require larger and
OUT(MAX)
L
more costly inductors; higher values of ∆I increase the
L
peak currents and the inductor core loss. An inductor
current ripple of 30% to 40% offers a good compromise
betweeninductorperformanceandinductorsizeandcost.
Inductor Current Sense Resistor R and Current Limit
S
The current sense resistor, R , monitors the inductor
S
However, for high duty cycle applications, a ∆I value of
L
current between the ISP and ISN pins, which are the in-
puts to the internal current sense amplifier. The common
mode input voltage of the current sense amplifier ranges
~20% should be used to prevent sub-harmonic oscillation
due to insufficient slope compensation.
3746f
20
LT3746
applicaTions inForMaTion
The largest inductor ripple current occurs at the highest
For maximum efficiency, both R
and C
should
DS(ON)
RSS
V . To guarantee that the ripple current stays below the
be minimized. Lower R
means less conduction loss
IN
DS(ON)
specified maximum, the inductor value should be chosen
while lower C
DS(ON)
reduces transition loss. Unfortunately,
is inversely related to C . Thus balancing the
RSS
according to the following equation:
R
RSS
conduction loss with the transition loss is a good criterion
V
IN(MAX) – VOUT
VOUT + VD
in selecting a MOSFET. For applications with higher V
L≥
•
IN
VIN(MAX) + VD
fSW • ∆IL
voltages (≥24V) a lower C
is more important than a
RSS
low R
.
DS(ON)
The inductor DC or RMS current rating must be greater
than the maximum output load current I and its
Catch Diode Selection
OUT(MAX)
saturation current should be higher than the maximum
inductorcurrentI .Toachievehighefficiency,theDCR
The catch diode D1 carries load current during the switch
offtime.Importantparametersforthecatchdiodeincludes
L(MAX)
resistance should be less than 0.1Ω, and the core material
peak repetitive reverse voltage (V
), forward voltage
RRM
should be intended for high frequency applications.
(V ), and maximum average forward current (I
). The
F
F(AV)
diode V
specification should exceed the maximum
RRM
Power MOSFET Selection
reverse voltage across it, i.e., V
. A fast switching
IN(MAX)
ImportantparametersfortheexternalP-channelMOSFET
schottky diode with lower V should be used to yield lower
F
M1includedrain-to-sourcebreakdownvoltage(V
,
power loss and higher efficiency.
(BR)DSS)
), maximum
maximum continuous drain current (I
D(MAX)
), total gate charge (Q ),
In continuous conduction mode, the average current
conducted by the catch diode is calculated as:
gate-to-source voltage (V
GS(MAX)
G
drain-to-source on resistance (R
), reverse transfer
DS(ON)
capacitance (C ). The MOSFET V
specification
RSS
(BR)DSS
ID(AVG) =IOUT • (1–D)
should exceed the maximum voltage across the source to
the drain of the MOSFET, which is V plus V . The
IN(MAX)
D
The worst-case condition for the diode is when V
is
OUT
OUT
I
should exceed the peak inductor current, I
.
D(MAX)
L(MAX)
shorted to ground with maximum V and maximum I
IN
Sincethegatedrivercircuitissuppliedbytheinternal6.8V
referenced regulator, the V rating should be
at present. In this case, the diode must safely conduct
the maximum load current almost 100% of the time. To
improve efficiency and to provide adequate margin for
short circuit operation, a schottky diode rated to at least
the maximum output current is recommended.
V
IN
GS(MAX)
at least 10V.
Each switching cycle the MOSFET is switched off and on,
a packet of gate charge Q is transferred from the V pin
G
IN
to the GATE pin, and then from the GATE pin to the CAP
C , C , and C
Capacitor Selection
pin. The resulting dQ /dt is a current that must be sup-
IN VCC
CAP
G
plied to the C
capacitor by the internal regulator. The
CAP
A local input bypass capacitor C is required for buck
IN
maximum20mAcurrentcapabilityoftheinternalregulator
converters because the input current is pulsed with fast
riseandfalltimes.Theinputcapacitorselectioncriteriaare
based on the voltage rating, bulk capacitance, and RMS
current capability. The capacitor voltage rating must be
limits the maximum Q
it can deliver to:
G(MAX)
20mA
fSW
QG(MAX)
=
greaterthanV
.Thebulkcapacitancedeterminesthe
IN(MAX)
input supply ripple voltage and the RMS current capability
Therefore, the Q at V = 6.8V from the MOSFET data
G
GS
is used to keep from overheating the capacitor.
sheet should be less than Q
.
G(MAX)
3746f
21
LT3746
applicaTions inForMaTion
The bulk capacitance is calculated based on maximum
The general discussion above also applies to the capacitor
C
attheV pinandthecapacitorC betweentheV
VCC
input ripple, ∆V :
IN
CC
CAP
IN
and CAP pins. Typically, a 10µF 10V-rated ceramic capaci-
DMAX • IOUT(MAX)
tor for C
and a 0.47µF 16V-rated ceramic capacitor for
VCC
CIN =
∆VIN • fSW
C
should be sufficient.
CAP
∆V is typically chosen at a level acceptable to the user.
C
OUT
Capacitor Selection
IN
100mV is a good starting point. For ceramic capacitors,
only X5R or X7R type should be used because they retain
their capacitance over wider voltage and temperature
ranges than other types such as Y5V or Z5U. Aluminum
electrolytic capacitors are a good choice for high voltage,
bulk capacitance due to their high capacitance per unit
area.
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT3746 to produce the DC output containing a con-
trolled voltage ripple. It also stores energy to satisfy load
transients and to stabilize the dual-loop operation. Thus
the selection criteria for C
are based on the voltage
OUT
rating, the equivalent series resistance ESR, and the bulk
capacitance. As always, choose the C with a voltage
The capacitor RMS current is:
OUT
rating greater than V
.
OUT(MAX)
V
•( V – V
)
OUT
OUT
IN
I
= I
•
OUT
CIN(RMS)
TheLT3746utilizestheoutputasthedominantpoletosta-
2
V
IN
bilizethedualloopoperation,sotheC
valuedetermines
OUT
the unity gain frequency f , which is set around 1/10 of
UGF
If applicable, calculate at the worst case condition,
V =2 • V . The capacitor RMS current rating speci-
theswitchingfrequency.TostabilizetheFBloopduringthe
startup and precharging phases and the LED loop during
the tracking phase, a low-ESR capacitor (tens of mΩ)
IN
OUT
fied by the manufacturer should exceed the calculated
. Due to their low ESR, ceramic capacitors are
I
CIN(RMS)
should be used and its minimum C
is calculated as:
OUT
a good choice for high voltage, high RMS current han-
dling. Note that the ripple current ratings from aluminum
electrolytic capacitor manufacturers are based on 2000
hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required.
0.25
RS • fUGF
1.5
VOUT(MAX)• RS • fUGF
C
OUT = MAX
,
Theadaptive-tracking-plus-prechargingtechniquemoves
the V with the grayscale PWM dimming frequency to
OUT
For a larger high voltage capacitor value, the combination
ofaluminumelectrolyticcapacitorsandceramiccapacitors
is an economical approach. Multiple capacitors may also
be paralleled to meet size or height requirements in the
design. Locate the capacitor very close to the MOSFET
switchandthecatchdiode,anduseshort,widePCBtraces
to minimize parasitic inductance.
improve system efficiency, choosing a ceramic capacitor
as the C inevitably generates acoustic noise due to the
OUT
piezo effect of the ceramic material. In an acoustic noise
sensitive application, low ESR tantalum or aluminum
capacitors are preferred. When choosing a capacitor,
look carefully through the data sheet to find out what the
actual capacitance is under operating conditions (applied
voltage and temperature). A physically larger capacitor, or
one with a higher voltage rating, may be required.
3746f
22
LT3746
applicaTions inForMaTion
Undervoltage Lockout (UVLO) and Shutdown
V
IN
V
V
V
V
IN
IN
LT3746 has three UVLO thresholds with hysteresis for
R
R
UV2
CC
CC
the EN/UVLO, V , and CAP pins. The part will remain in
FROM µCONTROLLER
CC
EN/UVLO
EN/UVLO
UVLO mode not switching until all the EN/UVLO, V , and
CC
(V - V ) voltages pass their respective typical thresh-
UV1
3746 F06
IN
CAP
olds (1.31V, 2.89V, and 4.9V). As shown in Figure 6, the
EN/UVLO pin can be controlled in two different ways. The
EN/UVLO pin can accept a digital input signal to enable or
disable the chip. Tie to 0.35V or lower to shut down the
chip or tie to 1.34V or higher for normal operation. This
(A)
(B)
Figure 6. Methods of Controlling the EN/UVLO Pin
pincanalsobeconnectedtoaresistordividerbetweenV
IN
Setting Nominal LED Current
andgroundtoprogramapowerinputV UVLOthreshold.
IN
The nominal LED current is defined as the average LED
current across 32-channel when all the individual dot cor-
rection registers are set to 0x20. The nominal LED current
After R
is selected, R
can be calculated by:
UV1
UV2
V
RUV2 = RUV1
•
IN(ON) –1
1.31V
is programmed by a single resistor, R , between the
ISET
I
pin and ground. The voltage at the I
pin, V
,
SET
SET
ISET
is trimmed to an accurate 1.205V, generating a current
where V
is the power input voltage above which the
IN(ON)
inversely proportional to R . The nominal LED current,
part goes into normal operation. It is important to check
the EN/UVLO pin voltage not to exceed its 6V absolute
maximum rating:
ISET
I
, can be calculated as:
LED(NOM)
VISET
RISET
ILED(NOM)
=
•1000
RUV1
RUV1+RUV2
VIN(MAX)
•
<6V
I
must be set between 4mA and 20mA. Typical
resistor values for various nominal LED currents
are listed in Table 3.
LED(NOM)
R
Soft-Start
ISET
During soft-start, the SS pin voltage smoothly ramps up
inductor current and output voltage. The effective voltage
range of SS pin is from 0V to 1V. Therefore, the typical
soft-start period is
Table 3. Nominal LED Current ILED(NOM) vs. RISET Value
I
(mA)
R
* (kΩ)
ISET
LED(NOM)
4
301
10
15
20
121
80.6
60.4
CSS •1V
12µA
tSS
=
* Recommend 1% Standard Values
where C is the capacitor connected at SS pin and
SS
Setting Dot Correction
12µA is the soft-start charge current. Whenever a UVLO
orthermalshutdownoccurs, theSSpinwillbedischarged
and the part will stop switching until the UVLO event has
disappearedandthe SS pin has reached itresetthreshold,
0.35V. The part then initiates a new soft-start cycle.
The LT3746 can adjust the LED current for each channel
independently. This fine current adjustment, also called
dot correction, is mainly used to calibrate the brightness
deviation between LED channels. The 6-bit (64 steps) dot
3746f
23
LT3746
applicaTions inForMaTion
correction setting adjusts each LED current from 0.5X to
1.5X of the nominal LED current according to:
Open/Short LED Fault
TheLT3746hasindividualLEDfaultdiagnosticcircuitrythat
detects both open and short LED faults for each channel.
The open LED fault is defined as any LED string is open
or disconnected from the circuit; and the short LED fault
is defined as any LED string is shorted across itself. The
open LED flag is set if the LED pin voltage is lower than
0.1V (typical) during on status with initial 500ns blanking.
The short LED flag is set if the LED pin voltage is higher
DCn+32
I
LEDn=ILED(NOM) •
64
where I
is the nth LED current and DC is the nth
n
LEDn
programmed dot correction setting (DC = 0 to 63). The
n
fine current step over the nominal LED current gives an
excellent resolution:
than 75% of the LED bus voltage V
any time. If one
OUT
∆ILED
LED channel is shorted across itself, the channel will be
turned off to eliminate unnecessary power dissipation.
The function can also be used to disable LED channels
by connecting their LED pins to the output directly. Both
the open and short LED flags are combined to set the LED
fault bits (S0 to S31) in the status frame to 1.
1
=
≈1.56%
ILED(NON) 64
which enhances the relative LED current match accuracy
if used as calibration.
Setting Grayscale
Thermal Protection
Although adjusting the LED current changes its luminous
intensity, or brightness, it will also affect the color match-
ing between LED channels by shifting the chromaticity
coordinate. The best way to adjust the brightness is to
control the amount of LED on/off time by pulse width
modulation (PWM).
The LT3746 has two over temperature thresholds: one
is the fixed internal thermal shutdown and the other one
is programmed by a resistor, R
pin and ground. When the junction temperature exceeds
165°C, the part will enter thermal shutdown mode, shut
downserialdatainterface,turnoffLEDchannels,andstop
switching. After the junction temperature drops below
155°C, the part will initiate a new soft start.
, between the T
TSET
SET
The LT3746 can adjust the brightness for each channel
independently.The12-bitgrayscalePWMdimmingresults
in 4096 linear brightness steps from 0% to 99.98%. The
brightness level GS % for channel n can be calculated
as:
When the R
is placed at the T
pin, a current equal
SET
TSET
n
to the current flowing through the R
passes the
ISET
R
, generating a voltage V
TSET
at the T pin, which
TSET
SET
is calculated as:
GSn
4096
GSn%=
•100%
RTSET
RISET
VTSET =1.205V •
where GS is the nth programmed grayscale setting
n
(GS = 0 to 4095).
n
3746f
24
LT3746
applicaTions inForMaTion
Then the V
is compared to an internal proportional-
whereN
isthenumberofLT3746chipsandf
REFRESH
TSET
LT3746
to-absolute-temperature voltage V
,
is the refresh rate of the whole system.
PTAT
Calculating Power Dissipation
VPTAT = 1.72mV •(TJ + 273.15)
where T is the LT3746 junction temperature in °C. When
The total power dissipation inside the chip can be calcu-
lated as:
J
V
is higher than V
, an overtemperature flag
PTAT
TSET
PTOTAL
=
OT = 1 is set. Once the R
exceeded, the part will also gradually derate the nominal
LED current I
without interrupting its normal operation.
programmed temperature is
TSET
VIN•(I VIN+ fSW •QG)+ VCC•IVCC
+
31 GS %•ILEDn • VLEDn
∑
n
n=0
to limit the total power dissipation
LED(NOM)
where I is the power input V quiescent current, I
VIN
IN
VCC
is the V supply current, and V
is the LED pin volt-
CC
LEDn
Cascading Devices and Determining Serial Data
Interface Clock
age for channel n.
From the total power dissipation P
, the junction
TOTAL
In a large LCD backlighting or LED display system, mul-
tiple LT3746 chips can be easily cascaded to drive all the
LED strings. The LT3746 adopts a 6-wire topology, which
balances the internal clock skew and matches the external
trace capacitance with an easy PCB layout.
temperature T can be calculated as:
J
TJ =TA +PTOTAL • θJA
Keep T below the maximum operating junction tempera-
J
The minimum serial data interface clock frequency f
ture 125°C.
SCKI
for a large display system can be calculated as:
fSCKI = NLT3746 •386 •fREFRESH
3746f
25
LT3746
Typical applicaTion
V
IN
10V TO 30V
0.47µF
16V
4.7µF
50V
V
CAP
GATE
IN
EN/UVLO
EN
M1
L1
22µH
4V MAXIMUM OUTPUT VOLTAGE
33mΩ
100k
V
CC
3V TO 5.5V
V
CC
D1
23.2k
10k
10µF
10V
SYNC
C1
220µF
GND
RT
SS
ISP
ISN
LT3746
105k
10nF
FB
I
SET
LED00
LED01
LED02
LED03
LED04
T
SET
60.4k
32.4k
409.6kHz CLOCK
PWMCK
LED05
.
.
.
LED26
LED27
LED28
LED29
LED30
LED31
SCKI
SDI
SCKO
SDO
TTL/CMOS
TTL/CMOS
LDI
LDO
3746 TA02
M1: VISHAY Si9407BDY
D1: DIODES DFLS160
L1: WÜRTH ELECTRONIK 7447779122
C1: SANYO 6TPE220MI
Figure 7. 32-Channel LED Driver, 500kHz Buck, 1 LED 10mA to 30mA per Channel, 100Hz 12-Bit Dimming
3746f
26
LT3746
package DescripTion
UHH Package
56-Lead Plastic QFN (5mm × 9mm)
(Reference LTC DWG # 05-08-1727 Rev A)
0.70 0.05
5.50 0.05
(2 SIDES)
4.10 0.05
(2 SIDES)
3.60 REF
(2 SIDES)
3.45 0.05
7.13 0.05
PACKAGE
OUTLINE
0.20 0.05
0.40 BSC
6.80 REF (2 SIDES)
8.10 0.05 (2 SIDES)
9.50 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
0.00 – 0.05
5.00 0.10
(2 SIDES)
3.60 REF
55 56
0.40 0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
9.00 0.10
(2 SIDES)
6.80 REF
7.13 0.10
3.45 0.10
(UH) QFN 0406 REV A
0.200 REF
0.20 0.05
0.40 BSC
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.200 REF
0.00 – 0.05
0.75 0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3746f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
tionthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LT3746
Typical applicaTion
V
IN
13V TO 42V
0.47µF
16V
4.7µF
50V
V
CAP
GATE
IN
EN
EN/UVLO
M1
L1
22µH
11V MAXIMUM OUTPUT VOLTAGE
33mΩ
100k
V
CC
3V TO 5.5V
V
CC
D1
80.6k
10k
10µF
10V
SYNC
C1
2 × 47µF
GND
RT
SS
ISP
ISN
LT3746
46.4k
60.4k
10nF
FB
I
SET
LED00
LED01
T
SET
32.4k
LED02
.
.
.
2.048MHz CLOCK
PWMCK
LED29
LED30
LED31
SCKI
SDI
SCKO
SDO
M1: VISHAY Si9407BDY
D1: DIODES DFLS160
L1: WÜRTH ELECTRONIK 7447779122
C1: SANYO 16TQC47M
TTL/CMOS
TTL/CMOS
LDI
LDO
3746 TA03
Figure 8. 32-Channel LED Driver, 1MHz Buck, 3 LEDs 10mA to 30mA per Channel, 500Hz 12-Bit Dimming
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
V : 2.8V to 16V, V
LT3476
LT3486
LT3496
LT3595
LT3598
LT3599
LT3754
LT3755/-1
LT3756/-1
LT3760
Quad Output 1.5A, 2MHz High Current LED Driver with
= 36, True Color PWM Dimming = 1000:1,
IN
OUT(MAX)
OUT(MAX)
1,000:1 Dimming
I
< 10µA, 5mm × 7mm QFN-10 Package
SD
Dual 1.3A , 2MHz High Current LED Driver
V : 2.5V to 24V, V
= 36, True Color PWM Dimming = 1000:1,
IN
SD
I
< 1µA, 5mm × 3mm DFN-16 TSSOP-16E Package
Triple Output 750mA, 2.1 MHz High Current LED Driver
with 3,000:1 Dimming
V : 3V to 30V, V
SD
= 60, True Color PWM Dimming = 3000:1,
OUT(MAX)
IN
I
< 1µA, 4mm × 5mm QFN-28 Package
45V, 2.5MHz 16-Channel Full Featured LED Driver
44V, 1.5A, 2.5MHz Boost 6-Channel 30mA LED Driver
44V, 2A, 2.5MHz Boost 4-Channel 120mA LED Driver
V : 4.5V to 45V, V
= 45, True Color PWM Dimming = 5000:1,
OUT(MAX)
IN
SD
I
< 1µA, 5mm × 9mm QFN-56 Package
V : 3V to 40V, V
SD
= 44, True Color PWM Dimming = 1000:1,
IN
OUT(MAX)
I
< 1µA, 4mm × 4mm QFN-24 Package
V : 3V to 40V, V
SD
= 44, True Color PWM Dimming = 1000:1,
IN
OUT(MAX)
I
< 1µA, 4mm × 4mm QFN-24 Package
60V, 1MHz Boost 16-Channel 50mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8% Current Matching
V : 4.5V to 40V, V
= 60, True Color PWM Dimming = 3000:1,
IN
SD
OUT(MAX)
I
< 1µA, 5mm × 5mm QFN-32 Package
High Side 40V, 1MHz LED Controller with True Color
3,000:1 PWM Dimming
V : 4.5V to 40V, V
= 60, True Color PWM Dimming = 3000:1,
IN
SD
OUT(MAX)
I
< 1µA, 3mm × 3mm QFN-16 MSOP-16E Package
High Side 100V, 1MHz LED Controller with True Color
3,000:1 PWM Dimming
V : 6V to 100V, V
SD
= 100, True Color PWM Dimming = 3000:1,
OUT(MAX)
IN
I
< 1µA, 3mm × 3mm QFN-16 MSOP-16E Package
60V, 1MHz Boost 8-Channel 100mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8% Current Matching
V : 4.5V to 40V, V
= 60, True Color PWM Dimming = 3000:1,
OUT(MAX)
IN
SD
I
< 1µA, TSSOP-28E Package
3746f
LT 0311 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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