LT3758A_15_技术文档

LT3758/LT3758A

High Input Voltage,

Boost, Flyback, SEPIC and

Inverting Controller

FeAtures

Description

The LT^®3758/LT3758A are wide input range, current

mode, DC/DC controllers which are capable of generating

either positive or negative output voltages. They can be

configured as either a boost, flyback, SEPIC or inverting

converter. The LT3758/LT3758A drive a low side external

N-channelpowerMOSFETfromaninternalregulated7.2V

supply. The fixed frequency, current-mode architecture

results in stable operation over a wide range of supply

and output voltages.

n

Wide Input Voltage Range: 5.5V to 100V

n

Positive or Negative Output Voltage Programming

with a Single Feedback Pin

n

Current Mode Control Provides Excellent Transient

Response

n

Programmable Operating Frequency (100kHz to

1MHz) with One External Resistor

n

Synchronizable to an External Clock

n

Low Shutdown Current < 1µA

n

Internal 7.2V Low Dropout Voltage Regulator

The operating frequency of LT3758/LT3758A can be set

with an external resistor over a 100kHz to 1MHz range,

and can be synchronized to an external clock using the

SYNC pin. A minimum operating supply voltage of 5.5V,

and a low shutdown quiescent current of less than 1µA,

make the LT3758/LT3758A ideally suited for battery-

powered systems.

n

Programmable Input Undervoltage Lockout with

Hysteresis

Programmable Soft-Start

Small 10-Lead DFN (3mm × 3mm) and

MSOPE Packages

n

ApplicAtions

The LT3758/LT3758A feature soft-start and frequency

foldbackfunctionstolimitinductorcurrentduringstart-up

and output short-circuit. The LT3758A has improved load

transient performance compared to the LT3758.

n

Automotive

n

Telecom

n

Industrial

L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks

and No R

and ThinSOT are trademarks of Linear Technology Corporation. All other

SENSE

trademarks are the property of their respective owners. Patents pending.

typicAl ApplicAtion

12V Output Nonisolated Flyback Power Supply

D1

V

12V

1.2A

IN

OUT

36V TO

72V

0.022µF

100V

C

IN

6.2k

2.2µF

100V

X7R

1M

T1

1,2,3

(SERIES)

4,5,6

(PARALLEL)

V

IN

D

SN

SHDN/UVLO

44.2k

SW

LT3758

105k

1%

SYNC

GATE

M1

SENSE

RT

SS

FBX

63.4k

200kHz

V

GND INTV

CC

C

1N4148

5.1Ω

0.47µF

C

4.7µF

10V

VCC

10k

10nF

C

47µF

X5R

OUT

15.8k

1%

100pF

0.030Ω

X5R

3758 TA01

3758afd

1

LT3758/LT3758A

Absolute MAxiMuM rAtings ^{(Note 1)}

V , SHDN/UVLO (Note 7) ......................................100V

Operating Junction Temperature Range (Notes 2, 8)

LT3758E/LT3758AE........................... –40°C to 125°C

LT3758I/LT3758AI............................. –40°C to 125°C

LT3758H/LT3758AH .......................... –40°C to 150°C

LT3758MP/LT3758AMP..................... –55°C to 150°C

Storage Temperature Range

IN

INTV ....................................................V + 0.3V, 20V

CC

IN

GATE........................................................ INTV + 0.3V

CC

SYNC ..........................................................................8V

V , SS.........................................................................3V

C

RT

1.5V

...............................................................................................

SENSE.................................................................... 0.3V

FBX ................................................................. –6V to 6V

DFN.................................................... –65°C to 125°C

MSOP ................................................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MSOP ...............................................................300°C

pin conFigurAtion

TOP VIEW

V

1

2

3

4

5

10

9

V

IN

C

V

FBX

SS

RT

SYNC

1

2

3

4

5

10

9

V

IN

C

FBX

SS

SHDN/UVLO

11

8

INTV

8

INTV

CC

7

6

GATE

RT

7

GATE

SENSE

SYNC

6

SENSE

MSE PACKAGE

10-LEAD PLASTIC MSOP

= 150°C, θ = 40°C/W

JA

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

DD PACKAGE

T

JMAX

10-LEAD (3mm × 3mm) PLASTIC DFN

= 125°C, θ = 43°C/W

JA

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

T

JMAX

orDer inForMAtion

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

LDNK

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT3758EDD#PBF

LT3758EDD#TRPBF

LT3758IDD#TRPBF

LT3758EMSE#TRPBF

LT3758IMSE#TRPBF

LT3758HMSE#TRPBF

LT3758MPMSE#TRPBF

LT3758AEDD#TRPBF

LT3758AIDD#TRPBF

LT3758AEMSE#TRPBF

LT3758AIMSE#TRPBF

LT3758AHMSE#TRPBF

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

10-Lead (3mm × 3mm) Plastic DFN

10-Lead (3mm × 3mm) Plastic MSOP

10-Lead (3mm × 3mm) Plastic DFN

10-Lead (3mm × 3mm) Plastic MSOP

LT3758IDD#PBF

LDNK

LT3758EMSE#PBF

LT3758IMSE #PBF

LT3758HMSE#PBF

LT3758MPMSE #PBF

LT3758AEDD#PBF

LT3758AIDD#PBF

LT3758AEMSE#PBF

LT3758AIMSE#PBF

LT3758AHMSE#PBF

LT3758AMPMSE#PBF

LTDNM

LGGS

LTGGK

LT3758AMPMSE#TRPBF LTGGK

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3758afd

2

LT3758/LT3758A

electricAl chArActeristics ^Thel denotes the specifications which apply over the full operating temp-

erature range, otherwise specifications are at T_A= 25°C. V_IN= 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Operating Range

5.5

100

V

IN

V

Shutdown I

SHDN/UVLO = 0V

SHDN/UVLO = 1.15V

0.1

1

6

µA

Q

V

Operating I

V = 0.3V, R = 41.2k

1.75

350

110

–65

2.2

400

120

mA

µA

IN

Q

C

T

Operating I with Internal LDO Disabled

V = 0.3V, R = 41.2k, INTV = 7.5V

C T CC

IN

Q

l

SENSE Current Limit Threshold

SENSE Input Bias Current

Error Amplifier

100

mV

µA

Current Out of Pin

l

FBX Regulation Voltage (V

FBX Overvoltage Lockout

FBX Pin Input Current

)

FBX > 0V (Note 3)

FBX < 0V (Note 3)

1.569

1.6

1.631

V

FBX(REG)

–0.816 –0.800 –0.784

FBX > 0V (Note 4)

FBX < 0V (Note 4)

6

7

8

11

10

14

%

FBX = 1.6V (Note 3)

FBX = –0.8V (Note 3)

70

100

10

nA

–10

Transconductance g (∆I /∆FBX)

(Note 3)

230

5

µS

m

VC

V Output Impedance

C

MΩ

V

Line Regulation (∆V /[∆V • V

])

FBX > 0V, 5.5V < V < 100V (Notes 3, 6)

0.006

0.005

0.025

0.03

%/V

FBX

IN

FBX(REG)

IN

FBX < 0V, 5.5V < V < 100V (Notes 3, 6)

IN

V Current Mode Gain (∆V /∆V

)

5.5

V/V

µA

C

VC

SENSE

V Source Current

C

V = 1.5V

C

–15

V Sink Current

C

FBX = 1.7V

FBX = –0.85V

12

11

µA

Oscillator

Switching Frequency

R = 41.2k to GND, FBX = 1.6V

270

300

100

330

0.4

kHz

T

R = 140k to GND, FBX = 1.6V

T

R = 10.5k to GND, FBX = 1.6V

1000

T

RT Voltage

FBX = 1.6V

1.2

220

V

ns

Minimum Off-Time

Minimum On-Time

SYNC Input Low

SYNC Input High

SS Pull-Up Current

Low Dropout Regulator

1.5

SS = 0V, Current Out of Pin

–10

7.2

µA

V

l

INTV Regulation Voltage

7

7.4

4.7

CC

INTV Undervoltage Lockout Threshold

Falling INTV

4.3

4.5

0.5

V

CC

UVLO Hysteresis

INTV Overvoltage Lockout Threshold

17.5

V

CC

INTV Current Limit

V

= 100V

= 20V

11

–1

16

50

22

mA

CC

IN

INTV Load Regulation (∆V

/V

)

0 < I

< 10mA, V = 8V

–0.4

0.005

500

%

%/V

mV

CC

INTVCC INTVCC

INTVCC

IN

INTV Line Regulation (∆V

/[∆V • V

]) 8V < V < 100V

0.02

CC

INTVCC

IN

INTVCC

IN

Dropout Voltage (V – V

)

V

IN

= 6V, I

= 10mA

INTVCC

IN

INTVCC

3758afd

3

LT3758/LT3758A

electricAl chArActeristics ^Thel denotes the specifications which apply over the full operating temp-

erature range, otherwise specifications are at T_A= 25°C. V_IN= 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.

PARAMETER

INTV Current in Shutdown

CONDITIONS

SHDN/UVLO = 0V, INTV = 8V

MIN

TYP

MAX

UNITS

µA

16

CC

INTV Voltage to Bypass Internal LDO

7.5

V

CC

Logic Inputs

l

SHDN/UVLO Threshold Voltage Falling

SHDN/UVLO Input Low Voltage

SHDN/UVLO Pin Bias Current Low

SHDN/UVLO Pin Bias Current High

Gate Driver

V

= INTV = 8V

1.17

1.7

1.22

1.27

0.4

V

IN

CC

I

Drops Below 1µA

VIN

SHDN/UVLO = 1.15V

SHDN/UVLO = 1.33V

2

2.5

µA

nA

10

100

t Gate Driver Output Rise Time

C = 3300pF (Note 5), INTV = 7.5V

22

20

ns

V

r

L

CC

t Gate Driver Output Fall Time

f

C = 3300pF (Note 5), INTV = 7.5V

L CC

Gate Output Low (V

)

OL

0.05

Gate Output High (V

)

OH

INTV

V

CC

–0.05

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: The LT3758/LT3758A are tested in a feedback loop which servos

V

FBX

to the reference voltages (1.6V and –0.8V) with the V pin forced

C

to 1.3V.

Note 4: FBX overvoltage lockout is measured at V

relative

FBX(OVERVOLTAGE)

Note 2: The LT3758E/LT3758AE are guaranteed to meet performance

specifications from the 0°C to 125°C junction temperature. Specifications

over the –40°C to 125°C operating junction temperature range are

assured by design, characterization and correlation with statistical process

controls. The LT3758I/LT3758AI are guaranteed over the full –40°C to

125°C operating junction temperature range. The LT3758H/LT3758AH are

guaranteed over the full –40°C to 150°C operating junction temperature

range. High junction temperatures degrade operating lifetimes. Operating

lifetime is derated at junction temperatures greater than 125°C. The

LT3758MP/LT3758AMP are 100% tested and guaranteed over the full

–55°C to 150°C operating junction temperature range.

to regulated V

.

FBX(REG)

Note 5: Rise and fall times are measured at 10% and 90% levels.

Note 6: SHDN/UVLO = 1.33V when V = 5.5V.

IN

Note 7: For V below 6V, the SHDN/UVLO pin must not exceed V .

IN

Note 8: The LT3758/LT3758A include overtemperature protection that

is intended to protect the device during momentary overload conditions.

Junction temperature will exceed the maximum operating junction

temperature when overtemperature protection is active. Continuous

operation above the specified maximum operating junction temperature

may impair device reliability.

3758afd

4

LT3758/LT3758A

typicAl perForMAnce chArActeristics ^T_A^{= 25°C, unless otherwise noted.}

Positive Feedback Voltage

vs Temperature, V_IN

Negative Feedback Voltage

vs Temperature, V_IN

1605

1600

1595

1590

1585

1580

–790

–792

–794

–796

–798

–800

–802

–804

V

= INTV = 5.5V

CC

IN

V

= 100V

SHDN/UVLO = 1.33V

IN

V

= 24V

IN

V

= 8V

IN

V

= 8V

IN

V

= 100V

IN

V

= INTV = 5.5V

CC

IN

SHDN/UVLO = 1.33V

V

IN

= 24V

–75 –50 –25

0

25 50 75 100 125 150

–75 –50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3758 G01

3758 G02

Quiescent Current

vs Temperature, V_IN

Dynamic Quiescent Current

vs Switching Frequency

1.9

1.8

1.7

1.6

1.5

35

30

25

20

15

10

5

C

= 3300pF

GATE

V

= 100V

IN

V

= 24V

IN

V

= INTV = 5.5V

CC

IN

0

–75 –50 –25

0

25 50 75 100 125 150

0

300 400 500 600 700 800 900 1000

100 200

TEMPERATURE (°C)

SWITCHING FREQUENCY (kHz)

3758 G03

3758 G04

Normalized Switching

Frequency vs FBX

R_Tvs Switching Frequency

120

100

80

60

40

20

0

1000

100

10

–0.8

0

0.4

0.8

1.2

1.6

–0.4

0

300 400 500 600 700 800 900 1000

100 200

FBX VOLTAGE (V)

SWITCHING FREQUENCY (kHz)

3758 G05

3758 G06

3758afd

5

LT3758/LT3758A

typicAl perForMAnce chArActeristics ^T_A^{= 25°C, unless otherwise noted.}

Switching Frequency

vs Temperature

SENSE Current Limit Threshold

vs Temperature

120

115

110

105

100

330

320

310

300

290

280

270

R

= 41.2K

T

–75 –50 –25

0

25 50 75 100 125 150

–75 –50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3758 G08

3758 G07

SENSE Current Limit Threshold

vs Duty Cycle

SHDN/UVLO Threshold

vs Temperature

1.28

1.26

1.24

1.22

1.20

1.18

115

110

105

100

95

SHDN/UVLO RISING

SHDN/UVLO FALLING

0

20

40

60

80

100

–75 –50 –25

0

25 50 75 100 125 150

DUTY CYCLE (%)

TEMPERATURE (°C)

3758 G10

3758 G09

SHDN/UVLO Hysteresis Current

vs Temperature

SHDN/UVLO Current vs Voltage

2.4

2.2

2.0

1.8

1.6

50

40

30

20

10

0

–75 –50 –25

0

25 50 75 100 125 150

0

20

40

60

80

100

TEMPERATURE (°C)

SHDN/UVLO VOLTAGE (V)

3758 G12

3758 G11

3758afd

6

LT3758/LT3758A

T_A= 25°C, unless otherwise noted.

typicAl perForMAnce chArActeristics

INTV_CCMinimum Output

Current vs V_IN

INTV_CCvs Temperature

INTV_CCLoad Regulation

7.4

7.3

7.2

7.1

7.0

7.3

7.2

45

40

35

30

25

20

15

10

5

T = 150°C

J

V

= 8V

IN

7.1

7

INTV = 4.7V

CC

6.9

6.8

INTV = 6V

CC

0

1

10

100

0

10

15

20

25

–75 –50 –25

0

25 50 75 100 125 150

5

V

(V)

TEMPERATURE (°C)

IN

INTV LOAD (mA)

CC

3758 G13

3758 G14

3758 G15

INTV_CCDropout Voltage

vs Current, Temperature

Gate Drive Rise

and Fall Time vs C_L

INTV_CCLine Regulation

7.30

7.25

7.20

7.15

7.10

1000

900

800

700

600

500

400

300

200

100

0

90

80

70

60

50

40

30

20

10

0

V

= 6V

INTV = 7.2V

CC

IN

150°C

125°C

75°C

25°C

RISE TIME

FALL TIME

0°C

–55°C

0

10 20 30 40 50 60 70 80 90 100

(V)

0

5

10

15

(nF)

20

25

30

0

2

4

6

8

10

V

INTV LOAD (mA)

C

IN

CC

L

3758 G16

3758 G17

3758 G18

Gate Drive Rise

and Fall Time vs INTV_CC

FBX Frequency Foldback

Waveforms During Overcurrent

Typical Start-Up Waveforms

30

25

20

15

10

5

C

= 3300pF

V = 48V

IN

V

= 48V

L

IN

V

OUT

20V/DIV

RISE TIME

V

OUT

SW

FALL TIME

10V/DIV

50V/DIV

I

+ I

L1A L1B

I

+ I

L1A L1B

1A/DIV

2A/DIV

3758 G20

3758 G21

2ms/DIV

50µs/DIV

SEE TYPICAL APPLICATION: 18V TO 72V INPUT,

24V OUTPUT SEPIC CONVERTER

SEE TYPICAL APPLICATION: 18V TO 72V INPUT,

24V OUTPUT SEPIC CONVERTER

0

9

12

15

3

6

INTV (V)

CC

3758 G19

3758afd

7

LT3758/LT3758A

pin Functions

V (Pin 1): Error Amplifier Compensation Pin. Used to

GATE (Pin 7): N-Channel MOSFET Gate Driver Output.

Switches between INTV and GND. Driven to GND when

C

stabilize the voltage loop with an external RC network.

CC

IC is shut down, during thermal lockout or when INTV

CC

FBX (Pin 2): Positive and Negative Feedback Pin. Re-

ceives the feedback voltage from the external resistor

divider across the output. Also modulates the switching

frequency during start-up and fault conditions when FBX

is close to GND.

is above or below the overvoltage or UV thresholds,

respectively.

INTV (Pin 8): Regulated Supply for Internal Loads and

CC

Gate Driver. Supplied from V and regulated to 7.2V (typi-

IN

cal). INTV must be bypassed with a minimum of 4.7µF

CC

SS(Pin3):Soft-StartPin.Thispinmodulatescompensation

capacitor placed close to pin. INTV can be connected

CC

pin voltage (V ) clamp. The soft-start interval is set with

C

directly to V , if V is less than 17.5V. INTV can also

IN

CC

an external capacitor. The pin has a 10µA (typical) pull-up

current source to an internal 2.5V rail. The soft-start pin

is reset to GND by an undervoltage condition at SHDN/

be connected to a power supply whose voltage is higher

than 7.5V, and lower than V , provided that supply does

IN

not exceed 17.5V.

UVLO, an INTV undervoltage or overvoltage condition

CC

or an internal thermal lockout.

SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect

Pin. An accurate 1.22V (nominal) falling threshold with

externally programmable hysteresis detects when power

is okayto enable switching. Rising hysteresisis generated

by the external resistor divider and an accurate internal

2µA pull-down current. An undervoltage condition resets

sort-start. Tie to 0.4V, or less, to disable the device and

RT (Pin 4): Switching Frequency Adjustment Pin. Set the

frequency using a resistor to GND. Do not leave this pin

open.

SYNC (Pin 5): Frequency Synchronization Pin. Used to

synchronize the switching frequency to an outside clock.

If this feature is used, an R resistor should be chosen to

reduce V quiescent current below 1µA.

T

IN

programaswitchingfrequency20%slowerthantheSYNC

pulse frequency. Tie the SYNC pin to GND if this feature is

not used. SYNC is bypassed when FBX is close to GND.

V (Pin 10): Input Supply Pin. Must be locally bypassed

IN

with a 0.22µF, or larger, capacitor placed close to the pin.

ExposedPad(Pin11):Ground. Thispinalsoservesasthe

negativeterminalofthecurrentsenseresistor.Theexposed

pad must be soldered directly to the local ground plane.

SENSE (Pin 6): The Current Sense Input for the Control

Loop. Kelvin connect this pin to the positive terminal of

theswitchcurrentsenseresistorinthesourceoftheNFET.

The negative terminal of the current sense resistor should

be connected to GND plane close to the IC.

3758afd

8

LT3758/LT3758A

block DiAgrAM

C

DC

L1

D1

V

IN

V

OUT

R4

R3

+

C

IN

L2

C

OUT1

C

R2

R1

OUT2

+

•

FBX

9

10

V

IN

SHDN/UVLO

A10

–

+

I

S1

2.5V

2µA

1.22V

2.5V

INTERNAL

REGULATOR

AND UVLO

I

S3

CURRENT

LIMIT

I

S2

17.5V

V

C

10µA

+

–

UVLO

A9

1

7.2V LDO

INTV

Q3

CC

C

VCC

C

C2

8

7

G4

G3

A8

R

C

+

–

C

C1

5V UP

A11

A12

1.72V

4.5V DOWN

–

+

TSD

165˚C

DRIVER

G6

SR1

V

C

–

+

GATE

–

+

G5

G2

A7

R

O

M1

–0.88V

S

Q2

PWM

COMPARATOR

110mV

–

+

1.6V

+

–

A6

A5

A1

SLOPE

RAMP

V

ISENSE

FBX

SENSE

FBX

2

6

+

–

+

–

A2

RAMP

R

SENSE

GND

–0.8V

GENERATOR

1.28V

–

+

11

A3

100kHz-1MHz

OSCILLATOR

G1

1.2V

+

FREQUENCY

FOLDBACK

+

A4

Q1

–

R5

8k

FREQ

PROG

D3

D2

SS

3

SYNC

RT

5

4

3758 F01

C

R

T

SS

Figure 1. LT3758 Block Diagram Working as a SEPIC Converter

3758afd

9

LT3758/LT3758A

ApplicAtions inForMAtion

Main Control Loop

The LT3758 has overvoltage protection functions to

protect the converter from excessive output voltage

overshoot during start-up or recovery from a short-circuit

condition. An overvoltage comparator A11 (with 20mV

hysteresis) senses when the FBX pin voltage exceeds the

positive regulated voltage (1.6V) by 8% and provides a

reset pulse. Similarly, an overvoltage comparator A12

(with 10mV hysteresis) senses when the FBX pin voltage

exceeds the negative regulated voltage (–0.8V) by 11%

and provides a reset pulse. Both reset pulses are sent to

the main RS latch (SR1) through G6 and G5. The power

MOSFET switch M1 is actively held off for the duration of

an output overvoltage condition.

The LT3758 uses a fixed frequency, current mode control

scheme to provide excellent line and load regulation. Op-

eration can be best understood by referring to the Block

Diagram in Figure 1.

ThestartofeachoscillatorcyclesetstheSRlatch(SR1)and

turns on the external power MOSFET switch M1 through

driver G2. The switch current flows through the external

current sensing resistor R

and generates a voltage

SENSE

proportional to the switch current. This current sense

voltage V (amplified by A5) is added to a stabilizing

ISENSE

slope compensation ramp and the resulting sum (SLOPE)

isfedintothepositiveterminalofthePWM comparatorA7.

When SLOPE exceeds the level at the negative input of A7

Programming Turn-On and Turn-Off Thresholds with

the SHDN/UVLO Pin

(V pin), SR1 is reset, turning off the power switch. The

C

level at the negative input of A7 is set by the error amplifier

A1 (or A2) and is an amplified version of the difference

between the feedback voltage (FBX pin) and the reference

voltage (1.6V or –0.8V, depending on the configuration).

In this manner, the error amplifier sets the correct peak

switch current level to keep the output in regulation.

The SHDN/UVLO pin controls whether the LT3758 is

enabled or is in shutdown state. A micropower 1.22V

reference, a comparator A10 and a controllable current

sourceI allowtheusertoaccuratelyprogramthesupply

S1

voltage at which the IC turns on and off. The falling value

can be accurately set by the resistor dividers R3 and R4.

When SHDN/UVLO is above 0.4V, and below the 1.22V

TheLT3758hasaswitchcurrentlimitfunction.Thecurrent

sense voltage is input to the current limit comparator A6.

If the SENSE pin voltage is higher than the sense current

threshold, the small pull-down current source I (typical

S1

2µA) is active.

limitthresholdV

(110mV, typical), A6willreset

SENSE(MAX)

SR1 and turn off M1 immediately.

The purpose of this current is to allow the user to program

therisinghysteresis.TheBlockDiagramofthecomparator

and the external resistors is shown in Figure 1. The typical

falling threshold voltage and rising threshold voltage can

be calculated by the following equations:

The LT3758 is capable of generating either positive or

negative output voltage with a single FBX pin. It can be

configured as a boost, flyback or SEPIC converter to gen-

erate positive output voltage, or as an inverting converter

to generate negative output voltage. When configured as

a SEPIC converter, as shown in Figure 1, the FBX pin is

pulled up to the internal bias voltage of 1.6V by a volt-

(R3+ R4)

V_VIN,FALLING= 1.22•

R4

V_VIN,RISING= 2µA •R3+ V_IN,FALLING

age divider (R1 and R2) connected from V

to GND.

OUT

For applications where the SHDN/UVLO pin is only used

as a logic input, the SHDN/UVLO pin can be connected

Comparator A2 becomes inactive and comparator A1

performstheinvertingamplificationfromFBXtoV .When

C

directly to the input voltage V through a 1k resistor for

IN

the LT3758 is in an inverting configuration, the FBX pin

always-on operation.

is pulled down to –0.8V by a voltage divider connected

from V

to GND. Comparator A1 becomes inactive and

OUT

comparator A2 performs the noninverting amplification

from FBX to V .

C

3758afd

10

LT3758/LT3758A

ApplicAtions inForMAtion

INTV Regulator Bypassing and Operation

The LT3758 uses packages with an Exposed Pad for en-

hanced thermal conduction. With proper soldering to the

Exposed Pad on the underside of the package and a full

copper plane underneath the device, thermal resistance

CC

An internal, low dropout (LDO) voltage regulator produces

the 7.2V INTV supply which powers the gate driver, as

CC

shown in Figure 1. The LT3758 contains an undervoltage

(θ )willbeabout43°C/WfortheDDpackageand40°C/W

JA

lockout comparator A8 and an overvoltage lockout com-

fortheMSEpackage. Foranambientboardtemperatureof

paratorA9fortheINTV supply.TheINTV undervoltage

CC

T = 70°C and maximum junction temperature of 125°C,

A

(UV) threshold is 4.5V (typical), with 0.5V hysteresis, to

ensure that the MOSFETs have sufficient gate drive voltage

before turning on. The logic circuitry within the LT3758 is

the maximum I

be calculated as:

(I

) of the DD package can

DRIVE DRIVE(MAX)

also powered from the internal INTV supply.

(T_J− T_A)

(θ_JA• V_IN)

1.28W

V_IN

CC

I_DRIVE(MAX)

=

− I_Q=

− 1.6mA

The INTV overvoltage threshold is set to be 17.5V

CC

(typical) to protect the gate of the power MOSFET. When

The LT3758 has an internal INTV

I

current limit

CC DRIVE

INTV is below the UV threshold, or above the overvolt-

CC

function to protect the IC from excessive on-chip power

age threshold, the GATE pin will be forced to GND and the

dissipation. The I

current limit decreases as the V

DRIVE

IN

soft-start operation will be triggered.

increases(seetheINTV MinimumOutputCurrentvsV

CC

graphintheTypicalPerformanceCharacteristicssection).

If I reaches the current limit, INTV voltage will fall

The INTV regulator must be bypassed to ground im-

CC

mediately adjacent to the IC pins with a minimum of 4.7µF

ceramic capacitor. Good bypassing is necessary to supply

the high transient currents required by the MOSFET gate

driver.

DRIVE

CC

and may trigger the soft-start.

BasedontheprecedingequationandtheINTV Minimum

CC

Output Current vs V graph, the user can calculate the

IN

maximum MOSFET gate charge the LT3758 can drive at

In an actual application, most of the IC supply current is

used to drive the gate capacitance of the power MOSFET.

Theon-chippowerdissipationcanbeasignificantconcern

when a large power MOSFET is being driven at a high fre-

a given V and switch frequency. A plot of the maximum

IN

Q vs V at different frequencies to guarantee a minimum

G

IN

4.7V INTV is shown in Figure 2.

CC

quency and the V voltage is high. It is important to limit

IN

the power dissipation through selection of MOSFET and/

or operating frequency so the LT3758 does not exceed its

maximum junction temperature rating. The junction tem-

140

300kHz

120

100

80

60

40

20

0

peratureT canbeestimatedusingthefollowingequations:

J

T = T + P • θ

JA

J

A

IC

T = ambient temperature

A

1MHz

θ

= junction-to-ambient thermal resistance

JA

P = IC power consumption

IC

10

(V)

100

1

= V • (I + I )

DRIVE

IN

Q

V

IN

3758 F02

I = V operation I = 1.6mA

Q

IN

Q

Figure 2. Recommended Maximum Q_Gvs V_INat Different

Frequencies to Ensure INTV_CCHigher Than 4.7V

I

= average gate drive current = f • Q

G

DRIVE

f = switching frequency

Q = power MOSFET total gate charge

G

3758afd

11

LT3758/LT3758A

ApplicAtions inForMAtion

AsillustratedinFigure2, atrade-offbetweentheoperating

frequencyandthesizeofthepowerMOSFETmaybeneeded

in order to maintain a reliable IC junction temperature.

Prior to lowering the operating frequency, however, be

sure to check with power MOSFET manufacturers for their

A resistor R can be connected, as shown in Figure 3, to

VCC

limit the inrush current from V . Regardless of whether

OUT

or not the INTV pin is connected to an external voltage

CC

source, it is always necessary to have the driver circuitry

bypassed with a 4.7µF low ESR ceramic capacitor to

most recent low Q , low R

devices. Power MOSFET

ground immediately adjacent to the INTV and GND pins.

G

DS(ON)

CC

manufacturingtechnologiesarecontinuallyimproving,with

newer and better performance devices being introduced

almost yearly.

Operating Frequency and Synchronization

The choice of operating frequency may be determined

by on-chip power dissipation, otherwise it is a trade-off

between efficiency and component size. Low frequency

operation improves efficiency by reducing gate drive cur-

rent and MOSFET and diode switching losses. However,

lower frequency operation requires a physically larger

inductor. Switching frequency also has implications for

loopcompensation.TheLT3758usesaconstant-frequency

architecture that can be programmed over a 100kHz to

1000kHz range with a single external resistor from the

RT pin to ground, as shown in Figure 1. The RT pin must

have an external resistor to GND for proper operation of

An effective approach to reduce the power consumption

of the internal LDO for gate drive is to tie the INTV pin

CC

to an external voltage source high enough to turn off the

internal LDO regulator.

If the input voltage V does not exceed the absolute

IN

maximum rating of both the power MOSFET gate-source

voltage(V )andtheINTV overvoltagelockoutthreshold

GS

CC

voltage (17.5V), the INTV pin can be shorted directly

CC

to the V pin. In this condition, the internal LDO will be

IN

turned off and the gate driver will be powered directly

from the input voltage V . With the INTV pin shorted to

IN

CC

the LT3758. A table for selecting the value of R for a given

operating frequency is shown in Table 1.

T

V , however, a small current (around 16µA) will load the

IN

INTV in shutdown mode. For applications that require

CC

Table 1. Timing Resistor (R_T) Value

the lowest shutdown mode input supply current, do not

connect the INTV pin to V .

SWITCHING FREQUENCY (kHz)

R (kΩ)

T

CC

IN

100

200

300

400

500

600

700

800

900

1000

140

63.4

41.2

30.9

24.3

19.6

16.5

14

In SEPIC or flyback applications, the INTV pin can be

CC

connected to the output voltage V

through a blocking

OUT

diode, as shown in Figure 3, if V

conditions:

meets the following

OUT

1. V

2. V

3. V

< V (pin voltage)

OUT

IN

< 17.5V

< maximum V rating of power MOSFET

GS

12.1

10.5

LT3758

INTV

D

VCC

R

VCC

V

OUT

CC

TheoperatingfrequencyoftheLT3758canbesynchronized

to an external clock source. By providing a digital clock

signal into the SYNC pin, the LT3758 will operate at the

C

VCC

4.7µF

GND

3758 F03

SYNCclockfrequency.Ifthisfeatureisused,anR resistor

T

should be chosen to program a switching frequency 20%

slowerthanSYNCpulsefrequency. Itisrecommendedthe

SYNC pulse have a minimum pulse width of 200ns. Tie

the SYNC pin to GND if this feature is not used.

3758afd

Figure 3. Connecting INTV_CCto V_OUT

12

LT3758/LT3758A

ApplicAtions inForMAtion

Duty Cycle Consideration

Soft-Start

Switching duty cycle is a key variable defining converter

operation.Assuch,itslimitsmustbeconsidered.Minimum

on-time is the smallest time duration that the LT3758 is

capable of turning on the power MOSFET. This time is

generally about 220ns (typical) (see Minimum On-Time

in the Electrical Characteristics table). In each switching

cycle, the LT3758 keeps the power switch off for at least

220ns (typical) (see Minimum Off-Time in the Electrical

Characteristics table).

The LT3758 contains several features to limit peak switch

currents and output voltage (V ) overshoot during

OUT

start-up or recovery from a fault condition. The primary

purpose of these features is to prevent damage to external

components or the load.

High peak switch currents during start-up may occur in

switching regulators. Since V

is far from its final value,

OUT

the feedback loop is saturated and the regulator tries to

chargetheoutputcapacitorasquicklyaspossible,resulting

in large peak currents. A large surge current may cause

inductor saturation or power switch failure.

The minimum on-time and minimum off-time and the

switching frequency define the minimum and maximum

switching duty cycles a converter is able to generate:

The LT3758 addresses this mechanism with the SS pin.

As shown in Figure 1, the SS pin reduces the power

Minimum duty cycle = minimum on-time • frequency

Maximum duty cycle = 1 – (minimum off-time • frequency)

MOSFET current by pulling down the V pin through

C

Q2. In this way the SS allows the output capacitor to

charge gradually toward its final value while limiting the

start-up peak currents. The typical start-up waveforms

are shown in the Typical Performance Characteristics

Programming the Output Voltage

The output voltage V

is set by a resistor divider, as

OUT

shown in Figure 1. The positive and negative V

by the following equations:

are set

OUT

section. The inductor current I slewing rate is limited by

L

the soft-start function.

R2

R1







Besides start-up (with SHDN/UVLO), soft-start can also

be triggered by the following faults:

V_OUT,POSITIVE= 1.6V • 1+







R2

R1







1. INTV > 17.5V

CC

V_OUT,NEGATIVE= –0.8V • 1+







2. INTV < 4.5V

CC

The resistors R1 and R2 are typically chosen so that

the error caused by the current flowing into the FBX pin

during normal operation is less than 1% (this translates

to a maximum value of R1 at about 158k).

3. Thermal lockout

Any of these three faults will cause the LT3758 to stop

switching immediately. The SS pin will be discharged by

Q3. When all faults are cleared and the SS pin has been

discharged below 0.2V, a 10µA current source I starts

charging the SS pin, initiating a soft-start operation.

In the applications where V

is pulled up by an external

OUT

S2

positivepowersupply,theFBXpinisalsopulledupthrough

theR2andR1network.MakesuretheFBXdoesnotexceed

its absolute maximum rating (6V). The R5, D2, and D3 in

Figure 1 provide a resistive clamp in the positive direction.

To ensure FBX is lower than 6V, choose sufficiently large

R1 and R2 to meet the following condition:

The soft-start interval is set by the soft-start capacitor

selection according to the equation:

1.25V

10µA

T_SS= C_SS

•

R2

R1

R2

8kΩ





6V • 1+

+ 3.5V •

> V_OUT(MAX)









where V

is the maximum V

that is pulled up

OUT(MAX)

by an external power supply.

OUT

3758afd

13

LT3758/LT3758A

ApplicAtions inForMAtion

FBX Frequency Foldback

load transient response, when compared to the LT3758.

New internal circuits ensure that the transient from not

switching to switching at high current can be made in a

few cycles. The optimum values depend on the converter

topology, the component values and the operating condi-

tions (including the input voltage, load current, etc.). To

compensate the feedback loop of the LT3758/LT3758A,

a series resistor-capacitor network is usually connected

When V

is very low during start-up or a GND fault on

OUT

the output, the switching regulator must operate at low

duty cycles to maintain the power switch current within

the current limit range, since the inductor current decay

rate is very low during switch off time. The minimum on-

time limitation may prevent the switcher from attaining a

sufficiently low duty cycle at the programmed switching

frequency. So, the switch current will keep increasing

through each switch cycle, exceeding the programmed

current limit. To prevent the switch peak currents from

exceeding the programmed value, the LT3758 contains

a frequency foldback function to reduce the switching

frequency when the FBX voltage is low (see the Normal-

ized Switching Frequency vs FBX graph in the Typical

Performance Characteristics section).

from the V pin to GND. Figure 1 shows the typical V

C

compensationnetwork.Formostapplications,thecapacitor

should be in the range of 470pF to 22nF, and the resistor

should be in the range of 5k to 50k. A small capacitor is

often connected in parallel with the RC compensation

networktoattenuatetheV voltagerippleinducedfromthe

C

output voltage ripple through the internal error amplifier.

The parallel capacitor usually ranges in value from 10pF to

100pF. A practical approach to design the compensation

network is to start with one ofthe circuitsin thisdata sheet

that is similar to your application, and tune the compensa-

tionnetworktooptimizetheperformance. Stabilityshould

thenbecheckedacrossalloperatingconditions, including

load current, input voltage and temperature.

During frequency foldback, external clock synchroniza-

tion is disabled to prevent interference with frequency

reducing operation.

Thermal Lockout

If LT3758 die temperature reaches 165°C (typical), the

part will go into thermal lockout. The power switch will

be turned off. A soft-start operation will be triggered. The

part will be enabled again when the die temperature has

dropped by 5°C (nominal).

SENSE Pin Programming

For control and protection, the LT3758 measures the

powerMOSFETcurrentbyusingasenseresistor(R

)

SENSE

between GND and the MOSFET source. Figure 4 shows a

typical waveform of the sense voltage (V ) across the

SENSE

Loop Compensation

senseresistor. ItisimportanttouseKelvintracesbetween

the SENSE pin and R , and to place the IC GND as

Loop compensation determinesthe stability and transient

performance. The LT3758/LT3758A use current mode

control to regulate the output which simplifies loop com-

pensation. The LT3758A improves the no-load to heavy

SENSE

close as possible to the GND terminal of the R

proper operation.

for

SENSE

V

SENSE

∆V

V

SENSE = χ • SENSE(MAX)

V

SENSE(PEAK)

SENSE(MAX)

t

DT

S

T

S

3758 F04

Figure 4. The Sense Voltage During a Switching Cycle

3758afd

14

LT3758/LT3758A

ApplicAtions inForMAtion

Due to the current limit function of the SENSE pin, R

APPLICATION CIRCUITS

SENSE

shouldbeselectedtoguaranteethatthepeakcurrentsense

voltageV duringsteadystatenormaloperation

is lower than the SENSE current limit threshold (see the

TheLT3758canbeconfiguredasdifferenttopologies. The

first topology to be analyzed will be the boost converter,

followed by the flyback, SEPIC and inverting converters.

SENSE(PEAK)

Electrical Characteristics table). Given a 20% margin,

V

is set to be 80mV. Then, the maximum

Boost Converter: Switch Duty Cycle and Frequency

SENSE(PEAK)

switch ripple current percentage can be calculated using

the following equation:

The LT3758 can be configured as a boost converter for

the applications where the converter output voltage is

higher than the input voltage. Remember that boost con-

verters are not short-circuit protected. Under a shorted

output condition, the inductor current is limited only by

the input supply capability. For applications requiring a

step-up converter that is short-circuit protected, please

refer to the Applications Information section covering

SEPIC converters.

∆V_SENSE

c =

80mV − 0.5• ∆V_SENSE

c

is used in subsequent design examples to calculate in-

ductor value. ∆V is the ripple voltage across R

.

SENSE

TheLT3758switchingcontrollerincorporates100nstiming

interval to blank the ringing on the current sense signal

immediately after M1 is turned on. This ringing is caused

by the parasitic inductance and capacitance of the PCB

trace, the sense resistor, the diode, and the MOSFET. The

100ns timing interval is adequate for most of the LT3758

applications. In the applications that have very large and

long ringing on the current sense signal, a small RC filter

can be added to filter out the excess ringing. Figure 5

shows the RC filter on the SENSE pin. It is usually suf-

The conversion ratio as a function of duty cycle is:

V_OUT

V_IN1− D

1

=

in continuous conduction mode (CCM).

For a boost converter operating in CCM, the duty cycle

of the main switch can be calculated based on the output

voltage (V ) and the input voltage (V ). The maximum

ficient to choose 22Ω for R and 2.2nF to 10nF for C

.

FLT

OUT

duty cycle (D

minimum input voltage:

IN

Keep R ’s resistance low. Remember that there is 65µA

) occurs when the converter has the

FLT

MAX

(typical) flowing out of the SENSE pin. Adding R will

FLT

affect the SENSE current limit threshold:

V_OUT− V_IN(MIN)

D_MAX

=

V

= 110mV – 65µA • R

SENSE_ILIM

FLT

V_OUT

Discontinuous conduction mode (DCM) provides higher

conversionratiosatagivenfrequencyatthecostofreduced

efficiencies and higher switching currents.

M

1

GATE

LT3758

R

Boost Converter: Inductor and Sense Resistor Selection

FLT

SENSE

For the boost topology, the maximum average inductor

current is:

GND

C

FLT

R

SENSE

1

3758 F05

I_L(MAX)= I_O(MAX)

•

1− D_MAX

Figure 5. The RC Filter on the SENSE Pin

Then, the ripple current can be calculated by:

1

∆I_L= c •I_L(MAX)= c •I_O(MAX)

•

1− D_MAX

3758afd

15

LT3758/LT3758A

ApplicAtions inForMAtion

c

The power MOSFET will see full output voltage, plus a

diode forward voltage, and any additional ringing across

its drain-to-source during its off-time. It is recommended

The constant in the preceding equation represents the

percentage peak-to-peak ripple current in the inductor,

relative to I

.

L(MAX)

to choose a MOSFET whose B

is higher than V

by

VDSS

OUT

Theinductorripplecurrenthasadirecteffectonthechoice

of the inductor value. Choosing smaller values of ∆I

a safety margin (a 10V safety margin is usually sufficient).

L

The power dissipated by the MOSFET in a boost converter is:

requires large inductances and reduces the current loop

gain(theconverterwillapproachvoltagemode).Accepting

2

P

=I

RSS

• R

• D

+ 2 • V • I

OUT L(MAX)

FET

• C

L(MAX) DS(ON) MAX

larger values of ∆I provides fast transient response and

L

• f/1A

allowstheuseoflowinductances,butresultsinhigherinput

The first term in the preceding equation represents the

conduction losses in the device, and the second term, the

current ripple and greater core losses. It is recommended

c

that fall within the range of 0.2 to 0.6.

switching loss. C

is the reverse transfer capacitance,

RSS

Givenanoperatinginputvoltagerange,andhavingchosen

the operating frequency and ripple current in the inductor,

theinductorvalueoftheboostconvertercanbedetermined

using the following equation:

which is usually specified in the MOSFET characteristics.

For maximum efficiency, R and C should be

DS(ON)

RSS

minimized. From a known power dissipated in the power

MOSFET, its junction temperature can be obtained using

the following equation:

V

L = ^IN(MIN)•D_MAX

∆I_L• f

T = T + P • θ = T + P • (θ + θ )

J

A

FET

JA

A

FET

JC

CA

The peak and RMS inductor current are:

T must not exceed the MOSFET maximum junction

J

temperature rating. It is recommended to measure the

MOSFETtemperatureinsteadystatetoensurethatabsolute

maximum ratings are not exceeded.

c

2







I_L(PEAK)= I_L(MAX)• 1+







c²

12

I_L(RMS)= I_L(MAX)• 1+

Boost Converter: Output Diode Selection

To maximize efficiency, a fast switching diode with low

forward drop and low reverse leakage is desirable. The

peak reverse voltage that the diode must withstand is

equal to the regulator output voltage plus any additional

ringing across its anode-to-cathode during the on-time.

The average forward current in normal operation is equal

to the output current, and the peak current is equal to:

Based on these equations, the user should choose the

inductors having sufficient saturation and RMS current

ratings.

Set the sense voltage at I

to be the minimum of the

L(PEAK)

SENSE current limit threshold with a 20% margin. The

sense resistor value can then be calculated to be:

80mV

I_L(PEAK)

c

2







R_SENSE

=

I_D(PEAK)= I_L(PEAK)= 1+

•I

L(MAX)







It is recommended that the peak repetitive reverse voltage

rating V is higher than V by a safety margin (a 10V

Boost Converter: Power MOSFET Selection

RRM

OUT

safety margin is usually sufficient).

Important parameters for the power MOSFET include the

drain-source voltage rating (V ), the threshold voltage

DS

The power dissipated by the diode is:

(V

), the on-resistance (R

), the gate to source

GD

GS(TH)

DS(ON)

P = I

D

• V

D

O(MAX)

and gate to drain charges (Q and Q ), the maximum

GS

drain current (I

resistances (R and R ).

) and the MOSFET’s thermal

and the diode junction temperature is:

T = T + P • R

D(MAX)

θJC

θJA

J

A

D

θJA

3758afd

16

LT3758/LT3758A

ApplicAtions inForMAtion

Theoutputcapacitorinaboostregulatorexperienceshigh

RMSripplecurrents, asshowninFigure6. TheRMSripple

current rating of the output capacitor can be determined

using the following equation:

The R to be used in this equation normally includes the

θJA

R

θJC

for the device plus the thermal resistance from the

board to the ambient temperature in the enclosure. T must

notexceedthediodemaximumjunctiontemperaturerating.

J

D_MAX

1− D_MAX

Boost Converter: Output Capacitor Selection

I_RMS(COUT)≥ I_O(MAX)

•

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

must be considered when choosing the correct output

capacitors for a given output ripple voltage. The effect of

thesethreeparameters(ESR,ESLandbulkC)ontheoutput

voltage ripple waveform for a typical boost converter is

illustrated in Figure 6.

Multiple capacitors are often paralleled to meet ESR

requirements. Typically, once the ESR requirement is

satisfied, the capacitance is adequate for filtering and has

therequiredRMScurrentrating.Additionalceramiccapaci-

tors in parallel are commonly used to reduce the effect of

parasiticinductanceintheoutputcapacitor,whichreduces

high frequency switching noise on the converter output.

t

OFF

ON

∆V

COUT

Boost Converter: Input Capacitor Selection

V

OUT

(AC)

The input capacitor of a boost converter is less critical

than the output capacitor, due to the fact that the inductor

is in series with the input, and the input current wave-

form is continuous. The input voltage source impedance

determines the size of the input capacitor, which is typi-

cally in the range of 10µF to 100µF. A low ESR capacitor

is recommended, although it is not as critical as for the

output capacitor.

RINGING DUE TO

TOTAL INDUCTANCE

(BOARD + CAP)

∆V

ESR

3758 F06

Figure 6. The Output Ripple Waveform of a Boost Converter

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

The RMS input capacitor ripple current for a boost con-

verter is:

between the ESR step ∆V

and the charging/discharg-

. For the purpose of simplicity, we will choose

ESR

ing ∆V

COUT

I

= 0.3 • ∆I

L

RMS(CIN)

2% for the maximum output ripple, to be divided equally

between ∆V and ∆V . This percentage ripple will

ESR

COUT

change, depending on the requirements of the applica-

tion, and the following equations can easily be modified.

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor can be determined using the fol-

lowing equation:

FLYBACK CONVERTER APPLICATIONS

The LT3758 can be configured as a flyback converter

for the applications where the converters have multiple

outputs, high output voltages or isolated outputs. Figure

7 shows a simplified flyback converter.

0.01• V_OUT

I_D(PEAK)

The flyback converter has a very low parts count for mul-

tipleoutputs, andwithprudentselectionofturnsratio, can

have high output/input voltage conversion ratios with a

desirable duty cycle. However, it has low efficiency due to

thehighpeakcurrents,highpeakvoltagesandconsequent

power loss. The flyback converter is commonly used for

an output power of less than 50W.

ESR_COUT

≤

For the bulk C component, which also contributes 1% to

the total ripple:

I_O(MAX)

C_OUT

≥

0.01• V_OUT• f

3758afd

17

LT3758/LT3758A

ApplicAtions inForMAtion

The flyback converter can be designed to operate either

in continuous or discontinuous mode. Compared to con-

tinuous mode, discontinuous mode has the advantage of

smaller transformer inductances and easy loop compen-

sation, and the disadvantage of higher peak-to-average

current and lower efficiency.

to the number of variables involved. The user can choose

either a duty cycle or a turns ratio as the start point. The

following trade-offs should be considered when select-

ing the switch duty cycle or turns ratio, to optimize the

converter performance. A higher duty cycle affects the

flyback converter in the following aspects:

• Lower MOSFET RMS current I

, but higher

SW(RMS)

SUGGESTED

RCD SNUBBER

D

N :N

MOSFET V peak voltage

P

S

DS

V

IN

+

–

SN

+

V

• Lower diode peak reverse voltage, but higher diode

RMS current I

C

I

D

C

R

IN

SN

C

L

OUT

P

S

D(RMS)

–

D

SN

• Higher transformer turns ratio (N /N )

P

S

I

SW

The choice,

LT3758

GATE

+

DS

–

M

V

D

1

SENSE

=

D+ D2 3

R

SENSE

GND

(for discontinuous mode operation with a given D3) gives

the power MOSFET the lowest power stress (the product

of RMS current and peak voltage). The choice,

3758 F07

Figure 7. A Simplified Flyback Converter

D

2

=

Flyback Converter: Switch Duty Cycle and Turns Ratio

D+ D2 3

(for discontinuous mode operation with a given D3) gives

the diode the lowest power stress (the product of RMS

current and peak voltage). An extreme high or low duty

cycleresultsinhighpowerstressontheMOSFETordiode,

and reduces efficiency. It is recommended to choose a

duty cycle between 20% and 80%.

The flyback converter conversion ratio in the continuous

mode operation is:

V_OUTN_S

V_INN_P1− D

D

=

•

Where N /N is the second to primary turns ratio.

S

P

V

Figure 8 shows the waveforms of the flyback converter

in discontinuous mode operation. During each switching

DS

period T , three subintervals occur: DT , D2T , D3T .

S

During DT , M is on, and D is reverse-biased. During

S

I

SW

D2T , M is off, and L is conducting current. Both L and

S

P

L currents are zero during D3T .

S

I

SW(MAX)

The flyback converter conversion ratio in the discontinu-

ous mode operation is:

I

D

V_OUTN_S

V_INN_PD2

D

=

•

I

D(MAX)

DT

D2T

D3T

S

t

S

Accordingtotheprecedingequations,theuserhasrelative

freedom in selecting the switch duty cycle or turns ratio to

suit a given application. The selections of the duty cycle

and the turns ratio are somewhat iterative processes, due

T

S

3758 F08

Figure 8. Waveforms of the Flyback Converter

in Discontinuous Mode Operation

3758afd

18

LT3758/LT3758A

ApplicAtions inForMAtion

Flyback Converter: Transformer Design for

Discontinuous Mode Operation

The primary and second inductor values of the flyback

converter transformer can be determined using the fol-

lowing equations:

The transformer design for discontinuous mode of opera-

tion is chosen as presented here. According to Figure 8,

2

D

• V

• h

IN(MIN)

MAX

the minimum D3 (D3 ) occurs when the the converter

L =

MIN

P

2 •P

• f

OUT(MAX)

has the minimum V and the maximum output power

IN

MIN

(P ). Choose D3

to be equal to or higher than 10%

2

OUT

D2 •(V

+ V )

D

OUT

to guarantee the converter is always in discontinuous

mode operation. Choosing higher D3 allows the use of

low inductances but results in higher switch peak current.

L =

S

2 •I

• f

OUT(MAX)

The primary to second turns ratio is:

The user can choose a D

as the start point. Then, the

MAX

N_P

N_S

L_P

L_S

maximum average primary currents can be calculated by

the following equation:

=

P_OUT(MAX)

Flyback Converter: Snubber Design

I_LP(MAX)= I_SW(MAX)

=

D_MAX• V_IN(MIN)• h

Transformer leakage inductance (on either the primary or

secondary) causes a voltage spike to occur after the MOS-

FET turn-off. This is increasingly prominent at higher load

currents, where more stored energy must be dissipated.

In some cases a snubber circuit will be required to avoid

overvoltagebreakdownattheMOSFET’sdrainnode.There

are different snubber circuits, and Application Note 19 is

a good reference on snubber design. An RCD snubber is

shown in Figure 7.

where h is the converter efficiency.

If the flyback converter has multiple outputs, P

is the sum of all the output power.

OUT(MAX)

The maximum average secondary current is:

I_OUT(MAX)

I_LS(MAX)= I_D(MAX)

where

D2 = 1 – D

=

D2

The snubber resistor value (R ) can be calculated by the

SN

– D3

MAX

following equation:

the primary and secondary RMS currents are:

N_P

N_S

V²− V_SN• V_OUT

•

SN

D_MAX

I_LP(RMS)= 2•I_LP(MAX)

I_LS(RMS)= 2•I_LS(MAX)

•

R_SN= 2 •

I²_SW(PEAK)•L_LK• f

3

D2

3

where V is the snubber capacitor voltage. A smaller

SN

V

results in a larger snubber loss. A reasonable V is

SN

According to Figure 8, the primary and secondary peak

currents are:

2 to 2.5 times of:

V_OUT•N_P

I

= I

= 2 • I

SW(PEAK) LP(MAX)

LP(PEAK)

LS(PEAK)

N_S

= I

= 2 • I

D(PEAK)

LS(MAX)

3758afd

19

LT3758/LT3758A

ApplicAtions inForMAtion

L istheleakageinductanceoftheprimarywinding,which

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

equation:

LK

is usually specified in the transformer characteristics. L

LK

canbeobtainedbymeasuringtheprimaryinductancewith

the secondary windings shorted. The snubber capacitor

T = T + P • θ = T + P • (θ + θ )

J

A

FET

JA

A

FET

JC

CA

value(C )canbedeterminedusingthefollowingequation:

CN

T must not exceed the MOSFET maximum junction

J

V_SN

∆V_SN•R_CN• f

C_CN

=

temperature rating. It is recommended to measure the

MOSFETtemperatureinsteadystatetoensurethatabsolute

maximum ratings are not exceeded.

where ∆V is the voltage ripple across C . A reasonable

SN

CN

∆V is 5% to 10% of V . The reverse voltage rating of

SN

Flyback Converter: Output Diode Selection

D

should be higher than the sum of V and V

.

SN

IN(MAX)

The output diode in a flyback converter is subject to large

RMS current and peak reverse voltage stresses. A fast

switching diode with a low forward drop and a low reverse

leakage is desired. Schottky diodes are recommended if

the output voltage is below 100V.

Flyback Converter: Sense Resistor Selection

In a flyback converter, when the power switch is turned on,

the current flowing through the sense resistor (I ) is:

SENSE

I

= I

LP

SENSE

Approximate the required peak repetitive reverse voltage

Set the sense voltage at I

to be the minimum of

LP(PEAK)

rating V

using:

RRM

the SENSE current limit threshold with a 20% margin. The

sense resistor value can then be calculated to be:

N_S

N_P

V_RRM

>

• V_IN(MAX)+ V_OUT

80mV

I_LP(PEAK)

R_SENSE

=

The power dissipated by the diode is:

P = I • V

D

O(MAX)

D

Flyback Converter: Power MOSFET Selection

and the diode junction temperature is:

T = T + P • R

Fortheflybackconfiguration, theMOSFETisselectedwith

a V rating high enough to handle the maximum V , the

DC

IN

J

A

D

θJA

reflected secondary voltage and the voltage spike due to

The R to be used in this equation normally includes the

θJA

theleakageinductance.ApproximatetherequiredMOSFET

R

θJC

for the device, plus the thermal resistance from the

V

DC

rating using:

board to the ambient temperature in the enclosure. T must

notexceedthediodemaximumjunctiontemperaturerating.

J

BV

> V

DSS

DS(PEAK)

where

Flyback Converter: Output Capacitor Selection

V

= V

+ V

DS(PEAK)

IN(MAX) SN

The output capacitor of the flyback converter has a similar

operation condition as that of the boost converter. Refer

totheBoostConverter:OutputCapacitorSelectionsection

The power dissipated by the MOSFET in a flyback con-

verter is:

2

for the calculation of C

and ESR

.

P

C

= I

• R

+ 2 • V

• I

•

OUT

COUT

FET

RSS

M(RMS)

• f/1A

DS(ON)

DS(PEAK) L(MAX)

The RMS ripple current rating of the output capacitors

in discontinuous operation can be determined using the

following equation:

The first term in this equation represents the conduction

losses in the device, and the second term, the switching

loss. C

is the reverse transfer capacitance, which is

RSS

4− (3•D2)

I_{RMS(COUT),DISCONTINUOUS}≥ I_O(MAX)

•

usually specified in the MOSFET characteristics.

3•D2

3758afd

20

LT3758/LT3758A

ApplicAtions inForMAtion

Flyback Converter: Input Capacitor Selection

Themaximumdutycycle(D )occurswhentheconverter

MAX

has the minimum input voltage:

The input capacitor in a flyback converter is subject to

a large RMS current due to the discontinuous primary

current. To prevent large voltage transients, use a low

ESR input capacitor sized for the maximum RMS current.

The RMS ripple current rating of the input capacitors in

discontinuous operation can be determined using the

following equation:

V_OUT+ V_D

V_IN(MIN)+ V_OUT+ V_D

D_MAX

=

SEPIC Converter: Inductor and Sense Resistor Selection

As shown in Figure 1, the SEPIC converter contains two

inductors:L1andL2.L1andL2canbeindependent,butcan

also be wound on the same core, since identical voltages

are applied to L1 and L2 throughout the switching cycle.

P_OUT(MAX)

4− (3•D_MAX

3•D_MAX

)

I_{RMS(CIN),DISCONTINUOUS}

≥

•

V_IN(MIN)• h

For the SEPIC topology, the current through L1 is the

converter input current. Based on the fact that, ideally, the

output power is equal to the input power, the maximum

average inductor currents of L1 and L2 are:

SEPIC CONVERTER APPLICATIONS

The LT3758 can be configured as a SEPIC (single-ended

primary inductance converter), as shown in Figure 1. This

topology allows for the input to be higher, equal, or lower

than the desired output voltage. The conversion ratio as

a function of duty cycle is:

D

MAX

I

= I

•

L1(MAX) IN(MAX) O(MAX)

1− D

MAX

= I

L2(MAX) O(MAX)

V_OUT+ V_D

D

1− D

=

In a SEPIC converter, the switch current is equal to I

L2

average switch current is defined as:

+

V_IN

L1

I

when the power switch is on, therefore, the maximum

in continuous conduction mode (CCM).

In a SEPIC converter, no DC path exists between the input

and output. This is an advantage over the boost converter

for applications requiring the output to be disconnected

from the input source when the circuit is in shutdown.

1

I_SW(MAX)= I_L1(MAX)+ I_L2(MAX)= I_O(MAX)

•

1− D_MAX

and the peak switch current is:

Compared to the flyback converter, the SEPIC converter

has the advantage that both the power MOSFET and the

c

2

1







I_SW(PEAK)= 1+

•I

•







O(MAX)

output diode voltages are clamped by the capacitors (C ,

1− D_MAX

IN

C

DC

and C ), therefore, there is less voltage ringing

OUT

c

The constant in the preceding equations represents the

percentage peak-to-peak ripple current in the switch, rela-

across the power MOSFET and the output diodes. The

SEPIC converter requires much smaller input capacitors

than those of the flyback converter. This is due to the fact

that, in the SEPIC converter, the inductor L1 is in series

with the input, and the ripple current flowing through the

input capacitor is continuous.

tive to I

, as shown in Figure 9. Then, the switch

SW(MAX)

ripple current ∆I can be calculated by:

SW

c

∆I = • I

SW

SW(MAX)

The inductor ripple currents ∆I and ∆I are identical:

L1

L2

SEPIC Converter: Switch Duty Cycle and Frequency

∆I = ∆I = 0.5 • ∆I

SW

L1

L2

For a SEPIC converter operating in CCM, the duty cycle

of the main switch can be calculated based on the output

The inductor ripple current has a direct effect on the

choice of the inductor value. Choosing smaller values of

L

voltage (V ), the input voltage (V ) and the diode

OUT

IN

∆I requires large inductances and reduces the current

forward voltage (V ).

D

loop gain (the converter will approach voltage mode).

3758afd

21

LT3758/LT3758A

ApplicAtions inForMAtion

where

c_L1=

Accepting larger values of ∆I allows the use of low in-

L

ductances, but results in higher input current ripple and

∆I_L1

I_L1(MAX)

c

greater core losses. It is recommended that falls in the

range of 0.2 to 0.6.

c²

12

L2

I_L2(RMS)= I_L2(MAX)• 1+

I

SW

∆I

I

SW = χ • SW(MAX)

where

c_L2=

I

SW(MAX)

∆I_L2

I_{L2 (MAX)}

t

DT

S

T

S

3758 F09

Basedontheprecedingequations,theusershouldchoose

the inductors having sufficient saturation and RMS cur-

rent ratings.

Figure 9. The Switch Current Waveform of the SEPIC Converter

Givenanoperatinginputvoltagerange,andhavingchosen

the operating frequency and ripple current in the inductor,

theinductorvalue(L1andL2areindependent)oftheSEPIC

convertercanbedeterminedusingthefollowingequation:

In a SEPIC converter, when the power switch is turned on,

the current flowing through the sense resistor (I

the switch current.

) is

SENSE

Set the sense voltage at I

to be the minimum

SENSE(PEAK)

V_IN(MIN)

of the SENSE current limit threshold with a 20% margin.

The sense resistor value can then be calculated to be:

L1= L2=

•D_MAX

0.5• ∆I_SW• f

80 mV

I_SW(PEAK)

For most SEPIC applications, the equal inductor values

will fall in the range of 1µH to 100µH.

R_SENSE

=

By making L1 = L2, and winding them on the same core,

the value of inductance in the preceding equation is re-

placed by 2L, due to mutual inductance:

SEPIC Converter: Power MOSFET Selection

For the SEPIC configuration, choose a MOSFET with a

V

rating higher than the sum of the output voltage and

DC

V_IN(MIN)

L =

•D_MAX

input voltage by a safety margin (a 10V safety margin is

∆I_SW• f

usually sufficient).

Thismaintainsthesameripplecurrentandenergystorage

in the inductors. The peak inductor currents are:

The power dissipated by the MOSFET in a SEPIC con-

verter is:

I

= I

+ 0.5 • ∆I

2

L1(PEAK)

L2(PEAK)

L1(MAX)

L2(MAX)

L1

L2

P

= I

• R

• D

MAX

FET

SW(MAX)

DS(ON)

2

+ 2 • (V

+ V ) • I

• C

• f/1A

IN(MIN)

OUT

L(MAX)

RSS

The RMS inductor currents are:

The first term in this equation represents the conduction

losses in the device, and the second term, the switching

c²

loss. C

is the reverse transfer capacitance, which is

L1

12

RSS

I_L1(RMS)= I_L1(MAX)• 1+

usually specified in the MOSFET characteristics.

For maximum efficiency, R

and C

should be

DS(ON)

RSS

minimized. From a known power dissipated in the power

3758afd

22

LT3758/LT3758A

ApplicAtions inForMAtion

MOSFET, its junction temperature can be obtained using

the following equation:

C

has nearly a rectangular current waveform. During

DC

the switch off-time, the current through C is I , while

DC

IN

approximately –I flows during the on-time. The RMS

O

T = T + P • θ = T + P • (θ + θ )

J

A

FET

JA

A

FET

JC

CA

rating of the coupling capacitor is determined by the fol-

T must not exceed the MOSFET maximum junction

lowing equation:

J

temperature rating. It is recommended to measure the

MOSFETtemperatureinsteadystatetoensurethatabsolute

maximum ratings are not exceeded.

V

+ V

D

OUT

I

> I

•

RMS(CDC) O(MAX)

V

IN(MIN)

SEPIC Converter: Output Diode Selection

A low ESR and ESL, X5R or X7R ceramic capacitor works

well for C .

To maximize efficiency, a fast switching diode with a low

forward drop and low reverse leakage is desirable. The

average forward current in normal operation is equal to

the output current, and the peak current is equal to:

DC

INVERTING CONVERTER APPLICATIONS

TheLT3758canbeconfiguredasadual-inductorinverting

c

2

1







topology, as shown in Figure 10. The V

to V ratio is:

OUT

IN

I_D(PEAK)= 1+

•I

•







O(MAX)

1− D_MAX

V_OUT− V_D

D

1− D

= −

V_IN

It is recommended that the peak repetitive reverse voltage

rating V is higher than V + V by a safety

RRM

OUT

IN(MAX)

in continuous conduction mode (CCM).

margin (a 10V safety margin is usually sufficient).

The power dissipated by the diode is:

C

+

DC

L1

L2

–

V

IN

P = I

D

• V

D

O(MAX)

+

–

C

IN

and the diode junction temperature is:

C

V

OUT

+

T = T + P • R

θJA

LT3758

GATE

J

A

D

D1

M1

The R used in this equation normally includes the R

θJA

θJC

SENSE

for the device, plus the thermal resistance from the board,

R

SENSE

to the ambient temperature in the enclosure. T must not

+

J

GND

3758 F10

exceed the diode maximum junction temperature rating.

SEPIC Converter: Output and Input Capacitor Selection

Figure 10. A Simplified Inverting Converter

The selections of the output and input capacitors of the

SEPICconverteraresimilartothoseoftheboostconverter.

Please refer to the Boost Converter: Output Capacitor

Selection and Boost Converter: Input Capacitor Selection

sections.

Inverting Converter: Switch Duty Cycle and Frequency

For an inverting converter operating in CCM, the duty

cycle of the main switch can be calculated based on the

negativeoutputvoltage(V )andtheinputvoltage(V ).

OUT

IN

SEPIC Converter: Selecting the DC Coupling Capacitor

Themaximumdutycycle(D )occurswhentheconverter

MAX

has the minimum input voltage:

The DC voltage rating of the DC coupling capacitor (C ,

DC

as shown in Figure 1) should be larger than the maximum

input voltage:

V_OUT− V_D

V_OUT− V_D− V_IN(MIN)

D_MAX

=

V

> V

IN(MAX)

CDC

3758afd

23

LT3758/LT3758A

ApplicAtions inForMAtion

Inverting Converter: Inductor, Sense Resistor, Power

MOSFET, Output Diode and Input Capacitor Selections

rating of the coupling capacitor is determined by the fol-

lowing equation:

The selections of the inductor, sense resistor, power

MOSFET, output diode and input capacitor of an invert-

ing converter are similar to those of the SEPIC converter.

PleaserefertothecorrespondingSEPICconvertersections.

D_MAX

1− D_MAX

I_RMS(CDC)> I_O(MAX)

•

A low ESR and ESL, X5R or X7R ceramic capacitor works

well for C .

DC

Inverting Converter: Output Capacitor Selection

Board Layout

The inverting converter requires much smaller output

capacitors than those of the boost, flyback and SEPIC

convertersforsimilaroutputripples. Thisisduetothefact

that, in the inverting converter, the inductor L2 is in series

with the output, and the ripple current flowing through the

outputcapacitorsarecontinuous.Theoutputripplevoltage

is produced by the ripple current of L2 flowing through

the ESR and bulk capacitance of the output capacitor:

The high speed operation of the LT3758 demands careful

attention to board layout and component placement. The

Exposed Pad of the package is the only GND terminal of

the IC, and is important for thermal management of the

IC. Therefore, it is crucial to achieve a good electrical and

thermal contact between the Exposed Pad and the ground

plane of the board. For the LT3758 to deliver its full output

power, it is imperative that a good thermal path be pro-

vided to dissipate the heat generated within the package.

It is recommended that multiple vias in the printed circuit

board be used to conduct heat away from the IC and into

a copper plane with as much area as possible.









1

∆V_OUT(P–P)= ∆I_L2• ESR_COUT

+



8 • f •C_OUT



After specifying the maximum output ripple, the user can

select the output capacitors according to the preceding

equation.

To prevent radiation and high frequency resonance prob-

lems, proper layout of the components connected to the

IC is essential, especially the power paths with higher di/

dt. The following high di/dt loops of different topologies

should be kept as tight as possible to reduce inductive

ringing:

The ESR can be minimized by using high quality X5R or

X7R dielectric ceramic capacitors. In many applications,

ceramic capacitors are sufficient to limit the output volt-

age ripple.

The RMS ripple current rating of the output capacitor

needs to be greater than:

• In boost configuration, the high di/dt loop contains

the output capacitor, the sensing resistor, the power

MOSFET and the Schottky diode.

I

> 0.3 • ∆I

L2

RMS(COUT)

• In flyback configuration, the high di/dt primary loop

contains the input capacitor, the primary winding, the

power MOSFET and the sensing resistor. The high di/

dt secondary loop contains the output capacitor, the

secondary winding and the output diode.

Inverting Converter: Selecting the DC Coupling Capacitor

The DC voltage rating of the DC coupling capacitor (C ,

DC

asshowninFigure10)shouldbelargerthanthemaximum

input voltage minus the output voltage (negative voltage):

V

> V

– V

• In SEPIC configuration, the high di/dt loop contains

the power MOSFET, sense resistor, output capacitor,

Schottky diode and the coupling capacitor.

CDC

IN(MAX) OUT

C

has nearly a rectangular current waveform. During

DC

the switch off-time, the current through C is I , while

approximately –I flows during the on-time. The RMS

DC

IN

• In inverting configuration, the high di/dt loop contains

power MOSFET, sense resistor, Schottky diode and the

coupling capacitor.

O

3758afd

24

LT3758/LT3758A

ApplicAtions inForMAtion

Check the stress on the power MOSFET by measuring its

drain-to-sourcevoltagedirectlyacrossthedeviceterminals

(reference the ground of a single scope probe directly to

the source pad on the PC board). Beware of inductive

ringing, which can exceed the maximum specified voltage

rating of the MOSFET. If this ringing cannot be avoided,

and exceeds the maximum rating of the device, either

choose a higher voltage device or specify an avalanche-

rated power MOSFET.

regulation and true remote sensing, the top of the output

voltage sensing resistor divider should connect indepen-

dently to the top of the output capacitor (Kelvin connec-

tion), staying away from any high dV/dt traces. Place the

divider resistors near the LT3758 in order to keep the high

impedance FBX node short.

Figure 11 shows the suggested layout of the 10V to 40V

input, 48V output boost converter in the Typical Applica-

tions section.

The small-signal components should be placed away

from high frequency switching nodes. For optimum load

C

IN

V

IN

C

C1

C2

L1

R3

R

C

R1

R2

C

1

2

3

4

5

10

LT3758

9

8

7

6

C

SS

VCC

R

T

1

2

3

4

8

7

6

5

M1

R

S

VIAS TO GROUND

PLANE

D1

C

OUT1

OUT2

V

OUT

3758 F11

Figure 11. Suggested Layout of the 10V to 40V Input, 48V Output

Boost Converter in the Typical Applications Section

3758afd

25

LT3758/LT3758A

ApplicAtions inForMAtion

Recommended Component Manufacturers

Some of the recommended component manufacturers

are listed in Table 2.

Table 2. Recommended Component Manufacturers

VENDOR

AVX

COMPONENTS

WEB ADDRESS

avx.com

Capacitors

BH Electronics

Inductors,

Transformers

bhelectronics.com

Coilcraft

Inductors

Diodes

coilcraft.com

bussmann.com

diodes.com

Cooper Bussmann

Diodes, Inc

Fairchild

MOSFETs

Diodes

fairchildsemi.com

General Semiconductor

generalsemiconductor.

com

International Rectifier

IRC

MOSFETs, Diodes

Sense Resistors

Tantalum Capacitors

Toroid Cores

Diodes

irf.com

irctt.com

Kemet

kemet.com

Magnetics Inc

Microsemi

Murata-Erie

Nichicon

mag-inc.com

microsemi.com

murata.co.jp

nichicon.com

onsemi.com

panasonic.com

pulseeng.com

sanyo.co.jp

Inductors, Capacitors

Capacitors

On Semiconductor

Panasonic

Pulse

Diodes

Capacitors

Inductors

Sanyo

Capacitors

Sumida

Inductors

sumida.com

t-yuden.com

Taiyo Yuden

TDK

Capacitors

Capacitors, Inductors component.tdk.com

Thermalloy

Tokin

Heat Sinks

Capacitors

aavidthermalloy.com

nec-tokinamerica.com

tokoam.com

Toko

Inductors

United Chemi-Con

Vishay/Dale

Vishay/Siliconix

Würth Elektronik

Vishay/Sprague

Zetex

Capacitors

chemi-com.com

vishay.com

Resistors

MOSFETs

vishay.com

Inductors

we-online.com

vishay.com

Capacitors

Small-Signal Discretes

zetex.com

3758afd

26

LT3758/LT3758A

typicAl ApplicAtions

10V to 40V Input, 48V Output Boost Converter

V

IN

10V TO 40V

C

IN

L1

18.7µH

R3

200k

4.7µF

50V

X7R

×2

V

IN

D1

SHDN/UVLO

V

OUT

R4

48V

1A

32.4k

LT3758

R2

464k

M1

SYNC

GATE

SENSE

RT

SS

C

+

OUT1

FBX

R

100µF

63V

T

V

GND INTV

CC

C

41.2k

C

300kHz

OUT2

R1

15.8k

C

4.7µF

10V

C

SS

VCC

4.7µF

R

C

10k

R

S

0.68µF

50V

X7R

×4

0.012Ω

C

C1

10nF

C2

X5R

100pF

3758 TA02a

C

, C

OUT1

: MURATA GRM32ER71H475KA88L

: PANASONIC ECG EEV-TG1J101UP

D1: VISHAY SILICONIX 30BQ060

L1: PULSE PB2020.223

M1: VISHAY SILICONIX SI7460DP

IN OUT2

Efficiency vs Output Current

Start-Up Waveforms

100

V

= 24V

IN

90

80

70

60

V

= 40V

IN

V

OUT

V

= 24V

IN

20V/DIV

50

I

40

30

20

10

L1

2A/DIV

3758 TA02c

V

= 10V

IN

5ms/DIV

0.001

0.1

0.01

OUTPUT CURRENT (A)

1

3758 TA02b

3758afd

27

LT3758/LT3758A

typicAl ApplicAtions

12V Output Nonisolated Flyback Power Supply

D1

V

12V

1.2A

OUT

V

IN

36V TO 72V

0.022µF

6.2k

C

IN

100V

1M

2.2µF

100V

X7R

T1

1,2,3

4,5,6

(PARALLEL)

V

IN

(SERIES)

D

SN

SHDN/UVLO

44.2k

SW

LT3758

105k

1%

SYNC

GATE

M1

SENSE

RT

SS

FBX

V

C

GND INTV

CC

63.4k

200kHz

1N4148

5.1Ω

0.47µF

100pF

C

4.7µF

10V

VCC

10k

10nF

C

47µF

X5R

OUT

15.8k

1%

0.030Ω

X5R

3758 TA03a

C

: MURATA GRM32ER72A225KA35L

D1: ON SEMICONDUCTOR MBRS360T3G

IN

T1: COILTRONICS VP2-0066

M1: VISHAY SILICONIX SI4848DY

D

: VISHAY SILICONIX ES1D

: MURATA GRM32ER61C476ME15L

SN

C

OUT

Efficiency vs Output Current

Start-Up Waveform

100

90

80

70

60

50

V

= 48V

V

= 48V

IN

V

OUT

5V/DIV

40

30

3758 TA03c

5ms/DIV

20

0.01

0.1

1

10

OUTPUT CURRENT (A)

3758 TA03b

Frequency Foldback Waveforms

When Output Short-Circuit

V

= 48V

IN

V

OUT

5V/DIV

V

SW

50V/DIV

3758 TA03d

20µs/DIV

3758afd

28

LT3758/LT3758A

typicAl ApplicAtions

VFD (Vacuum Fluorescent Display) Flyback Power Supply

D1

V

96V

80mA

OUT

C

OUT2

2.2µF

100V

X7R

4

5

V

IN

D2

V

64V

OUT2

9V TO 16V

C

22µF

25V

IN

T1

1, 2, 3

40mA

178k

V

IN

C

1µF

OUT1

22Ω

SHDN/UVLO

100V

X7R

220pF

32.4k

95.3k

M1 SW

LT3758

SYNC

GATE

6

SENSE

RT

SS

FBX

V

GND INTV

CC

C

0.47µF

63.4k

200kHz

C

4.7µF

10V

VCC

10k

10nF

0.019Ω

0.5W

47pF

1.62k

X5R

3758 TA04a

C

: MURATA GRM32ER61E226KE15L

D2: VISHAY SILICONIX ES1C

M1: VISHAY SILICONIX Si4100DY

T1: COILTRONICS VP1-0102

IN

: MURATA GRM31CR72A105K01L

: MURATA GRM32ER72A225KA35L

OUT1

OUT2

D1: VISHAY SILICONIX ES1D

(*PRIMARY = 3 WINDINGS IN PARALLEL)

Start-Up Waveforms

Switching Waveforms

V

= 12V

V

IN

OUT1

OUT2

V

OUT1

1V/DIV

(AC)

V

OUT2

1V/DIV

(AC)

V

,

V

OUT1

SW

V

50V/DIV

OUT2

20V/DIV

3758 TA04b

3758 TA04c

10ms/DIV

2µs/DIV

3758afd

29

LT3758/LT3758A

typicAl ApplicAtions

36V to 72V Input, 3.3V Output Isolated Telecom Power Supply

PA1277NL

4

+

-

V

3.3V

3A

OUT

5

6

V

IN

36V TO 72V

0.022µF

100V

C

OUT

5.6k

IN

100µF

6.3V

×3

2.2µF

100V

X7R

BAV21W

UPS840

7

8

3

V

OUT

1M

V

IN

FDC2512

GATE

BAS516

10Ω

2

SHDN/UVLO

SENSE

44.2k

4.7µF

25V

X5R

0.03Ω

LT3758

100pF

BAT54CWTIG

100k

47pF

SYNC

INTV

CC

1

4.7µF

25V

X5R

FBX

RT

16k

274Ω

V

BAS516

SS

C

GND

63.4k

200kHz

LT4430

PS2801-1

0.47µF

47nF

0.47µF

V

OPTO

IN

2k

2200pF

250VAC

GND COMP

OC 0.5V FB

1µF

22.1k

3758 TA05a

Efficiency vs Output Current

100

90

80

70

60

50

V

= 36V

V

= 72V

IN

V

= 48V

IN

40

30

20

0.01

0.1

1

10

OUTPUT CURRENT (A)

3758 TA05b

3758afd

30

LT3758/LT3758A

typicAl ApplicAtions

18V to 72V Input, 24V Output SEPIC Converter

V

IN

18V TO 72V

C

IN2

C

10µF

100V

DC

+

IN1

•

2.2µF

100V

X7R

2.2µF

100V

232k

20k

V

L1A

IN

X7R, ×2

SHDN/UVLO

D1

V

OUT

24V

1A

LT3758A

SYNC

GATE

M1

L1B

280k

1%

•

SENSE

0.025Ω

RT

SS

FBX

V

C

GND INTV

CC

C

33µF

41.2k

300kHz

OUT1

+

20k

1%

35V

C

10k

10nF

0.47µF

OUT1

×2

C

4.7µF

10V

VCC

10µF

25V

X5R

×4

X5R

3758 TA06a

C

: PANASONIC EEE2AA100UP

L1A, L1B: COILTRONICS DRQ127-470

M1: FAIRCHILD SEMICONDUCTOR FDMS2572

D1: ON SEMICONDUCTOR MBRS3100T3G

IN1

, C : TAIYO YUDEN HMK325B7225KN-T

IN2 DC

: MURATA GRM31CR61E106KA12L

: KEMET T495X336K035AS

OUT1

OUT2

Efficiency vs Output Current

Load Step Waveform

100

90

V

= 48V

IN

V

= 18V

IN

V

OUT

80

70

2V/DIV

AC-COUPLED

V

= 72V

IN

V

= 48V

IN

60

50

40

1A

I

OUT

1A/DIV

0A

30

20

10

3758 TA06c

500µs/DIV

0.001

0.1

0.01

OUTPUT CURRENT (A)

1

3758 TA06b

Frequency Foldback Waveforms

When Output Short-Circuit

Start-Up Waveform

V

= 48V

V

= 48V

IN

V

OUT

20V/DIV

V

OUT

SW

10V/DIV

50V/DIV

IL

1A + 1B

1A/DIV

2A/DIV

3758 TA06d

3758 TA06e

2ms/DIV

50µs/DIV

3758afd

31

LT3758/LT3758A

typicAl ApplicAtions

10V to 40V Input, –12V Output Inverting Converter

V

IN

10V TO 40V

C

IN2

C

DC

+

IN1

•

R1

200k

4.7µF

50V

X7R

×2

2.2µF

4.7µF

50V

×2

V

L1A

IN

100V

X7R, ×2

L1B

SHDN/UVLO

V

OUT

R2

32.4k

–12V

2A

LT3758A

SYNC

GATE

M1

D1

SENSE

105k

7.5k

0.015Ω

RT

SS

FBX

GND INTV

CC

V

C

41.2k

300kHz

OUT2

47µF

+

20V

10k

6.8nF

0.47µF

C

×2

C

4.7µF

10V

OUT1

VCC

22µF

16V

X5R

×4

X5R

3758 TA07a

C

: KEMET T495X475K050AS

D1: VISHAY SILICONIX 30BQ060

L1A, L1B: COILTRONICS DRQ127-150

M1: VISHAY SILICONIX SI7850DP

IN1

, C : MURATA GRM32ER71H475KA88L

IN2 DC

: MURATA GRM32ER61C226KE20

: KEMET T495X476K020AS

OUT1

OUT2

Efficiency vs Output Current

Load Step Waveforms

100

90

V

= 24V

IN

V

= 10V

IN

V

OUT

V

= 24V

80

70

1V/DIV

IN

V

= 40V

IN

AC-COUPLED

60

50

40

1A

I

OUT

1A/DIV

0A

30

20

10

3758 TA07c

500µs/DIV

0.001

0.1

1

10

0.01

OUTPUT CURRENT (A)

3758 TA07b

Frequency Foldback Waveforms

When Output Short-Circuit

Start-Up Waveforms

V

= 24V

V

= 24V

IN

V

OUT

10V/DIV

5V/DIV

V

SW

20V/DIV

IL

1A + 1B

2A/DIV

IL

1A + 1B

3758 TA07d

3758 TA07e

5A/DIV

5ms/DIV

50µs/DIV

3758afd

32

LT3758/LT3758A

pAckAge Description

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

0.70 ±0.05

3.55 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50

BSC

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.125

0.40 ± 0.10

TYP

6

10

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

PIN 1

TOP MARK

(SEE NOTE 6)

CHAMFER

(DD) DFN REV C 0310

5

1

0.25 ± 0.05

0.50 BSC

0.75 ±0.05

0.200 REF

2.38 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

3758afd

33

LT3758/LT3758A

pAckAge Description

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev H)

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.88

(.074)

1.88 ±0.102

(.074 ±.004)

0.889 ±0.127

(.035 ±.005)

1

0.29

REF

1.68

(.066)

0.05 REF

5.23

(.206)

MIN

1.68 ±0.102

3.20 – 3.45

DETAIL “B”

(.066 ±.004) (.126 – .136)

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

10

NO MEASUREMENT PURPOSE

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ±.0015)

TYP

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

0.497 ±0.076

(.0196 ±.003)

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

REF

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

4.90 ±0.152

(.193 ±.006)

DETAIL “A”

0° – 6° TYP

0.254

(.010)

1

2

3

4 5

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

0.50

(.0197)

BSC

MSOP (MSE) 0911 REV H

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

3758afd

34

LT3758/LT3758A

revision history

REV

DATE

DESCRIPTION

PAGE NUMBER

A

3/10

Deleted Bullet from Features and Last Line of Description

Updated All Sections to Include H-Grade and Military Grade

Deleted Vendor Telephone Information from Table 2 in Applications Information Section

Revised TA04 and TA04c in Typical Applications

Replaced Related Parts List

1

2 to 7

26

29

36

8

B

5/10

5/11

Revised last sentence of SYNC Pin description

Updated Block Diagram

9

Revised value in last sentence of Programming Turn-on and Turn-off Thresholds in the SHDN/UVLO Pin Section

Revised penultimate sentence of Operating Frequency and Synchronization section

Revised MP-grade temperature range in Absolute Maximum Ratings and Order Information

Revised Note 2

10

13

C

D

2

4

19

Revised formula in Applications Information

07/12 Added LT3758A version

Updated Block Diagram

Throughout

9

13

Updated Programming the Output Voltage section

Updated Loop Compensation section

14

Updated the schematic and Load Step Waveforms in the Typical Applications section

31, 32

3758afd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

35

LT3758/LT3758A

typicAl ApplicAtions

8V to 72V Input, 12V Output SEPIC Converter

Efficiency vs Output Current

100

90

V

IN

8V TO 72V

C

V

= 8V

DC

IN

•

C

IN

2.2µF

100V

154k

V

2.2µF

100V

X7R

×2

L1A

IN

80

70

D1

V

= 42V

IN

X7R, ×2

MBRS3100T3G

SHDN/UVLO

V

12V

2A

OUT

V

= 72V

IN

32.4k

60

50

40

LT3758

SYNC

GATE

M1

C

OUT1

L1B

+

Si7456DP

47µF

20V

×2

105k

1%

•

SENSE

0.012Ω

30

20

10

RT

SS

FBX

V

C

GND INTV

CC

41.2k

300kHz

15.8k

1%

0.001

0.01

0.1

1

10

C

OUT2

10µF

16V

X5R

×4

OUTPUT CURRENT (A)

3758 TA08b

10k

10nF

C

0.47µF

VCC

4.7µF

10V

X5R

3758 TA08a

L1A, L1B: COILTRONICS DRQ127-220

relAteD pArts

PART NUMBER

DESCRIPTION

COMMENTS

LT3757A

Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable

IN

Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages

LT3759

LT3957A

LT3958

Boost, SEPIC and Inverting Controller

1.6V ≤ V ≤ 42V, Current Mode Control, 100kHz to 1MHz Programmable

IN

Operation Frequency, MSOP-12E Packages

Boost, Flyback, SEPIC and Inverting Controller 3V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation

with 5A, 40V Switch

IN

Frequency, 5mm × 6mm QFN Package

Boost, Flyback, SEPIC and Inverting Controller 5V ≤ V ≤ 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation

with 3.3A, 84V Switch

IN

Frequency, 5mm × 6mm QFN Package

LT3573/LT3574/

LT3575

40V Isolated Flyback Converters

Monolithic No-Opto Flybacks with Integrated 1.25A/0.65A/2.5A Switch

LT3511/LT3512

LT3798

100V Isolated Flyback Converters

Monolithic No-Opto Flybacks with Integrated 240mA/420mA Switch

Offline Isolated No Opto-Coupler Flyback

Controller with Active PFC

V

IN

and V

Limited Only by External Components, MSOP-16 Package

OUT

LT3799/LT3799-1

Offline Isolated Flyback LED Controllers with

Active PFC

V

and V

Limited Only by External Components, MSOP-16 Package

IN

OUT

3758afd

LT 0712 REV D • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

●

 LINEAR TECHNOLOGY CORPORATION 2009

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3758A_15
厂家：	Linear
描述：	High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller
文件：	总36页 (文件大小：515K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3758A_15 [Linear]

相关型号：

LT3758EDD#PBF

LT3758EDD#TRPBF

LT3758EDDPBF

LT3758EDDTRPBF

LT3758EMSE#PBF

LT3758EMSE#TRPBF

LT3758EMSEPBF

LT3758EMSETRPBF

LT3758HMSE#PBF

LT3758IDD#PBF

LT3758IDDPBF

LT3758IDDTRPBF