LT3782AEUFD#TRPBF [Linear]
2-Phase Step-Up DC/DC Controller;
| 型号： | LT3782AEUFD#TRPBF |
| 厂家： | 
Linear |
| 描述： | 2-Phase Step-Up DC/DC Controller |
| 文件： | 总20页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3782A
2-Phase Step-Up
DC/DC Controller
FeaTures
DescripTion
The LT®3782A is a current mode 2-phase step-up DC/DC
converter controller. Its high switching frequency (up to
500kHz) and 2-phase operation reduce system filtering
capacitance and inductance requirements.
n
2-Phase Operation Reduces Required Input and
Output Capacitance
n
Programmable Switching Frequency:
150kHz to 500kHz
6V to 40V Input Range
10V Gate Drive with V ≥13V
High Current Gate Drive (4A)
Programmable Soft-Start and Current Limit
Programmable Slope Compensation for
High Noise Immunity
n
With 10V gate drive (V ≥13V) and 4A peak drive current,
CC
n
CC
the LT3782A can drive most industrial grade high power
MOSFETs with high efficiency. For synchronous applica-
tions, the LT3782A provides synchronous gate signals
with programmable falling edge delay to avoid cross
conduction when using external MOSFET drivers. Other
features include programmable undervoltage lockout,
soft-start, current limit, duty cycle clamp (50% or higher)
and slope compensation. The LT3782A is identical to the
LT3782 except that the LT3782A has a tighter current
sense mismatch tolerance.
n
n
n
n
MOSFET Gate Signals with Programmable
Falling Edge Delay for External Synchronous Drivers
Programmable Undervoltage Lockout
Programmable Duty Cycle Clamp (50% or Higher)
Thermally Enhanced 28-Lead TSSOP and 4mm ×
5mm QFN Packages
n
n
n
The LT3782A is available in thermally enhanced 28-lead
TSSOP and 4mm × 5mm QFN packages.
applicaTions
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks, ThinSOT
n
Industrial Equipment
and No R
are trademarks of Linear Technology Corporation. All other trademarks are the
SENSE
property of their respective owners. Protected by U.S. Patents including 6144194.
n
Telecom Infrastructure
n
Interleaved Isolated Power Supply
Typical applicaTion
50V 4A Boost Converter
Efficiency and Power Loss
vs Load Current
20µH
V
V
IN
10V TO 36V
OUT
50V, 4A
97
18
15
12
9
20µH
10µF
D1
V
GBIAS1
GBIAS2
CC
×2
V
= 24V
IN
EFFICIENCY
+
10µF
×2
1µF
2µF
95
93
91
89
87
85
D2
220µF
825k
274k
V
= 12V
= 12V
GBIAS
BGATE1
IN
Q1
RUN
V
IN
LT3782A
0.004Ω
V
EE1
V
= 24V
IN
59k
6
Q2
SLOPE
DELAY
DCL
BGATE2
POWER LOSS
3
80k
0.004Ω
475k
0
R
SET
V
EE2
+
0
1
2
3
4
5
10Ω
10nF
10Ω
10nF
I
(A)
SS
OUT
24.9k
0.1µF
3782A TA01b
SENSE1
SENSE1
–
V
C
+
–
SENSE2
SENSE2
13k
6.8nF
D1, D2: 30BQ060PbF
Q1, Q2: Si7852DP-T1-E3
100pF
FB
GND
3782A TA01
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LT3782A
absoluTe MaxiMuM raTings
(Note 1)
V
Supply Voltage ...................................................40V
SS...........................................................300µA Max I
CC
SS
+
+
GBIAS, GBIAS1, GBIAS2 Pin
SENSE1 , SENSE2 ,
–
–
(Externally Forced)....................................................14V
SYNC, RUN Pin.........................................................30V
Operating Junction Temperature
SENSE1 , SENSE2 ..................................... –0.3V to 2V
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
Range (Notes 2, 3)................................. –40°C to 125°C
For FE Package .....................................................300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
1
2
GBIAS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SGATE2
SGATE1
NC
V
CC
3
NC
NC
28 27 26 25 24 23
4
GND
SYNC
DELAY
DCL
1
2
3
4
5
6
7
8
22 BGATE1
21
20
19
18
17
16
15
GBIAS1
NC
5
V
EE1
SYNC
DELAY
DCL
6
BGATE1
GBIAS1
GBIAS2
BGATE2
+
SENSE1
NC
29
GND
7
29
GND
–
SENSE1
+
GBIAS2
BGATE2
8
SENSE1
SLOPE
–
9
SENSE1
R
V
SET
EE2
10
11
12
13
14
V
EE2
SLOPE
–
SENSE2
NC
NC
R
SET
–
9
10 11 12 13 14
UFD PACKAGE
RUN
FB
SENSE2
SENSE2
+
V
C
SS
28-LEAD (4mm × 5mm) PLASTIC QFN
= 125°C, θ = 37°C/ W
FE PACKAGE
T
28-LEAD PLASTIC TSSOP
JMAX
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 30°C/ W
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LT3782AEFE#PBF
LT3782AIFE#PBF
LT3782AEUFD#PBF
LT3782AIUFD#PBF
LEAD BASED FINISH
LT3782AEFE
TAPE AND REEL
PART MARKING*
LT3782AFE
LT3782AFE
3782A
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3782AEFE#TRPBF
LT3782AIFE#TRPBF
LT3782AEUFD#TRPBF
LT3782AIUFD#TRPBF
TAPE AND REEL
28-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
28-Lead Plastic TSSOP
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
3782A
PART MARKING*
LT3782AFE
LT3782AFE
3782A
LT3782AEFE#TR
28-Lead Plastic TSSOP
LT3782AIFE
LT3782AIFE#TR
28-Lead Plastic TSSOP
LT3782AEUFD
LT3782AEUFD#TR
LT3782AIUFD#TR
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
LT3782AIUFD
3782A
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT3782A
The l denotes the specifications which apply over the full operating junction
elecTrical characTerisTics
temperature range, otherwise specifications are at TJ = 25°C. VCC = 13V, RSET = 80k, no load on any outputs, unless otherwise noted.
PARAMETER
Overall
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Supply Voltage (V
)
6
40
16
V
CC
Supply Current (I
Shutdown
)
V ≤ 0.5V (Switching Off), V ≤ 40V
11
mA
VCC
C
CC
RUN Threshold
2.3
2.44
80
2.6
V
RUN Threshold Hysteresis
Supply Current in Shutdown
mV
1V ≤ RUN ≤ V
0.4
40
0.65
90
mA
µA
REF
RUN ≤ 0.3V, V ≤ 30V
CC
l
RUN Pin Input Current
V
= 2.3V
–0.5
–2
µA
RUN
Voltage Amplifier g
m
Reference Voltage (V
)
2.42
2.4
2.44
2.464
2.488
V
V
REF
l
l
l
Transconductance
V
V
= 1V, ∆I
=
2µA
200
260
0.2
1.5
0.35
11
370
0.6
µmho
µA
V
VC
VC
Input Current I
= V
= 0
= 0
FB
FB
REF
V High
C
I
VC
I
VC
V Low
C
0.4
14
28
V
Source Current I
V
= 0.7V – 1V, V = V – 100mV
8
13
0.3
6
µA
µA
V
VC
VC
VC
FB
REF
Sink Current I
V
= 0.7V – 1V, V = V + 100mV
20
VC
FB
REF
l
V Threshold for Switching Off (BGATE1, BGATE2 Low)
C
Soft-Start Current I
V
= 0.1V – 2.8V
10
15
µA
SS
SS
Current Amplifier CA1, CA2
Voltage Gain ∆V /∆V
4
C
SENSE
+
–
+
–
Current Limit (V
– V
) (V
– V
)
V
= 2.3V
55
63
70
10
mV
mV
µA
SENSE1
SENSE1
–
SENSE2
SENSE2
FB
Current Limit Mismatch
(∆V
– ∆V
), V = 2.3V
–10
SENSE1
SENSE2
FB
+
+
–
Input Current (I
, I
, I
, I
)
∆V
= 0V
SENSE
60
SENSE1 SENSE1 SENSE2 SENSE2
Oscillator
l
l
l
Switching Frequency
R
SET
R
SET
R
SET
= 130k
= 80k
= 40k
130
212
386
154
250
465
177
288
533
kHz
kHz
kHz
Synchronization Pulse Threshold on SYNC Pin
Rising Edge V
0.8
1.2
2
V
SYNC
Synchronization Frequency Range
(Note: Operation Switching Frequency Equals
Half of the Synchronization Frequency)
R
SET
R
SET
R
SET
= 130k
= 80k
= 40k
180
290
550
240
392
715
kHz
kHz
kHz
V
R
SET
= 80k
2.3
V
RSET
l
l
Maximum Duty Cycle
V
= V – 25mV, R > 80k
90
83
94
90
%
%
FB
REF
SET
SET
R
= 40k
Duty Cycle Limit
R
SET
= 80k, V
≤ 0.3V
= 1.2V
50
75
%
%
DCL
DCL
DCL
V
V
= V
Max Duty Cycle
RSET
l
DCL Pin Input Current
V
≤ 0.3V
–0.1
–0.3
µA
DCL
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LT3782A
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TJ = 25°C. VCC = 13V, RSET = 80k, no load on any outputs, unless otherwise noted.
PARAMETER
Gate Driver
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
I
< 70mA
GBIAS
10.2
11
11.7
10.5
V
GBIAS
l
l
BGATE1, BGATE2 High Voltage
13V ≤ V ≤ 24V, I
V
= –100mA
7.8
3.8
9.2
5
V
V
CC
= 8V, I
BGATE
= –100mA
BGATE
CC
BGATE1, BGATE2 Source Current (Peak)
Capacitive Load >22µF
Capacitive Load >50µF
3
4
A
A
l
l
BGATE1, BGATE2 Low Voltage
8V ≤ V ≤ 24V, I
= 100mA
0.5
0.7
V
CC
BGATE
BGATE1, BGATE2 Sink Current (Peak)
Capacitive Load >22µF
Capacitive Load >50µF
3
4
A
A
SGATE1, SGATE2 High Voltage
SGATE1, SGATE2 Low Voltage
SGATE1, SGATE2 Peak Current
Delay of BGATE High
8V ≤ V ≤ 24V, I
= –20mA
= 20mA
4.5
5.5
0.5
100
6.7
0.7
V
V
CC
SGATE
8V ≤ V ≤ 24V, I
CC
SGATE
500pF Load
mA
DELAY Pin and R Pin Shorted
100
150
250
500
ns
ns
ns
ns
SET
V
DELAY
V
DELAY
V
DELAY
= 1V
= 0.5V
= 0.25V
l
Delay Pin Input Current
V
DELAY
= 0.25V
–0.1
–0.3
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
full –40°C to 125°C operating junction temperature range. The maximum
ambient temperature is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 2: The LT3782AE is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3782AI is guaranteed to meet performance specifications over the
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Typical perForMance characTerisTics TJ = 25°C unless otherwise noted.
∆VREF vs VCC, ∆Frequency vs VCC
(RSET = 80k)
VGBIAS vs IGBIAS
ICC vs VCC
11.0
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10.0
20
18
16
14
12
10
8
3
2
12
10
8
1
∆V
REF
0
6
–1
–2
–3
–4
–5
4
2
∆FREQUENCY
6
0
4
–2
–4
2
0
50
(mA)
0
100
6
8
10 12 14 16 18 20 22 24 26 28 30
(V)
6
9
12
15 18
(V)
21 24 27 30
I
V
GBIAS
V
CC
CC
3782A G01
3782A G02
3782A G03
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LT3782A
Typical perForMance characTerisTics TJ = 25°C, unless otherwise noted.
Current Limit Threshold
vs Temperature
Reference Voltage
vs Temperature
Switching Frequency vs RFREQ
600
500
400
300
200
100
2.446
2.444
2.442
2.440
2.438
2.436
2.434
70
67
64
61
58
55
0
20 40 60 80 100 120 140 160 180 200
(kΩ)
30
55
–45 –20
5
80 105 130
0
25
75
100
125
150
50
R
JUNCTION TEMPERATURE (°C)
TEMPERATURE (°C)
FREQ
3782A G04
3782A G10
3782A G05
SGATE (Low) to BGATE (High)
Delay vs VDELAY (RSET = 80k)
V
GBIAS vs IGBIAS at Start-Up
(Charging 2µF)
1000
900
800
700
600
500
400
300
200
100
0
14
800
700
600
500
400
300
200
100
0
12
10
8
V
GBIAS
6
4
I
GBIAS
2
0
–2
0
0.5
1.0
V
1.5
(V)
2.0
2.5
0
250µ
500µ
750µ
1m
TIME (s)
DELAY
3782A G07
3782A G06
Switching Frequency
vs Duty Cycle
Maximum Duty Cycle Limit
vs VDCL (RSET = 80k)
105
100
95
120
110
100
90
80
90
70
60
85
50
40
80
0.9 1.2
(V)
100
200
300
400
500
600
0
0.3 0.6
1.5 1.8 2.1 2.4
SWITCHING FREQUENCY (kHz)
V
DCL
3782A G08
3782A G09
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LT3782A
pin FuncTions (FE/UFD)
SGATE2(Pin1/Pin26):SecondPhaseSynchronousDrive
Signal. An external driver buffer is needed to drive the top
synchronous power FET.
SS (Pin 14/Pin 11): Soft-Start. A capacitor on this pin sets
the output ramp up rate. The typical time for SS to reach
the programmed level is (C • 2.44V)/10µA.
SGATE1 (Pin 2/Pin 27): First Phase Synchronous Drive
Signal. An external driver buffer is needed to drive the top
synchronous power FET.
V (Pin15/Pin12):Theoutputoftheg erroramplifierand
C m
the control signal of the current loop of the current-mode
PWM. Switching starts at 0.7V, and higher V voltages
C
corresponds to higher inductor current.
GND (Pin 4, Exposed Pad Pin 29/Pin 28, Exposed Pad
Pin 29): Ground. Solder the exposed pad to the PCB
ground plane for rated thermal performance. The exposed
pad should be connected to the GND pin as close to the
IC as possible.
FB (Pin 16/Pin 13): Error Amplifier Inverting Input. A
resistor divider to this pin sets the output voltage.
RUN (Pin 17/Pin 14): LT3782A goes into shutdown mode
when V
is below 2.3V and goes to low bias current
RUN
SYNC (Pin 5/Pin 1): Synchronization Input. The pulse
widthcanrangefrom10%to70%. Notethattheoperating
frequency is half of the sync frequency.
shutdown mode when V
is below 0.3V.
RUN
V
(Pin 19/Pin 16): Gate Driver BGATE2 Ground. This
EE2
pin should be connected to ground as close to the IC as
DELAY(Pin6/Pin2):Whensynchronousdriversareused,
the programmable delay that delays BGATE turns on after
SGATE turns off.
possible.
BGATE2 (Pin 20/Pin 17): Second Phase MOSFET Driver.
GBIAS2 (Pin 21/Pin 18): Bias for Gate Driver BGATE2.
ShouldbeconnectedtoGBIASoranexternalpowersupply
between 12V to 14V.
DCL (Pin 7/Pin 3): This pin programs the limit of the
maximum duty cycle. When connected to V
, it oper-
RSET
ates at natural maximum duty cycle, approximately 90%.
GBIAS1 (Pin 22/Pin 21): Bias for Gate Driver BGATE1.
Should be connected to GBIAS2.
+
SENSE1 (Pin8/Pin4):FirstPhaseCurrentSenseAmplifier
Positive Input. An RC filter is required across the current
sense resistor. Current limit threshold is set at 63mV.
BGATE1 (Pin 23/Pin 22): First Phase MOSFET Driver.
–
V
(Pin 24/Pin 23): Gate Driver BGATE1 Ground. This
SENSE1 (Pin 9/Pin 5): First Phase Current Sense Ampli-
EE1
pin should be connected to ground as close to the IC as
fier Negative Input.
possible.
SLOPE (Pin 10/Pin 6): A resistor from SLOPE to GND
increases the internal current mode PWM slope com-
pensation.
V
CC
(Pin 27/Pin 24): Chip Power Supply. Good supply
bypassing is required.
GBIAS (Pin 28/Pin 25): Internal 11V regulator output for
biasing internal circuitry. Should be connected to GBIAS1
and GBIAS2. A bypass low ESR capacitor of 2µF or larger
is needed and should be connected directly to the pin to
minimize parasitic impedance.
R
(Pin 11/Pin 7): A resistor from R to GND sets the
SET
SET
oscillator charging current and the operating frequency.
–
SENSE2 (Pin 12/Pin 8): Second Phase Current Sense
Amplifier Negative Input.
+
SENSE2 (Pin 13/Pin 10): Second Phase Current Sense
NC(Pins3,18,25,26/Pins9,15,19,20):NotConnected.
Can be connected to GND.
Amplifier Positive Input. An RC filter is required across
the current sense resistor. Current limit threshold is set
at 63mV.
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LT3782A
block DiagraM
V
V
OUT
IN
L1
D1
V
CC
15µH
V
= V – 1V AND CLAMPED AT 11V
CC
GBIAS
C
IN
20µF
27
REGULATOR
L2
D2
GBIAS1
+
15µH
C
LOW POWER
SHUTDOWN
OUT
100µF
22
21
28
+
–
+
–
+
R6
R8
GBIAS2
GBIAS
C3
2µF
A5
A11
A8
RUN
17
–
+
+
+
0.5V
7V
A6
V
CC
– 2.5V
R
F1
+
–
R
F2
A7
+
A20
2.44V
SGATE1
DELAY
2
6
A4
A1
ONE SHOT
GBIAS1
A9
R
SET
+
–
+
A12
2.5V
BGATE1
BGATE1
A13
23
8
M1
R
A14
R1
50k
SLOPE COMP
CH1
R7
+
–
SENSE1
S1
10Ω
C2
2nF
+
BLANKING
SENSE1
PWM1
R3
9
V
–
+
EE1
24
A3
BGATE1
CL1
–
+
SGATE1
SET
DELAY
60mV
SGATE2
1
A15
A17
+
–
+
A16
2.5V
DELAY
BGATE2
ONE SHOT
GBIAS2
BGATE2
A18
A2
20
13
M2
A19
R2
50k
SLOPE COMP
CH2
R9
+
–
R
S2
SENSE2
10Ω
SET
SLOPE
SYNC
C4
2nF
+
BLANKING
CH1
CH2
SENSE2
SLOPE
COMP
PWM2
10
5
R4
S
R
S
R
12
19
V
–
EE2
A10
R
SET
D6
D7
FB
11
OSC
CK
D
Q
Q
+
–
16
–
3782A BD
LOGIC
R
FREQ
+
GM
C5
20pF
NOTE:
CL2
PACKAGE BOTTOM METAL PLATE (PIN 29)
IS FUSED TO CHIP DIE AGND
V
REF
+
GND
I1
10µA
60mV
4
D4
4V
V
C
SS
14
7
15
R5
2k
C7
10nF
DCL
C1
2000pF
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LT3782A
applicaTions inForMaTion
Operation
Soft-Start and Shutdown
The LT3782A is a two phase constant frequency current
mode boost controller. Switching frequency can be pro-
grammed up to 500kHz. During normal switching cycles,
the two channels are controlled by internal flip-flops and
are 180 degrees out-of-phase.
During soft-start, the voltage on the SS pin (V ) controls
SS
the output voltage. The output voltage thus ramps up fol-
lowing V . The effective range of V is from 0V to 2.44V.
SS
SS
The typical time for the output to reach the programmed
level is:
ReferringtotheBlockDiagram, theLT3782A’sbasicfunc-
C • 2.44V
t =
tionsincludeatransconductanceamplifier(g )toregulate
m
10µA
the output voltage and to control the current mode PWM
current loop. It also includes the necessary logic and flip-
flop to control the PWM switching cycles, two high speed
gate drivers to drive high power N-channel MOSFETs, and
2-phase control signals to drive external gate drivers for
optional synchronous operation.
C is the capacitor connected from the SS pin to GND.
Undervoltage Lockout and Shutdown
Only when V
is higher than 2.45V V
will be active
RUN
GBIAS
and the switching enabled. The LT3782A goes into low
current shutdown when V is below 0.3V. A resistor
In normal operation, each switching cycle starts with a
switch turn-on. The inductor current of each channel is
sampled through the current sense resistor and amplified
RUN
divider can be used on RUN pin to set the desired V
undervoltage lockout voltage. 80mV of hysteresis is built
in on RUN pin thresholds.
CC
then compared to the error amplifier output V to turn
C
the switch off. The phase delay of the second channel is
controlled by the divide-by-two D flip-flop and is exactly
180 degrees out-of-phase of the first channel. With a re-
sistor divider connected to the FB pin, the output voltage
is programmed to the desired value. The 10V gate drivers
aresufficienttodrivemosthighpowerN-channelMOSFET
in many industrial applications.
Oscillation Frequency Setting and Synchronization
The switching frequency of LT3782A can be set up to
500kHz by a resistor R
from pin R to ground.
FREQ
SET
For f = 250kHz, R
= 80k
SET
FREQ
Oncetheswitchingfrequencyf ischosen, R
canbe
SET
FREQ
foundfromtheSwitchingFrequencyvsR
graphfound
FREQ
Additional important features include shutdown, cur-
rent limit, soft-start, synchronization and programmable
maximum duty cycle. Additional slope compensation can
be added also.
under the Typical Performance Characteristics section.
Note that because of the 2-phase operation, the internal
oscillator is running at twice the switching frequency. To
synchronizetheLT3782Atothesystemfrequencyf
,
SYSTEM
Output Voltage Programming
the synchronizing frequency f
should be two times
SYNC
f
,andtheLT3782Aswitchingfrequencyf should
With a 2.44V feedback reference voltage V , the output
SYSTEM
SET
REF
be set below 80% of f
.
V
is programmed by a resistor divider as shown in
SYSTEM
OUT
the Block Diagram.
f
= 2f
and f < (f
• 0.8)
SYNC
SYSTEM
SET
SYSTEM
⎛
⎞
⎟
⎠
RF1
RF2
For example, to synchronize the LT3782A to 200kHz sys-
tem frequency f , f needs to be set at 400kHz
VOUT = 2.44 1+
⎜
SYSTEM SYNC
⎝
and f
needs to be set at 160kHz. From the Switching
SET
Frequency vs R
graph found under the Typical Per-
FREQ
formance Characteristics section, R
= 130k.
FREQ
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LT3782A
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Witha200nsone-shottimeronchip,theLT3782Aprovides
flexibility on the external sync pulse width. The sync pulse
threshold is about 1.2V (Figure 1). This pin can be floated
when the sync function is not used.
-
to drive external MOSFET drivers for synchronous recti
fier operation. Note that SGATE drives the top switch and
BGATEdrivesthebottomswitch.To avoidcrossconduction
between top and bottom switches, the BGATE turn-on is
delayed 100ns (when DELAY pin is tied to R pin) from
SET
Current Limit
SGATE turn-off (see Figure 2). If a longer delay is needed
to compensate for the propagation delay of external gate
Current limit is set by the 63mV threshold across SEN1P,
SEN1N for channel one and SEN2P, SEN2N for channel
driver,aresistordividercanbeusedfromR togroundto
SET
program V
for the longer delay needed. For example,
two. By connecting an external resistor R (see Block
DELAY
S
for a switching frequency of 250kHz and delay of 150ns,
then R + R should be 80k and V should
Diagram), the current limit is set for 63mV/R . R should
S
S
be placed very close to the power switch with very short
traces. A low pass R filter is needed across R to filter out
FREQ1
be 1V, with V
= 32.5k (see Figure 3).
FREQ2
DELAY
= 47.5k and R
= 2.3V then R
RSET
FREQ1 FREQ2
C
S
the switching spikes. Good Kelvin sensing is required for
accurate current limit. The input bypass capacitor ground
should be at the same ground point of the current sense
resistor to minimize the ground current path.
Duty Cycle Limit
When DCL pin is shorted to R
pin and switching fre-
> 80k), the maximum
duty cycle of LT3782A will be at least 90%. The maximum
duty cycle can be clamped to 50% by grounding the DCL
voltage to 1.2V with a
resistor divider from R pin to ground. The typical DCL
SET
quency is less than 250kHz (R
FREQ
Synchronous Rectifier Switches
For high output voltage applications, the power loss of the
catchdiodesarerelativelysmallbecauseofhighdutycycle.
If diodes power loss or heat is a concern, the LT3782A
provides PWM signals through SGATE1 and SGATE2 pins
pin or to 75% by forcing the V
DCL
SET
pin input current is 0.1µA.
5V TO 20V
5k
LT3782A
BGATE1
SYNC
SGATE1
SET
DELAY
VN2222
3782A F01
PULSE WIDTH > 200ns
3782A F02
Figure 1. Synchronizing with External Clock
Figure 2. Delay Timing
DELAY
LT3782A
R
SET
R
3782A F03
FREQ1
47.5k
R
FREQ2
32.5k
Figure 3. Increase Delay Time
3782afc
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Slope Compensation
Based on the fact that, ideally, the output power is equal
to the input power, the maximum average input current is:
IO(MAX)
The LT3782A is designed for high voltage and/or high
current applications, and very often these applications
generate noise spikes that can be picked up by the cur-
rent sensing amplifier and cause switching jitter. To avoid
switching jitter, careful layout is absolutely necessary to
minimize the current sensing noise pickup. Sometimes
increasing slope compensation to overcome the noise
can help to reduce jitter. The built-in slope compensa-
I
=
IN(MAX)
1–DMAX
The peak current is:
IO(MAX)
IIN(PEAK) = 1.2 •
1–DMAX
The maximum duty cycle, D
, should be calculated at
MAX
tion can be increased by adding a resistor R
from
SLOPE
increases
allowed is
minimum V .
IN
SLOPE pin to ground. Note that smaller R
SLOPE
SLOPE
Power Inductor Selection
slope compensation and the minimum R
/2.
R
FREQ
In a boost circuit, a power inductor should be designed
to carry the maximum input DC current. The inductance
should be small enough to generate enough ripple current
to provide adequate signal to noise ratio to the LT3782A.
An empirical starting of the inductor ripple current (per
phase) is about 40% of maximum DC current, which is
half of the input DC current in a 2-phase circuit:
Layout Considerations
To prevent EMI, the power MOSFETs and input bypass
capacitor leads should be kept as short as possible. A
groundplaneshouldbeusedundertheswitchingcircuitry
to prevent interplane coupling and to act as a thermal
spreading path. Note that the bottom pad of the package
is the heat sink, as well as the IC signal ground, and must
be soldered to the ground plane.
IOUT(MAX) • VOUT
IOUT(MAX) • VOUT
ΔIL ≅ 40% •
= 20% •
2V
V
IN
IN
Inaboostconverter,theconversiongain(assuming100%
efficiency) is calculated as (ignoring the forward voltage
drop of the boost diode):
where V , V
and I
are the DC input voltage, output
OUT
IN OUT
voltage and output current, respectively.
And the inductance is estimated to be:
VOUT
1
=
V •D
fs • ΔIL
IN
V
1−D
L =
IN
where D is the duty ratio of the main switch. D can then
be estimated from the input and output voltages:
where f is the switching frequency per phase.
s
The saturation current level of inductor is estimated to be:
V
V
VOUT
IN(MIN)
IN
D = 1−
;DMAX = 1−
VOUT
IOUT(MAX) • VOUT
ΔIL
I
IN
ISAT
≥
+
≅ 70% •
2
2
V
IN(MIN)
The Peak and Average Input Currents
The control circuit in the LT3782A measures the input
current by using a sense resistor in each MOSFET source,
so the output current needs to be reflected back to the
input in order to dimension the power MOSFET properly.
3782afc
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LT3782A
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Sense Resistor Selection
taken to ensure that the converter is capable of delivering
therequiredloadcurrentoveralloperatingconditions(line
voltage and temperature), and for the worst-case speci-
During the switch on-time, the control circuit limits the
maximum voltage drop across the sense resistor to about
63mV. The peak inductor current is therefore limited to
63mV/R. The relationship between the maximum load
fications for V
and the R
of the MOSFET
SENSE(MAX)
DS(ON)
listed in the manufacturer’s data sheet.
The power dissipated by the MOSFET in a 2-phase boost
current, duty cycle and the sense resistor R
is:
SENSE
converter is:
1–DMAX
2
R ≤ VSENSE(MAX)
•
⎛
⎜
⎝
⎞
⎟
⎠
IO(MAX)
2
IO(MAX)
1.2 •
2
PFET
=
•RDS(ON) •D •ρT
1–D
(
)
Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-sourcebreakdownvoltage(BV ),thethreshold
⎛
⎞
⎟
⎠
IO(MAX)
⎜
2
⎝
2
DSS
DS(ON)
+k • VO •
•CRSS • f
1–D
voltage(V
),theon-resistance(R
)versusgate-
(
)
GS(TH)
to-source voltage, the gate-to-source and gate-to-drain
2
The first term in the equation above represents the I R
losses in the device, and the second term, the switching
losses.Theconstant,k=1.7,isanempiricalfactorinversely
related to the gate drive current and has the dimension
charges (Q and Q , respectively), the maximum drain
GS
GD
current (I
) and the MOSFET’s thermal resistances
D(MAX)
and R
(R
).
TH(JA)
TH(JC)
of 1/current. The ρ term accounts for the temperature
The gate drive voltage is set by the 10V GBIAS regulator.
Consequently, 10V rated MOSFETs are required in most
high voltage LT3782A applications.
T
coefficientoftheR
oftheMOSFET,whichistypically
DS(ON)
0.4%/°C. Figure 4 illustrates the variation of normalized
R
over temperature for a typical power MOSFET.
DS(ON)
Pay close attention to the BV
specifications for the
DSS
MOSFETs relative to the maximum actual switch voltage
in the application. The switch node can ring during the
turn-off of the MOSFET due to layout parasitics. Check
the switching waveforms of the MOSFET directly across
the drain and source terminals using the actual PC board
layout(notjustonalabbreadboard!)forexcessiveringing.
2.0
1.5
1.0
0.5
0
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET,thepowerdissipatedbythedevicemustbeknown.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3782A F04
the positive temperature coefficient of its R
). As a
DS(ON)
Figure 4. Normalized RDS(ON) vs Temperature
result, some iterative calculation is normally required to
determine a reasonably accurate value. Care should be
3782afc
11
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From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
willfurtherreducetheinputcapacitorripplecurrentrating.
The ripple current is plotted in Figure 5. Please note that
the ripple current is normalized against:
VIN
T = T + P • R
J
A
FET
TH(JA)
Inorm
=
L • fs
The R
to be used in this equation normally includes
TH(JA)
the R
for the device plus the thermal resistance from
TH(JC)
the case to the ambient temperature (R
). This value
TH(CA)
Output Capacitor Selection
of T can then be compared to the original, assumed value
J
The voltage rating of the output capacitor must be greater
than the maximum output voltage with sufficient derat-
ing. Because the ripple current in output capacitor is a
pulsating square wave in a boost circuit, it is important
that the ripple current rating of the output capacitor
be high enough to deal with this large ripple current.
Figure 6 shows the output ripple current in the 1- and
2-phase designs. As shown, the output ripple current of a
2-phase boost circuit reaches almost zero when the duty
cycleequals50%ortheoutputvoltageistwiceasmuchas
theinputvoltage.Thusthe2-phasetechniquesignificantly
reduces the output capacitor size.
used in the iterative calculation process.
Input Capacitor Choice
The input capacitor must have high enough voltage and
ripplecurrentratingstohandlethemaximuminputvoltage
and RMS ripple current rating. The input ripple current in
a boost circuit is very small because the input current is
continuous.With2-phaseoperation,theripplecancellation
1.00
0.90
0.80
0.70
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.60
1-PHASE
0.50
0.40
2-PHASE
0.30
0.20
0.10
0
1-PHASE
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE
2-PHASE
3782A F05
VIN
=
0.4 0.5
DUTY CYCLE OR (1-V /V
0.1 0.2 0.3
0.6 0.7 0.8 0.9
Inorm
)
IN OUT
L • fs
3782A F06
The RMS Ripple Current is About 29% of
the Peak-to-Peak Ripple Current.
Figure 6. Normalized Output RMS Ripple Currents in Boost
Converter: 1-Phase and 2-Phase. IOUT Is the DC Output Current.
Figure 5. Normalized Input Peak-to-Peak Ripple Current
3782afc
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For a given V and V , we can calculate the duty cycle D
improvement. Although all dissipative elements in the
circuit produce losses, four main sources usually account
for the majority of the losses in LT3782A application
circuits:
IN
OUT
andthenderivetheoutputRMSripplecurrentfromFigure6.
After choosing output capacitors with sufficient RMS
ripple current rating, we also need to consider the ESR
requirement if electrolytic caps, tantalum caps, POSCAPs
or SP CAPs are selected. Given the required output ripple
1. The supply current into V . The V current is the sum
IN
IN
of the DC supply current I (given in the Electrical Char-
Q
voltagespec∆V (inRMSvalue)andthecalculatedRMS
OUT
acteristics)andtheMOSFETdriverandcontrolcurrents.
ripple current ∆I , one can estimate the ESR value of
OUT
The DC supply current into the V pin is typically about
IN
the output capacitor to be
7mA and represents a small power loss (much less
ΔVOUT
ESR ≤
than 1%) that increases with V . The driver current
IN
resultsfromswitchingthegatecapacitanceofthepower
MOSFET; this current is typically much larger than the
DC current. Each time the MOSFET is switched on and
ΔIOUT
External Regulator to Bias Gate Drivers
then off, a packet of gate charge Q is transferred from
G
For applications with V higher than 24V, the IC tempera-
GBIAS to ground. The resulting dQ/dt is a current that
IN
turemaygettoohigh.To reduceheat,anexternalregulator
must be supplied to the GBIAS capacitor through the
between12Vto14Vshouldbeusedtooverridetheinternal
V pin by an external supply. In normal operation:
IN
V
regulator to supply the current needed for BGATE1
GBIAS
I
≈ I = f • Q
Q G
Q(TOT)
and BGATE2 (see Figure 7).
P = V • (I + f • Q )
IC
IN
Q
G
Efficiency Considerations
2. Power MOSFET switching and conduction losses:
2
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (¥100%). Percent
efficiency can be expressed as:
⎛
⎜
⎜
⎞
⎟
⎟
IO(MAX)
2
PFET
=
•RDS(ON) •DMAX •ρT
1–D
⎜
⎟
MAX
⎜
⎟
% Efficiency = 100% – (L1 + L2 + L3 + …),
⎝
⎠
where L1, L2, etc. are the individual loss components
as a percentage of the input power. It is often useful to
analyze individual losses to determine what is limiting
the efficiency and which change would produce the most
IO(MAX)
2
2
+ k • VO •
•CRSS • f
1–DMAX
LT3782A
GBIAS
+
12V
GBIAS1
GBIAS2
3782A F07
2µF
Figure 7
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3. The I R losses in the sense resistor can be calculated
2
PCB Layout Considerations
almost by inspection:
To achieve best performance from an LT3782A circuit,
the PC board layout must be carefully done. For lower
power applications, a two-layer PC board is sufficient.
However, at higher power levels, a multiplayer PC board
is recommended. Using a solid ground plane under the
circuit is the easiest way to ensure that switching noise
does not affect the operation.
2
⎛
⎜
⎜
⎞
⎟
⎟
IO(MAX)
2
PR(SENSE)
=
•R •DMAX
1–D
⎜
⎟
MAX
⎜
⎟
⎝
⎠
4. The losses in the inductor are simply the DC input cur-
rent squared times the winding resistance. Expressing
In order to help dissipate the power from MOSFETs and
diodes, keep the ground plane on the layers closest to the
layers where power components are mounted. Use power
planes for MOSFETs and diodes in order to improve the
spreadingoftheheatfromthesecomponentsintothePCB.
this loss as a function of the output current yields:
2
⎛
⎜
⎜
⎞
⎟
⎟
IO(MAX)
2
PR(WINDING)
=
•RW
1–D
⎜
⎟
MAX
⎜
⎟
⎝
⎠
Forbestelectricalperformance,theLT3782Acircuitshould
be laid out as follows:
5. Losses in the boost diode. The power dissipation in the
boost diode is:
Place all power components in a tight area. This will
minimize the size of high current loops. Orient the input
andoutputcapacitorsandcurrentsenseresistorsinaway
that minimizes the distance between the pads connected
to ground plane.
IO(MAX)
PDIODE
=
• VD
2
The boost diode can be a major source of power loss
in a boost converter. For 13.2V input, 42V output at 3A,
a Schottky diode with a 0.4V forward voltage would
dissipate 600mW, which represents about 1% of the
input power. Diode losses can become significant at
low output voltages where the forward voltage is a
significant percentage of the output voltage.
Place the LT3782A and associated components tightly
together and next to the section with power components.
Use a local via to ground plane for all pads that connect to
ground. Use multiple vias for power components.
Connect the current sense inputs of LT3782A directly
to the current sense resistor pads. Connect the current
sense traces on the opposite sides of pads from the traces
carrying the MOSFETs source currents to ground. This
technique is referred to as Kelvin sensing.
6. Other losses, including C and C ESR dissipation and
IN
O
inductor core losses, generally account for less than
2% of the total losses.
3782afc
14
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LT3782A
Typical applicaTions
10V to 24V Input to 24V, 8A Output Boost Converter
10V TO 24V INPUT
1
28
SGATE2
GBIAS
2R2
2
27
SGATE1
V
CC
L1
3
26
25
24
23
D1
PDS1040
PB2020-103
NC
NC
NC
1µF
4
Q1
GND
PH3330
LT3782A
5
6
C
OUT2
330µF, 35V, ×2
SYNC
V
EE1
CS1
DELAY
BGATE1
GBIAS1
GBIAS2
0.004Ω
7
8
22
21
DCL
OUTPUT
24V
8A
10Ω
+
–
CS1
SENSE1
C
C
OUT1
22µF, 25V, ×4
IN
2.2µF
10nF
22µF
25V
9
20
19
SENSE1
SLOPE
BGATE2
0.004Ω
CS2
59k
82k
10
V
EE2
NC
825k
274k
11
12
18
17
R
SET
Q2
PH3330
–
+
SENSE2
RUN
FB
10nF
10Ω
24.9k
221k
13
14
16
15
L2
PB2020-103
CS2
SENSE2
SS
D2
PDS1040
V
C
3782A TA02
4.7nF
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
C
C1
R
C1
C
C2
6.8nF
13.3k
*OUTPUT CURRENT WITH BOTH INPUTS PRESENT
100pF
Efficiency
100
98
96
94
92
90
88
86
15V
IN
12V
IN
0
1
2
3
4
5
6
7
8
I
(A)
OUT
3782A TA02b
3782afc
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LT3782A
Typical applicaTions
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LT3782A
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
2.74
(.108)
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.60 0.10
4.50 0.10
SEE NOTE 4
6.40
2.74
(.252)
(.108)
BSC
0.45 0.05
1.05 0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV K 0913
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
3782afc
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LT3782A
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 ±0.05
4.00 ±0.10
(2 SIDES)
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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revision hisTory
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DATE
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A
2/10
Change Ambient Temp on FE Package
Changes to Order Information
Addition to Note 2
2
2
4
Change T = 25°C to T = 25°C
3, 4, 5
A
J
Changes to Pin Functions
6
Changes to Block Diagram
7
Changes to Typical Applications
16, 20
Updated Related Parts
20
1
B
C
4/10
4/14
Add Part Numbers for D1, D2, Q1 and Q2 on Typical Application
Addition to Note 2
4
Adjusted RUN Threshold in the Electrical Characteristics table.
Changed the RUN Pin description in the Pin Functions section.
Changed Duty Cycle Limit in the Applications Information section.
3
6
9
3782afc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
19
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3782A
Typical applicaTion
28V Output Base Station Power Converter with Redundant Input
V
INA
0V TO 28V*
1
2
3
4
5
6
28
27
26
25
24
23
SGATE2
SGATE1
NC
GBIAS
2R2
L1
10µH
V
CC
D1
PDS1040
BAS516
NC
NC
Q1
PH4840S
1µF
GND
C
INA
22µF
LT3782A
C
OUT2
330µF, 35V, ×2
CS1
0.004Ω
SYNC
DELAY
V
EE1
BGATE1
GBIAS1
GBIAS2
7
8
22
21
DCL
OUTPUT
28V
4A (8A**)
10Ω
+
–
CS1
SENSE1
C
OUT1
2.2µF
10nF
10µF, 50V, ×4
9
20
19
SENSE1
SLOPE
BGATE2
0.004Ω
CS2
59k
82k
10
V
EE2
NC
C
INB
22µF
825k
274k
11
12
18
17
R
SET
Q2
PH4840S
–
+
SENSE2
RUN
FB
10nF
10Ω
24.9k
261k
13
14
16
15
L2
10µH
BAS516
CS2
SENSE2
SS
D2
PDS1040
V
C
3782A TA03
NOTE:
4.7nF
V
INB
0V TO 28V*
C
C1
4.7nF
*INPUT VOLTAGE RANGE FOR VINA AND VINB IS 0V TO 28V.
AT LEAST ONE OF THE INPUTS MUST BE 12V OR HIGHER.
R
C1
C
C2
100pF
15k
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
**OUTPUT CURRENT WITH BOTH INPUTS 12V OR HIGHER
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC3862/LTC3862-1 Multiphase Current Mode Step-Up DC/DC
Controller
2.5V ≤ V ≤ 32V, 5V or 10V Gate Drive, 75kHz to 500kHz, TSSOP-24,
IN
SSOP-24, 5mm × 5mm QFN-24
LTC3788/LTC3788-1 Multiphase, Dual Output Synchronous Step-Up 2.5V ≤ V ≤ 38V, V
Up to 60V, 50kHz to 900kHz, 5mm × 5mm QFN-32,
IN
OUT
Controller
SSOP-28
LTC3813
100V Maximum V
Current Mode
No R
™, 1Ω Gate Driver, Adjustable Off-Time, SSOP-28
, 1Ω Gate Driver, Adjustable Off-Time, TSSOP-16
OUT
SENSE
Synchronous Step-Up DC/DC Controller
LTC3814-5
60V Maximum V
Current Mode Synchronous No R
OUT
SENSE
Step-Up DC/DC Controller
LTC1871/LTC1871-1/ Wide Input Range, No R
Low Quiescent
Adjustable Fixed Synchronizable 50kHz to 1MHz Operating Frequency,
2.5V ≤ V ≤ 36V, MSOP-10
SENSE
LTC1871-7
Current Flyback, Boost and SEPIC DC/DC
Controller
IN
LT3757
Boost, Flyback, SEPIC and Inverting DC/DC
Controller
2.9V ≤ V ≤ 40V, Adjustable Fixed Synchronizable 100kHz to 1MHz Operating
IN
Frequency, 3mm × 3mm DFN-10 and MSOP-10E
LT3758
Boost, Flyback, SEPIC and Inverting DC/DC
Controller
5.5V ≤ V ≤ 100V, Adjustable Fixed Synchronizable 100kHz to 1MHz Operating
IN
Frequency, 3mm × 3mm DFN-10 and MSOP-10E
LTC3805/LTC3805-5 Adjustable Frequency Boost, Flyback and SEPIC
DC/DC Controller
V
and V
Limited Only by External Components, 3mm × 3mm DFN-10,
IN
OUT
MSOP-10E
LTC3803/LTC3803-3/ Flyback DC/DC Controller with Fixed 200kHz or
V
and V Limited Only by External Components, 6-Pin ThinSOT™ Package
OUT
IN
LTC3803-5
300kHz Operating Frequency
LTC3872
No R
Current Mode Boost DC/DC
550kHz Fixed Frequency, 2.75V ≤ V ≤ 9.8V, ThinSOT Package
IN
SENSE
Controller
LTC3780
High Efficiency Synchronous 4-Switch
Buck-Boost DC/DC Controller
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 30V, SSOP-24, 5mm × 5mm QFN-32
IN
OUT
3782afc
LT 0414 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
LINEAR TECHNOLOGY CORPORATION 2008
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT3782A
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