LT3804EFE [Linear]
Secondary Side Dual Output Controller with Opto Driver; 次级侧双输出控制器，光电驱动程序
| 型号： | LT3804EFE |
| 厂家： | 
Linear |
| 描述： | Secondary Side Dual Output Controller with Opto Driver |
| 文件： | 总16页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LT3804
Secondary Side Dual
Output Controller with Opto Driver
U
June 2003
DESCRIPTIO
FEATURES
The LT®3804 is a high efficiency step-down switching
regulatorwithoptocouplerfeedbackcontrolforregulating
multiple outputs in single-secondary winding isolated
power supplies.
■
Regulates Two Secondary Outputs
Optocoupler Feedback Driver and Second Output
Synchronous Driver Controller
■
■
■
■
■
■
■
True Differential Remote Sensing Regulation
High Switching Frequency: up to 800kHz
Programmable Current Limit
Programmable Soft-Start and Power Good
Automatic Frequency Synchronization
Available in Thermally Enhanced 28-Lead TSSOP
TheLT3804contains anerroramplifierand anoptocoupler
driver to regulate the first (main) output. For the second
output regulation, the LT3804 contains a complete PWM
controller todrivedualsynchronousN-channelMOSFETs.
With leading edge modulation, it operates with either
current or voltage mode control of the primary side. The
LT3804 is synchronized to the falling edge of the trans-
former secondary winding and can be used in single-
ended or double-ended isolated power converter topolo-
gies. A user selectable discontinuous conduction mode
improves light load efficiency.
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APPLICATIO S
■
48V Input Isolated DC/DC Converters
■
Multiple Output Power Supplies
■
Offline Converters
DC/DC Power Modules
■
True differential Kelvin sensing is used for each output
feedback amplifier to achieve high regulation accuracy
and design simplicity. Other features include soft start,
current limit and power good flags.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
V
OUT1
3.3V
V
IN
+
–
L1
1.8µH
V
V
AT 15A
OS1
36V
0.003Ω
+
+
V
CC
BIAS
TO 72V
C
OUT1
LT3804
OS1
SYNC
CL1N
•
•
L2
1.8µH
Q1
OUT2
TGATE
SW
Q4
CL1P
V
1.8V
AT 15A
OUT2
0.003Ω
LTC1693-1
V
CC
OUT1
IN1
C
OUT2
Q3
x2
Q2
x2
BGATE
PGND
CSET
IN2
390pF
–
+
V
V
GNDS1
OS1
CL2P
CL2N
•
•
•
•
TG
BG
604Ω
V
AOUT2
OS1
V
V
FB1
LT3781
2.74k
3.01k
SG
V
FB2
V
V
1.5k
REF
AOUT1
+
–
V
C
FB
GNDS2
OPTO
3804 F01
C
, C : SANYO POSCAP 4TPE680MF 680µF/4V
OUT1 OUT2
ISOLATION
BOUNDARY
L1, L2: SUMIDA CEP125-IR8MC-H
Q1-Q4: SILICONIX Si7892DP
Figure 1. 250kHz, 3.3V and 1.8V Output Isolated DC/DC Converter (Simplified Schematic)
3804i
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LT3804
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
VCC Supply Voltage.................................................. 26V
BOOST Pin Voltage with Respect to SW Pin ............ 10V
BOOST Pin Voltage with Respect to GND Pin .......... 35V
SYNC Pin Voltage (Note 2) ..................................... 30V
GNDS1 Pin Voltage................................................... 1V
GNDS2 Pin Voltage................................................... 1V
Operating Junction Temperature Range
LT3804E (Note 3) ..............................–40°C to 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
NUMBER
CL1P
CL1N
1
2
28 I
LCOMP1
27 GBIAS
26 BGATE
LT3804EFE
I
3
LCOMP2
BOOST
4
25 V
CC
TGATE
SW
5
24 PGND
23 OPTO
6
29
CSET
7
22
21
20
19
18
17
16
15
V
AOUT1
8
SYNC
SS2
CL2N
9
CL2P
10
11
12
13
14
PGIN1
PGIN2
GNDS2
GNDS1
PGOOD
V
FB1
SS1
BGS
V
FB2
V
AOUT2
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD IS SGND (PIN 29)
MUST BE CONNECTED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, GNDS1=GNDS2=0V, operating maximum VCC = 25V, no load
on any outputs, unless otherwise noted.
PARAMETER
Overall
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage (V
)
●
8
25
13
V
CC
Supply Current (I
)
V
V
≤ 1.2V (Switching Off)
9
mA
VCC
AOUT2
BOOST
BOOST Pin Current
= V + 8V, 0V ≤ V ≤ 24V
SW SW
TGATE High
TGATE Low
2
2
3
3
mA
mA
Voltage Amplifier V ,V
A1 A2
Reference Voltage (V
,V
)
Common Mode: ±20mV (0°C to 125°C)
(–40°C to 125°C)
0.591
0.587
0.6
0.609
0.609
V
V
REF1 REF2
●
●
∆V over Common Mode: ±100mV
REF
–3
3
mV
µA
µA
V
V
, V Pin Input Current
FB1 FB2
V
= V
, V = V
REF1 FB2 REF2
0.2
–50
1.75
1.45
0.7
0.5
FB1
Remote Ground Pin (GNDS1,GNDS2) Current
–100mV ≤ GNDS1, GNDS2 ≤ 100mV
–100
V
V
V
V
V
V
V
High at OA1 Threshold 1.5V
V
V
V
V
V
= V
= V
= V
= V
= V
– 10mV, I
– 10mV, I
+ 10mV, I
– 10mV, I
+ 10mV, I
= –50µA
= –50µA
= 100µA
= –50µA
= 100µA
AOUT1
AOUT1
AOUT1
AOUT2
AOUT2
AOUT1
AOUT2
FB1
FB1
FB1
FB2
FB2
REF1
REF1
REF1
REF2
REF2
VAOUT1
VAOUT1
VAOUT1
VAOUT2
VAOUT2
High at OA1 Threshold 1.25V
V
Low
V
High
4.5
V
Low
0.8
V
Source Current
Source Current
●
●
100
70
230
150
100
10
400
250
µA
µA
dB
MHz
µA
Open-Loop Gain
Gain Bandwidth Product
Soft-Start Current (SS1,SS2)
5
10
24
3804i
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LT3804
ELECTRICAL CHARACTERISTICS
on any outputs, unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, GNDS1=GNDS2=0V, operating maximum VCC = 25V, no load
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Opto Driver Amplifier OA1
OA1 Upper Threshold
OA1 Threshold Hysteresis
●
1.4
1.55
0.25
6
1.65
V
V
V
V
V
OA1 Voltage Gain (V
/V
)
1.2V < V
< 4V, R = 1k
OPTO
●
●
●
5.6
4.5
0
6.4
6
OPTO AOUT1
OPTO
V
V
High
Low
V
V
= 0.9V, I = –10mA
OPTO
5.2
0.1
OPTO
OPTO
OPTO
AOUT1
= V
– 10mV, R = 1k
OPTO
0.25
FB1
REF1
I
Short-Circuit Current Limit
V
V
=V
OPTO
– 10mV, GNDS1 = 0V,
FB1 REF1
= 4V
●
–50
–25
–12
mA
Power Good
Power Good Window Threshold
(PGIN1-GNDS1, PGIN2-GNDS2)
–100mV < GNDS1, GNDS2 < 100mV
0V < PGIN1, PGIN2 < 1V
0.85
100
1.15
0.35
300
300
V
REF
Input Current (PGIN1,PGIN2)
Delay Time for Power Bad
Output Low (PGOOD)
0.2
200
150
µA
25mV Overdrive on PGIN1,PGIN2
2mA into the Pin
●
●
µs
mV
Current Limit Amplifier CA1, CA2
Current Limit Threshold (CL1P-CL1N, CL2P-CL2N)
Common Mode Voltage from 0V to V – 2.5V
CC
V
= 1.2V, V
= 2.5V,
●
40
0
50
8
60
15
mV
mV
V
AOUT1
AOUT2
BGATE Off Threshold at (V
-V
), BGS Pin Float Commond Mode Voltage from 0V to V – 2.5V
CL2P CL2N CC
Switching Off Threshold at I
V
V
0.15
LCOMP2
ILCOMP2
Input Current (CL1P, CL1N, CL2P, CL2N)
Oscillator
= V
, V
= V
CL2N
100
µA
CL2P
CL1N CL2P
Switching Frequency
C = 500pF (NO SYNC)
S
C = 200pF (NO SYNC)
S
●
●
●
170
240
400
200
280
470
240
340
570
kHz
kHz
kHz
S
C = 333pF (NO SYNC)
Synchronization Frequency Range
C = 500pF
S
C = 200pF
S
●
●
●
245
345
575
400
500
800
kHz
kHz
kHz
S
C = 333pF
CSET Ramp Valley Voltage
C = 1000pF (NO SYNC)
0.90
1.15
2.4
2.5
80
1.4
V
V
S
CSET Peak-to-Peak Voltage
C = 1000pF (NO SYNC)
S
Synchronization Pulse Threshold on SYNC Pin
Maximum Duty Cycle
Falling Edge V
V
SYNC
V
= V
– 5mV, C > 333pF
●
●
75
%
FB2
REF2
S
Gate Drivers (TGATE, BGATE)
V
V
V
V
V
I
I
I
I
I
< 25mA
7.5
5
8
6
6
8.5
7.5
7.5
0.5
0.5
V
V
GBIAS
TGATE
BGATE
TGATE
BGATE
GBIAS
TGATE
BGATE
TGATE
BGATE
High (V
High
– V
)
< 50mA, V
< 50mA
= V
– 0.5V
TGATE
SW
BOOST
GBIAS
●
●
●
5
V
Low (V
Low
-V
)
< –50mA
< 50mA
V
TGATE SW
V
Peak Gate Drive Current
Gate Drive Rise and Fall Time
10nF Load
1nF Load
1
A
25
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: The LT3804E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 2: If highter than 30V on SYNC pin is needed, add a 10kΩ resistor in
series with the pin.
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LT3804
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TYPICAL PERFOR A CE CHARACTERISTICS
Voltage Amplifier VA1, VA2 Gain
and Phase
VGBIAS vs IGBIAS Over Junction
Temperature
ICC vs VCC (Switching Off)
120
80
–0
8.1
8.0
7.9
7.8
7.7
13
12
11
10
9
T
= 25°C
T
A
= 25°C
A
–40°C
25°C
GAIN
–50
(–111°)
PHASE
40
–100
8
7
0
–150
–180
125°C
6
0dB, 10MHz
–20
5
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
0
10
I
20
26
8
10 12 14 16 18 20 22 24
(mA)
V
CC
(V)
GBIAS
3804 G03
3804 G01
3804 G02
VREF vs Temperature
∆VREF vs VCC, ∆FREQ vs VCC
CSET vs Switching Frequency
0.602
T
= 25°C
A
CSET = 500pF
A
3
2
800
600
400
200
1.00
0.95
0.90
0.85
0.80
0.75
0.70
T
= 25°C
0.601
0.600
0.599
0.598
0.587
0.596
CSET
MAXIMUM DUTY CYCLE
1
∆V
REF
0
–1
1
∆FREQ
0
–1
10
15
20
25
200
100 300 400 500 600 700 800 900 1000
50
100 125
–40 –20
0
25
75
V
CC
(V)
CSET (pF)
JUNCTION TEMPERATURE (°C)
3804 G04
3804 G05
3804 G06
Current Limit Amplifier CA1 Gain
at VCC = 11V, VCL2N = 5V
Switching Frequency vs
Temperature
GBIAS vs IGBIAS (Charging 2.2µF)
8
7
6
5
4
3
2
1
0
CSET = 500pF
V
V
A
= 11V
= 5V
C
T
= 2.2µF
CC
CL2N
= 25°C
GBIAS
A
300
250
200
150
100
50
12
10
8
= 25°C
215
210
205
200
195
T
V
GBIAS
6
CSET PEAK
4
I
GBIAS
2
CSET VALLEY
0
0
30
40
50
– V
60
70
0
500µs
TIME
1ms
50
100 125
–40 –20
0
25
75
V
(mV)
CL2P
CL2N
JUNCTION TEMPERATURE (°C)
3804 G09
3804 G08
3804 G07
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LT3804
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PI FU CTIO S
CL1P (Pin 1): Current Limit Amplifier CA1 Positive Input. BGS (Pin 16): Bottom Gate Switching Control. CA2 moni-
CA1 drives optocoupler when the first output is in current tors the inductor current and prohibits BGATE from turn-
limit.The threshold is set at 50mV.
ingonwhentheinductorcurrentislow(below8mVacross
the current sense resistor RS2) allowing discontinous
mode operation and avoiding reverse inductor current.
Grounding BGS disables this function, so that the PWM is
always in continuous mode except during start-up.
CL1N (Pin 2): Current Limit Amplifier CA1 Negative Input.
When used, CL1N is connected to the output, and CL1P is
connected to the other end of the output current sense
resistor.
SS1(Pin17):Soft-StartfortheFirstOutput.Acapacitoron
this pin sets the output ramp-up rate. The typical time for
SS1 to reach the programmed level is: (C • 0.6V)/10µA.
ILCOMP2 (Pin 3): Current Limit Amplifier CA2 Compensa-
tion Node. At second output current limit, CA2 pulls down
on this pin to regulate output current.
VFB1 (Pin 18): Voltage Amplifier VA1 Inverting Input. A
resistor divider to this pin sets the first output voltage. The
reference voltage at this pin is VREF1 (0.6V referred to
remote sensing ground GNDS1).
BOOST (Pin 4): Topside (Boosted) Driver Supply.This pin
is used to bootstrap and supply the topside power switch
gatedrivecircuitry.InnormaloperationVBOOST ispowered
fromtheinternallygenerated8VGBIAS;VBOOST=VSW+8V
when TGATE is on.
PGOOD (Pin 19): Power Good. PGOOD goes high to
indicate power good only when both PGIN1 and PGIN2
sensepowergood. Apullupresistorisrequiredonthispin
if the power good function is used.
TGATE (Pin 5): Topside (Boosted) N-Channel MOSFET
Driver. WhenTGATEison, thevoltageisequaltoVSW+6V.
SW (Pin 6): Switch Node Connection to Inductor.
CL2P (Pin 20): Second 0utput Current Limit Amplifier
CA2 Positive Input.The threshold is set at 50mV.
CSET(Pin7): OscillatorFrequencySettingPin.Thecapaci-
tor from this pin to ground sets the PWM switching
frequency.
CL2N (Pin 21): Current Limit Amplifier CA2 Negative
Input. When used, CL2N is connected to the output
capacitor, and CL2P is connected to the other end of the
output current sense resistor.
SYNC (Pin 8): Synchronization Input. This pin should be
connected to the secondary side output of the power
transformer with a series resistor. A filtering capacitor of
10pf is recommended.
VAOUT1 (Pin 22): Voltage Amplifier VA1 Output.
OPTO (Pin 23): Optocoupler Driver. A resistor to the opto
diode is required to set the optocoupler bias current.
Maximum sourcing current is 10mA at 5V.
SS2 (Pin 9): Soft-Start for the Second Output. A capacitor
on this pin sets the output ramp-up rate. The typical time
forSS2to reachthe programmedlevelis: (C•0.6V)/10µA.
PGND (Pin 24): Ground of the Bottom Side N-Channel
MOSFET Driver.
PGIN1 (Pin 10): First Output Power Good Input.The volt-
age setting resistor divider should be connected to GNDS1
if remote sensing is used.
VCC (Pin 25): Supply of the Chip. A low ESR capacitor is
required to bypass the supply.
PGIN2 (Pin 11): Second Output Power Good Input. The
voltage setting resistor divider should be connected to BGATE (Pin 26): Bottom Side N-Channel MOSFET Driver.
GNDS2 if remote sensing is used.
GBIAS (Pin 27): 8V Regulator Output for Boostrapping
GNDS2 (Pin 12): Second Output Remote Ground Sensing. VBOOST. A bypass capacitor of at least 2µF is needed.
GNDS1 (Pin 13): First Output Remote Ground Sensing.
ILCOMP1 (Pin 28): Current Limit Amplifier CA1 Compensa-
tion Node . When the first output is in current limit, CA1
pulls down VAOUT1 pin to regulate the first output current.
VFB2 (Pin 14): Voltage Amplifier VA2 Inverting Input. A
resistor divider to this pin sets the second output voltage.
The reference voltage at this pin is VREF2 (0.6V referred to ExposedPad(Pin29):SignalGround. Mustbeelectrically
remote sensing ground GNDS2).
connected on PCB.
VAOUT2 (Pin 15): Voltage Amplifier VA2 Output.
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LT3804
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BLOCK DIAGRA
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LT3804
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OPERATIO
To generate isolated multiple outputs, most systems use
either multiple secondary windings or cascade regulators
for each additional output. Multiple secondary windings
sacrifice regulation of the auxiliary outputs. Cascaded
regulators require a larger inductor for the main output,
because all of the power is processed in series. By gener-
ating the auxiliary output(s) from the secondary winding
ofthemainoutput, theLT3804allowsforparallelprocess-
ing of the output power. This minimizes the main output
inductor size and directly regulates the auxiliary output.
With synchronous rectification, the system efficiency is
greatly improved.
During normal operation (see Figure 2), a switching cycle
begins at the falling edge of the transformer secondary
voltage VS.
Theinternaloscillatorisreset,turningoffthetopMOSFET,
M1, and turning on the bottom MOSFET, M2. During this
portion of the cycle, the inductor current is discharged by
the output voltage VOUT2. The transformer secondary
voltage, VS, will go high during this portion of the cycle.
Since M1 is off, the switch node voltage, VSW, remains
zero. The inductor current continues to be discharged by
the output voltage VOUT2. This condition lasts until the
ramp signal intersects the feedback error amplifier output
VAOUT2. The top MOSFET M1 turns on, pulling the switch
node voltage to VS. The inductor current of the LT3804
circuitisthenchargedbyVS –VOUT2. Theeffectiveontime
of this buck circuit ends when the secondary voltage
becomes zero. The next cycle repeats. The ideal equation
for duty cycle of the LT3804 is:
The LT3804 regulates both the main and one auxiliary
output, with true remote sensing to achieve high output
accuracy.Toregulatethefirstoutput,theLT3804contains
a high gain error amplifier VA1 and an optocoupler driver
OA1 with a unique feature that reduces output overshoot
toaminimum.FordetailsseetheApplicationsInformation
section. The second output includes a voltage amplifier,
VA2, (see Block Diagram)a voltage mode PWM with
trailing edge synchronization and leading edge modula-
tion, a current limit amplifier, CA2, and high speed syn-
chronous switch drivers.
D2 = VOUT2/VSP
where VOUT2 is the auxiliary output voltage, VSP is the
amplitude of the secondary voltage and D2 is the duty
cycle of the switching node voltage VSW, as defined in
Figure 2.
V
S
RESET
T
D T
1
TRANSFORMER
SECONDARY VOLTAGE
V
V
SP
SYNC SIGNAL V
RESET
RAMP V
CSET
V
AOUT2
TGATE
BGATE
I
L2
T
SWITCH NODE V
SW
D T
2
V
SP
3710 F02
Figure 2. Leading Edge Modulation, Trailing Edge Synchronization
3804i
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LT3804
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APPLICATIO S I FOR ATIO
Synchronization and Oscillator Frequency Setting
For accurate sensing results, GNDS1 and GNDS2 should
stay within –0.1V and 0.1V referred to GND. Note that if
either GNDS1orGNDS2isnotconnected, theLT3804will
be shut down.
The switching is synchronized to the secondary winding
falling edge and the synchronization threshold is typically
2.5V. The synchronization falling edge triggers an internal
inverted ramp (see Figure 2) and starts a new switching
cycle for the leading edge voltage mode PWM. The reason
for using leading edge modulation is to leave the trans-
former primary side peak current sensing undisturbed.
Forpropersynchronization,theoscillatorfrequencyshould
be set lower than the system switching frequency with
tolerances taken into account.
Power Good
When both outputs reach between 90% and 110% of the
programmedlevel, VPGOOD goeshigh(apull-upresistoris
required if the function is used) to signal power good. If
either output rises above 110% or drops below 90%,
V
PGOOD goes low after a 200µs delay. PGIN1 senses the
first output and PGIN2 senses the second output with a
resistor divider. PGIN1 and PGIN2 are compared to the
referencesVREF1 andVREF2 respectively. Resistordividers
should be connected to GNDS1 and GNDS2 with respect
to each output.
f
OSC < (fSL • 0.8)
fSL is the low limit of the system switching frequency and
0.8 is the tolerance of fOSC
.
For example, given a system operating at 200kHz with
15% tolerance, then fSL = 200kHz • 85% = 170kHz; and
fOSC <(170kHz•0.8), sofOSC shouldbesetbelow136kHz.
Current Limit CA1
The first output current limit is set by the 50mV threshold
across CL1P and CL1N, the inputs of the amplifier CA1. By
connecting an external resistor RS1(see Block Diagram),
the current limit is set for 50mV/RS1. C17 on ILCOMP1
stablizes the current limit loop. If current limit is not used,
both CL1P and CL1N should be grounded and C17 is not
needed.
Once fOSC is determined, CSET can be calculated by
CSET = (103540pF/fOSC(kHz)) – 18pF.
For fOSC = 200kHz, CSET = 500pF.
Output Voltage Programming
The LT3804 uses true remote sensing (separate ground
sensing pins, GNDS1 for the first output and GNDS2 for
the second output) to eliminate output error pickup due to
parasitic resistance.
Current Limit CA2
The second output current limit is set by the 50mV
threshold across CL2P and CL2N, the inputs of the ampli-
fierCA2. ByconnectinganexternalresistorRS2 (seeBlock
Diagram), the current limit is set for 50mV/RS2. R6 and C6
on ILCOMP2 stablize the current limit loop. If current limit
is not used, both CL2P and CL2N should be grounded and
the BGS pin should also be grounded to disable compara-
tor CA2; R6 and C6 are not needed.
The feedback reference voltages VREF1 and VREF2 are 0.6V
referred to GNDS1 and GNDS2 respectively. The output
voltage can be easily programmed by a resistor divider, as
shown in the Block Diagram:
V
OUT1 = 0.6 (1 + R13/R14)
VOUT2 = 0.6 (1 + R3/R4)
where R14 connects to GNDS1 and R4 connects to
GNDS2.
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LT3804
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APPLICATIO S I FOR ATIO
Filtering on the SYNC Input
Toshutdownthefirstoutput, theSS1pinshouldbepulled
below 50mV by a small signal VN2222 type N-channel
MOSFET.
A small RC filter with RS = 10k and CS = 10pF is necessary
on the SYNC pin to eliminate fast switching glitches
caused by coupling from external components and layout
parasitics.
Soft-Start and Shutdown Second Output
During soft-start, VSS2 is the reference voltage that con-
trols the output voltage, so the output ramps up following
VSS2. The effective range of VSS2 is from 0V to VREF2. The
typical time for the output to reach the programmed level
is:
Optocoupler Driver
Optocoupler driver OA1 is an amplifier with a fixed gain of
6 and can source up to 10mA into the optocoupler. An
external resistor is needed from the OPTO pin to the
optocouplerforDCbiasingtheoptocoupler. Withaunique
0.3V hysteresis on the threshold VTH, OA1 turns into a
comparatorwhenitdetectsoutputstartuporoutputshort.
This comparator action jumpstarts the optocoupler to
reduce the output overshoot drastically (see Figure 3).
t = (CSS2 • 0.6V)/10µA
During start up, BGATE will stay off until VSS2 reaches
1.6V. This prevents the bottom MOSFET from turning on
if the output is precharged. To shut down the second
output, the SS2 pin should be pulled below 50mV by a
small signal VN2222 type N-channel MOSFET. Note that
during shutdown BGATE will be locked off when VSS2
dropsbelow0.6V.ThispreventsthebottomMOSFETfrom
discharging the output, which could cause the output to
undershoot below ground.
Soft-Start and Shutdown First Output
During soft-start, VSS1 is the reference voltage that con-
trols the output voltage, so the output ramps up following
VSS1. The effective range of VSS1 is from 0V to VREF1. The
typical time for the output to reach the programmed level
is:
t = (CSS1 • 0.6V)/10µA
V
OUT1
5nF
R13
2.7k
STARTUP
OR SHORT
RELEASE
1k
22nF
V
OUT1
SHORT
470Ω
3.3V
V
V
OUT1
V
V
FB1
AOUT1
+
–
1.5V/
1.2V V
1.7V
1.4V
TH
AOUT1
OPTO
1k
–
OA1
90k
15k
R14
V
A1
600Ω
+
R
OPTO
1.5V
1.2V
V
V
TH
OPTO
V
REF1
0.6V
2V
0V
OPTO
3804 F03
LT3804
GNDS1
Figure 3. Optocoupler Driver
3804i
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LT3804
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APPLICATIO S I FOR ATIO
Output Inductor Selection
capacitor to the ground plane. A Schottky catch diode is
required on the switch node.
The key parameters for choosing the inductor include
inductance, RMSandsaturationcurrentratings, andDCR.
The inductance must be selected to achieve a reasonable
value of ripple current, which is determined by:
Power MOSFET Selection
The LT3804 drives two external N-channel MOSFETs to
deliver high currents at high efficiency. The gate drive
voltage is typically 6.5V. The key parameters for choosing
MOSFETs include drain to source voltage rating VDSS and
RDS(ON) at 6.5V gate drive. Note that the transformer
secondary voltage waveform will overshoot at its rising
edge due to the ringing between transformer leakage
inductance and parasitic capacitance. The VDSS of both
top and bottom MOSFETs must be sufficiently higher than
the maximum overshoot. It is recommended that an RC
snubberorvoltageclampingcircuitrybeplacedacrossthe
transformer secondary winding to limit the VS overshoot.
The RDS(ON) of the MOSFETs should be selected to deliver
the required current at the desired efficiency as well as to
meet the thermal requirement of the MOSFET package.
The conduction power losses of the MOSFETs are:
V
OUT •(1– D)
∆IL =
f •L
Where VOUT is the output voltage, D is the duty cycle, f is
switchingfrequencyandListheinductance. Typically, the
inductorripplecurrentisdesignedtobe20%to40%ofthe
maximum output current.
TheRMScurrentratingmustbehighenoughtodeliverthe
maximum output current. A sufficient saturation current
rating should prevent the inductor core from saturating.
These two current ratings can be determined by:
2
2
∆ILMAX
IRMS ≥ IO
+
PM1 IO2 • RDS(ON)M1 • D
PM2 IO2 • RDS(ON)M2 • (1 – D)
12
∆ILMAX
ISAT ≥ IO +
2
whereIO isthemaximumoutputcurrentofLT3804circuit,
and RDS(ON)M1 and RDS(ON)M2 are the on-resistance for
the top and bottom MOSFETs, respectively. The RDS(ON)
must be determined with 6.5V gate drive at the expected
operatingtemperature.Numeroushighperformancepower
MOSFETs are available from Siliconix, International Rec-
tifier and Fairchild. If the VDSS and RDS(ON) ratings are the
same,theMOSFETswiththelowestgatechargeQG should
be chosen to minimize the power loss associated with the
MOSFET gate drives, the switching transitions, and the
controller bias supply.
where IO is the maximum DC output current and ∆ILMAX is
the maximum peak-to-peak inductor ripple current. To
optimize the efficiency, we usually choose the inductor
with the minimum DCR if the inductance and current
ratings are the same.
Output N-Channel MOSFET Drivers
The LT3804 employs high speed N-channel MOSFET
synchronous drivers to achieve high system efficiency.
GBIAS is the 8V regulator output to bias and supply the
drivers and should be properly bypassed with a low ESR
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Light Load Operation of Second Output
Design Example
IftheBGSpinisgrounded,theLT3804staysincontinuous
mode independent of load condition except during soft-
start operation (see the Soft-Start section). If the BGS pin
is left open under light load, VRS2 will drop below 8mV,
BGATE will be turned off(see comparator CA2 of Block
Diagram), and the LT3804 will enter discontinous mode
operation.
Figure 4 shows an application example of LT3804. It is a
dual output high efficiency isolated DC/DC power supply
with 36V to 72V input range, 3.3V/15A and 1.8V/15A
outputs. The basic power stage topology is a two-switch
forward converter with synchronous rectification. The
primary side controller uses an LT3781, a current mode
two-switch forward controller with built-in MOSFET driv-
ers. On the secondary side, the LT3804 is used to provide
the voltage feedback for the 3.3V output. The output from
the built-in optocoupler driver is fed into an optocoupler
(MOC207) and then transferred to LT3781 on the primary
side to complete the 3.3V regulation. An LTC1693-1 high
speed dual N-channel MOSFET driver provides the gate
drive for the synchronous MOSFETs at the 3.3V output
stage. The LTC1693-1 driver’s input signals come from
SG and BG outputs of the LT3781 through two small gate
drive transformers (T2 and T3).
Second Output Capacitor Selection
The selection of the output capacitor is determined by the
output ripple and load transient requirements. In low
output voltage applications, always choose capacitors
with low ESR. The output ripple voltage is approximated
by:
1
∆VOUT ≈ ∆IL ESR +
8fCOUT
The LT3804 also precisely regulates the 1.8V output by
further reducing and controlling the duty cycle of the
switching waveform from the power transformer (T1)
secondary winding. In fact, the 1.8V circuit is a special
synchronous buck converter whose input is a pulsed
waveform instead of a DC voltage.
where ∆IL is the inductor peak-to-peak ripple current. A
partial list of low ESR high performance capacitor types
includesSPcapacitorsfromPanasonicandCornellDubilier,
POSCAPs and OS-CON capacitors from Sanyo, T510 and
T520 surface mount capacitors from Kemet.
True differential remote sensing is provided for both
outputs to achieve high regulation accuracies. Power
good indicator PGOOD will be high only if both outputs are
within ±10% of their nominal values.
Layout Considerations
For maximum efficiency, the switching rise and fall times
should be less than 20ns. To prevent radiation, the power
MOSFETs,SWpinandinputbypasscapacitorleadsshould
be kept as short as possible. A ground plane should be
used under the switching circuitry to prevent interplane
coupling and to act as a thermal spreading path. Note that
the bottom metal of the package is the heat sink as well as
the IC signal ground, and must be soldered to the ground
plane.
The LT3804 provides current limit function for both 1.8V
and 3.3V outputs. The current limits for 3.3V and 1.8V
outputs are estimated to be 50mV/R55 and 50mV/R49,
respectively.
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LT3804
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A planar transformer PA0191 by Pulse Engineering is
employed as the power transformer in this design. This
transformer is constructed on a PQ20 core with nine turns
ofprimarywindings, twoturnsofsecondarywindingsand
seven turns of auxiliary windings for the LT3781 bias
supply. Si7892DP MOSFETs are selected for the second-
ary side due to their low RDS (ON), 30V VDSS rating and
compact, thermally enhanced PowerPak SO-8 package.
The switching frequency of the circuit is about 230kHz.
1500V input to output isolation is provided. Additional
features of this design include primary side on/off control,
input over voltage protection, under voltage lockout, soft
startandboardovertemperatureshutdown.Thecomplete
design is mounted within a standard half brick PC board
with about half inch height.
3804i
12
LT3804
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C
V
S G N D
P G N D
S E N S E
S S
B G
S Y N C
T H E R M
B S T R E F
T G
F S E T
R E F
5 V
V B S T
3804i
13
LT3804
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FROM TRANSFORMER
+V
1.8V
15A
O2
SECONDARY WINDING
SEC
V
CCS
C12
680µF
2.5V
POSCAP
×3
+
C45
R57
10k
10pF
C47
1µF
D14
C44
C36
4.7µF
16V
D15
8
25
V
4
CMDSH-3
0.1µF
(2R5TPD680M ×3)
V
OPTO
CMDSH-3
CCS
R5
16V
SYNC
BOOST
GBAIS
CC
23
19
16
7
27
5
OPTO
PGOOD
BGS
Q13
100k
LT3804
Si7892DP
L4
R49
0.003Ω
1%
PGOOD
TGATE
SW
1.8µH
CEP125-1R8
6
R64
26
20
21
15
14
12
11
3
CSET
CLIP
BGATE
CL2P
CL2N
10Ω
C37, 680pF
1
CLIP
CLIN
Q14
Si7892DP
×2
C49, 1000pF
R13
2
CLIN
22
18
13
10
28
C46
1000pF
V
V
V
V
AOUT1
FB1
AOUT2
FB2
C50
C39
330pF
R50
3.3k
C38
1000pF
1.5k
0.033µF
GNDS1
PGIN1
GNDS2
PGIN2
C51
6.8nF
R65
10Ω
R19
1k
VO1
+
V
O2S
C42
4700pF R54
I
I
C24
LCOMP1
LCOMP2
R62
R53
4.7nF
3.01k 3.01k
1%
SS1 PGND SS2
220Ω
R58
10k
C35
180pF
R12
10k
+
VO1S
1%
17 24
9
R14
3.01k
1%
R15
3.01k
1%
1.8V OUTPUT
REMOTE SENSE
C48
180pF
R60
1.5k
1%
R61
1.5k
1%
3.3V OUTPUT
REMOTE SENSE
C43
0.1µF
R66
R67
665Ω 665Ω
–
1%
1%
V
O2S
–
VO1S
R63
10Ω
R68
10Ω
3804 TA01
Figure 4. 36V – 72VDC to 3.3V/15A and 1.8V/15A Dual Output Isolated Power Supply (Page 2 of 2)
3804i
14
LT3804
U
PACKAGE DESCRIPTIO
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
2.74
(.108)
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
4.50 ±0.10
SEE NOTE 4
6.40
BSC
2.74
(.108)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.65
(.0256)
BSC
0.45 – 0.75
(.018 – .030)
0.09 – 0.20
(.0036 – .0079)
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP 0203
0.195 – 0.30
(.0077 – .0118)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3804i
15
LT3804
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1339
High Power Synchronous DC/DC Controller
Isolated Flyback Switching Regulator
Programmable Reference
Operation Up to 60V Maximum
General Purpose with External Application Resistor
0.4% Initial Voltage Tolerance
Operation Up to 60V Maximum
LT1425
LT1431
LT1680
High Power DC/DC Step-Up Controller
General Purpose Isolated Flyback Controller
High Power Isolated Flyback Controller
LT1725
Drives External Power MOSFET with External I
Resistor
SENSE
LT1737
Sense Output Voltage Directly from Primary-Side Winding
LT1950
PWM Controller for Forward, Flyback,
Boost and SEPIC
3V ≤ V ≤ 25V, Volt-Second Clamp, Leading-Edge Blanking,
Slope Compensation
IN
LT3710
LTC3722
LT3781
Secondary Side Synchronous Post Regulator
Synchronous Phase Modulated Full-Bridge Controller
Dual Transistor Synchronous Forward Controller
Generates Regulated Auxiliary Output in Isolated DC/DC Converters,
Dual N-Channel MOSFET Synchronous Drivers
Adaptive or Manual Delay Control for Zero Voltage Switching,
Adjustable Maximum ZVS Delay, Current Mode and Voltage Mode.
Operation Up to 72V Maximum
3804i
LT/TP 0603 1K • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
相关型号：
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LT3804 - Secondary Side Dual Output Controller with Opto Driver; Package: TSSOP; Pins: 28; Temperature Range: -40°C to 85°C
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LT3804EFE#TRPBF
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