LT4356-3 [Linear]
Surge Stopper with Fault Latchoff; 浪涌抑制器具有故障闭锁
| 型号： | LT4356-3 |
| 厂家： | 
Linear |
| 描述： | Surge Stopper with Fault Latchoff |
| 文件： | 总24页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4356-3
Surge Stopper with
Fault Latchoff
FEATURES
DESCRIPTION
The LT®4356-3 surge stopper protects loads from high
voltage transients. It regulates the output during an
overvoltage event, such as load dump in automobiles,
by controlling the gate of an external N-channel MOSFET.
The output is limited to a safe value thereby allowing the
loadstocontinuefunctioning.TheLT4356-3alsomonitors
n
Stops High Voltage Surges
n
Adjustable Output Clamp Voltage
n
Overcurrent Protection
n
Wide Operation Range: 4V to 80V
n
Reverse Input Protection to –60V
n
Low 7μA Shutdown Current
n
Adjustable Latchoff Fault Timer
the voltage drop between the V and SNS pins to protect
CC
n
Controls N-channel MOSFET
against overcurrent faults. An internal amplifier limits
the current sense voltage to 50mV. In either fault condi-
tion, a timer is started inversely proportional to MOSFET
stress. If the timer expires, the FLT pin pulls low to warn
of an impending power down. If the condition persists,
the MOSFET is turned off, until the SHDN pin pulls low
momentarily.
n
Shutdown Pin Withstands –60V to 100V
n
Fault Output Indication
n
Spare Amplifier for Level Detection Comparator or
Linear Regulator Controller
Available in (4mm × 3mm) 12-Pin DFN,
n
10-Pin MSOP or 16-Pin SO Packages
The spare amplifier may be used as a voltage detection
comparator or as a linear regulator controller driving an
external PNP pass transistor.
APPLICATIONS
n
Automotive/Avionic Surge Protection
n
Hot Swap/Live Insertion
Back-to-back FETs can be used in lieu of a Schottky diode
for reverse input protection, reducing voltage drop and
powerloss. Ashutdownpinreducesthequiescentcurrent
to less than 7μA during shutdown.
n
High Side Switch for Battery Powered Systems
Intrinsic Safety Applications
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
4A, 12V Overvoltage Output Regulator
Overvoltage Protector Regulates Output at
27V During Transient
10mΩ
IRLR2908
V
OUT
V
IN
12V
C
LOAD
= 6.8μF
= 500mA
80V INPUT SURGE
TMR
I
10Ω
102k
V
IN
V
SNS GATE OUT
FB
20V/DIV
CC
383k
V
CC
SHDN
12V
12V
4.99k
27V ADJUSTABLE CLAMP
100ms/DIV
DC-DC
+
IN
LT4356DE-3
V
OUT
CONVERTER
20V/DIV
100k
EN
SHDN
GND
UNDERVOLTAGE
A
FLT
FAULT
LT4356-3TA01b
OUT
GND
TMR
43563 TA01
0.1μF
43563f
1
LT4356-3
(Notes 1 and 2)
ABSOLUTE MAXIMUM RATINGS
V , SHDN ................................................ –60V to 100V
Storage Temperature Range
CC
SNS............................. V – 30V or –60V to V + 0.3V
DE12.................................................. –65°C to 125°C
MS, SO .............................................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
CC
CC
OUT, A , FLT, EN...................................... –0.3V to 80V
OUT
GATE (Note 3).................................–0.3V to V
+ 10V
OUT
+
FB, TMR, IN ................................................ –0.3V to 6V
MS, SO ............................................................. 300°C
+
A
, EN, FLT, IN ...................................................–3mA
OUT
Operating Temperature Range
LT4356C-3 ............................................... 0°C to 70°C
LT4356I-3 ............................................ –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
+
TOP VIEW
TMR
FB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
+
TMR
FB
1
2
3
4
5
6
12 IN
11
10 GND
NC
TOP VIEW
A
OUT
NC
A
OUT
FB
OUT
1
2
3
4
5
10 TMR
OUT
GATE
SNS
9
8
7
6
GND
EN
OUT
GATE
NC
NC
13
GATE
SNS
9
8
7
EN
GND
EN
FLT
V
CC
SHDN
FLT
MS PACKAGE
10-LEAD PLASTIC MSOP
V
SHDN
CC
SNS
FLT
V
SHDN
CC
T
= 125°C, θ = 120°C/W
JA
JMAX
DE PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 13) PCB GND CONNECTION OPTIONAL
S PACKAGE
16-LEAD PLASTIC SO
= 150°C, θ = 100°C/W
T
JMAX
T
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LT4356CDE-3#PBF
LT4356IDE-3#PBF
LT4356CMS-3#PBF
LT4356IMS-3#PBF
LT4356CS-3#PBF
LT4356IS-3#PBF
LEAD BASED FINISH
LT4356CDE-3
TAPE AND REEL
PART MARKING*
43563
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT4356CDE-3#TRPBF
LT4356IDE-3#TRPBF
LT4356CMS-3#TRPBF
LT4356IMS-3#TRPBF
LT4356CS-3#TRPBF
LT4356IS-3#TRPBF
TAPE AND REEL
0°C to 70°C
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
43563
–40°C to 85°C
0°C to 70°C
LTFFK
LTFFK
10-Lead Plastic MSOP
–40°C to 85°C
0°C to 70°C
LT4356S-3
LT4356S-3
PART MARKING*
43563
16-Lead Plastic SO
16-Lead Plastic SO
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
PACKAGE DESCRIPTION
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LT4356CDE-3#TR
LT4356IDE-3#TR
LT4356IDE-3
43563
–40°C to 85°C
0°C to 70°C
LT4356CMS-3
LT4356CMS-3#TR
LT4356IMS-3#TR
LT4356CS-3#TR
LTFFK
LT4356IMS-3
LTFFK
10-Lead Plastic MSOP
–40°C to 85°C
0°C to 70°C
LT4356CS-3
LT4356S-3
LT4356S-3
16-Lead Plastic SO
LT4356IS-3
LT4356CS-3#TR
16-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
43563f
2
LT4356-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
Operating Voltage Range
Supply Current
MIN
TYP
MAX
80
UNITS
V
l
l
V
4
CC
I
CC
V
V
V
= Float
1
1.5
mA
CC
SHDN
+
= 0V, IN = 1.3V
7
7
25
30
μA
μA
SHDN
l
l
l
I
R
Reverse Input Current
V
V
= V = –30V, SHDN Open
0.3
0.8
1
2
mA
mA
SNS
SNS
CC
= V = V
= –30V
CC
SHDN
l
l
GATE Pin Output High Voltage
GATE Pin Pull-Up Current
GATE Pin Pull-Down Current
V
= 4V; (V
– V
GATE
)
4.5
10
8
V
V
ΔV
CC
GATE
OUT
GATE
80V ≥ V ≥ 8V; (V
– V
)
16
CC
OUT
l
l
I
V
GATE
V
GATE
= 12V; V = 12V
= 48V; V = 48V
–4
–4.5
–23
–30
–36
–50
μA
μA
GATE(UP)
GATE(DN)
CC
CC
l
l
l
I
Overvoltage, V = 1.4V, V
= 12V
75
5
1.5
150
10
5
mA
mA
mA
FB
CC
GATE
Overcurrent, V – V
= 120mV, V
= 12V
GATE
SNS
Shutdown Mode, V
= 0V, V
= 12V
GATE
SHDN
l
l
V
FB Pin Servo Voltage
FB Pin Input Current
V
V
= 12V; V = 12V
OUT
1.225
1.25
0.3
1.275
1
V
FB
GATE
I
FB
= 1.25V
FB
μA
l
l
Overcurrent Fault Threshold
45
46
50
51
55
56
mV
mV
ΔV
ΔV
SNS
ΔV
SNS
= (V – V ), V = 12V
CC SNS CC
SNS
= (V – V ), V = 48V
CC
SNS
CC
l
l
I
I
SNS Pin Input Current
V
= V = 12V to 48V
5
10
22
μA
SNS
SNS
CC
FLT, EN Pins Leakage Current
FLT, EN = 80V
A = 80V
OUT
2.5
4.5
μA
μA
LEAK
A
Pin Leakage Current
OUT
l
l
l
l
l
I
TMR Pin Pull-up Current
V
TMR
= 1V, V = 1.5V, (V – V ) = 0.5V
–1.5
–44
–3.5
–2.5
–195
–2.5
–50
–5.5
–4.5
–260
–4
μA
μA
μA
μA
μA
TMR
TMR
FB
CC
OUT
V
= 1V, V = 1.5V, (V – V ) = 75V
–56
FB
CC
OUT
V
= 1.3V, V = 1.5V
–8.5
–6.5
–315
TMR
FB
SNS
SNS
V
= 1V, ΔV
= 1V, ΔV
= 60mV, (V – V ) = 0.5V
TMR
CC OUT
V
TMR
= 60mV, (V – V ) = 80V
CC
OUT
l
l
l
l
l
TMR Pin Pull-down Current
TMR Pin Thresholds
1.5
1.22
80
2.2
1.25
100
1.25
0.3
2.7
1.28
120
1.28
1
μA
V
V
= 1V, V = 1V, ΔV = 0V
SNS
TMR
FB
V
FLT From High to Low, V = 5V to 80V
TMR
CC
Early Warning Period
From FLT going Low to GATE going Low, V = 5V to 80V
mV
V
ΔV
CC
TMR
+
+
V
IN Pin Threshold
1.22
IN
+
+
+
I
IN Pin Input Current
V
= 1.25V
μA
IN
IN
l
l
V
FLT, EN, A
Pins Output Low
I
I
= 2mA
= 0.1mA
2
300
8
800
V
mV
OL
OUT
SINK
SINK
l
l
I
OUT Pin Input Current
V
V
= V = 12V
200
6
300
14
μA
mA
OUT
OUT
OUT
CC
= V = 12V, V
= 0V
CC
SHDN
43563f
3
LT4356-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
0.5
1.4
MAX
UNITS
l
OUT Pin High Threshold
0.25
0.7
V
ΔV
ΔV = V – V ; EN From Low to High
OUT
OUT
CC
OUT
V
SHDN Pin Threshold
V
= 12V to 48V
0.6
0.4
1.7
2.1
V
V
SHDN
CC
l
l
l
l
l
V
SHDN Pin Float Voltage
V
V
= 12V to 48V
0.6
–1
1.2
–4
2
–8
4
V
μA
μs
μs
SHDN(FLT)
CC
I
t
t
SHDN Pin Current
= 0V
SHDN
SHDN
)
Overcurrent Turn Off Delay Time
Overvoltage Turn Off Delay Time
2
GATE From High to Low, ΔV
= 0 → 120mV
OFF(OC
SNS
0.25
1
GATE From High to Low, V = 0 → 1.5V
OFF(OV)
FB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
the OUT pin. Driving this pin to voltages beyond the clamp may damage
the device.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
ICC vs VCC ICC (Shutdown) vs VCC
ICC (Shutdown) vs Temperature
1000
800
600
400
200
0
35
30
25
20
15
10
5
60
50
40
30
20
10
0
0
0
10 20 30 40 50 60 70 80
(V)
–50 –25
0
25
50
75 100 125
0
10 20 30 40 50 60 70 80
(V)
V
TEMPERATURE (°C)
V
CC
CC
43563 G02
43563 G03
43563 G01
43563f
4
LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
GATE Pull-Up Current vs
Temperature
SHDN Current vs Temperature
GATE Pull-Up Current vs VCC
6
5
4
3
2
1
0
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V
= 0V
V
= V
= 12V
OUT
SHDN
GATE
0
0
–50 –25
0
25
50
75 100 125
0
10 20 30 40 50 60 70 80
(V)
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
V
TEMPERATURE (°C)
CC
43563 G04
43563 G05
43563 G06
GATE Pull-Down Current vs
Temperature
GATE Pull-Down Current vs
Temperature
ΔVGATE vs IGATE
220
200
180
160
140
120
100
12
10
8
14
12
10
8
OVERVOLTAGE CONDITION
= 1.5V
OVERCURRENT CONDITION
ΔV = 120mV
V
= 12V
OUT
V
FB
SNS
6
6
4
4
2
2
0
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
0
2
4
6
8
10 12 14 16
(μA)
TEMPERATURE (°C)
TEMPERATURE (°C)
I
GATE
43563 G07
43563 G08
43563 G09
43563f
5
LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
Overvoltage TMR Current vs
(VCC – VOUT
ΔVGATE vs Temperature
ΔVGATE vs VCC
)
14
12
10
8
16
14
12
10
8
48
40
32
24
16
8
I
= –1μA
OVERVOLTAGE CONDITION
GATE
T
= 130°C
= –45°C
A
V
V
= 5V
= 1V
OUT
TMR
V
V
= 8V
= 4V
CC
CC
T
A
T
= 25°C
A
6
6
4
4
2
2
I
= –1μA
CC
GATE
OUT
V
= V
0
0
0
–50 –25
0
25
50
75 100 125
0
10 20 30 40 50 60 70 80
(V)
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
V
V
– V
(V)
OUT
CC
CC
43563 G10
43563 G11
43563 G12
Warning Period
TMR Current vs VCC
TMR Pull-Down Current vs
Temperature
Overcurrent TMR Current vs
(VCC – VOUT
)
14
12
10
8
3.0
2.5
2.0
1.5
1.0
0.5
0
280
240
200
160
120
80
OVERVOLTAGE, EARLY
WARNING PERIOD
V
= 1V
TMR
OVERCURRENT CONDITION
V
V
= 0V
= 1V
OUT
TMR
V
FB
V
TMR
= 1.5V
= 1.3V
6
4
2
40
0
0
0
10 20 30 40 50 60 70 80
(V)
–50 –25
0
25
50
75 100 125
0
10 20 30 40 50 60 70 80
– V (V)
V
TEMPERATURE (°C)
V
CC
CC
OUT
43563 G14
43563 G15
43563 G13
43563f
6
LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
Overvoltage Turn-Off Time vs
Temperature
Output Low Voltage vs Current
4.0
500
400
300
200
100
0
OVERVOLTAGE CONDITION
= 1.5V
V
FB
3.5
A
OUT
3.0
2.5
2.0
1.5
1.0
0.5
0
FLT
EN
0
0.5
1.0
1.5
2.0
2.5
3.0
–50 –25
0
25
50
75 100 125
CURRENT (mA)
TEMPERATURE (°C)
43563 G16
43563 G17
Overcurrent Turn-Off Time vs
Temperature
Reverse Current vs Reverse
Voltage
–20
–15
–10
–5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
OVERCURRENT CONDITION
ΔV = 120mV
V
= SNS
CC
SNS
0
–40
–50 –25
0
25
50
75 100 125
0
–20
–60
–80
TEMPERATURE (°C)
V
(V)
CC
43563 G18
43563 G19
43563f
7
LT4356-3
PIN FUNCTIONS
OUT: Output Voltage Sense Input. This pin senses the
voltage at the source of the N-channel MOSFET and sets
the fault timer current. When the OUT pin voltage reaches
A
: Amplifier Output. Open collector output of the auxil-
OUT
iary amplifier. It is capable of sinking up to 2mA from 80V.
The negative input of the amplifier is internally connected
to a 1.25V reference.
0.7V away from V , the EN pin goes high impedance.
CC
SHDN: Shutdown Control Input. The LT4356-3 can be
shut down to a low current mode by pulling the SHDN
pin below the shutdown threshold of 0.6V. Pull this pin
above 1.7V or disconnect it and allow the internal current
source to turn the part back on. After GATE pin pulls low
due to fault time out, the part can be restarted by pull-
ing the SHDN pin low for at least 100μs and pulled high
with a slew rate faster than 10V/ms. The leakage current
to ground at the pin should be limited to no more than
1μA if no pull up device is used to turn the part on. The
SHDN pin can be pulled up to 100V or below GND by 60V
without damage.
EN: Open-Collector Enable Output. The EN pin goes high
impedance when the voltage at the OUT pin is above (V
CC
– 0.7V), indicating the external MOSFET is fully on. The
state of the pin is latched until the OUT pin voltage resets
at below 0.5V and goes back up above 2V. The internal
NPN is capable of sinking up to 3mA of current from 80V
to drive an LED or opto-coupler.
Exposed Pad: Exposed pad may be left open or connected
to device ground (GND).
FB: Voltage Regulator Feedback Input. Connect this pin
to the center tap of the output resistive divider connected
between the OUT pin and ground. During an overvoltage
condition, the GATE pin is servoed to maintain a 1.25V
threshold at the FB pin. This pin is clamped internally to
7V. Tie to GND to disable the OV clamp.
SNS:CurrentSenseInput.Connectthispintotheoutputof
thecurrentsenseresistor.Thecurrentlimitcircuitcontrols
the GATE pin to limit the sense voltage between V and
CC
SNS pins to 50mV. At the same time the sense amplifier
also starts a current source to charge up the TMR pin.
This pin can be pulled below GND by up to 60V, though
FLT: Open-Collector Fault Output. This pin pulls low
after the voltage at the TMR pin has reached the fault
threshold of 1.25V. It indicates the pass transistor is
about to turn off because either the supply voltage has
stayed at an elevated level for an extended period of
time (voltage fault) or the device is in an overcurrent
condition (current fault). The internal NPN is capable of
sinking up to 3mA of current from 80V to drive an LED or
opto-coupler.
the voltage difference with the V pin must be limited to
CC
less than 30V. Connect to V if unused.
CC
TMR: Fault Timer Input. Connect a capacitor between this
pin and ground to set the times for early warning and fault
periods. The current charging up this pin during fault
conditions depends on the voltage difference between the
V
CC
and OUT pins. When V
reaches 1.25V, the FLT pin
TMR
GATE:N-ChannelMOSFETGateDriveOutput.TheGATEpin
ispulledupbyaninternalchargepumpcurrentsourceand
clamped to 14V above the OUT pin. Both voltage and cur-
rent amplifiers control the GATE pin to regulate the output
voltage and limit the current through the MOSFET.
pulls low to indicate the detection of a fault condition. If
the condition persists, the pass transistor turns off when
TMR
low even after the fault condition has disappeared and the
voltage at the TMR pin has reached 0.5V.
V
reachesthethresholdof1.35V.TheGATEpinremains
GND: Device Ground.
V : Positive Supply Voltage Input. The positive supply
CC
input ranges from 4V to 80V for normal operation. It
can also be pulled below ground potential by up to 60V
during a reverse battery condition, without damaging the
part. The supply current is reduced to 7μA with all the
functional blocks off.
+
IN : Positive Input of the Auxiliary Amplifier. This amplifier
can be used as a level detection comparator with external
hysteresis or linear regulator controlling an external PNP
transistor. This pin is clamped internally to 7V. Connect
to ground if unused.
43563f
8
LT4356-3
BLOCK DIAGRAM
V
SNS
GATE
OUT
CC
14V
+
50mV
–
CHARGE
PUMP
FB
+
–
+
–
VA
IA
1.25V
SHDN
FLT
A
OUT
OC
OUT
OV
–
+
1.25V
SHDN
EN
CONTROL
LOGIC
AUXILLARY
AMPLIFIER
GATEOFF FLT
+
IN
1.35V
–
+
V
CC
+
–
0.5V
I
TMR
+
–
2μA
1.25V
TMR
GND
43563 BD
43563f
9
LT4356-3
OPERATION
Some power systems must cope with high voltage surges
of short duration such as those in automobiles. Load
circuitry must be protected from these transients, yet
high availability systems must continue operating during
these events.
The potential at the TMR pin starts decreasing as soon
as the overvoltage condition disappears, but the GATE
pin remains low even when the voltage at the TMR pin
reaches 0.5V. Pulling the SHDN pin low momentarily will
turn the GATE pin back on.
The LT4356-3 is an overvoltage protection regulator that
drives an external N-channel MOSFET as the pass transis-
tor. It operates from a wide supply voltage range of 4V to
80V. It can also be pulled below ground potential by up
to 60V without damage. The low power supply require-
ment of 4V allows it to operate even during cold cranking
conditionsinautomotiveapplications. Theinternalcharge
pump turns on the N-channel MOSFET to supply current
to the loads with very little power loss. Two MOSFETs can
be connected back to back to replace an inline Schottky
diode for reverse input protection. This improves the ef-
ficiency and increases the available supply voltage level
to the load circuitry during cold crank.
The fault timer allows the loads to continue functioning
duringshorttransienteventswhileprotectingtheMOSFET
frombeingdamagedbyalongperiodofsupplyovervoltage,
such as a load dump in automobiles. The timer period var-
ies with the voltage across the MOSFET. A higher voltage
corresponds to a shorter fault timer period, ensuring the
MOSFET operates within its safe operating area (SOA).
TheLT4356-3sensesanovercurrentconditionbymonitor-
ing the voltage across an optional sense resistor placed
between the V and SNS pins. An active current limit
CC
circuit (IA) controls the GATE pin to limit the sense volt-
age to 50mV. A current is also generated to start charging
up the TMR pin. This current is about 5 times the current
generated during an overvoltage event. The FLT pin pulls
low when the voltage at the TMR pin reaches 1.25V and
the MOSFET is turned off when it reaches 1.35V.
Normally, the pass transistor is fully on, powering the
loads with very little voltage drop. When the supply volt-
age surges too high, the voltage amplifier (VA) controls
the gate of the MOSFET and regulates the voltage at the
source pin to a level that is set by the external resistor
divider from the OUT pin to ground and the internal 1.25V
reference. A current source starts charging up the capaci-
tor connected at the TMR pin to ground. If the voltage at
A spare amplifier (SA) is provided with the negative input
connected to an internal 1.25V reference. The output pull
down device is capable of sinking up to 2mA of current
allowing it to drive an LED or opto coupler. This amplifier
can be configured as a linear regulator controller driving
an external PNP transistor or a comparator function to
monitor voltages.
the TMR pin, V , reaches 1.25V, the FLT pin pulls low
TMR
to indicate impending turn-off due to the overvoltage
condition. The pass transistor stays on until the TMR
pin reaches 1.35V, at which point the GATE pin pulls low
turning off the MOSFET.
The SHDN pin turns off the pass transistor and reduces
the supply current to less than 7μA.
43563f
10
LT4356-3
APPLICATIONS INFORMATION
The LT4356-3 can limit the voltage and current to the load
circuitry during supply transients or overcurrent events.
The total fault timer period should be set to ride through
short overvoltage transients while not causing damage
to the pass transistor. The selection of this N-channel
MOSFET pass transistor is critical for this application.
It must stay on and provide a low impedance path from
the input supply to the load during normal operation and
then dissipate power during overvoltage or overcurrent
conditions.
Overcurrent Fault
The LT4356-3 features an adjustable current limit that
protects against short circuits or excessive load current.
During an overcurrent event, the GATE pin is regulated to
limit the current sense voltage across the V and SNS
pins to 50mV.
CC
Anovercurrentfaultoccurswhenthecurrentlimitcircuitry
has been engaged for longer than the time-out delay set
by the timer capacitor. The GATE pin is then immediately
pulled low by a 10mA current to GND turning off the
MOSFET. The GATE pin stays low until the SHDN pin is
pulled low for at least 100μs and pulled high with a slew
rate faster than 10V/ms.
The following sections describe the overcurrent and the
overvoltage faults, and the selection of the timer capacitor
value based on the required warning time. The selection
of the N-channel MOSFET pass transistor is discussed
next. Auxiliary amplifier, reverse input, and the shutdown
functionsarecoveredaftertheMOSFETselection.External
component selection is discussed in detail in the Design
Example section.
Fault Timer
The LT4356-3 includes an adjustable fault timer pin. Con-
necting a capacitor from the TMR pin to ground sets the
delay timer period before the MOSFET is turned off. The
same capacitor also sets the cool down period before the
MOSFETisallowedtoturnbackonafterthefaultcondition
has disappeared.
Overvoltage Fault
The LT4356-3 limits the voltage at the OUT pin during an
overvoltage situation. An internal voltage amplifier regu-
lates the GATE pin voltage to maintain a 1.25V threshold at
the FB pin. During this period of time, the power MOSFET
is still on and continues to supply current to the load. This
allows uninterrupted operation during short overvoltage
transient events.
Once a fault condition, either overvoltage or overcurrent,
is detected, a current source charges up the TMR pin. The
current level varies depending on the voltage drop across
thedrainandsourceterminalsofthepowerMOSFET(V ),
which is typically from the V pin to the OUT pin. This
scheme takes better advantage of the available Safe Oper-
ating Area (SOA) of the MOSFET than would a fixed timer
current. The timer function operates down to V = 5V
across the whole temperature range.
DS
CC
When the voltage regulation loop is engaged for longer
than the time-out period, set by the timer capacitor con-
nected from the TMR pin to ground, an overvoltage fault
is detected. The GATE pin is pulled down to the OUT pin
by a 150mA current. This prevents the power MOSFET
from being damaged during a long period of overvoltage,
such as during load dump in automobiles. Pulling the
SHDN pin low for at least 100μs and pulled high with a
slew rate faster than 10V/ms will allow the GATE pin to
pull back up.
CC
43563f
11
LT4356-3
APPLICATIONS INFORMATION
Fault Timer Current
When the voltage at the TMR pin, V , reaches the 1.25V
TMR
threshold, the FLT pin pulls low to indicate the detection
of a fault condition and provide warning to the load of
the impending power loss. In the case of an overvoltage
fault, the timer current then switches to a fixed 5μA. The
interval between FLT asserting low and the MOSFET turn-
ing off is given by:
The timer current starts at around 2μA with 0.5V or less
of V , increasing linearly to 50μA with 75V of V dur-
DS
DS
ing an overvoltage fault (Figure 1). During an overcurrent
fault, it starts at 4μA with 0.5V or less of V but increases
DS
to 260μA with 80V across the MOSFET (Figure 2). This
arrangement allows the pass transistor to turn off faster
duringanovercurrentevent,sincemorepowerisdissipated
during this condition. Refer to the Typical Performance
Characteristics section for the timer current at different
CTMR • 100mV
tWARNING
=
5μA
V
in both overvoltage and overcurrent events.
DS
V
TMR(V)
I
= 5μA
I
= 5μA
TMR
TMR
1.35
1.25
V
TMR
= 75V
= 50μA)
DS
(I
V
TMR
= 10V
= 8μA)
DS
(I
0.50
TIME
t
t
WARNING
= 20ms/μF
FLT
= 15ms/μF
t
= 93.75ms/μF
t
WARNING
= 20ms/μF
FLT
TOTAL FAULT TIMER = t + t
43563 F01
FLT WARNING
Figure 1. Overvoltage Fault Timer Current
V
TMR(V)
1.35
1.25
V
TMR
= 80V
DS
V
TMR
= 10V
= 35μA)
(I
= 260μA)
DS
(I
0.50
TIME
t
WARNING
= 0.38ms/μF
t
FLT
= 2.88ms/μF
t
= 21.43ms/μF
FLT
t
WARNING
43563 F02
= 2.86ms/μF
TOTAL FAULT TIMER = t + t
FLT WARNING
Figure 2. Overcurrent Fault Timer Current
43563f
12
LT4356-3
APPLICATIONS INFORMATION
This fixed early warning period allows the systems to per-
formnecessarybackuporhousekeepingfunctionsbefore
than 8V, a logic level MOSFET is required since the gate
drive can be as low as 4.5V.
the power supply is cut off. After V
crosses the 1.35V
TMR
The SOA of the MOSFET must encompass all fault condi-
tions. In normal operation the pass transistor is fully on,
dissipating very little power. But during either overvoltage
or overcurrent faults, the GATE pin is servoed to regu-
late either the output voltage or the current through the
MOSFET. Large current and high voltage drop across the
MOSFET can coexist in these cases. The SOA curves of
the MOSFET must be considered carefully along with the
selection of the fault timer capacitor.
threshold, the pass transistor turns off immediately. Note
that during an overcurrent event, the timer current is not
reduced to 5μA after V
has reached 1.25V threshold,
TMR
since it would lengthen the overall fault timer period and
cause more stress on the power MOSFET.
As soon as the fault condition has disappeared, a 2μA
current discharges the timer capacitor back to 0.5V. Once
the TMR pin returns to 0.5V, the fault condition may be
reset by pulling SHDN low for at least 100μs and pulled
high with a slew rate faster than 10V/ms. The FLT output
goes high when the fault condition is reset.
Transient Stress in the MOSFET
During an overvoltage event, the LT4356-3 drives a series
passMOSFETtoregulatetheoutputvoltageatanacceptable
level.Theloadcircuitrymaycontinueoperatingthroughout
this interval, but only at the expense of dissipation in the
MOSFET pass device. MOSFET dissipation or stress is a
function of the input voltage waveform, regulation voltage
and load current. The MOSFET must be sized to survive
this stress.
MOSFET Selection
TheLT4356-3drivesanN-channelMOSFETtoconductthe
load current. The important features of the MOSFET are
on-resistanceR
(BR)DSS
,themaximumdrain-sourcevoltage
DS(ON)
V
, the threshold voltage, and the SOA.
The maximum allowable drain-source voltage must be
higher than the supply voltage. If the output is shorted
to ground or during an overvoltage event, the full supply
voltage will appear across the MOSFET.
Most transient event specifications use the model shown
in Figure 3. The idealized waveform comprises a linear
ramp of rise time t, reaching a peak voltage of V and
r
PK
exponentially decaying back to V with a time constant
IN
The gate drive for the MOSFET is guaranteed to be more
of t. A common automotive transient specification has
than10Vandlessthan16VforthoseapplicationswithV
CC
constants of t = 10μs, V = 80V and τ = 1ms. A surge
r
PK
higher than 8V. This allows the use of standard threshold
voltage N-channel MOSFETs. For systems with V less
conditionknownas“loaddump”hasconstantsoft = 5ms,
r
CC
V
= 60V and τ = 200ms.
PK
V
PK
T
V
IN
t
r
43563 F03
Figure 3. Prototypical Transient Waveform
43563f
13
LT4356-3
APPLICATIONS INFORMATION
V
MOSFET stress is the result of power dissipated within
the device. For long duration surges of 100ms or more,
stress is increasingly dominated by heat transfer; this is
a matter of device packaging and mounting, and heatsink
thermal mass. This is analyzed by simulation, using the
MOSFET thermal model.
PK
T
V
REG
V
IN
t
r
Forshortdurationtransientsoflessthan100ms, MOSFET
survival is increasingly a matter of safe operating area
(SOA), an intrinsic property of the MOSFET. SOA quanti-
43563 F04
Figure 4. Safe Operating Area Required to Survive Prototypical
Transient Waveform
fies the time required at any given condition of V and
DS
I to raise the junction temperature of the MOSFET to its
D
Typically V
≈ V and τ >> t simplyfying the above to
IN r
REG
rated maximum. MOSFET SOA is expressed in units of
2
watt-squared-seconds(P t).Thisfigureisessentiallycon-
1
2 τ
(W2 )
S
2
P2t = ILOAD V – V
(
)
stant for intervals of less than 100ms for any given device
type, and rises to infinity under DC operating conditions.
Destruction mechanisms other than bulk die temperature
distort the lines of an accurately drawn SOA graph so that
PK
REG
2
For the transient conditions of V = 80V, V = 12V, V
PK
IN
REG
2
= 16V, t = 10μs and τ = 1ms, and a load current of 3A, P t
r
2
2
P t is not the same for all combinations of I and V .
is18.4W s—easilyhandledbyaMOSFETinaD-pakpack-
D
DS
2
2
In particular P t tends to degrade as V approaches the
age. The P t of other transient waveshapes is evaluated by
DS
maximum rating, rendering some devices useless for
integrating the square of MOSFET power versus time.
absorbing energy above a certain voltage.
Calculating Short-Circuit Stress
Calculating Transient Stress
SOAstressmustalsobecalculatedforshort-circuitcondi-
2
To select a MOSFET suitable for any given application, the
SOA stress must be calculated for each input transient
whichshallnotinterruptoperation.Itisthenasimplematter
to chose a device which has adequate SOA to survive the
tions. Short-circuit P t is given by:
2
2
2
P t = (V • ΔV /R ) • t
(W s)
IN
SNS SNS
TMR
where, ΔV
is the SENSE pin threshold, and t
is the
TMR
SNS
2
overcurrent timer interval.
maximumcalculatedstress.P tforaprototypicaltransient
waveform is calculated as follows (Figure 4).
For V = 14.7V, V
= 50mV, R
= 12mΩ and C
SNS TMR
IN
SNS
2
2
= 100nF, P t is 6.6W s—less than the transient SOA
calculated in the previous example. Nevertheless, to
accountforcircuittolerancesthisfigureshouldbedoubled
Let
a = V
– V
IN
IN
REG
b = V – V
PK
2
to 13.2W s.
(V = Nominal Input Voltage)
IN
Limiting Inrush Current and GATE Pin Compensation
Then
The LT4356-3 limits the inrush current to any load capaci-
tance by controlling the GATE pin voltage slew rate. An
external capacitor can be connected from GATE to ground
to slow down the inrush current further at the expense of
slower turn-off time. The gate capacitor is set at:
3
⎡
⎢
⎢
⎢
⎢
⎣
⎤
⎥
⎥
⎥
⎥
⎦
b– a
b
1
3
1
2
(
)
tr
+
2
P2t = ILOAD
b
⎛
⎞
τ 2a2 ln + 3a2 +b2 − 4ab
⎜
⎟
⎠
⎝
a
IGATE(UP)
C1 =
•CL
I
INRUSH
43563f
14
LT4356-3
APPLICATIONS INFORMATION
The LT4356-3 does not need extra compensation compo-
nents at the GATE pin for stability during an overvoltage or
overcurrentevent.However,withfast,highvoltagetransient
stepsattheinput, agatecapacitor, C1, togroundisneeded
to prevent turn-on of the N-channel MOSFET.
2N2905A OR
BCP53
*4.7Ω
INPUT
OUTPUT
*OPTIONAL FOR
CURRENT LIMIT
R6
100k
D1*
BAV99
11
The extra gate capacitance slows down the turn off time
during fault conditions and may allow excessive current
duringanoutputshortevent.Anextraresistor,R1,inseries
with the gate capacitor can improve the turn off time. A
diode, D1, should be placed across R1 with the cathode
connected to C1 as shown in Figure 5.
A
OUT
LT4356DE-3
43563 F06
Figure 6. Auxiliary LDO Output with Optional Current Limit
Reverse Input Protection
A blocking diode is commonly employed when reverse
input potential is possible, such as in automotive applica-
tions. This diode causes extra power loss, generates heat,
and reduces the available supply voltage range. During
cold crank, the extra voltage drop across the diode is
particularly undesirable.
Q1
D1
IN4148W
R3
R1
C1
GATE
The LT4356-3 is designed to withstand reverse voltage
without damage to itself or the load. The V , SNS, and
LT4356-3
CC
SHDN pins can withstand up to 60V of DC voltage below
the GND potential. Back-to-back MOSFETs must be used
to eliminate the current path through their body diodes
(Figure 7). Figure 8 shows the approach with a P-Channel
MOSFET in place of Q2.
43563 F05
Figure 5
Auxiliary Amplifier
An uncommitted amplifier is included in the LT4356-3 to
provide flexibility in the system design. With the negative
input connected internally to the 1.25V reference, the am-
plifier can be connected as a level detect comparator with
R
Q2
IRLR2908
Q1
IRLR2908
SNS
10mΩ
V
V
OUT
IN
12V
12V, 3A
CLAMPED
AT 16V
D2*
SMAJ58CA
R4
10Ω
R3
10Ω
R5
1M
Q3
2N3904
external hysteresis. The open collector output pin, A
,
OUT
R1
is capable of driving an opto or LED. It can also interface
with the system via a pull-up resistor to a supply voltage
up to 80V.
59k
D1
1N4148
R7
10k
5
4
3
SNS
GATE OUT
FB
6
2
The amplifier can also be configured as a low dropout
linearregulatorcontroller. WithanexternalPNPtransistor,
such as 2N2905A, it can supply up to 100mA of current
with only a few hundred mV of dropout voltage. Current
limit can be easily included by adding two diodes and one
resistor (Figure 6).
V
CC
R2
4.99k
LT4356DE-3
7
11
12
SHDN
8
9
A
FLT
OUT
+
IN
EN
43563 F07
GND
10
TMR
1
C
TMR
0.1μF
*DIODES INC.
Figure 7. Overvoltage Regulator with N-channel MOSFET
Reverse Input Protection
43563f
15
LT4356-3
APPLICATIONS INFORMATION
R
R
Q2
Q1
Q1
IRLR2908
SNS
10mΩ
SNS
10mΩ
Si4435
IRLR2908
V
IN
12V
V
OUT
12V, 3A
V
IN
D1
1N5245
15V
C *
L
22μF
D2
SMAJ58A
CLAMPED AT 16V
D2*
SMAJ58CA
R3
R3
R1
R6
10k
R1
10Ω
10Ω
59k
59k
5
4
3
5
SNS
4
3
SNS GATE OUT
6
GATE OUT
V
CC
2
FB
6
2
R4
383k
V
FB
7
CC
V
CC
SHDN
R2
4.99k
R2
4.99k
12
DC-DC
+
IN
LT4356DE-3
CONVERTER
R5
LT4356DE-3
9
8
100k
7
11
12
EN
SHDN
GND
SHDN
11
8
9
UNDERVOLTAGE
A
OUT
FLT
FAULT
A
GND
10
TMR
FLT
OUT
43563 F09
1
+
*SANYO 25CE22GA
IN
EN
C
TMR
47nF
GND
10
TMR
1
43563 F08
C
TMR
0.1μF
*DIODES INC.
Figure 9. Overvoltage Regulator with Low-Battery Detection
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
Atotalbulkcapacitanceofatleast22μFlowESRisrequired
close to the source pin of MOSFET Q1. In addition, the
bulk capacitance should be at least 10 times larger than
the total ceramic bypassing capacitor on the input of the
DC/DC converter.
Shutdown
The LT4356-3 can be shut down to a low current mode
whenthevoltageattheSHDNpingoesbelowtheshutdown
threshold of 0.6V. The quiescent current drops to 7μA.
Layout Considerations
To achieve accurate current sensing, Kelvin connection
The SHDN pin can be pulled up to V or below GND by
CC
to the current sense resistor (R
in Figure 9) is recom-
SNS
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn
on the part while clamping the pin to 2.5V. The leakage
current at the pin should be limited to no more than 1μA
if no pull up device is used to help turn it on.
mended. The minimum trace width for 1oz copper foil is
0.02" per amp to ensure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530μΩ/square.Smallresistancescancauselargeerrorsin
highcurrentapplications.Noiseimmunitywillbeimproved
significantly by locating resistive dividers close to the pins
Supply Transient Protection
The LT4356-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. Neverthe-
less, voltagetransientsabove100Vmaycausepermanent
damage.Duringashort-circuitcondition,thelargechange
incurrentflowingthroughpowersupplytracesandassoci-
ated wiring can cause inductive voltage transients which
could exceed 100V. To minimize the voltage transients, the
power trace parasitic inductance should be minimized by
using wide traces. A small surge suppressor, D2, in Figure
9, at the input will clamp the voltage spikes.
with short V and GND traces.
CC
Design Example
As a design example, take an application with the follow-
ing specifications: V = 8V to 14V DC with transient up
CC
to 80V, V
≤ 16V, current limit (I ) at 5A, low battery
OUT
LIM
detection at 6V, and 1ms of overvoltage early warning
(Figure 9).
43563f
16
LT4356-3
APPLICATIONS INFORMATION
First, calculate the resistive divider value to limit V
16V during an overvoltage event:
to
Finally,calculateR4andR5forthe6Vlowbatterythreshold
detection:
OUT
1.25V • R1 + R2
1.25V • R4 + R5
(
)
=16V
(
)
VREG
=
6V =
R2
R5
Set the current through R1 and R2 during the overvoltage
condition to 250μA.
Choose 100kΩ for R5.
6V – 1.25V • R5
(
)
R4 =
= 380kΩ
1.25V
1.25V
R2 =
= 5kΩ
250μA
Choose 4.99kΩ for R2.
16V – 1.25V • R2
Select 383kΩ for R4.
The pass transistor, Q1, should be chosen to withstand
the output short condition with V = 14V.
(
)
CC
R1 =
= 58.88kΩ
1.25V
The closest standard value for R1 is 59kΩ.
The total overcurrent fault time is:
47nF • 0.85V
tOC
=
= 0.878ms
45.5μA
Next calculate the sense resistor, R , value:
SNS
50mV 50mV
The power dissipation on Q1 equals to:
RSNS
=
=
= 10mΩ
ILIM
5A
14V • 50mV
P =
= 70W
10mΩ
C
is then chosen for 1ms of early warning time:
TMR
These conditions are well within the Safe Operating Area
of IRLR2908.
1ms • 5μA
CTMR
=
= 50nF
100mV
The closest standard value for C
is 47nF.
TMR
43563f
17
LT4356-3
TYPICAL APPLICATIONS
Wide Input Range 5V to 28V Hot Swap with Undervoltage Lockout
R
Q1
SNS
0.02Ω
SUD50N03-10
V
V
OUT
IN
100μF
R6
118k
R3
10Ω
C1
47nF
V
SNS GATE OUT
FB
CC
SHDN
A
OUT
+
IN
LT4356DE-3
R7
49.9k
FLT
EN
GND
TMR
43563 TA10
C
TMR
1μF
24V Overvoltage Regulator Withstands 150V at VIN
Q1
IRF640
V
V
OUT
IN
24V
CLAMPED AT 32V
R9
1k
1W
R3
10Ω
R1
118k
5
4
3
SNS
GATE
OUT
6
2
V
FB
CC
D2*
SMAT70A
R2
4.99k
LT4356DE-3
7
8
9
SHDN
FLT
EN
GND
10
TMR
1
43563 TA05
C
TMR
*DIODES INC.
0.1μF
43563f
18
LT4356-3
TYPICAL APPLICATIONS
Overvoltage Regulator with Low Battery Detection and Output Keep Alive During Shutdown
1k
0.5W
R
SNS
Q1
IRLR2908
V
10mΩ
OUT
V
IN
12V, 4A
12V
CLAMPED AT 16V
D2*
SMAJ58A
R3
D1
10Ω
Q2
1N4746A
18V
R4
402k
VN2222
1W
5
SNS
4
3
OUT
R1
294k
GATE
6
V
2
CC
FB
R2
24.9k
V
DD
R6
47k
LT4356DE-3
12
7
11
8
+
IN
A
LBO
OUT
R5
105k
SHDN
FLT
9
EN
GND
10
TMR
1
*DIODES INC.
43563 TA03
C
TMR
0.1μF
2.5A, 48V Hot Swap with Overvoltage Output Regulation at 72V and UV Shutdown at 35V
R
Q1
FDB3632
SNS
15mΩ
V
V
OUT
IN
48V
48V
2.5A
R4
140k
R6
100k
D2*
SMAT70A
R3
10Ω
C
L
300μF
C1
6.8nF
6
5
4
3
OUT
D1
1N4714
BV = 33V
V
SNS GATE
R7
CC
1M
12
2
+
IN
7
SHDN
R5
4.02k
R8
47k
R1
226k
LT4356DE-3
FB
R2
4.02k
8
9
FLT
11
EN
A
PWRGD
OUT
GND
10
TMR
1
*DIODES INC.
43563 TA06
C
TMR
0.1μF
43563f
19
LT4356-3
TYPICAL APPLICATIONS
2.5A, 28V Hot Swap with Overvoltage Output Regulation at 36V and UV Shutdown at 15V
R
Q1
FDB3632
SNS
15mΩ
V
V
OUT
IN
28V
28V
2.5A
R4
113k
R6
27k
D2*
SMAT70A
R3
10Ω
C
L
300μF
C1
6.8nF
6
5
4
3
OUT
D1
1N4700
BV = 13V
V
SNS GATE
R7
CC
1M
12
2
+
IN
7
SHDN
R5
4.02k
R8
47k
R1
110k
LT4356DE-3
FB
R2
4.02k
8
9
FLT
11
EN
A
PWRGD
OUT
GND
10
TMR
1
*DIODES INC.
43563 TA07
C
TMR
0.1μF
Overvoltage Regulator with Reverse Input Protection Up to –80V
R
Q2
IRLR2908
Q1
IRLR2908
SNS
10mΩ
V
V
OUT
IN
12V
12V, 3A
CLAMPED
AT 16V
D2*
SMAJ58CA
R4
10Ω
R3
10Ω
R5
1M
Q3
2N3904
6
5
SNS
4
3
R1
59k
V
GATE OUT
FB
CC
D1
1N4148
2
R7
10k
R2
4.99k
LT4356DE-3
7
SHDN
11
12
8
9
A
FLT
OUT
+
IN
EN
43563 TA09
GND
10
TMR
1
*DIODES INC.
C
TMR
0.1μF
43563f
20
LT4356-3
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
0.70 p0.05
3.30 p0.05
1.70 p 0.05
3.60 p0.05
2.20 p0.05
PACKAGE OUTLINE
0.25 p 0.05
2.50 REF
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.40 p 0.10
4.00 p0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.05
TYP
3.30 p0.10
3.00 p0.10
(2 SIDES)
1.70 p 0.10
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
(UE12/DE12) DFN 0806 REV D
6
1
0.25 p 0.05
0.75 p0.05
0.200 REF
0.50 BSC
2.50 REF
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
43563f
21
LT4356-3
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127
(.035 .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 0.102
(.118 .004)
(NOTE 3)
(.0197)
0.497 0.076
(.0196 .003)
REF
0.50
0.305 0.038
(.0120 .0015)
TYP
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
1
2
3
4 5
0.53 0.152
(.021 .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 0.0508
(.004 .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
43563f
22
LT4356-3
PACKAGE DESCRIPTION
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.386 – .394
(9.804 – 10.008)
.045 p.005
NOTE 3
.050 BSC
16
N
15
14
13
12
11
10
9
N
1
.245
MIN
.160 p.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
2
3
N/2
N/2
8
.030 p.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
2
3
5
6
7
1
4
.010 – .020
(0.254 – 0.508)
s 45o
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0o – 8o TYP
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
.016 – .050
(0.406 – 1.270)
S16 0502
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
43563f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT4356-3
TYPICAL APPLICATION
Overvoltage Regulator with Linear Regulator Up to 100mA
Q2
2N2905A
2.5V, 100mA
C5
10μF
R
Q1
IRLR2908
SNS
10mΩ
V
IN
12V
V
OUT
12V, 3A
CLAMPED AT 16V
D2*
SMAJ58A
R3
R1
10Ω
59k
5
4
3
SNS
GATE
OUT
R6
100k
6
2
V
A
FB
CC
R2
4.99k
R4
249k
C3
47nF
LT4356DE-3
11
7
12
8
+
IN
OUT
R5
249k
SHDN
FLT
9
EN
GND
10
TMR
*DIODES INC.
43563 TA04
1
C
TMR
0.1μF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1641-1/LT1641-2 Positive High Voltage Hot Swap™ Controllers
Active Current Limiting, Supplies From 9V to 80V
ThinSOT™ Package, 2.7V to 28V
LTC1696
LTC1735
Overvoltage Protection Controller
High Efficiency Synchronous Step-Down
Switching Regulator
Output Fault Protection, 16-Pin SSOP
LTC1778
No R
™ Wide Input Range Synchronous
Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
≤ (0.9)(V ),
OUT IN
SENSE
IN
Step-Down Controller
I
Up to 20A
OUT
LTC2909
Triple/Dual Inputs UV/OV Negative Monitor
Single/Dual UV/OV Voltage Monitor
Quad UV/OV Monitor
Pin Selectable Input Polarity Allows Negative and OV Monitoring
Ads UV and OV Trip Values, 1.5% Threshold Accuracy
For Positive and Negative Supplies
LTC2912/LTC2913
LTC2914
LTC3727/LTC3727-1 2-Phase, Dual, Synchronous Controller
LTC3827/LTC3827-1 Low I , Dual, Synchronous Controller
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 14V
IN
OUT
OUT
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V, 80μA Quiescent Current
Q
IN
LTC3835/LTC3835-1 Low I , Synchronous Step-Down Controller
Single Channel LTC3827/LTC3827-1
4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, 120μA Quiescent Current
Q
LT3845
LT3850
Low I , Synchronous Step-Down Controller
Q
IN
OUT
Dual, 550kHz, 2-Phase Sychronous Step-Down
Controller
Dual 180° Phased Controllers, V 4V to 24V, 97% Duty Cycle, 4mm × 4mm
IN
QFN-28, SSOP-28 Packages
LT4256
Positive 48V Hot Swap Controller with
Open-Circuit Detect
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to
80V Supply
LTC4260
Positive High Voltage Hot Swap Controller with
Wide Operating Range 8.5V to 80V
2
ADC and I C
LTC4352
Ideal MOSFET ORing Diode
External N-channel MOSFETs Replace ORing Diodes, 0V to 18V
Controls Two N-channel MOSFETs, 1μs Turn-Off, 80V Operation
Controls Two N-channel MOSFETs, 0.5μs Turn-Off, 80V Operation
LTC4354
Negative Voltage Diode-OR Controller
Positive Voltage Diode-OR Controller
LTC4355
Hot Swap, No R
and ThinSOT are trademarks of Linear Technology Corporation.
SENSE
43563f
LT 0309 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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