LT5502 [Linear]
400MHz Quadrature IF Demodulator with RSSI; 400MHz的中频正交解调器，带有RSSI
| 型号： | LT5502 |
| 厂家： | 
Linear |
| 描述： | 400MHz Quadrature IF Demodulator with RSSI |
| 文件： | 总12页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LT5502
400MHz Quadrature
IF Demodulator with RSSI
January 2001
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DESCRIPTIO
FEATURES
TheLT®5502isa70MHzto400MHzmonolithicintegrated
quadrature IF demodulator. It consists of an IF limiter,
quadrature down mixers, integrated lowpass filters, and
divide-by-two LO buffers. The demodulator provides all
building blocks for demodulation of I and Q baseband
signals with a single supply voltage of 1.8V to 5.25V. The
IFlimiterhas84dBsmall-signalgain, andabuilt-inreceive
signal strength indicator (RSSI) with over 90dB linear
range. The input referred noise-spectral-density is
1.45nV/√Hz, which is equivalent to a 4dB noise figure
when the input is terminated with a 50Ω source. The
integrated lowpass output filters act as antialiasing and
pulse-shaping filters for demodulated I/Q-baseband sig-
nals. The 3dB cutoff frequency of the filters is about
7.7MHz. The VCO frequency is required to be twice the
desired operating frequency to provide quadrature local
oscillator (LO) signals to the mixers. The standby mode
provides fast transient response to the receive mode with
reduced supply current when the I/Q outputs are
■
Single 1.8V to 5.25V Supply
■
IF Frequency Range: 70MHz to 400MHz
■
84dB Limiting IF Gain
■
90dB Linear RSSI Range
■
7.7MHz Lowpass Output Filter
■
Baseband I/Q Amplitude Imbalance: <0.7dB
■
4dB Noise Figure
Low Supply Current: 25mA
Outputs Biased Up While in Standby
Shutdown Current: 1µA
24-Lead Narrow SSOP Package
■
■
■
■
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APPLICATIO S
■
IEEE802.11
■
High Speed Wireless LAN
■
Wireless Local Loop
AC-coupled to a baseband chip.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
I/Q Output Swing, RSSI Output vs IF Input Power
2V
C2
C1
1200
1000
800
1.2
1.0
0.8
0.6
0.4
0.2
1µF
1nF
C3
22nF
+
IF
V
CC
+
I
OUT
IF
INPUT
R1
240Ω
–
–
IF
BASEBAND
DIFFERENTIAL
I/Q OUTPUTS
I
OUT
90°
0°
+
2XLO
+
Q
OUT
600
2XLO
INPUT
÷2
–
Q
OUT
–
2XLO
EN
400
RSSI
LT5502
GND
ENABLE
C4
1.8pF
200
–85
–55
–40
–25
–10
5
–70
5502 TA01a
IF INPUT POWER (dBm)
5502 TA01b
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LT5502
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Power Supply Voltage ............................................ 5.5V
LO Input Power .................................................. 10dBm
IF Input Power .................................................... 10dBm
Operating Ambient
Temperature (Note 2) ..............................–40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Voltage on any Pin not to Exceed ............................. VCC
+
–
+
–
I
I
1
2
3
4
5
6
7
8
9
Q
Q
V
24
23
22
21
20
19
18
17
16
15
14
13
OUT
OUT
OUT
OUT
LT5502EGN
GND
CC
V
GND
CC
GND
GND
+
+
IF
2XLO
2XLO
–
–
IF
GND
GND
V
CC
V
CC
EN 10
RSSI
GND
STBY 11
+
–
IFt 12
IFt
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
TJMAX = 150°C, θJA = 85°C/W
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
VCC = 3V, f2XLO = 570MHz, P2XLO = –10dBm, fIF = 280MHz,
PIF = –50dBm, TA = 25°C, unless otherwise noted. (Note 3)
SYMBOL
IF Input
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
Frequency Range
70 to 400
MHz
dBm
dB
IF
3dB Limiting Sensitivity
Noise Figure
–79
4
Terminated 50Ω Source
DC Common Mode Voltage
2.6
V
Demodulator I/Q Output
I/Q Output Voltage Swing
Differential
850
0.1
0.6
mV
P-P
I/Q Amplitude Mismatch
I/Q Phase Mismatch
0.7
dB
DEG
kΩ
V
Output Driving Capability
DC Common Mode Voltage
Differential; C
= 10pF
1.5
MAX
1.84
RSSI
Linear Dynamic Range (Note 4)
Output Impedance
Output Voltage
±3dB Linearity Error
90
3.8
0.41
1.01
8.7
1
dB
kΩ
Input = –70dBm
0.27
0.8
0.54
1.2
V
Output Voltage
Input = 0dBm
V
Output Voltage Slope
Linearity Error
Input from –70dBm to 0dBm
Input from –70dBm to 0dBm
mV/dB
dB
Baseband Lowpass Filter
3dB Cutoff Frequency
Group Delay Ripple
7.7
MHz
ns
16.4
2
LT5502
ELECTRICAL CHARACTERISTICS
VCC = 3V, f2XLO = 570MHz, P2XLO = –10dBm, fIF = 280MHz,
P
IF = –50dBm, TA = 25°C, unless otherwise noted. (Note 3)
SYMBOL
2XLO
PARAMETER
CONDITIONS
MIN
–20
1.8
TYP
140 to 800
2.6
MAX
UNITS
f
Frequency Range
Input Power
MHz
dBm
V
2XLO
P
–5
2XLO
DC Common Mode Voltage
Power Supply
V
Supply Voltage
5.25
32
V
mA
µA
CC
I
I
Supply Current
EN = High
25
1
CC
OFF
Shutdown Current
Standby Mode Current
EN = Low; Standby = Low
EN = Low; Standby = High
100
3.5
2.6
mA
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 3: Tests are performed as shown in the configuration of Figure 3.
a device may be impaired.
Note 4: Tests are performed as shown in the configuration of Figure 1 for
Note 2: Specifications over the –40°C to 85°C temperature range are
assured by design, characterization and correlation with statistical process
controls.
IF input.
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TYPICAL PERFOR A CE CHARACTERISTICS
(Note 3)
Power Supply Current
vs Temperature
I/Q Output Swing vs Temperature
I/Q Output Swing vs IF Input Power
1200
1000
800
36
32
28
24
20
16
1200
1000
800
V
IF
= 3V
f
= 280MHz
CC
IF
f
= 280MHz
T
= 85°C
= 25°C
A
T
= 85°C
= 25°C
A
T
= 85°C
A
T
T
A
= 25°C
A
T
A
600
T
= –40°C
T
= –40°C
A
A
600
T
= –40°C
400
A
400
200
1.8
2.5
3.5
4.5
3.5
–70
–55 –40
–25
–10
5.5
1.8
4.5
5.5
–85
2.5
5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
IF INPUT POWER (dBm)
5502 G01
5502 G02
5502 G03
3
LT5502
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TYPICAL PERFOR A CE CHARACTERISTICS (Note 3)
I/Q Output Swing vs IF Input Power
RSSI Output vs Temperature
RSSI Output Voltage vs IF Frequency
1200
1000
800
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
V
T
= 3V
V
T
= 3V
CC
A
V
f
= 3V
CC
A
CC
IF
= 25°C
= 25°C
= 280MHz
f
= 280MHz
IF
f
= 70MHz
IF
T
= 85°C
f
= 70MHz
A
IF
f
= 280MHz
IF
T
= –40°C
A
600
T
= 25°C
A
f
= 400MHz
IF
400
f
= 400MHz
–40
IF
200
–70
–55 –40
–25
–10
–85
–70
–55
–25
–10
–85
5
–55
5
–85
–70
–40
–25
–10
5
IF INPUT POWER (dBm)
IF INPUT POWER (dBm)
IF INPUT POWER (dBm)
5502 G04
5502 G06
5502 G05
IF Input Sensitivity
vs Temperature
RSSI Output Voltage vs VCC
IF Input Sensitivity vs IF Frequency
1.2
1.0
0.8
0.6
0.4
0.2
–73
–75
–77
–79
–81
–83
–73
–76
–79
–82
–85
f
= 280MHz
= 25°C
f
= 280MHz
IF
A
V
= 3V
CC
IF
T
T
= 85°C
A
T
= 85°C
A
T
A
= 25°C
V
= 3V
CC
T
= –40°C
A
T
= 25°C
A
V
= 5.5V
–70
CC
T
= –40°C
A
V
= 1.8V
CC
–55 –40
–25
–10
–85
5
1.8
2.5
3.5
4.5
70
100 150 200 250 300 350 400
5.5
IF INPUT POWER (dBm)
SUPPLY VOLTAGE (V)
IF FREQUENCY (MHz)
5502 G07
5502 G09
5502 G08
LPF Frequency Response
vs Baseband Frequency
LPF Group Delay
LPF Frequency Response vs VCC
vs Baseband Frequency
110
95
80
65
50
35
20
5
0
5
0
110
90
V
CC
= 3V
V
= 3V
V
A
= 1.8V, 3V, 5.5V
CC
CC
T
A
= –40°C
T
= 25°C
T
= 85°C
A
–5
–5
T
A
= 85°C
T
= 25°C
–10
–15
–20
–25
–30
–35
–10
–15
–20
–25
–30
–35
A
70
T = 25°C
A
T
= –40°C
A
50
30
4
8
16
0
4
8
12
16
20
0
20
12
4
8
16
0
20
12
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
5502 G11
5502 G10
5502 G12
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LT5502
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PI FU CTIO S
IOUT+ (Pin 1): Positive Baseband Output Pin of I-Channel.
The DC bias voltage is VCC – 1.16V. This pin should not be
shorted to ground.
IOUT– (Pin 2): Negative Baseband Input Pin of I-Channel.
The DC bias voltage is VCC – 1.16V. This pin should not be
shorted to ground.
voltage. When the input voltage is less than 0.7V or down
to ground, it is turned off.
IFt+ (Pin 12): Interstage IF Positive Pin. The DC bias
voltage is VCC – 0.25V.
IFt– (Pin 13): Interstage IF Negative Pin. The DC bias
voltage is VCC – 0.25V.
GND (Pins 3, 5, 8, 9, 14, 20, 21): Ground Pin.
RSSI (Pin 15): RSSI Output Pin.
VCC (Pins 4, 16, 17, 22): Power Supply Pin. This pin
should be decoupled using 1000pF and 0.1µF capacitors.
IF+ (Pin 6): Positive IF Input Pin. The DC bias voltage is
VCC – 0.4V.
2XLO– (Pin 18): Negative Carrier Input Pin. The input-
signal’s frequency must be twice that of the desired
demodulator LO frequency. The DC bias voltage is VCC
0.4V.
–
IF– (Pin 7): Negative IF Input Pin. The DC bias voltage is
2XLO+ (Pin 19): Positive Carrier Input Pin. The input-
VCC – 0.4V.
signal’s frequency must be twice that of the desired
demodulator LO frequency. The DC bias voltage is VCC
0.4V.
–
EN (Pin 10): Enable Pin. When the input voltage is higher
than 0.9V or up to VCC, the circuit is completely turned on.
When the input voltage is less than 0.7V or down to
ground, the circuit is turned off except the part of the
circuit associated with standby mode.
–
QOUT (Pin 23): Negative Baseband Output Pin of the
Q-Channel. The DC bias voltage is VCC – 1.16V. This pin
should not be shorted to ground.
+
STBY (Pin 11): Standby Pin. When the input voltage is
higher than 0.9V or up to VCC, the circuit of standby mode
is turned on to bias the I/Q buffers to desired quiescent
QOUT (Pin 24): Positive Baseband Output Pin of the
Q-Channel. The DC bias voltage is VCC – 1.16V. This pin
should not be shorted to ground.
W
BLOCK DIAGRA
+
–
IFt
12
IFt
13
I-MIXER
LPF
LPF
+
–
1
2
I
I
OUT
1
1
LIMITER
2
LIMITER
1
+
OUT
IF
6
7
LO
BUFFERS
DIVIDE 2
0°/90°
–
IF
+
24
Q
OUT
OUT
–
23 Q
Q-MIXER
RSSI
BIAS
15
10
EN
19
18
–
+
2XLO
5502 BD
RSSI
2XLO
5
LT5502
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APPLICATIO S I FOR ATIO
The LT5502 consists of the following sections: IF limiter, The 1:4 IF input transformer can also be replaced with a
I/Q demodulators, quadrature LO carrier generator, inte- narrow band single-to-differential conversion circuit
grated lowpass filters (LPFs), and bias circuitry.
using three discreet elements as shown in Figure 1. Their
nominal values are listed in Table 1. Due to the parasitics
of the PCB, their values need to be compensated. The
receiver’s input sensitivity in this case is improved to
–85dBm even without interstage filtering. The matching
circuitisessentiallyasecondorderbandpassfilter. There-
fore, the requirement for the front-end channel-select
filter can be eased too.
An IF signal is fed to the inputs of the IF limiter. The limited
IF signal is then demodulated into I/Q baseband signals
using the quadrature LO carriers that are generated from
the divide-by-two circuit. The demodulated I/Q signals are
passed through 5th order LPFs and buffered with an
output driver.
IF Limiter
MATCHING NETWORK
The IF limiter has 84dB small-signal gain with a frequency
range of 70MHz to 400MHz. It consists of two cascaded
stages of IF amplifiers/limiters. The differential outputs of
the first stage are connected internally to the differential
inputs of the second stage. An interstage filtering is
possibleinbetween(Pin12andPin13)withminimumoff-
chipcomponents.ItcanbeasimpleparallelLCtankcircuit
L1 and C8 as shown in Figure 3. The 22nF blocking
capacitor, C19, is used for the proper operation of the
internal DC offset canceling circuit. To achieve the best
receiver sensitivity, a differential configuration at the IF
input is recommended due to its better immunity to 2XLO
signal coupling to the IF limiter. Otherwise, the 2XLO
interference, presented at the IF inputs, may saturate the
IF limiter and reduce the gain of the wanted IF signal. The
receiver’s 3dB input-limiting sensitivity will be affected
correspondingly. The interstage bandpass filter will mini-
mize both 2XLO feedthrough and the receiver’s noise
bandwidth. Therefore, the receiver’s input sensitivity can
be improved. Without the interstage filter, the second
stage will be limited by the broadband noise amplified by
the first stage. The noise bandwidth in this case can be as
highas500MHz.The3dBinputlimitingsensitivityisabout
–79dBm at an IF frequency of 280MHz when terminated
with 200Ω at the input. The differential IF input impedance
is 2.2kΩ. Therefore, a 240Ω resistor is used for R3 as
shown in Figure 3. Using a bandpass filter with 50MHz
bandwidth, the input sensitivity is improved to –86dBm.
C
C5
S1
3.3pF
22nF
IF
+
–
TO IF
INPUT
L
SH
120nH
C
3.3pF
S2
TO IF
5502 F01
Figure 1. IF Input Matching Network at 280MHz
Table 1. The Component Values of Matching Network
LSH, CS1 and CS2
f
(MHz)
70
L
(nH)
C /C (pF)
S1 S2
IF
SH
642
13.7
9.6
6.4
4.8
3.8
3.2
2.7
2.4
100
150
200
250
300
350
400
422
256
176
130
101
80.4
66.0
Inanapplicationwherealowerinputsensitivityissatisfac-
tory, oneoftheIFinputscanbesimplyAC-terminatedwith
a 50Ω resistor and the other AC-grounded. The input
receiver’s sensitivity is about – 76dBm at 280MHz in this
case.
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LT5502
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APPLICATIO S I FOR ATIO
The receive signal strength indicator (RSSI) is built into
the IF limiter. The input IF signal is detected in a current
output proportional to the IF input power. The current
outputsfromtwocascadedstagesofIFamplifiers/limiters
are summed and converted into the RSSI voltage. The
RSSI output has an excellent linear range of 90dB. The
characteristic of RSSI output voltage versus input IF
power is independent of temperature and process varia-
tion. The nominal output impedance is 3.8kΩ. An off-chip
capacitor C7 is needed to reduce the RSSI voltage ripple.
Its value can be determined using the following formula:
matched in gain response and group delay. The 3dB
corner frequency is 7.7MHz and the group delay ripple is
16.4ns. The I/Q differential outputs have output driving
capability of 1.5kΩ with maximum capacitive loading of
10pF. The outputs are internally biased at VCC –1.16V.
Figure 2 shows the simplified output circuit schematic of
I-channel or Q-channnel.
V
CC
I-CHANNEL
(OR Q-CHANNEL):
DIFFERENTIAL
1
+
SIGNALS FROM LPF
I
OUT
C7 ≥
F
+
–
(OR Q
)
OUT
760π • f
IF
–
I
OUT
(OR Q
)
OUT
I/Q Demodulators
+
–
+
–
200µA
200µA
The quadrature demodulators are double balanced mix-
ers, down converting the limited IF signals from the IF
Limiter into I/Q baseband signals. The quadrature LO
carriers are obtained from the internal quadrature LO
carrier generator. The nominal output voltage of differen-
tial I/Q baseband signals is about 850mVP-P. These mag-
nitudes are well matched, and their phases are 90° apart.
5502 F02
Figure 2. Simplified Circuit Schematic
of I-Channel (or Q-Channel) Outputs
The I/Q baseband outputs can be directly DC-coupled to
the inputs of a baseband chip. For AC-coupled applica-
tions with large coupling capacitors, the STBY pin can be
used to prebias the outputs to the desired quiescent
voltage at much reduced current. This mode only draws
2.6mA. When the EN pin is then turned on, the chip is
quickly switched to normal operating mode without long
time constants due to charging or discharging the large
coupling capacitors. Table 2 shows the logic of the EN pin
andSTBYpin.Inbothnormaloperatingmodeandstandby
mode, the maximum discharging current is about 200µA,
and the maximum charging current is more than 10mA.
Quadrature LO Carrier Generator
The quadrature LO carrier generator consists of a divide-
by-two circuit and LO buffers. An input signal (2XLO) with
twice the desired LO carrier frequency is used as the clock
for the divide-by-two circuit, producing the quadrature LO
carriers for the demodulators. The outputs are buffered
and then drive the down converting mixers. With a full
differential approach, the quadrature LO carriers are well
matched.
Integrated Low Pass Filters
Table 2. The logic of different operating modes
EN
STBY
Low
Comments
Shutdown Mode
Standby Mode
The 5th order integrated lowpass filters are used for
filtering the down converted baseband outputs for both
the I-channel and the Q-channel. They serve as anti-
aliasing and pulse-shaping filters. The I/Q filters are well
Low
Low
High
High
Low or High
Normal Operation Mode
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LT5502
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TYPICAL APPLICATIO S
+
–
+
–
V
CC2
I
I
Q
Q
OUT
OUT
OUT
OUT
C9
1µF
C24
10µF
C20
1µF
C25
10µF
R15
51.1k
R8
51.1k
R9
51.1k
R14
51.1k
C10
1µF
C14
1µF
V
CC1
7
7
C13
1µF
C17
1µF
3
3
2
R7
49.9
R16
49.9
+
+
J2
J3
U2
LT1809CS
U3
LT1809CS
6
6
C1
1µF
C2
1nF
Q
I
OUT
OUT
2
–
–
4
4
R6
2.55k
R12
2.55k
C11
1µF
C15
1µF
U1
C12
1.8pF
C16
1.8pF
R10
5.11k
R13
5.11k
LT5502
24
1
2
3
4
5
6
7
8
9
C3
1nF
+
+
–
I
I
Q
OUT
OUT
OUT
23
22
21
20
19
18
17
16
15
14
13
–
Q
OUT
V
T1
JTX-4-10T
T2
GND
J1
J4
CC
JTX-4-10T
V
GND
GND
2XLO
2XLO
CC
IF
IN
÷2
2XLO
6
1
GND
+
+
C5
IF
IF
R3
R4
–
–
22nF
240Ω
240Ω
6
1
4:1
MINI-CIRCUIT
GND
GND
EN
V
V
CC
CC
1:4
10
11
12
MINI-CIRCUIT
RSSI
RSSI
GND
IFt
STBY
C18
1µF
R2
20k
+
–
IFt
V
C4
1nF
C7
1.8pF
CC2
C23
1µF
1 = EN
R1
20k
L1
C8
2 = STBY
C19
22nF
SW1
R17
IF INTERSTAGE
OPTIONAL CIRCUIT
5502 F02
Figure 3. Evaluation Circuit Schematic With I/Q Output Buffers
8
LT5502
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TYPICAL APPLICATIO S
Figure 4.Component Side Silkscreen of Evaluation Board
Figure 5. Component Side Layout of Evaluation Board
9
LT5502
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TYPICAL APPLICATIO S
Figure 6.Bottom Side Silkscreen of Evaluation Board
Figure 7. Bottom Side Layout of Evaluation Board
10
LT5502
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
24-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.337 – 0.344*
(8.560 – 8.738)
0.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
9 10 11 12
0.015 ± 0.004
(0.38 ± 0.10)
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
× 45°
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN24 (SSOP) 1098
11
LT5502
U
TYPICAL APPLICATIO
Example: 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)
2V
0.1µF
100pF
V
BASEBAND
4,16,17,22
LPF
13
CC
12
RX INPUT:
2.4GHz TO
2.5GHz
I
PROCESSOR
280MHz IF
SAW BP
FILTER
I MIXER
0°
LO
BUFFER
OUTPUTS
1
2
A/D
LIMITER
1
LIMITER
2
3.3pF 22nF
120nH
6
7
RX
BUFFER
BUFFER
FRONT END
Q
1st LO,
2.12GHz
TO 2.22GHz
OUTPUTS
24
23
90°
A/D
Q MIXER
MAIN
SYNTHESIZER
LPF
11
10
f/2
STBY
EN
3.3pF
LT5502
19
15
18
RSSI
3,5,8,9,
14,20,21
1nF
1nF
1.8pF
2.7pF
30nH
30nH
2nd LO,
560MHz
200Ω
IF
SYNTHESIZER
2.7pF
5502 TA02
5502i LT/TP 0101 2K • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2001
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