LT6411CUD#PBF [Linear]
LT6411 - 650MHz Differential ADC Driver/Dual Selectable Gain Amplifier; Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LT6411CUD#PBF |
| 厂家： | 
Linear |
| 描述： | LT6411 - 650MHz Differential ADC Driver/Dual Selectable Gain Amplifier; Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C 放大器 |
| 文件： | 总16页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT6411
650MHz Differential ADC
Driver/Dual Selectable
Gain Amplifier
FEATURES
DESCRIPTION
TheLT®6411isadualamplifierwithindividuallyselectable
gains of +1, +2 and –1. The amplifiers have excellent dis-
tortion performance for driving ADCs as well as excellent
bandwidth and slew rate for video, data transmission and
other high speed applications. Single-ended to differential
conversion with a system gain of 2 is particularly straight-
forward by configuring one amplifier with a gain of +1
and the other amplifier with a gain of –1. The LT6411 can
be used on split supplies as large as 6ꢀ and on a single
supply as low as 4.5ꢀ.
■
650MHz –3dB Small-Signal Bandwidth
■
600MHz –3dB Large-Signal Bandwidth
■
High Slew Rate: 3300V/µs
Easily Configured for Single-Ended to Differential
■
Conversion
200MHz 0.1dꢁ ꢁandwidth
User Selectable Gain of +1, +2 and –1
No External Resistors Required
■
■
■
■
46.5dꢁmEquivalentOIP3at30MHzWhenDrivingan
ADC
■
IM3 with 2ꢀ Composite, Differential Output:
P-P
Each amplifier draws only 8mA of quiescent current when
enabled. When disabled, the output pins become high
impedance and each amplifier draws less than 350µA.
–87dꢁc at 30MHz, –83dꢁc at 70MHz
■
■
■
■
■
■
■
–77dꢁ SFDR at 30MHz, 2ꢀ Differential Output
P-P
6ns 0.1% Settling Time for 2ꢀ Step
The LT6411 is manufactured on Linear Technology’s
proprietary, low voltage, complimentary, bipolar process
and is available in the ultra-compact, 3mm × 3mm, 16pin
QFN package.
Low Supply Current: 8mA per Ampifier
Differential Gain of 0.02%, Differential Phase of 0.01°
50dꢁ Channel Separation at 100MHz
Wide Supply Range: 2.25ꢀ ꢂ4.5ꢀV to 6.3ꢀ ꢂ12.6ꢀV
3mm × 3mm 16-Pin QFN Package
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIONS
■
Differential ADC Driver
■
Single-Ended to Differential Conversion
■
Differential ꢀideo Line Driver
TYPICAL APPLICATION
30MHz 2-Tone 32768 Point FFT, LT6411
Driving an LTC®2249 14-Bit ADC
Differential ADC Driver
5V
0
–10
–20
–30
V
CC
LT6411
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
24Ω
24Ω
+
–
1.9V
DC
–
+
A
A
370Ω
370Ω
370Ω
IN
LTC2249
14-BIT ADC
80Msps
30MHz
INPUT
370Ω
IN
1.9V
–
+
DC
6411 TA01a
V
0
5
10 15 20 25 30 35 40
EE
DGND
FREQUENCY (MHz)
6411 TA01b
EN
6411f
1
LT6411
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
Total Supply ꢀoltage ꢂꢀ to ꢀ V ..........................12.6ꢀ
TOP VIEW
CC
EE
Input Current ꢂNote 2V.......................................... 10mA
Output Current ꢂContinuousV ............................... 70mA
EN to DGND ꢀoltage ꢂNote 2V ..................................5.5ꢀ
Output Short-Circuit Duration ꢂNote 3V ............ Indefinite
Operating Temperature Range ꢂNote 4V ... –40°C to 85°C
Specified Temperature Range ꢂNote 5V .... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
Junction Temperature ........................................... 125°C
16 15 14 13
1
2
3
4
12
11
10
9
V
V
V
DGND
EN
EE
EE
EE
17
V
CC
NC
VCC
5
6
7
8
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
= 125°C, θ = 68°C/W, θ = 4.2°C/W
T
JMAX
JA
JC
EXPOSED PAD ꢂPIN 17V IS ꢀ , MUST ꢁE SOLDERED TO PCꢁ
EE
ORDER PART NUMꢁER
UD PART MARKING*
LCGP
LCGP
LT6411CUD
LT6411IUD
Order Options Tape and Reel: Add #TR
Lead Free: Add #PꢁF Lead Free Tape and Reel: Add #TRPꢁF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*Temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS The
unless otherwise noted.
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, A = 2, R = 150Ω, C = 1.5pF, V = 0.4V, V
= 0V,
A
S
V
L
L
EN
DGND
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ꢀ
Input Referred Offset ꢀoltage
ꢀ
= 0ꢀ, ꢀ = ꢀ /2
3
10
20
mꢀ
mꢀ
OS
IN
OS
OUT
●
●
●
I
Input Current
–17
500
1
50
µA
kΩ
pF
IN
R
Input Resistance
Input Capacitance
ꢀ
IN
=
1ꢀ
150
56
IN
C
f = 100kHz
IN
ꢀ
Maximum Input Common Mode ꢀoltage
Minimum Input Common Mode ꢀoltage
ꢀ
ꢀ
– 1
CC
ꢀ
ꢀ
CMR
+ 1
EE
●
●
●
PSRR
Power Supply Rejection Ratio
Input Current Power Supply Rejection
Gain Error
ꢀ ꢂTotalV = 4.5ꢀ to 12ꢀ ꢂNote 6V
S
62
dꢁ
µA/ꢀ
%
I
ꢀ ꢂTotalV = 4.5ꢀ to 12ꢀ ꢂNote 6V
S
1
4
5
PSRR
A ERR
ꢀ
ꢀ
ꢀ
=
=
2ꢀ
2ꢀ
–1.2
1
OUT
OUT
A MATCH Gain Matching
ꢀ
%
ꢀ
Maximum Output ꢀoltage Swing
R = 1k
L
R = 150Ω
L
3.70
3.25
3.10
3.ꢃ5
3.6
ꢀ
ꢀ
ꢀ
OUT
L
R = 150Ω
●
●
I
S
Supply Current, Per Amplifier
Supply Current, Disabled, per Amplifier
Enable Pin Current
8
11
14
mA
mA
●
●
ꢀ
EN
ꢀ
EN
= 4ꢀ
= Open
22
0.5
350
350
µA
µA
●
●
I
EN
ꢀ
EN
ꢀ
EN
= 0.4ꢀ
= ꢀ
–200
–ꢃ5
0.5
µA
µA
+
50
6411f
2
LT6411
ELECTRICAL CHARACTERISTICS The
unless otherwise noted.
●
denotes the specifications which apply over the full operating
= 0V,
temperature range, otherwise specifications are at T = 25°C. V = 5V, A = 2, R = 150Ω, C = 1.5pF, V = 0.4V, V
A
S
V
L
L
EN
DGND
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
105
3300
650
200
600
525
263
MAX
UNITS
mA
●
I
Output Short-Circuit Current
Slew Rate
R = 0Ω, ꢀ =
L IN
1ꢀ
50
SC
SR
1ꢀ on 2ꢀ Output Step ꢂNote ꢃV
1700
ꢀ/µs
MHz
MHz
MHz
MHz
MHz
–3dꢁ ꢁW
Small-Signal –3dꢁ ꢁandwidth
ꢀ
OUT
ꢀ
OUT
ꢀ
OUT
ꢀ
OUT
ꢀ
OUT
= 200mꢀ , Single Ended
P-P
0.1dꢁ ꢁW Gain Flatness 0.1dꢁ ꢁandwidth
= 200mꢀ , Single Ended
P-P
FPꢁW
Full Power ꢁandwidth 2ꢀ Differential
Full Power ꢁandwidth 2ꢀ
Full Power ꢁandwidth 4ꢀ
All Hostile Crosstalk
= 2ꢀ Differential, –3dꢁ
P-P
= 2ꢀ ꢂNote 7V
270
P-P
= 4ꢀ ꢂNote 7V
P-P
f = 10MHz, ꢀ
= 2ꢀ
–75
–50
dꢁ
dꢁ
OUT
P-P
f = 100MHz, ꢀ
= 2ꢀ
P-P
OUT
t
Settling Time
0.1% to ꢀ
, ꢀ = 2ꢀ
6
ns
ps
s
FINAL STEP
t , t
r
Small-Signal Rise and Fall Time
Differential Gain
10% to ꢃ0%, ꢀ
= 200mꢀ
P-P
550
0.02
0.01
f
OUT
dG
dP
ꢂNote 8V
%
Diffierential Phase
ꢂNote 8V
Deg
The
CC
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C.
A
V
= 5V, V = 0V, A = 2, No R
, V = 0.4V, V
= 0V, unless otherwise noted.
EE
V
LOAD EN
DGND
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Noise/Harmonic Performance Input/Output Characteristics
1MHz Signal
HD
Second/Third Harmonic Distortion
2ꢀ Differential
P-P
–88
–87
dꢁc
dꢁc
P-P
2ꢀ Differential, R = 200Ω Differential
L
IMD3
Third-Order IMD
2ꢀ Differential Composite, f1 = 0.ꢃ5MHz,
–ꢃ3
dꢁc
1M
P-P
f2 = 1.05MHz
2ꢀ Differential Composite, f1 = 0.ꢃ5MHz,
–ꢃ1
dꢁc
P-P
f2 = 1.05MHz, R = 200Ω Differential
L
OIP3
NF
Output Third-Order Intercept
Noise Figure
Differential, f1 = 0.ꢃ5MHz, f2 = 1.05MHz ꢂNote 10V
Single Ended
4ꢃ.5
25.1
8
dꢁm
dꢁ
1M
e
n1M
Input Referred Noise ꢀoltage Density
1dꢁ Compression Point
nꢀ/√Hz
dꢁm
P1dꢁ
10MHz Signal
ꢂNote 10V
1ꢃ.5
HD
Second/Third Harmonic Distortion
2ꢀ Differential
P-P
–85
–76
dꢁc
dꢁc
P-P
2ꢀ Differential, R = 200Ω Differential
L
IMD3
Third-Order IMD
2ꢀ Differential Composite, R = 1k,
–ꢃ2
dꢁc
10M
P-P
L
f1 = ꢃ.5MHz, f2 = 10.5MHz
2ꢀ Differential Composite, f1 = ꢃ.5MHz,
–8ꢃ
dꢁc
P-P
f2 = 10.5MHz, R = 200Ω Differential
L
OIP3
NF
Output Third-Order Intercept
Noise Figure
Differential, f1 = ꢃ.5MHz, f2 = 10.5MHz ꢂNote 10V
Single Ended
4ꢃ
dꢁm
dꢁ
10M
24.7
7.7
e
Input Referred Noise ꢀoltage Density
1dꢁ Compression Point
nꢀ/√Hz
dꢁm
n10M
P1dꢁ
ꢂNote 10V
1ꢃ.5
6411f
3
LT6411
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, V = 0V, A = 2, No R
, V = 0.4V, V
= 0V,
A
CC
EE
V
LOAD EN
DGND
unless otherwise noted.
SYMBOL PARAMETER
30MHz Signal
CONDITIONS
MIN
TYP
MAX
UNITS
HD
Second/Third Harmonic Distortion
2ꢀ Differential
P-P
–77
–64
dꢁc
dꢁc
P-P
2ꢀ Differential, R = 200Ω Differential
L
IMD3
Third-Order IMD
2ꢀ Differential Composite, f1 = 2ꢃ.5MHz,
–87
dꢁc
30M
P-P
Differential, f2 = 30.5MHz
2ꢀ Differential Composite, f1 = 2ꢃ.5MHz,
–75
dꢁc
P-P
f2 = 30.5MHz, R = 200Ω Differential
L
OIP3
NF
Output Third-Order Intercept
Noise Figure
Differential, f1 = 2ꢃ.5MHz, f2 = 30.5MHz ꢂNote 10V
Single Ended
46.5
24.6
7.6
dꢁm
dꢁ
30M
e
Input Referred Noise ꢀoltage Density
1dꢁ Compression Point
nꢀ/√Hz
dꢁm
n30M
P1dꢁ
70MHz Signal
ꢂNote 10V
1ꢃ.5
HD
Second/Third Harmonic Distortion
2ꢀ Differential
P-P
–63
–52
dꢁc
dꢁc
P-P
2ꢀ Differential, R = 200Ω Differential
L
IMD3
Third-Order IMD
2ꢀ Differential Composite, f1 = 6ꢃ.5MHz,
–83
dꢁc
70M
P-P
Differential, f2 = 70.5MHz
2ꢀ Differential Composite, f1 = 6ꢃ.5MHz,
–64
dꢁc
P-P
f2 = 70.5MHz, R = 200Ω Differential
L
OIP3
NF
Output Third-Order Intercept
Noise Figure
Differential, f1 = 6ꢃ.5MHz, f2 = 70.5MHz ꢂNote 10V
Single Ended
44.5
24.7
7.7
dꢁm
dꢁ
70M
e
Input Referred Noise ꢀoltage Density
1dꢁ Compression Point
nꢀ/√Hz
dꢁm
n70M
P1dꢁ
ꢂNote 10V
1ꢃ.5
Note 7: Full power bandwidth is calculated from the slew rate:
FPꢁW = SR/ꢂπ • ꢀ
Note 8: Differential gain and phase are measured using a Tektronix
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This parameter is guaranteed to meet specified performance
through design and characterization. It is not production tested.
Note 3: As long as output current and junction temperature are kept
below the Absolute Maximum Ratings, no damage to the part will occur.
Depending on the supply voltage, a heat sink may be required.
V
P-P
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set. The resolution of this equipment is better than 0.05%
and 0.05°. Ten identical amplifier stages were cascaded giving an effective
resolution of better than 0.005% and 0.005°.
Note 9: Slew rate is 100% production tested on channel 1. Slew rate of
channel 2 is guaranteed through design and characterization.
Note 4: The LT6411C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: The LT6411C is guaranteed to meet specified performance from
0°C to 70°C. The LT6411C is designed, characterized and expected to
meet specified performance from –40°C and 85°C but is not tested or
QA sampled at these temperatures. The LT6411I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 10: Since the LT6411 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power is very small. In order to compare the
LT6411 with typical g amplifiers that require 50Ω output loading, the
m
LT6411 output voltage swing driving an ADC is converted to OIP3 and
P1dꢁ as if it were driving a 50Ω load.
Note 6: The two supply voltage settings for power supply rejection
are shifted from the typical ꢀ points for ease of testing. The first
S
measurement is taken at ꢀ = 3ꢀ, ꢀ = –1.5ꢀ to provide the required 3ꢀ
CC
EE
headroom for the enable circuitry to function with EN, DGND and all inputs
connected to 0ꢀ. The second measurement is taken at ꢀ = 8ꢀ, ꢀ = –4ꢀ.
CC
EE
6411f
4
LT6411
TYPICAL PERFORMANCE CHARACTERISTICS
All measurements are per amplifier with single-ended outputs unless otherwise noted.
Supply Current per Ampifier
vs Supply Voltage
Supply Current per Amplifier
vs Temperature
Supply Current per Amplifier
vs EN Pin Voltage
12
10
8
12
12
10
8
V
R
V
=
5V
V
V
T
= –V
, V
V
V
V
=
5V
= 0V
IN
S
L
CC
EE
S
+
–
= ∞
, V , V = 0V
IN
EN DGND IN
= 25°C
A
DGND
+
–
+
–
T
= –55°C
, V = 0V
A
10
8
, V = 0V
IN
IN
IN
V
EN
= 0V
T
= 25°C
A
T
= 125°C
A
V
EN
= 0.4V
6
6
6
4
4
4
2
2
2
0
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
EN PIN VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
10 11 12
–55 –35 –15
5
25 45 65 85 105 125
TOTAL SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
6411 G03
6411 G02
6411 G01
Output Offset Voltage
vs Temperature
Positive Input Bias Current
vs Input Voltage
EN Pin Current vs EN Pin Voltage
20
0
20
15
0
–20
V
V
A
= 5V
V
A
=
= 2
5V
S
V
V
=
5V
= 0V
S
V
S
= 0V
IN
= 2
V
DGND
10
–40
T
= 125°C
A
5
T
= 125°C
A
–60
–20
–40
–60
0
T
T
= 25°C
T
= –55°C
A
A
–80
–5
T
= 25°C
= –55°C
A
A
–100
–120
–140
–10
–15
–20
–55 –35 –15
5
25 45 65 85 105 125
–2.5
–1.5
–0.5
0.5
1.5
2.5
0
3
4
5
1
2
TEMPERATURE (°C)
INPUT VOLTAGE (V)
EN PIN VOLTAGE (V)
6411 G04
6411 G05
6411 G06
Output Voltage Swing vs I
(Output High)
Output Voltage Swing vs I
(Output Low)
LOAD
LOAD
Output Voltage vs Input Voltage
5
4
5
4
3
2
1
0
0
–1
–2
–3
–4
–5
V
R
A
= 5V
= 1k
= 1
V
A
V
=
5V
V
A
V
=
5V
S
L
V
S
V
S
V
= 2
= 2
= 2V
= –2V
IN
IN
3
T
= 25°C
T = 25°C
A
2
A
T
= –55°C
A
1
T
= 125°C
A
T
= 25°C
A
0
–1
–2
–3
–4
–5
T
= –55°C
A
T
= 125°C
T
A
= –55°C
A
T
= 125°C
A
0
10 20 30 40 50 60 70 80 90 100
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5
INPUT VOLTAGE (V)
0
10 20 30 40 50 60 70 80 90 100
SOURCE CURRENT (mA)
6411 G08
SINK CURRENT (mA)
6411 G07
6411 G09
6411f
5
LT6411
TYPICAL PERFORMANCE CHARACTERISTICS
All measurements are per amplifier with single-ended outputs unless otherwise noted.
Positive Input Impedance
vs Frequency
Input Noise Spectral Density
PSRR vs Frequency
70
60
50
40
30
20
10
0
1000
100
10
1000
100
10
V
A
T
=
5V
V
S
V
T
A
=
= 2
= 25°C
5V
V
V
T
=
5V
S
V
A
S
PSRR
= 2
= 0V
A
IN
= 25°C
= 25°C
A
–PSRR
e
n
+PSRR
i
n
1
1
0.1
0.01
0.001
0.01
0.1
1
10
100
0.1
1
10
100
1000
0.001
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6553 G10
6411 G11
6411 G12
Frequency Response
vs Gain Configuration
Frequency Response with
Capacitive Loads
Gain Flatness vs Frequency
18
16
14
12
10
8
9
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
V
A
V
=
5V
V
A
V
=
5V
S
V
S
V
= 2
= 2
A
= 2, V
= 2V
OUT P-P
V
= 2V
= 200mV
OUT
= 150Ω
= 25°C
P-P
OUT
P-P
6
3
C
= 12pF
R
L
R
T
= 150Ω
L
L
A
= 2, V
= 200mV
V
OUT
P-P
T
= 25°C
A
A
C
L
= 6.8pF
CHANNEL 1
A
= 1, A = –1,V
V
= 200mV
V
OUT
P-P
6
4
0
C
L
= 2.2pF
CHANNEL 2
2
A
= 1, V
= 2V
OUT P-P
V
0
A
= –1, V
= 2V
OUT P-P
V
–3
–6
V
= 5V
= 150Ω
= 25°C
S
L
–2
–4
–6
R
T
A
0.1
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
6411 G13
6411 G14
6553 G15
Harmonic Distortion vs Frequency,
Differential Input
Harmonic Distortion vs Amplitude,
30MHz, Differential Input
Harmonic Distortion vs Load,
30MHz, Differential Input
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
A
V
= 2, V = 5V
CC
V
A
V
= 2V , DIFFERENTIAL
V
A
V
T
= 2V , DIFFERENTIAL
OUT P-P
V
OUT
V
EE
P-P
= 0V, V = 1.6V
= 2, V = 5V
= 2, V = 5V
EE
= ∞
CM
CC
V CC
R
T
= 0V, V = 1.6V
= 0V, V = 1.6V
L
CM
EE
CM
= 25°C
DIFFERENTIAL R
= 25°C
= 25°C
A
A
LOAD
T
A
HD3, R = 200Ω
L
HD3, R = ∞
L
HD2, R = 200Ω
L
HD3
HD2
HD3
HD2
HD2, R = ∞
L
1
10
FREQUENCY (MHz)
100
0.4
1.8
0
100 200 300 400 500 600 700 800 9001000
DIFFERENTIAL R (Ω)
0.6 0.8 1.0 1.2 1.4 1.6
2.0
DIFFERENTIAL OUTPUT AMPLITUDE (V
)
P-P
LOAD
6411 G16
6411 G17
1011 G06
6411f
6
LT6411
TYPICAL PERFORMANCE CHARACTERISTICS
All measurements are per amplifier with single-ended outputs unless otherwise noted.
Third Order Intermodulation
Distortion vs Frequency,
Differential Input
Output Third Order Intercept
vs Frequency, Differential Input
Output Impedance vs Frequency
0
–10
–20
60
50
40
30
1000
100
10
V
= 2V , COMPOSITE, DIFFERENTIAL
P-P
OUT
DISABLED
EN
R
= ∞
L
1MHz TONE SPACING
V
= 4V
COMPUTED FOR 50Ω ENVIRONMENT
A
V
= 2, V = 5V
V
EE
CC
= 0V, V = 1.6V
CM
–30 DIFFERENTIAL R
LOAD
T
= 25°C
A
R
= 200Ω
–40
–50
–60
–70
–80
–90
–100
L
V
= 2V , COMPOSITE, DIFFERENTIAL
P-P
1MHz TONE SPACING
R
= 200Ω
OUT
L
20
10
0
ENABLED
1
A
V
= 2, V = 5V
V
EE
CC
R
= ∞
L
V
EN
= 0.4V
= 0V, V = 1.6V
V
= 5V
= 150Ω
= 25°C
CM
S
L
DIFFERENTIAL R
= 25°C
R
T
LOAD
T
A
A
0.1
0
20
30
40
50
60
70
0
10
20
30
40
50
60
70
0.1
10
10
0.01
1
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6411 G19
6411 G20
6411 G21
Video Amplitude Transient
Response
Small-Signal Transient Response
Large-Signal Transient Response
0.15
0.10
0.05
0
2.0
1.5
1.0
4
3
V
A
V
= 100mV
= 2
V
A
V
= 700mV
= 2
IN
V
S
P-P
IN
V
S
P-P
V
A
V
= 2.5V
= 2
IN
V
S
P-P
=
5V
=
5V
=
5V
R
T
= 150Ω
= 25°C
R
T
= 150Ω
= 25°C
L
A
L
A
R
A
= 150Ω
= 25°C
L
2
T
1
0
0.5
0
–1
–2
–3
– 4
–0.05
–0.10
–0.15
–0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
12 14 16 18 20
8
10
0
2
4
6
8
10 12 14 16 18 20
TIME (ns)
TIME (ns)
TIME (ns)
6411 G22
6411 G23
6411 G24
Gain Error Distribution
Crosstalk vs Frequency
Gain Matching Distribution
0
–20
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
V
V
=
OUT
= 150Ω
= 25°C
5V
2V
V
V
=
OUT
= 150Ω
= 25°C
5V
2V
S
V
V
=
OUT
= 150Ω
= 25°C
5V
S
S
=
=
= 2V
P-P
R
T
R
T
L
R
T
L
L
A
A
A
–40
–60
DRIVE 2
LISTEN 1
–80
DRIVE 1
–100
–120
LISTEN 2
0
–3.0
0
0
1
10
100
1000
–3.0 –2.0 –1.0
1.0
2.0
3.0
–2.0 –1.0
0
1.0
2.0
3.0
FREQUENCY (MHz)
GAIN MATCHING–BETWEEN CHANNELS (%)
GAIN ERROR–INDIVIDUAL CHANNEL (%)
1635 G25
6411 G26
6411 G27
6411f
7
LT6411
PIN FUNCTIONS
V (Pins 1, 2): Negative Supply ꢀoltage. ꢀ pins are not
EN (Pin 11): Enable Control Pin. An internal pull-up resis-
tor of 46k will turn the part off if the pin is allowed to float
and defines the pin’s impedance. When the pin is pulled
low, the part is enabled.
EE
EE
internally connected to each other and must all be con-
nected externally. Proper supply bypassing is necessary
for best performance. See the Applications Information
section.
DGND (Pin 12): Digital Ground Reference for Enable Pin.
This pin is normally connected to ground.
V (Pins 3, 7): Negative Supply ꢀoltage for Output Stage.
EE
EE
ꢀ
pins are not internally connected to each other and
+
IN1 (Pin 13): Channel 1 Positive Input. This pin has a
mustallbeconnectedexternally. Propersupplybypassing
is necessary for best performance. See the Applications
Information section.
nominalimpedanceof400kΩanddoesnothaveaninternal
termination resistor.
–
IN1 (Pin 14): This pin connects to the internal resistor
NC (Pin 4): This pin is not internally connected.
network of the channel 1 amplifier, connecting by a 370Ω
OUT2 (Pin 5): Output of Channel 2. The gain between the
inputandtheoutputofthischannelissetbytheconnection
of the channel 2 input pins. See Table 1 in Applications
Information for details.
resistor to the inverting input.
–
IN2 (Pin 15): This pin connects to the internal resistor
network of the channel 2 amplifier, connecting by a 370Ω
resistor to the inverting input.
V
ꢀ
(Pins 6, 9): Positive Supply ꢀoltage for Output Stage.
pins are not internally connected to each other and
+
CC
CC
IN2 (Pin 16): Channel 2 Positive Input. This pin has a
nominalimpedanceof400kΩanddoesnothaveaninternal
mustallbeconnectedexternally. Propersupplybypassing
is necessary for best performance. See the Applications
Information section.
termination resistor.
Exposed Pad (Pin 17): The pad is internally connected to
ꢀ
ꢂPin 1V. If split supplies are used, do not tie the pad
EE
OUT1 (Pin 8): Output of Channel 1. The gain between the
inputandtheoutputofthischannelissetbytheconnection
of the channel 1 input pins. See Table 1 in Applications
Information for details.
to ground.
V
(Pin 10): Positive Supply ꢀoltage. ꢀ pins are not
CC
CC
internally connected to each other and must all be con-
nected externally. Proper supply bypassing is necessary
for best performance. See the Applications Information
section.
6411f
8
LT6411
APPLICATIONS INFORMATION
Since the EN pin is referenced to DGND, it may need to be
pulled below ground in those cases. In order to protect the
internal enable circuitry, the EN pin should not be forced
more than 0.5ꢀ below DGND.
Power Supplies
The LT6411 can be operated on as little as 2.25ꢀ or a
single 4.5ꢀ supply and as much as 6ꢀ or a single 12ꢀ
supply. Internally, each supply is independent to improve
channel isolation. Note that the Exposed Pad is internally
In single supply applications above 5.5ꢀ, an additional
resistor may be needed from the EN pin to DGND if the
pin is ever allowed to float. For example, on a 12ꢀ single
supply, a 33k resistor would protect the pin from floating
too high while still allowing the internal pull-up resistor
to disable the part.
connected to ꢀ and must not be grounded when using
EE
splitsupplies.Donotleaveanysupplypinsdisconnected
or the part may not function correctly!
Enable/Shutdown
The LT6411 has a TTL compatible shutdown mode con-
trolled by the EN pin and referenced to the DGND pin. If
the amplifier will be enabled at all times, the EN pin can
be connected directly to DGND. If the enable function is
desired, either driving the pin above 2ꢀ or allowing the
internal 46k pull-up resistor to pull the EN pin to the top
railwilldisabletheamplifier. Whendisabled,theDCoutput
impedance will rise to approximately 740Ω through the
internal feedback and gain resistors ꢂassuming inputs at
groundV. Supply current into the amplifier in the disabled
The DGND pin should not be pulled above the EN pin since
doing so will turn on an ESD protection diode. If the EN
pin voltage is forced a diode drop below the DGND pin,
current should be limited to 10mA or less.
The enable/disable times of the LT6411 are fast when
driven with a logic input. Turn on ꢂfrom 50% EN input to
50% outputV typically occurs in less than 50ns. Turn off
is slower, but is less than 300ns.
Gain Selection
state will be primarily through ꢀ and approximately
CC
The gain of the internal amplifiers of the LT6411 is config-
equal to ꢂꢀ – ꢀ V/46k.
CC
EN
+
–
ured by connecting the IN and IN pins to the input signal
or ground in the combinations shown in Figure 1.
It is important that the two following constraints on the
DGND pin and the EN pin are always followed:
–
AsshownintheSimplifiedSchematic,theIN pinsconnect
ꢀ
– ꢀ
≥ 3ꢀ
DGND
CC
totheinternalgainresistorofeachamplifier,andtherefore,
each pin can be configured independently. Floating the
–0.5ꢀ ≤ ꢀ – ꢀ
≤ 5.5ꢀ
EN
DGND
–
IN pins is not recommended as the parasitic capacitance
Split supplies of 3ꢀ to 5.5ꢀ will satisfy these require-
ments with DGND connected to 0ꢀ.
causes an AC gain of 2 at high frequencies, despite a DC
gain of +1. ꢁoth inputs are connected together in the gain
of +1 configuration to avoid this limitation.
In dual supply cases with ꢀ less than 3ꢀ, DGND should
CC
be connected to a potential below ground such as ꢀ .
EE
+V
+V
+V
A
V
= +1
A
V
= –1
IN+
OUT+
OUT+
OUT–
LT6411
LT6411
LT6411
OUT–
IN+
+
–
+
–
+
–
IN+
A
= +2
V
IN–
OUT+
IN–
–
+
–
+
–
+
IN–
OUT–
6411 F01
–V
–V
–V
Figure 1. LT6411 Configured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies
6411f
9
LT6411
APPLICATIONS INFORMATION
Input Considerations
the blocking capacitor to the gain setting resistors sets
the input and output DC common mode voltages equal.
When using the LT6411 to drive an A-to-D converter, the
DC common mode voltage level will affect the harmonic
distortionofthecombinedamplifier/ADCsystem. Figure4
shows the measured distortion of an LTC224ꢃ ADC when
driven by the LT6411 at different common mode voltage
levels with the inputs configured as shown in Figure 3.
Adjusting the DC bias voltage can optimize the design for
the lowest possible distortion.
The LT6411 input voltage range is from ꢀ + 1ꢀ to
EE
ꢀ
– 1ꢀ. Therefore, on split supplies the LT6411 input
CC
rangeisalwaysaslargeasorlargerthantheoutputswing.
–
On a single positive supply with a gain of +2 and IN con-
nected to ground, however, the input range limit of +1ꢀ
limits the linear output low swing to 2ꢀ ꢂ1ꢀ multiplied by
the internal gain of 2V.
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to
10mA. Continuing to drive the input beyond the output
limit can result in increased current drive and slightly
increased swing, but will also increase supply current
and may result in delays in transient response at larger
levels of overdrive.
If the input signals are within the input voltage range
and output swing of the LT6411, but outside the input
range of an ADC or other circuit the LT6411 is driving,
+V
+
V
C
C
IN+
IN–
LARGE
R1
LT6411
V
OUT+
OUT–
DC
OV
+
–
DC Biasing Differential Amplifier Applications
V
V
DC
DC
R2
The inputs of the LT6411 must be DC biased within the
input common mode voltage range, typically ꢀ + 1ꢀ to
+
EE
V
–
+
ꢀ
– 1ꢀ. If the inputs are AC coupled or DC biased be-
CC
LARGE
R1
V
DC
yond the input voltage range of a driven A-to-D converter,
DC biasing or level shifting will be required. In the basic
circuit configurations shown in Figure 1, the DC input
common mode voltage and the differential input signal
are both multiplied by the amplifier gain. In the gain of
+2 configuration, the DC common mode voltage gain can
OV
R2
6411 F03
Figure 3. Using Resistor Dividers to Set the
Input Common Mode Voltage When AC Coupling
–
be set to unity by adding a capacitor at the IN pins as
shown in Figure 2.
–50
V
= 5V, V = 0V
EE
CC
V
A = 2
–55
–60
–65
–70
–75
–80
–85
–90
If the inputs are AC coupled or the LT6411 is preceded
by a highpass filter, the input common mode voltage can
be set by resistor dividers as shown in Figure 3. Adding
+V
T
A
= 25°C
HD3
IN+
LT6411
OUT+
IM3
V
+
–
DC
V
V
DC
HD2
C
LARGE
2.0 2.1
1.6 1.7 1.8 1.9
2.2 2.3 2.4 2.5
OUT–
–
+
V
(V)
CM
IN–
6411 F04
DC
V
DC
Figure 4. Harmonic and Intermodulation Distortion of the
LT6411 Driving an LTC2249 Versus DC Common Mode
6411 F02
Voltage. Harmonic Distortion Measured with a –1dBFS Signal
at 30.2MHz. Intermodulation Distortion Measured with Two
–7dBFS Tones at 30.2MHz and 29.2MHz
Figure 2. LT6411 Configured with a Differential Gain of 2
and Unity DC Common Mode Gain
6411f
10
LT6411
APPLICATIONS INFORMATION
+V
the output signals can be AC coupled and DC biased in a
manner similar to what is shown at the inputs in Figure
3. A simpler alternative when using an ADC such as the
IN+
IN–
LT6411
OUT+
V
V
+
–
CM
V
V
CM
CM
LTC224ꢃ is to use the ADC’s ꢀ pin to set the optimal
CM
common mode voltage as shown in Figure 5.
Ifunitycommonmodegainanddifferencemoderesponse
to DC is desired, there is another configuration available.
Figure 6 shows the LT6411 connected to provide a differ-
ential signal gain of +3 with unity common mode gain. For
differentialsignalgainbetweenunityand+3,threeresistors
canbeaddedtoprovideattenuationandsetthedifferential
input impedance of the stage as illustrated in Figure 7. The
general expression for the differential gain is:
OUT–
–
+
CM
6411 F06
Figure 6. LT6411 Configured for a Differential Gain of +3
and Unity Common Mode Gain with Response to DC
+V
IN+
LT6411
R = 13.7Ω
OUT+
OUT–
2 •k
AV(DIFF) = 1+
k + 2
V
V
+
–
CM
V
V
CM
CM
Scaling factor ‘k’ is the multiple between the two equal-
value series input resistors and the resistor connected
between the two positive inputs. The correct value of R for
the external resistors can be computed from the desired
k • R = 27.4Ω
–
+
IN–
CM
R = 13.7Ω
6411 F07
differential input impedance, Z , as a function of k and
IN
the 370Ω internal gain setting resistors, as described in
Figure 7. LT6411 Configured with a Differential Input Impedance
of 50Ω, a Differential Gain of +2 and Unity Common Mode Gain
the equation:
ZIN • 370Ω
R =
370Ω k + 2 – Z k + 1
(
)
(
)
IN
In Figure 7 k = 2 and R = 13.7Ω, setting the differential
gain to +2 and the differential input impedance to ap-
proximately 50Ω.
+V
IN+
LT6411
C
C
LARGE
OV
+
–
LTC2249
10k
LARGE
–
+
V
IN–
CM
OV
10k
2.2µF
6411 F05
–V
Figure 5. Level Shifting the Output Common Mode Voltage of the LT6411 Using the V Pin of an LTC2249
CM
6411f
11
LT6411
APPLICATIONS INFORMATION
Layout and Grounding
supply. The smallest value capacitors should be placed
closest to the LT6411 package.
It is imperative that care is taken in PCꢁ layout in order
to utilize the very high speed and very low crosstalk of
the LT6411. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input or output traces must be run over a
distanceofseveralcentimeters,theyshoulduseacontrolled
impedance with matching series and shunt resistances to
maintain signal fidelity.
Iftheundriveninputpinsarenotconnecteddirectlytoalow
impedancegroundplane, theymustbecarefullybypassed
to maintain minimal impedance over frequency. Although
crosstalk will be very dependent on the board layout, a
recommended starting point for bypass capacitors would
be 470pF as close as possible to each input pin with one
4700pF capacitor in parallel.
Series termination resistors should be placed as close to
theoutputpinsaspossibletominimizeoutputcapacitance.
See the Typical Performance Characteristics section for
a plot of frequency response with various output capaci-
tors—only 12pF of parasitic output capacitance causes
6dꢁ of peaking in the frequency response!
To maintain the LT6411’s channel isolation, it is beneficial
to shield parallel input and output traces using a ground
plane or power supply traces. ꢀias between topside
and backside metal may be required to maintain a low
inductance ground near the part where numerous traces
converge.
LowESL/ESRbypasscapacitorsshouldbeplacedasclose
to the positive and negative supply pins as possible. One
ESD Protection
The LT6411 has reverse-biased ESD protection diodes
on all pins. If any pins are forced a diode drop above the
positive supply or a diode drop below the negative sup-
ply, large currents may flow through these diodes. If the
current is kept below 10mA, no damage to the devices
will occur.
4700pF ceramic capacitor is recommended for both ꢀ
CC
andꢀ .Additional470pFceramiccapacitorswithminimal
EE
trace length on each supply pin will further improve AC
and transient response as well as channel isolation. For
high current drive and large-signal transient applications,
additional 1µF to 10µF tantalums should be added on each
TYPICAL APPLICATIONS
Single-Ended to Differential Converter
5V
ꢁecause the gains of each channel of the LT6411 can
be configured independently, the LT6411 can be used to
provide a gain of +2 when amplifying differential signals
and when converting single-ended signals to differential.
With both channels connected to a single-ended input,
one channel configured with a gain of +1 and the other
configuredwithagainof–1,theoutputwillbeadifferential
versionoftheinputwithtwicethepeak-to-peakꢂdifferentialV
amplitude. Figure 8 shows the proper connections and
Figure ꢃ displays the resulting performance when driv-
ing an LTC224ꢃ. This configuration can preserve signal
amplitude when converting single ended video signals to
differentialsignalswhendrivingdoubleterminatedcables.
The 10k resistors in Figure 8 set the common mode volt-
age at the output.
V
CC
LT6411
+
IN1
+
–
370Ω
OUT1
OUT2
+
–
OUT
OUT
1µF
–
–
370Ω
370Ω
INPUT
IN1
IN2
370Ω
5V
10k
–
+
+
V
IN2
CM
0.1µF
10k
V
EE
DGND
EN
6411 F08
Figure 8. Single-Ended to Differential Converter
with Gain of +2 and Common Mode Control
6411f
12
LT6411
TYPICAL APPLICATIONS
0
5V
6,9,10
–10
13
+
–
50Ω
50Ω
IN
IN
–20
–30
–40
–50
+
14
15
LT6411
100Ω
RECEIVER
A
V
= 2
16
5
–
–60
–70
–80
–90
1,2,3,7
6411 F10
11,12
–5V
–100
–110
–120
–130
–140
Figure 10. Twisted-Pair Driver
of 100Ω, the cables can be terminated with a smaller
series resistance or a larger shunt resistance in order to
compensate for attenuation. A typical circuit for a twisted-
pair driver is shown in Figure 10.
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
6411 F09
Figure 9. 2-Tone Response of the LT6411 Configured with
Single-Ended Inputs Driving the LTC2249 at 29.5MHz, 30.5MHz
Single Supply Differential ADC Driver
The LT6411 is well suited for driving differential analog
to digital converters. The low output impedance of the
LT6411 is capable of driving a variety of filters as well as
interfacing with the typically high impedance inputs of
ADCs. Inaddition, theLT6411’sexcellentdistortionallows
the part to perform with an SFDR below the limits of many
high speed ADCs. The DC1057 demo board, shown sche-
matically in Figure 11 and physically in Figure 12, allows
implementation and testing of the LT6411 with a variety
of different Linear Technology high speed ADCs.
Twisted-Pair Line Driver
The LT6411 is ideal when used for driving inexpensive
unshielded twisted-pair wires as often found in telephone
or communications infrastructure. The input can be com-
posite video, or if three parts are used, RGꢁ or similar and
can be either single ended or differential. The LT6411 has
excellent performance with all formats.
Double termination of the video cable will enhance fidelity
and isolate the LT6411 from capacitive loads. Although
most twisted-pair cables have a characteristic impedance
6411f
13
LT6411
TYPICAL APPLICATIONS
V
CC
C
D1
0.1µF
E1
V
+
V
C1
CC
EE
OPT
C
D2
4700pF
“B” CASE
E2
GND
JP1
ENABLE
R1
C
D3
470pF
10Ω
0603
1
2
3
V
CC
V
CC
L2
TBD
0603
C
D4
0.1µF
R2
OPT
R4
R3
R5
C2
C5
J1
IN
+
OPT
A
0603
6
9
10 11 12
V EN DGND
R8
R9
10Ω
1%
R35
12.1Ω
1%
C3
10Ω
C4
V
R6
TBD
0603
V
V
T1
CC
CC CC CC
+
R7
1%
13
14
15
16
8
5
ETC1-1TTR
+
A
IN1
OUT1
IN
R37
OPT
5
1
LT6411
–
–
+
L1
TO
IN1
IN2
IN2
2
3
V
R11
10Ω
1%
R12
R36
EE
C6
C7
C9
TBD
ADC
R10
R14
10Ω
12.1Ω
C8
0603
INPUTS
4
R38
OPT
1%
1%
TBD
–
C11
J2
A
OUT2
NC
0603
IN
–
A
L3
TBD
0603
IN
R13
V
V
V
V
EE EE EE EE
C10
C12
1
2
3
7
4
R16
0Ω
V
EE
E7
R17
OPT
R18
D5
470pF
V
EE
C
C31
D8
C
OPT
R19
0Ω
0.1µF
+ OPT
V
0603
CC
C
C
“B” CASE
E8
D6
D7
4700pF 1µF
6411 F11 GND
Figure 11. DC1057 Demo Circuit Schematic
Figure 12. Layout of DC1057 Demo Circuit
6411f
14
LT6411
SIMPLIFIED SCHEMATIC
V
CC
V
CC
–
TO OTHER
AMPLIFIER
BIAS
IN
370Ω
V
CC
46k
1k
150Ω
+
EN
IN
370Ω
OUT
V
EE
DGND
V
V
EE
EE
6411 SS
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 0.05
3.00 0.10
(4 SIDES)
15 16
0.70 0.05
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
1.45 0.10
(4-SIDES)
3.50 0.05
2.10 0.05
1.45 0.05
(4 SIDES)
PACKAGE
OUTLINE
(UD16) QFN 0904
0.200 REF
0.25 0.05
0.50 BSC
0.25 0.05
0.50 BSC
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6411f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT6411
TYPICAL APPLICATION
or additional filtering. Figure 15 shows the corresponding
SFDR of –75.5dꢁc with a 30MHz tone. Figure 16 shows
the 2-tone response of the LT6411 with 2ꢃ.5MHz and
In cases where lowering the noise floor is paramount,
adding higher order lowpass or bandpass filtering can
significantly increase signal-to-noise ratio. In Figure 13,
the LT6411 is shown driving an LTC224ꢃ with a 2nd order
lowpass filter that has been carefully chosen to ensure
optimal intermodulation distortion. The response is
shown in Figure 14. The filter improves the SNR over the
unfiltered case by 6dꢁ to 6ꢃ.5dꢁ. With the filter, the SNR
of the ADC and the LT6411 are comparable; better SNR
can be achieved by using either a higher resolution ADC
30.5MHz inputs. Note that 0dꢁFS corresponds to a 2ꢀ
P-P
differential signal.
9
6
3
0
–3
–6
–9
–12
80.6Ω
5V
IN+
390nH
55Ω
10Ω
–
+
A
1.9V
1.9V
+
IN
IN
DC
DC
–
15pF
390nH
LT6411
LTC2249
IN–
–
A
+
1
10
100
1000
10Ω
55Ω
80.6Ω
6411 F13
FREQUENCY (MHz)
6411 F14
Figure 13. Optimized 30MHz LT6411 Differential ADC Driver
Figure 14. Frequency Response of the LT6411 and Filter
0
0
–10
–10
–20
–30
–40
–20
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
6411 F15
6411 F16
Figure 15. SNR and SFDR of the LT6411 and Filter
Driving the LTC2249
Figure 16. 2-Tone Response of the LT6411 and Filter
Driving the LTC2249 at 29.5MHz, 30.5MHz
RELATED PARTS
PART NUMBER
LT1ꢃꢃ3-2
LT1ꢃꢃ3-4
LT1ꢃꢃ3-10
LT1ꢃꢃ4
DESCRIPTION
800MHz Low Distortion, Low Noise ADC Driver, A = 2
COMMENTS
3.8nꢀ/√Hz Total Noise, Low Distortion to 100MHz
2.4nꢀ/√Hz Total Noise, Low Distortion to 100MHz
1.ꢃnꢀ/√Hz Total Noise, Low Distortion to 100MHz
70MHz Gain ꢁandwidth Differential In and Out
3.8nꢀ/√Hz Input Referred Noise, Low Distortion to 30MHz
Triple Amplifier with Fixed Gain
ꢀ
ꢃ00MHz Low Distortion, Low Noise ADC Driver, A = 4
ꢀ
700MHz Low Distortion, Low Noise ADC Driver, A = 10
ꢀ
Low Noise, Low Distortion Fully Differential Amplfier
LT6402-6
LT6553
300MHz Low Distortion, Low Noise ADC Driver, A = 2
ꢀ
650MHz Gain of 2 Triple ꢀideo Amplifier
650MHz Gain of 1 Triple ꢀideo Amplifier
LT6554
Triple Amplifier with Fixed Gain
6411f
LT 0606 • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy ꢁlvd., Milpitas, CA ꢃ5035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
ꢂ408V 432-1ꢃ00 FAX: ꢂ408V 434-0507 www.linear.com
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