LT685_1 [Linear]
High Speed Comparator; 高速比较器
| 型号： | LT685_1 |
| 厂家： | 
Linear |
| 描述： | High Speed Comparator |
| 文件： | 总8页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT685
High Speed Comparator
U
FEATURES
DESCRIPTIO
The LT®685 is an ultrafast comparator with differential
inputs and complementary outputs fully compatible with
ECL logic levels. The output current capability is adequate
for driving transmission lines terminated in 50Ω. The low
input offset and high resolution make this comparator
ideally suited for analog-to-digital signal processing
applications.
■
Ultrafast (5.5ns typ)
■
Complementary ECL Output
■
50Ω Line Driving Capability
■
Low Offset Voltage
■
Output Latch Capability
■
External Hysteresis Control
■
Pin Compatible with Am685
A latch function is provided to allow the comparator to be
used in a sample-hold mode. When the latch enable input
is ECL high, the comparator functions normally. When the
latch enable is driven low, the comparator outputs are
locked in their existing logical states. If the latch function
is not used, the latch enable must be connected to ground
or ECL high.
U
APPLICATIO S
■
High Speed A-to-D Converters
High Speed Sampling Circuits
■
■
Oscillators
The device is pin-compatible with the Am685. Hysteresis
has been added to improve switching time with slow input
signals as well as to minimize oscillation. A single resistor
between the hysteresis pin and V– adds input hysteresis
voltage as more current is drawn. If hysteresis is not
required, the pin can be left unconnected.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Comparator with Hysteresis
Hysteresis
100
HYSTERESIS IS ZERO
IF PIN LEFT OPEN
6V
GND1
+
V
GND2
V
+
IN
10
Q
Q
LT685
–
HYSTERESIS
–
V
R
R
L
R
L
LATCH
ENABLE
1
100 200
500
1k
2k
5k
10k
RESISTANCE (Ω)
V
–5.2V
T
LT685 • TA02
LT685 • TA01
685fa
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LT685
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Positive Supply Voltage ............................................. 7V
Negative Supply Voltage .......................................... –7V
Input Voltage ........................................................... ±4V
Differential Input Voltage ......................................... ±6V
Latch Pin Voltage.............................................. 2V to V–
Hysteresis Pin Voltage ...................................... 0V to V–
Output Current...................................................... 30mA
Power Dissipation (Note 2)................................ 500mW
Operating Temperature
LT685C......................................... –30°C ≤ TA ≤ 85°C
LT685M (OBSOLETE) ................. –55°C ≤ TA ≤ 125°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
GND #1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND #2
NC
NUMBER
+
V
LT685CN
LT685CH
LT685MH
TOP VIEW
NON-INVERTING INPUT
NC
GND #1
10
+
INVERTING INPUT
NC
GND #2
V
1
4
9
NC
LATCH ENABLE
NC
Q OUTPUT
Q OUTPUT
NC
NONINVERTING
INPUT
Q OUTPUT
2
8
7
+
–
3
INVERTING
INPUT
Q OUTPUT
–
V
HYSTERESIS
6
5
HYSTERESIS
LATCH
ENABLE
–
V
N16 PACKAGE
16-LEAD CERDIP
H PACKAGE
TO-5 METAL CAN
J16 PACKAGE (HERMETIC)
16-LEAD PDIP
ORDER PART
NUMBER
LT685CJ
OBSOLETE PACKAGE
OBSOLETE PACKAGE
Consider the N16 Package as an Alternate Source
LT685MJ
Consider the N16 Package as an Alternate Source
LT685 • POI01
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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LT685
V+ = 6.0V, V– = –5.2V, VT = –2V, RL = 50Ω, R = ∞ over the operating temp-
ELECTRICAL CHARACTERISTICS
erature ranges, unless otherwise noted.
LT685C
TYP
LT685M
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
VOS
Input Offset Voltage
TA = 25°C
1.0
±2.0
±2.5
1.0
±2.0
±3.0
mV
mV
dVOS/dT
lOS
Input Offset Voltage Drift
Input Offset Current
(Note 3)
±10
±10
µV/°C
TA = 25°C
0.3
5
±1.0
±1.3
0.3
5
±1.0
±1.6
µA
µA
IB
Input Bias Current
TA= 25°C
10
13
10
16
µA
µA
RIN
CIN
Input Resistance
Input Capacitance
TA = 25°C (Note 3)
TA = 25°C (Note 3)
6.0
6.0
kΩ
3.0
3.0
pF
VCM
lnput Voltage Range
±3.3
±3.3
V
dB
dB
CMRR
SVRR
VOH
Common Mode Rejection
Supply Voltage Rejection
Output High Voltage
80
70
80
70
TA = 25°C
TA = TMIN
TA = TMAX
–0.960
–1.060
–0.890
–0.810
–0.890
–0.700
–0.960
–1.100
–0.850
–0.810
–0.920
–0.620
V
V
V
VOL
Output Low Voltage
TA = 25°C
TA = TMIN
TA = TMAX
–1.850
–1.890
–1.825
–1.650
–1.675
–1.625
–1.850
–1.910
–1.810
–1.650
–1.690
–1.575
V
V
V
I+
Positive Supply Current
22
22
mA
I–
Negative Supply Current
Power Dissipation
26
26
mA
PDISS
300
300
mW
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LT685
U
(VIN = 100mV step, 5mV overdrive)
LT685C
SWITCHI G CHARACTERISTICS
LT685M
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
tPD
Propagation Delay
(Note 4)
TA = 25°C
TA = TMAX
TA = TMIN
4.5
5.0
4.0
5.5
6.5
9.5
6.5
4.5
5.5
3.5
5.5
6.5
12
6.5
ns
ns
ns
tPD(E)
Latch Enable to
Output Delay
(Note 3)
TA = 25°C
TA = TMAX
TA = TMIN
4.5
5.0
4.0
5.5
6.5
9.5
6.5
4.5
5.5
3.5
5.5
6.5
12
6.5
ns
ns
ns
tS
Minimum Set-Up Time
(Note 3)
T
MIN ≤ TA ≤ 25°C
3.0
4.0
3.0
6.0
ns
ns
TA = TMAX
tH
Minimum Hold Time
(Note 3)
TMIN ≤ TA ≤ TMAX
1.0
1.0
ns
tPW(E)
Minimum Latch Enable
Pulse Width (Note 3)
T
MIN ≤ TA ≤ 25°C
3.0
4.0
3.0
5.0
ns
ns
TA = TMAX
Note 1: Absolute Maximum Ratings are those values beyond which the life
Definitions:
of a device may be impaired.
t
: The propagation delay measured from the time the input signal
PD
Note 2: For the metal can package, derate at 6.8mW/°C for operation at
ambient temperatures above 100°C; for the hermetic dual-in-line package,
derate at 9mW/°C for operation at ambient temperatures above 105°C.
Note 3: Guaranteed by design, but not tested.
Note 4: Sample tested at 25°C only.
crosses the input offset voltage to the 50% point of the output transition.
: The propagation delay measured from the 50% point of the latch
enable signal positive transition to the 50% point of the output transition.
t
PD(E)
t : The minimum time before the negative transition of the latch enable
S
signal that an input signal change must be present in order to be acquired
and held at the outputs.
t : The minimum time after the negative transition of the latch enable
H
signal that the input signal must remain unchanged in order to be acquired
and held at the outputs.
t
: The minimum time that the latch enable signal must be HIGH in
PW (E)
order to acquire and hold an input signal change.
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LT685
W
W
SCHE ATIC DIAGRA
+
V
R2
300Ω
R1
300Ω
R23
1.7k
Q14
D2
D1
Q13
R6
525Ω
R5
Q33
Q31
525Ω
D4
D3
R22
2.9k
Q19
Q3
Q32
Q30
Q4
Q20
Q18
GND #2
R8
GND #1
Q17
Q7
Q8
NONINVERTING
INPUT
Q6
Q1
R7
D5
D7
D8
275Ω 275Ω
Q5
INVERTING
INPUT
Q2
R3
1.4k
R4
2.4k
D6
Q23
R21
846Ω
Q21
Q24
Q29
Q28
LATCH
ENABLE
R20
3.8k
Q22
Q9
Q10
R12
Q16
Q15
Q
Q
Q26
Q12
Q27
OUTPUT OUTPUT
Q25
Q11
R11
430Ω
R19
2.4k
R10
880Ω
R14
3k
R18
150Ω
R13
3.0k
R15
2.1k
R16
2.1k
R17
150Ω
200Ω
–
V
LT685 • S01
HYSTERESIS
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LT685
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Propagation Delays as a Function
of Temperature
Hysteresis as a Function of
Temperature
12
10
8
100
90
80
70
60
50
40
30
20
10
0
R = 200Ω
V
= 5mV
OD
6
4
2
V
V
= 2.5mV
= 20mV
OD
OD
R = 500Ω
V
= 10mV
OD
R = 1000Ω
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
TEMPERATURE (°C)
–25
TEMPERATURE (°C)
LTC685 • TPC01
LTC685 • TPC02
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PACKAGE DESCRIPTIO
H Package
10-Lead TO-5 Metal Can
(Reference LTC DWG # 05-08-1322)
0.335 – 0.370
(8.509 – 9.398)
DIA
0.305 – 0.335
(7.747 – 8.509)
0.040
0.050
(1.270)
MAX
(1.016)
MAX
0.165 – 0.185
(4.191 – 4.699)
REFERENCE
PLANE
SEATING
PLANE
GAUGE
PLANE
0.500 – 0.750
(12.700 – 19.050)
0.010 – 0.045*
(0.254 – 1.143)
0.016 – 0.021**
(0.406 – 0.533)
0.027 – 0.045
(0.686 – 1.143)
36°BSC
PIN 1
0.028 – 0.034
(0.711 – 0.864)
0.230
( 5.842)
TYP
0.110 – 0.160
*LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045" BELOW THE REFERENCE PLANE
0.016 – 0.024
**FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS
(0.406 – 0.610)
(2.794 – 4.064)
INSULATING
STANDOFF
H10(TO-5) 1197
OBSOLETE PACKAGE
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LT685
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PACKAGE DESCRIPTIO
J Package
16-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
0.840
(21.336)
CORNER LEADS OPTION
(4 PLCS)
0.005
(0.127)
MIN
MAX
16
10
15
14
12
11
9
8
13
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.220 – 0.310
(5.588 – 7.874)
0.025
(0.635)
RAD TYP
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
2
3
5
1
4
6
7
0.200
(5.080)
MAX
0.300 BSC
(0.762 BSC)
0.015 – 0.060
(0.380 – 1.520)
0.008 – 0.018
(0.203 – 0.457)
0° – 15°
0.045 – 0.065
(1.143 – 1.651)
0.125
(3.175)
MIN
0.100
(2.54)
BSC
0.014 – 0.026
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
(0.360 – 0.660)
J16 1298
OBSOLETE PACKAGE
685fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
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LT685
U
PACKAGE DESCRIPTIO
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
14
12
10
9
8
15
13
11
16
0.255 ± 0.015*
(6.477 ± 0.381)
2
1
3
4
6
5
7
0.300 – 0.325
0.130 ± 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 ± 0.127)
(1.143 – 1.651)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
–0.015
0.325
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
+0.889
8.255
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N16 1098
685fa
LW/TP 0902 1K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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■
LINEAR TECHNOLOGY CORPORATION 1988
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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