LT8580HDD#TRPBF [Linear]
LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: DFN; Pins: 8; Temperature Range: -40°C to 125°C;
| 型号： | LT8580HDD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: DFN; Pins: 8; Temperature Range: -40°C to 125°C |
| 文件： | 总32页 (文件大小：1393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT8580
Boost/SEPIC/Inverting
DC/DC Converter with 1A, 65V
Switch, Soft-Start and Synchronization
FEATURES
DESCRIPTION
The LT®8580 is a PWM DC/DC converter containing an
internal 1A, 65V switch. The LT8580 can be configured
n
1A, 65V Power Switch
n
Adjustable Switching Frequency
n
Single Feedback Resistor Sets V
as either a boost, SEPIC or inverting converter.
OUT
n
Synchronizable to External Clock
High Gain SHDN Pin Accepts Slowly Varying
Input Signals
The LT8580 has an adjustable oscillator, set by a resistor
fromtheRTpintoground. Additionally, theLT8580canbe
synchronizedtoanexternalclock.Theswitchingfrequency
of the part may be free running or synchronized, and can
be set between 200kHz and 1.5MHz.
n
n
n
n
n
Wide Input Voltage Range: 2.55V to 40V
Low V
Switch: 400mV at 0.75A (Typical)
CESAT
Integrated Soft-Start Function
The LT8580 also features innovative SHDN pin circuitry
that allows for slowly varying input signals and an adjust-
able undervoltage lockout function.
Easily Configurable as a Boost, SEPIC, or Inverting
Converter
User Configurable Undervoltage Lockout (UVLO)
Pin Compatible with LT3580
Tiny Thermally Enhanced 8-Lead 3mm × 3mm DFN
and 8-Lead MSOP Packages
n
n
n
Additional features such as frequency foldback and
soft-start are integrated. The LT8580 is available in tiny
thermally enhanced 3mm × 3mm 8-lead DFN and 8-lead
MSOP packages.
n
AEC-Q100 Qualification in Progress
All registered trademarks and trademarks are the property of their respective owners.
APPLICATIONS
n
VFD Bias Supplies
n
TFT-LCD Bias Supplies
n
GPS Receivers
n
DSL Modems
n
Local Power Supply
TYPICAL APPLICATION
1.5MHz, 5V to 12V Boost Converter
Efficiency and Power Loss
ꢘꢌꢌ
ꢝꢌ
ꢙꢌ
ꢜꢌ
ꢗꢌ
ꢖꢌ
ꢕꢌ
ꢛꢌ
ꢍꢌ
ꢕꢙꢌ
ꢕꢍꢌ
ꢛꢗꢌ
ꢛꢌꢌ
ꢍꢕꢌ
ꢘꢙꢌ
ꢘꢍꢌ
ꢗꢌ
ꢈꢍꢂꢎ
ꢄ
ꢅꢆꢇ
ꢄ
ꢑꢒ
ꢈꢉꢄ
ꢍꢄ
ꢉꢊꢊꢋꢌ
ꢈꢊꢐ
ꢄ
ꢑꢒ
ꢓꢔ
ꢃBꢛ
ꢄꢜ
ꢈꢏꢊꢐ
SHDN
ꢀ.ꢁꢂꢃ
ꢗꢇꢕꢍꢕꢊ
ꢉ.ꢉꢂꢃ
ꢓꢝꢒꢜ
Rꢇ
ꢘ.ꢊꢀꢐ
ꢏ.ꢏꢞꢃ
ꢙꢒꢚ ꢓꢓ
ꢀꢁꢟꢃ
ꢆꢎꢎꢏꢄꢏꢆꢇꢄꢐ
ꢍꢘ.ꢉꢐ
ꢊ.ꢉꢉꢂꢃ
ꢒꢁꢓꢆR ꢀꢁꢔꢔ
ꢕꢍꢕꢊ ꢇꢌꢊꢈꢖ
ꢌ
ꢍꢌꢌ
ꢌ
ꢖꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢘꢌꢌ
ꢘꢖꢌ
ꢙꢖꢙꢌ ꢈꢂꢌꢘꢚ
Rev. B
1
Document Feedback
For more information www.analog.com
LT8580
ABSOLUTE MAXIMUM RATINGS (Note 1)
V Voltage.................................................–0.3V to 40V
SHDN Voltage ............................................–0.3V to 40V
SYNC Voltage............................................–0.3V to 5.5V
Operating Junction Temperature Range
IN
SW Voltage ................................................–0.4V to 65V
RT Voltage ...................................................–0.3V to 5V
SS Voltage ................................................–0.3V to 2.5V
FBX Voltage.................................................................5V
FBX Current............................................................–1mA
VC Voltage ...................................................–0.3V to 2V
LT8580E (Notes 2, 5).........................–40°C to 125°C
LT8580I (Notes 2, 5)..........................–40°C to 125°C
LT8580H (Notes 2, 5) ........................ –40°C to 150°C
Storage Temperature Range ..................–65°C to 150°C
PIN CONFIGURATION
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢑꢒꢓ ꢆꢈꢔꢋ
ꢔBꢝ
ꢃꢉ
ꢜ
ꢛ
ꢐ
ꢚ
ꢌ
ꢘ
ꢗ
ꢖ
ꢓꢞꢕꢉ
ꢓꢓ
ꢄBꢅ
ꢆꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢌ ꢊꢐꢉꢇ
ꢍ ꢊꢊ
ꢕ
ꢖꢉꢗ
ꢙ
ꢋꢕꢇ
ꢎ
ꢏ
ꢆ
ꢈꢉ
Rꢑ
SHDN
ꢃ
ꢄꢕ
Rꢀ
ꢊꢋ
ꢓꢆ
SHDN
ꢘꢊꢌꢔ ꢓꢙꢇꢚꢙꢖꢔ
ꢌꢛꢜꢔꢙꢗ ꢓꢜꢙꢊꢑꢈꢇ ꢘꢊꢒꢓ
ꢇꢇ ꢂꢈꢉꢊꢈꢋꢅ
ꢌꢍꢎꢅꢈꢇ ꢏꢐꢑꢑ × ꢐꢑꢑꢒ ꢂꢎꢈꢓꢀꢄꢉ ꢇꢔꢕ
θ
= 35°C/W TO 40°C/W
JA
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
θ
= 43°C/W
JA
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LGKH
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8580EDD#PBF
LT8580EDD#TRPBF
LT8580IDD#TRPBF
LT8580HDD#TRPBF
LT8580EMS8E#TRPBF
LT8580IMS8E#TRPBF
LT8580HMS8E#TRPBF
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
LT8580IDD#PBF
LGKH
LT8580HDD#PBF
LGKH
LT8580EMS8E#PBF
LT8580IMS8E#PBF
LT8580HMS8E#PBF
AUTOMOTIVE PRODUCTS**
LT8580EMS8E#WPBF
LT8580IMS8E#WPBF
LT8580HMS8E#WPBF
LTGKJ
LTGKJ
8-Lead Plastic MSOP
LTGKJ
8-Lead Plastic MSOP
LT8580EMS8E#WTRPBF LTGKJ
LT8580IMS8E#WTRPBF LTGKJ
LT8580HMS8E#WTRPBF LTGKJ
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. B
2
For more information www.analog.com
LT8580
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Operating Voltage Range
LT8580E, LT8580I
LT8580H
2.55
2.9
40
40
V
V
l
l
l
l
Positive Feedback Voltage
Negative Feedback Voltage
Positive FBX Pin Bias Current
Negative FBX Pin Bias Current
Error Amplifier Transconductance
Error Amplifier Voltage Gain
Quiescent Current
1.185
–3
81
1.204
3
83.3
83.3
200
60
1.2
0
0.01
1.220
12
85
V
mV
µA
V
V
= Positive Feedback Voltage, Current Into Pin
= Negative Feedback Voltage, Current Out of Pin
FBX
81
86
µA
FBX
µmhos
V/V
mA
µA
%/V
V
V
= 2.5V, Not Switching
= 0V
1.7
1
0.05
SHDN
Quiescent Current in Shutdown
Reference Line Regulation
SHDN
2.5V ≤ V ≤ 40V
IN
l
l
Switching Frequency, f
R = 56.2k
T
1.23
165
1.5
200
1.77
235
MHz
kHz
OSC
T
R = 422k
Switching Frequency in Foldback
Switching Frequency Set Range
SYNC High Level for Synchronization
SYNC Low Level for Synchronization
SYNC Clock Pulse Duty Cycle
Recommended Minimum SYNC Ratio f
Minimum Off-Time
Compared to Normal f
SYNCing or Free Running
1/6
Ratio
kHz
V
OSC
l
l
l
200
1.3
1500
0.4
65
V
%
V
= 0V to 2V
35
SYNC
/f
3/4
100
120
SYNC OSC
ns
ns
Minimum On-Time
l
l
l
Switch Current Limit
Minimum Duty Cycle (Note 3)
Maximum Duty Cycle (Notes 3, 4), f
Maximum Duty Cycle (Notes 3, 4), f
1.2
0.6
0.4
1.5
1
0.8
1.8
1.5
1.4
A
A
A
= 1.5MHz
= 200kHz
OSC
OSC
Switch V
Switch Leakage Current
Soft-Start Charging Current
I
V
V
= 0.75A
400
0.01
6
mV
µA
µA
CESAT
SW
= 5V
1
8
SW
l
= 0.5V
4
SS
l
l
SHDN Minimum Input
Voltage High
Active Mode, SHDN Rising
Active Mode, SHDN Falling
1.23
1.21
1.31
1.27
1.4
1.33
V
V
l
SHDN Input Voltage Low
SHDN Pin Bias Current
Shutdown Mode
0.3
V
V
SHDN
V
SHDN
V
SHDN
= 3V
= 1.3V
= 0V
44
12
0
56
15
0.1
µA
µA
µA
9
SHDN Hysteresis
40
mV
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8580E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8580I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT8580H is guaranteed over the full –40°C to
150°C operating junction temperature range. Operating lifetime is derated
at junction temperatures greater than 125°C.
Note 3: Current limit guaranteed by design and/or correlation to static test.
Note 4: Current limit measured at equivalent of listed switching frequency.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Rev. B
3
For more information www.analog.com
LT8580
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise specified
Commanded Switch Current vs SS
Switch Current Limit vs Duty Cycle
Switch Saturation Voltage
ꢕ.ꢋꢋ
ꢊ.ꢔꢓ
ꢊ.ꢓꢋ
ꢊ.ꢕꢓ
ꢊ.ꢋꢋ
ꢋ.ꢔꢓ
ꢋ.ꢓꢋ
ꢋ.ꢕꢓ
ꢋ
ꢓ.ꢊ
ꢒ.ꢑ
ꢒ.ꢊ
ꢊ.ꢑ
ꢊ
ꢙꢌꢌ
ꢔꢌꢌ
ꢓꢌꢌ
ꢒꢌꢌ
ꢘꢌꢌ
ꢗꢌꢌ
ꢕꢌꢌ
ꢌ
ꢊ
ꢊ.ꢔ
ꢊ.ꢕ
ꢊ.ꢖ
ꢒ
ꢒ.ꢓ
ꢛꢋ ꢔꢋ
ꢀꢁꢂꢃ ꢄꢃꢄꢅꢆ ꢇꢈꢉ
ꢕ
ꢊ.ꢓ
ꢊꢋ ꢕꢋ ꢖꢋ ꢚꢋ ꢓꢋ
ꢘꢋ ꢗꢋ
ꢌ
ꢌ.ꢗꢓ
ꢌ.ꢓ
ꢌ.ꢙꢓ
ꢕ.ꢗꢓ
ꢕ.ꢓ
ꢀꢀ ꢁꢂꢃꢄꢅꢆꢇ ꢈꢁꢉ
ꢀꢁꢂꢃꢄꢅ ꢄꢆRRꢇꢈꢃ ꢉꢊꢋ
ꢖꢑꢖꢊ ꢆꢊꢗ
ꢘꢓꢘꢋ ꢙꢋꢊ
ꢖꢓꢖꢌ ꢐꢌꢗ
Switch Current Limit
vs Temperature
Positive and Negative Output
Voltage Regulation
ꢍ.ꢌ
ꢔ.ꢋ
ꢔ.ꢌ
ꢌ.ꢋ
ꢌ
ꢎ.ꢍꢍꢌ
ꢎ.ꢍꢎꢋ
ꢎ.ꢍꢎꢌ
ꢎ.ꢍꢌꢋ
ꢎ.ꢍꢌꢌ
ꢎ.ꢎꢛꢋ
ꢎ.ꢎꢛꢌ
ꢎ.ꢎꢚꢋ
ꢎ.ꢎꢚꢌ
ꢎ.ꢎꢏꢋ
ꢎ.ꢎꢏꢌ
ꢜꢌ
ꢍꢋ
ꢍꢌ
ꢎꢋ
ꢎꢌ
ꢋ
ꢌ
ꢊꢋ
ꢊꢎꢌ
ꢊꢎꢋ
ꢊꢍꢌ
ꢊꢋꢌ ꢊꢍꢋ
ꢌ
ꢍꢋ ꢋꢌ ꢕꢋ ꢔꢌꢌ ꢔꢍꢋ ꢔꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢖꢋꢖꢌ ꢗꢌꢘ
ꢊꢋꢌ ꢊꢍꢋ
ꢌ
ꢍꢋ ꢋꢌ ꢏꢋ ꢎꢌꢌ ꢎꢍꢋ ꢎꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢚꢋꢚꢌ ꢗꢌꢋ
Positive and Negative FBX Current
at Output Voltage Regulation
Oscillator Frequency
ꢎꢘ
ꢎꢋ
ꢎꢜ
ꢎꢛ
ꢎꢍ
ꢎꢚ
ꢎꢌ
ꢎꢘ
ꢕ.ꢔ
ꢕ.ꢙ
ꢕ.ꢖ
ꢕ.ꢍ
ꢕ.ꢌ
ꢌ.ꢔ
ꢌ.ꢙ
ꢌ.ꢖ
ꢌ.ꢍ
ꢌ
R
ꢚ ꢋꢙ.ꢍꢛ
ꢀ
ꢎꢋ
ꢎꢜ
ꢎꢛ
ꢎꢍ
ꢎꢚ
ꢎꢌ
R
ꢀ
ꢚ ꢖꢍꢍꢛ
ꢊꢋꢌ ꢊꢍꢋ
ꢌ
ꢍꢋ ꢋꢌ ꢙꢋ ꢚꢌꢌ ꢚꢍꢋ ꢚꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢊꢋꢌ ꢊꢍꢋ
ꢍꢋ ꢋꢌ ꢘꢋ
ꢕꢍꢋ
ꢕꢌꢌ ꢕꢋꢌ
ꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢎꢋꢎꢌ ꢗꢌꢘ
ꢔꢋꢔꢌ ꢗꢌꢘ
Rev. B
4
For more information www.analog.com
LT8580
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise specified
Oscillator Frequency During
Soft-Start
Internal UVLO
SHDN Pin Current
ꢍ.ꢕ
ꢍ.ꢚ
ꢍ.ꢋ
ꢍ.ꢖ
ꢍ.ꢗ
ꢍ.ꢍ
ꢍ.ꢎ
ꢓꢉ
ꢒꢐ
ꢗ
ꢑꢒꢐꢖꢍ
ꢒꢐꢖꢍ
ꢗꢘꢉꢖꢍ
ꢒꢉ
ꢑꢐ
ꢗꢖꢙ
ꢗꢖꢚ
ꢗꢖꢘ
ꢗꢖꢜ
ꢗꢖꢛ
ꢑꢉ
ꢐ
ꢎꢌꢂꢈRꢅꢎꢌꢇ
ꢌꢃꢌꢎꢌꢂꢈRꢅꢎꢌꢇ
ꢒꢃꢌꢀꢎꢇꢔRꢆꢅꢎꢃꢌꢑ ꢒꢃꢌꢀꢎꢇꢔRꢆꢅꢎꢃꢌꢑ
ꢋ
ꢉ
ꢋ
ꢋ.ꢙ ꢋ.ꢘ ꢋ.ꢛ ꢋ.ꢝ
ꢀBꢁ ꢂꢃꢄꢅꢆꢇꢈ ꢉꢂꢊ
ꢗ
ꢗ.ꢙ
ꢊꢋꢌ ꢊꢍꢋ
ꢌ
ꢍꢋ ꢋꢌ ꢕꢋ ꢎꢌꢌ ꢎꢍꢋ ꢎꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢉ
ꢉ.ꢒꢐ ꢉ.ꢐ ꢉ.ꢔꢐ
ꢑ
ꢑ.ꢒꢐ ꢑ.ꢐ ꢑ.ꢔꢐ
ꢒ
SHDN ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢝꢜꢝꢋ ꢇꢋꢝ
ꢘꢋꢘꢌ ꢔꢌꢙ
ꢕꢐꢕꢉ ꢅꢑꢉ
Minimum On Time
vs Temperature
SHDN Pin Current
Active/Lockout Threshold
ꢎ.ꢖꢌ
ꢎ.ꢕꢔ
ꢎ.ꢕꢓ
ꢎ.ꢕꢖ
ꢎ.ꢕꢍ
ꢎ.ꢕꢌ
ꢎ.ꢍꢔ
ꢎ.ꢍꢓ
ꢎ.ꢍꢖ
ꢎ.ꢍꢍ
ꢎ.ꢍꢌ
ꢓꢉꢉ
ꢒꢑꢉ
ꢒꢉꢉ
ꢐꢑꢉ
ꢐꢉꢉ
ꢔꢑꢉ
ꢔꢉꢉ
ꢑꢉ
ꢓꢌꢌ
ꢗꢋꢌ
ꢗꢌꢌ
ꢍꢋꢌ
ꢍꢌꢌ
ꢒꢋꢌ
ꢒꢌꢌ
ꢋꢌ
ꢔꢐꢑꢖꢍ
ꢐꢑꢖꢍ
ꢗꢓꢉꢖꢍ
Rꢁꢈꢐꢂꢂꢁꢏꢘꢁꢘ ꢂꢎꢏꢎꢂꢅꢂ ꢐꢏ ꢀꢎꢂꢁ
SHDN Rꢘꢙꢘꢚꢒ
SHDN ꢛꢄꢑꢑꢘꢚꢒ
ꢂꢁꢄꢑꢅRꢁꢘ ꢂꢎꢏꢎꢂꢅꢂ ꢐꢏ ꢀꢎꢂꢁ
ꢉ
ꢌ
ꢉ
ꢑ
ꢔꢉ ꢔꢑ ꢐꢉ ꢐꢑ ꢒꢉ ꢒꢑ ꢓꢉ
SHDN ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢕꢑꢕꢉ ꢅꢔꢔ
ꢊꢋꢌ ꢊꢍꢋ
ꢌ
ꢍꢋ ꢋꢌ ꢗꢋ ꢎꢌꢌ ꢎꢍꢋ ꢎꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢊꢋꢌ ꢊꢍꢋ
ꢌ
ꢍꢋ ꢋꢌ ꢔꢋ ꢒꢌꢌ ꢒꢍꢋ ꢒꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢔꢋꢔꢌ ꢒꢎꢍ
ꢕꢋꢕꢌ ꢖꢒꢗ
Rev. B
5
For more information www.analog.com
LT8580
PIN FUNCTIONS
FBX (Pin 1): Positive and Negative Feedback Pin. For a
sequence. Drive below 1.21V to disable the chip. Drive
above 1.40V to activate the chip and restart the soft-start
sequence. Do not float this pin.
noninverting or inverting converter, tie a resistor from the
FBX pin to V
according to the following equations:
OUT
RT (Pin 6): Timing Resistor Pin. Adjusts the switching
frequency. Place a resistor from this pin to ground to set
the frequency to a fixed free running level. Do not float
this pin.
V
− 1.204V
(
)
OUT
R
R
=
=
; Noninverting Converter
FBX
FBX
83.3µA
+ 3mV
V
(
)
OUT
; Inverting Converter
83.3µA
SS(Pin7):Soft-StartPin.Placeasoft-startcapacitorhere.
Upon start-up, the SS pin will be charged by a (nominally)
280k resistor to about 2.1V.
VC (Pin 2): Error Amplifier Output Pin. Tie external com-
pensation network to this pin.
SYNC (Pin 8): To synchronize the switching frequency to
an outside clock, simply drive this pin with a clock. The
high voltage level of the clock needs to exceed 1.3V, and
the low level should be less 0.4V. Drive this pin to less
than 0.4V to revert to the internal free-running clock. See
theApplicationsInformationsectionformoreinformation.
V (Pin 3): Input Supply Pin. Must be locally bypassed.
IN
SW (Pin 4): Switch Pin. This is the collector of the internal
NPN Power switch. Minimize the metal trace area connec-
ted to this pin to minimize EMI.
SHDN (Pin 5): Shutdown Pin. In conjunction with the
UVLO (undervoltage lockout) circuit, this pin is used
to enable/disable the chip and restart the soft-start
GND (Exposed Pad Pin 9): Ground. Exposed pad must
be soldered directly to local ground plane.
BLOCK DIAGRAM
R
C
V
IN
C
C
C
IN
SS
C
7
2
50k
SS
VC
SHDN
5
–
+
DISCHARGE
DETECT
L1
1.3V
280k
D1
SW
UVLO
VC
I
SR2
R
SOFT-
START
4
V
OUT
COMPARATOR
LIMIT
SR1
S
Q2
Q
S
–
+
DRIVER
C1
V
IN
A3
R
Q
Q1
1.204V
REFERENCE
3
+
+
R
FBX
14.5k
A4
∑
0.02Ω
GND
A1
A2
–
–
SLOPE
COMPENSATION
FBX
9
1
+
–
÷N
FREQUENCY
FOLDBACK
ADJUSTABLE
OSCILLATOR
14.5k
SYNC
BLOCK
SYNC
RT
8
6
R
T
8580 BD
Rev. B
6
For more information www.analog.com
LT8580
OPERATION
TheLT8580usesaconstant-frequency,currentmodecon-
trol scheme to provide excellent line and load regulation.
Refer to the Block Diagram for the following description
of the part’s operation. At the start of each oscillator cycle,
theSRlatch(SR1)isset, whichturnsonthepowerswitch,
Q1. The switch current flows through the internal current
sense resistor, generating a voltage proportional to the
switch current. This voltage (amplified by A4) is added
to a stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A3. When this
voltage exceeds the level at the negative input of A3, the
SR latch is reset, turning off the power switch. The level
at the negative input of A3 (VC pin) is set by the error
amplifier A1 (or A2) and is simply an amplified version of
the difference between the feedback voltage (FBX pin) and
the reference voltage (1.204V or 3mV, depending on the
configuration). In this manner, the error amplifier sets the
correct peak current level to keep the output in regulation.
an inverting configuration, the FBX pin is pulled down to
3mV by the R
resistor connected from V
to FBX.
FBX
OUT
Amplifier A1 becomes inactive and amplifier A2 performs
the noninverting amplification from FBX to VC.
SEPIC Topology
As shown in Figure 1, the LT8580 can be configured as
a SEPIC (single-ended primary inductance converter).
This topology allows for the input to be higher, equal, or
lower than the desired output voltage. Output disconnect
is inherently built into the SEPIC topology, meaning no DC
path exists between the input and output. This is useful
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
Inverting Topology
The LT8580 can also work in a dual inductor inverting
topology,asshowninFigure2.Thepart’suniquefeedback
pin allows for the inverting topology to be built by simply
changing the connection of external components. This
solution results in very low output voltage ripple due to
the inductor L2 in series with the output. Abrupt changes
in output capacitor current are eliminated because the
output inductor delivers current to the output during both
the off-time and the on-time of the LT8580 switch.
The LT8580 has an FBX pin architecture that can be used
for either noninverting or inverting configurations. When
configured as a noninverting converter, the FBX pin is
pulled up to the internal bias voltage of 1.204V by the
R
FBX
resistor connected from V
to FBX. Amplifier A2
OUT
becomes inactive and amplifier A1 performs the invert-
ing amplification from FBX to VC. When the LT8580 is in
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•
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•
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SHDN
ꢕBꢗ
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Rꢅ
Rꢅ
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Figure 1. SEPIC Topology Allows for the Input to Span
the Output Voltage. Coupled or Uncoupled Inductors
Can Be Used. Follow Noted Phasing if Coupled
Figure 2. Dual Inductor Inverting Topology Results in
Low Output Ripple. Coupled or Uncoupled Inductors
Can Be Used. Follow Noted Phasing if Coupled
Rev. B
7
For more information www.analog.com
LT8580
OPERATION
Start-Up Operation
of 300mV to 920mV. This feature reduces the minimum
duty cycle that the part can achieve thus allowing better
control of the switch current during start-up. When the
FBXvoltageispulledoutsideofthisrange,theswitching
frequency returns to normal.
Several functions are provided to enable a very clean
start-up for the LT8580.
• First, the SHDN pin voltage is monitored by an internal
voltage reference to give a precise turn-on voltage level.
Anexternalresistor(orresistordivider)canbeconnected
from the input power supply to the SHDN pin to provide
a user-programmable undervoltage lockout function.
Current Limit and Thermal Shutdown Operation
The LT8580 has a current limit circuit not shown in the
BlockDiagram.Theswitchcurrentisconstantlymonitored
and not allowed to exceed the maximum switch current at
agivendutycycle(seetheElectricalCharacteristicstable).
If the switch current reaches this value, the SR latch (SR1)
is reset regardless of the state of the comparator (A1/
A2). Also, not shown in the Block Diagram is the thermal
shutdown circuit. If the temperature of the part exceeds
approximately165°C,theSR2latchissetregardlessofthe
state of the amplifier (A1/A2). When the part temperature
falls below approximately 160°C, a full soft-start cycle will
then be initiated. The current limit and thermal shutdown
circuits protect the power switch as well as the external
components connected to the LT8580.
• Second, the soft-start circuitry provides for a gradual
ramp-up of the switch current. When the part is brought
out of shutdown, the external SS capacitor is first
discharged (providing protection against SHDN pin
glitches and slow ramping), then an integrated 280k
resistor pulls the SS pin up to ~2.1V. By connecting an
external capacitor to the SS pin, the voltage ramp rate
on the pin can be set. Typical values for the soft-start
capacitor range from 100nF to 1µF.
• Finally,thefrequencyfoldbackcircuitreducestheswitch-
ing frequency when the FBX pin is in a nominal range
Rev. B
8
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Setting Output Voltage
For the SEPIC or dual inductor inverting topology (see
Figure 1 and Figure 2):
The output voltage is set by connecting a resistor (R
)
FBX
V + |V
|
from V
to the FBX pin. R
is determined from the
D
OUT
OUT
FBX
DC ≅
following equation:
V + |V | + V − V
IN
D
OUT
CESAT
|V − V
|
FBX
OUT
The LT8580 can be used in configurations where the duty
cycle is higher than DC , but it must be operated in the
R
=
FBX
83.3µA
MAX
discontinuous conduction mode so that the effective duty
where V is 1.204V (typical) for noninverting topologies
FBX
cycle is reduced.
(i.e., boost and SEPIC regulators) and 3mV (typical) for
inverting topologies (see the Electrical Characteristics).
Inductor Selection
Power Switch Duty Cycle
General Guidelines: The high frequency operation of the
LT8580allowsfortheuseofsmallsurfacemountinductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. To
improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low
In order to maintain loop stability and deliver adequate
current to the load, the power NPN (Q1 in the Block Dia-
gram) cannot remain “on” for 100% of each clock cycle.
The maximum allowable duty cycle is given by:
2
DCR (copper wire resistance) to reduce I R losses, and
(T − Min Off Time)
P
DC
=
• 100%
MAX
must be able to handle the peak inductor current without
saturating. Note that in some applications, the current
handling requirements of the inductor can be lower, such
as in the SEPIC topology, where each inductor only carries
a fraction of the total switch current. Multilayer or chip
inductors usually do not have enough core area to sup-
port peak inductor currents in the 1A to 2A range. To
minimize radiated noise, use a toroidal or shielded induc-
tor. Note that the inductance of shielded types will drop
more as current increases, and will saturate more easily.
See Table 1 for a list of inductor manufacturers. Thorough
lab evaluation is recommended to verify that the following
guidelines properly suit the final application.
T
P
where T is the clock period and Min Off Time (found in
P
the Electrical Characteristics) is typically 100ns.
The application should be designed so that the operating
duty cycle does not exceed DC
.
MAX
The minimum allowable duty cycle is given by:
Min On Time
DC
=
• 100%
MIN
T
P
where T is the clock period and Minimum On Time is as
P
shown in the Typical Performance Characteristics.
Table 1. Inductor Manufacturers
The application should be designed so that the operating
Coilcraft
XAL5050, MSD7342, MSS7341 and www.coilcraft.com
LPS4018 Series
duty cycle is at least DC
.
MIN
Duty cycle equations for several common topologies are
Coiltronics DR, DRQ, LD and CD Series
www.coiltronics.com
www.sumida.com
given below, where V is the diode forward voltage drop
Sumida
CDRH8D58/LD, CDRH64B, and
CDRH70D430MN Series
D
and V
is typically 400mV at 0.75A.
CESAT
Würth
WE-PD, WE-DD, WE-TPC,
WE-LHMI and WE-LQS Series
www.we-online.com
For the boost topology:
− V + V
V
IN
D
OUT
DC ≅
Minimum Inductance: Although there can be a trade-off
with efficiency, it is often desirable to minimize board
space by choosing smaller inductors. When choosing
V
+ V − V
D
CESAT
OUT
Rev. B
9
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
an inductor, there are two conditions that limit the mini-
mum inductance: (1) providing adequate load current,
and (2) avoiding subharmonic oscillation. Choose an
inductance that is high enough to meet both of these
requirements.
AvoidingSubharmonicOscillations:TheLT8580’sinternal
slopecompensationcircuitcanpreventsubharmonicoscil-
lations that can occur when the duty cycle is greater than
50%, provided that the inductance exceeds a minimum
value. In applications that operate with duty cycles greater
than 50%, the inductance must be at least:
Adequate Load Current : Small value inductors result in
increased ripple currents and thus, due to the limited peak
switch current, decrease the average current that can be
V
2 DC − 1
1− DC
IN
L
>
MIN
1.25 • (DC − 300ns • f) • f
provided to a load (I ). In order to provide adequate
OUT
for boost topologies (see Figure 15)
load current, L should be at least:
L
L
= L1
MIN
= L1 = L2 for coupled dual inductor topologies
(see Figure 16 and Figure 17)
DC • V
MIN
IN
L
>
BOOST
⎛
⎞
⎟
⎠
|V | • I
OUT
OUT
• h
2(f) I
−
⎜
LIM
||
L
= L1 L2 for uncoupled dual inductor topologies
V
MIN
⎝
IN
(see Figure 16 and Figure 17)
for boost, topologies, or:
DC • V
Maximum Inductance: Excessive inductance can reduce
currentrippletolevelsthataredifficultforthecurrentcom-
parator (A3 in the Block Diagram) to cleanly discriminate,
thus causing duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
IN
L
>
DUAL
⎛
⎞
⎟
⎠
V
• I
OUT OUT
2(f) I
−
− I
⎜
LIM
OUT
V
• h
⎝
IN
for the SEPIC and inverting topologies.
where:
V − V
DC
f
IN
CESAT
L
=
•
MAX
I
MIN-RIPPLE
L
L
= L1 for boost topologies (see Figure 15)
BOOST
where
= L1 = L2 for coupled dual inductor topologies
(see Figure 16 and Figure 17)
DUAL
for boost topologies (see Figure 15)
= L1
L
L
MIN
= L1 = L2 for coupled dual inductor topologies
(see Figure 16 and Figure 17)
MIN
L
= L1||L2 for uncoupled dual inductor topologies
DUAL
(see Figure 16 and Figure 17)
||
L
= L1 L2 for uncoupled dual inductor topologies
MIN
DC = switch duty cycle (see previous section)
(see Figure 16 and Figure 17)
I
= switch current limit, typically about 1.2A at 50%
LIM
I
= typically 80mA
MIN(RIPPLE)
dutycycle(seetheTypicalPerformanceCharacteristics
Current Rating: Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss. In steady state, the
peakinputinductorcurrent(continuousconductionmode
only) is given by:
section).
h=powerconversionefficiency(typically85%forboost
and 83% for dual inductor topologies at high currents).
f = switching frequency
I
= maximum load current
OUT
|V
• I
|
V • DC
IN
OUT OUT
I
=
+
L1-PEAK
Negative values of L indicate that the output load current
OUT
LT8580.
V
• h
2 • L1• f
IN
I
exceeds the switch current limit capability of the
fortheboost,SEPICanddualinductorinvertingtopologies.
Rev. B
10
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Fordualdualinductortopologies,thepeakoutputinductor
current is given by:
Table 2 shows a list of several ceramic capacitor manufac-
turers. Consultthemanufacturersfordetailedinformation
on their entire selection of ceramic parts.
V
• 1− DC
(
)
OUT
I
= I
+
Table 2. Ceramic Capacitor Manufacturers
L2-PEAK
OUT
2 • L2 • f
For the dual inductor topologies, the total peak current is:
Kemet
www.kemet.com
www.murata.com
www.t-yuden.com
www.tdk.com
Murata
Taiyo Yuden
TDK
⎡
⎤
V
V • DC
IN
OUT
I
= I
1+
+
L-PEAK
OUT
⎢
⎥
h • V
2 • L • f
⎣
⎦
IN
Compensation—Adjustment
Note:Peakinductorcurrentislimitedbytheswitchcurrent
limit. Refer to the Electrical Characteristics table and to
the Switch Current Limit vs Duty Cycle plot in the Typical
Performance Characteristics.
To compensate the feedback loop of the LT8580, a series
resistor-capacitornetworkinparallelwithasinglecapacitor
should be connected from the VC pin to GND. For most
applications, the series capacitor should be in the range
of 470pF to 2.2nF with 1nF being a good starting value.
The parallel capacitor should range in value from 10pF to
100pF with 47pF a good starting value. The compensation
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
beusedattheoutputtominimizetheoutputripplevoltage.
Multilayer ceramic capacitors are an excellent choice, as
they have an extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
these materials retain their capacitance over wider voltage
andtemperatureranges.A0.47µFto10µFoutputcapacitor
is sufficient for most applications. Always use a capacitor
with a sufficient voltage rating. Many ceramic capacitors,
particularly 0805 or 0603 case sizes, have greatly reduced
capacitance at the desired output voltage. Solid tantalum
or OS-CON capacitors can be used, but they will occupy
more board area than a ceramic and will have a higher
ESR with greater output ripple.
resistor, R , is usually in the range of 5k to 50k. A good
C
technique to compensate a new application is to use a
100kΩ potentiometer in place of series resistor R . With
C
the series capacitor and parallel capacitor at 1nF and 47pF
respectively, adjust the potentiometer while observing
the transient response and the optimum value for R can
C
be found. Figure 3 (3a to 3c) illustrates this process for
the circuit of Figure 4 with a load current stepped be-
tween 60mA and 160mA. Figure 3a shows the transient
response with R equal to 2k. The phase margin is poor,
C
as evidenced by the excessive ringing in the output
voltage and inductor current. In Figure 3b, the value of
R is increased to 3k, which results in a more damped
C
Ceramic capacitors also make a good choice for the input
decoupling capacitor, which should be placed as closely
response.Figure3cshowstheresultswhenR isincreased
C
further to 6.04k. The transient response is nicely damped
as possible to the V pin of the LT8580 as well as to the
IN
and the compensation procedure is complete.
inductor connected to the input of the power path. If it is
not possible to optimally place a single input capacitor,
Compensation—Theory
then use one at the V pin of the chip (C ) and one at
IN
VIN
Like all other current mode switching regulators, the
LT8580 needs to be compensated for stable and efficient
operation. Two feedback loops are used in the LT8580—
a fast current loop which does not require compensation,
and a slower voltage loop which does. Standard bode plot
analysis can be used to understand and adjust the voltage
feedback loop.
the input of the power path (C
). See equations in
PWR
Table 4, Table 5 and Table 6 for sizing information. A 1µF
to2.2µFinputcapacitorissufficientformostapplications.
Rev. B
11
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
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(3a) Transient Response Shows Excessive Ringing
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(3c) Transient Response Is Well Damped
Figure 3. Transient Response
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Figure 4. 1.5MHz, 5V to 12V Boost Converter
Rev. B
12
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
As with any feedback loop, identifying the gain and phase
contribution of the various elements in the loop is critical.
Figure5showsthekeyequivalentelementsofaboostcon-
verter. Because of the fast current control loop, the power
stage of the IC, inductor and diode have been replaced by
a combination of the equivalent transconductance ampli-
From Figure 5, the DC gain, poles and zeros can be cal-
culated as follows:
2
Output Pole: P1=
2 • π • R • C
L
OUT
1
Error Amp Pole: P2 =
2 • π • R +R • C
[
]
fier g and the current controlled current source which
O
C
C
mp
converts I to (hV /V ) • I . g acts as a current
VIN
IN OUT
VIN mp
1
Error Amp Zero: Z1=
DC Gain:
source where the peak input current, I , is proportional
VIN
2 • π • R • C
C
C
to the VC voltage. h is the efficiency of the switching
regulator, and is typically about 85%.
(Breaking Loop at FBX Pin)
Notethatthemaximumoutputcurrentsofg andg are
mp
ma
∂V
∂I
∂V
∂V
finite.Thelimitsforg areintheElectricalCharacteristics
C
VIN
OUT
VIN
FBX
mp
A
= A (0) =
•
•
•
=
DC
ma
OL
∂V
∂V
∂I
•
∂V
OUT
section(switchcurrentlimit), andg isnominallylimited
FBX
C
ma
to about +15µA and –17µA.
⎛
⎞
⎟
⎠
V
R
0.5R2
R1+ 0.5R2
IN
L
g
• R • g • h •
•
⎜
⎝
(
)
0
mp
V
2
OUT
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ꢆꢑꢏ
ꢊꢒ
V • R
IN
L
2
ꢟ.ꢇꢦꢧꢛ
4 • π • V
• L
RꢋꢕꢋRꢋꢌꢅꢋ
Rꢟ
OUT
ꢁ
ꢀ
f
ꢛ
ꢅ
S
ꢂ
High Frequency Pole: P3 >
ꢃꢄ
Rꢇ
Rꢇ
ꢕBꢝ
3
R
R
ꢆ
ꢅ
ꢅ
ꢣꢤꢣꢦ ꢕꢦꢤ
ꢕ
1
ꢅ
ꢅ
Phase Lead Zero: Z4 =
2 • π • R1• C
1
PL
ꢅ ꢈ ꢅꢆꢉꢊꢋꢌꢍꢎꢏꢐꢆꢌ ꢅꢎꢊꢎꢅꢐꢏꢆR
ꢅ
Phase Lead Pole: P4 =
Error Amp Filter Pole:
ꢅ
ꢅ
ꢈ ꢆꢑꢏꢊꢑꢏ ꢅꢎꢊꢎꢅꢐꢏꢆR
ꢈ ꢊꢓꢎꢍꢋ ꢒꢋꢎꢔ ꢅꢎꢊꢎꢅꢐꢏꢆR
ꢅ ꢈ ꢓꢐꢖꢓ ꢕRꢋꢗꢑꢋꢌꢅꢘ ꢕꢐꢒꢏꢋR ꢅꢎꢊꢎꢅꢐꢏꢆR
ꢈ ꢏRꢎꢌꢍꢅꢆꢌꢔꢑꢅꢏꢎꢌꢅꢋ ꢎꢉꢊꢒꢐꢕꢐꢋR ꢐꢌꢍꢐꢔꢋ ꢐꢅ
ꢈ ꢊꢆꢚꢋR ꢍꢏꢎꢖꢋ ꢏRꢎꢌꢍꢅꢆꢌꢔꢑꢅꢏꢎꢌꢅꢋ ꢎꢉꢊꢒꢐꢕꢐꢋR
R ꢈ ꢅꢆꢉꢊꢋꢌꢍꢎꢏꢐꢆꢌ RꢋꢍꢐꢍꢏꢆR
R ꢈ ꢆꢑꢏꢊꢑꢏ Rꢋꢍꢐꢍꢏꢎꢌꢅꢋ ꢔꢋꢕꢐꢌꢋꢔ ꢎꢍ ꢛ
ꢒ
R2
ꢆꢑꢏ
R1•
R1+
ꢊꢒ
2
R2
2
2 • π •
• C
PL
ꢕ
ꢂ
ꢂ
ꢃꢄ
ꢃꢙ
ꢅ
ꢔꢐꢛꢐꢔꢋꢔ Bꢘ ꢐ
ꢒꢆꢎꢔꢜꢉꢎꢝꢞ
ꢆꢑꢏ
R ꢈ ꢆꢑꢏꢊꢑꢏ Rꢋꢍꢐꢍꢏꢎꢌꢅꢋ ꢆꢕ ꢂ
ꢆ
ꢃꢄ
Rꢟꢠ Rꢇꢈ ꢕꢋꢋꢔBꢎꢅꢡ RꢋꢍꢐꢍꢏꢆR ꢔꢐꢛꢐꢔꢋR ꢌꢋꢏꢚꢆRꢡ
1
C
C
10
P5 =
, C <
R
ꢋꢍR
ꢈ ꢆꢑꢏꢊꢑꢏ ꢅꢎꢊꢎꢅꢐꢏꢆR ꢋꢍR
F
R • R
C
O
O
ηꢈ ꢅꢆꢌꢛꢋRꢏꢋR ꢋꢕꢕꢐꢅꢐꢋꢌꢅꢘ ꢜꢢꢣꢤꢥ ꢎꢏ ꢓꢐꢖꢓꢋR ꢅꢑRRꢋꢌꢏꢍꢞ
2 • π •
• C
F
R + R
C
Figure 5. Boost Converter Equivalent Model
The current mode zero (Z3) is a right-half plane zero
which can be an issue in feedback control design, but is
manageable with proper external component selection.
Rev. B
13
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Using the circuit in Figure 4 as an example, Table 3 shows
the parameters used to generate the bode plot shown in
Figure 6.
In Figure 6, the phase is –126° when the gain reaches 0dB
giving a phase margin of 54°. The crossover frequency is
14kHz, which is more than three times lower than the fre-
quencyoftheRHPzerotoachieveadequatephasemargin.
ꢋꢚꢌ
ꢋꢖꢌ
ꢋꢌꢌ
ꢕꢌ
ꢌ
ꢛꢚꢙ
Diode Selection
ꢒꢈꢏꢓꢁ
ꢛꢝꢌ
Schottkydiodes, withtheirlowforward-voltagedropsand
fast switching speeds, are recommended for use with the
ꢛꢋꢜꢙ
ꢛꢋꢕꢌ
ꢛꢖꢖꢙ
ꢛꢖꢞꢌ
ꢛꢜꢋꢙ
ꢛꢜꢍꢌ
LT8580. For applications where V (see Tables 4, 5 and
ꢍꢌ
R
6) < 40V, the Diodes, Inc. SBR1V40LP is a good choice.
ꢙꢚ° ꢏꢟ
ꢚꢌ
ꢎꢏꢐꢄ
ꢋꢌꢌ
ꢋꢚꢗꢈꢉ
Where V > 40V, the Diodes Inc. DFLS1100 works well.
R
ꢖꢌ
These diodes are rated to handle an average forward
ꢌ
current of 1A.
ꢛꢖꢌ
ꢋꢌ
ꢋꢗ
ꢋꢌꢗ
ꢋꢌꢌꢗ
ꢋꢘ
Oscillator
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢕꢙꢕꢌ ꢀꢌꢍ
The operating frequency of the LT8580 can be set by the
internal free-running oscillator. When the SYNC pin is
driven low (< 0.4V), the frequency of operation is set by a
Figure 6. Bode Plot for Example Boost Converter
resistor from R to ground. An internally trimmed timing
T
Table 3. Bode Plot Parameters
capacitor resides inside the IC. The oscillator frequency
is calculated using the following formula:
PARAMETER
VALUE
60
UNITS
W
COMMENT
Application Specific
Application Specific
Application Specific
Not Adjustable
Adjustable
R
L
C
4.7
10
µF
OUT
85.5
f
=
OSC
R
R
mW
kW
pF
ESR
O
(R + 1)
T
300
3300
47
where f
is in MHz and R is in kΩ. Conversely, R
T T
OSC
C
C
C
C
(in kΩ) can be calculated from the desired frequency
(in MHz) using:
pF
Optional/Adjustable
Optional/Adjustable
Adjustable
F
0
pF
PL
R
C
6.04
130
14.6
12
kW
kW
kW
V
85.5
R =
− 1
T
R1
R2
Adjustable
f
OSC
Not Adjustable
Application Specific
Application Specific
Not Adjustable
Not Adjustable
Application Specific
Adjustable
V
OUT
V
IN
Clock Synchronization
5
V
TheoperatingfrequencyoftheLT8580canbesynchronized
to an external clock source. To synchronize to the external
source, simply provide a digital clock signal into the SYNC
pin. The LT8580 will operate at the SYNC clock frequency.
The LT8580 will revert to the internal free-running oscilla-
tor clock after SYNC is driven low for a few free-running
clock periods.
g
ma
g
mp
L
200
7
µmho
mho
µH
15
f
S
1.5
MHz
Rev. B
14
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Driving SYNC high for an extended period of time effec-
tively stops the operating clock and prevents latch SR1
from becoming set (see the Block Diagram). As a result,
the switching operation of the LT8580 will stop.
This capacitor is slowly charged to ~2.1V by an internal
280k resistor once the part is activated. SS pin voltages
below ~1.1V reduce the internal current limit. Thus, the
gradualrampingoftheSSvoltagealsograduallyincreases
the current limit as the capacitor charges. This, in turn,
allows the output capacitor to charge gradually toward its
final value while limiting the start-up current.
The duty cycle of the SYNC signal must be between 35%
and 65% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
In the event of a commanded shutdown or lockout (SHDN
pin), internal undervoltage lockout (UVLO) or a thermal
lockout,thesoft-startcapacitorisautomaticallydischarged
to ~200mV before charging resumes, thus assuring that
the soft-start occurs after every reactivation of the chip.
(1) SYNC may not toggle outside the frequency range of
200kHz to 1.5MHz unless it is stopped low to enable
the free-running oscillator.
(2) The SYNC frequency can always be higher than the
free-running oscillator frequency, f , but should not
OSC
be less than 25% below f
.
Shutdown
OSC
The SHDN pin is used to enable or disable the chip. For
most applications, SHDN can be driven by a digital logic
source. Voltages above 1.4V enable normal active op-
eration. Voltages below 300mV will shutdown the chip,
resulting in extremely low quiescent current.
Operating Frequency Selection
There are several considerations in selecting the operat-
ing frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz, and in
thatcase, a1.5MHzswitchingconverterfrequencymaybe
employed. The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade-off is efficiency, since the switching losses due
to NPN base charge (see Thermal Calculations), Schottky
diode charge, and other capacitive loss terms increase
proportionally with frequency.
While the SHDN voltage transitions through the lockout
voltagerange(0.3Vto1.21V)thepowerswitchisdisabled
and the SR2 latch is set (see the Block Diagram). This
causesthesoft-startcapacitortobegindischarging,which
continues until the capacitor is discharged and active op-
eration is enabled. Although the power switch is disabled,
SHDN voltages in the lockout range do not necessarily
reduce quiescent current until the SHDN voltage is near
or below the shutdown threshold.
Also note that SHDN can be driven above V or V
as
IN
OUT
long as the SHDN voltage is limited to less than 40V.
Soft-Start
ꢇꢌꢄꢆꢑꢅ
ꢀꢈꢊRꢒꢇꢋ ꢊꢓꢅRꢇꢄꢆꢊꢈꢍ
TheLT8580containsasoft-startcircuittolimitpeakswitch
currents during start-up. High start-up current is inherent
in switching regulators in general since the feedback loop
is saturated due to V
regulator tries to charge the output capacitor as quickly as
possible, which results in large peak currents.
ꢘ.ꢛꢚꢑ
ꢀꢁꢂꢃꢄꢅRꢅꢃꢆꢃ ꢇꢈꢉ ꢄꢊꢋꢅRꢇꢈꢌꢅꢍ
ꢘ.ꢙꢘꢑ
ꢋꢊꢌꢔꢊꢎꢄ
being far from its final value. The
OUT
ꢀꢓꢊꢏꢅR ꢃꢏꢆꢄꢌꢁ ꢊꢕ ꢖ
ꢃꢃ ꢌꢇꢓꢇꢌꢆꢄꢊR ꢉꢆꢃꢌꢁꢇRꢗꢅꢉꢍ
ꢚ.ꢜꢑ
ꢃꢁꢎꢄꢉꢊꢏꢈ
ꢀꢋꢊꢏ ꢐꢎꢆꢅꢃꢌꢅꢈꢄ ꢌꢎRRꢅꢈꢄꢍ
The start-up current can be limited by connecting an
external capacitor (typically 100nF to 1µF) to the SS pin.
ꢚ.ꢚꢑ
ꢝꢞꢝꢚ ꢕꢚꢟ
Figure 7. Chip States vs SHDN Voltage
Rev. B
15
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Configurable Undervoltage Lockout
For example, to disable the LT8580 for V voltages below
IN
3.5V using the single resistor configuration, choose:
Figure 8 shows how to configure an undervoltage lock-
out (UVLO) for the LT8580. Typically, UVLO is used in
situations where the input supply is current-limited, has
a relatively high source resistance, or ramps up/down
slowly. A switching regulator draws constant power from
the source, so source current increases as source voltage
drops. This looks like a negative resistance load to the
source and can cause the source to current-limit or latch
low under low source voltage conditions. UVLO prevents
the regulator from operating at source voltages where
these problems might occur.
3.5V − 1.27V
R
=
= 187k
UVLO1
⎛
⎜
⎝
⎞
⎟
⎠
1.27V
∞
+ 12µA
To activate the LT8580 for V voltages greater than
IN
4.5V using the double resistor configuration, choose
R
= 10k and:
UVLO2
4.5V − 1.31V
R
=
= 22.1k
UVLO1
⎛
⎜
⎝
⎞
⎟
⎠
1.31V
10k
+ 12µA
The shutdown pin comparator has voltage hysteresis with
typicalthresholdsof1.31V(rising)and1.27V(falling). Re-
Internal Undervoltage Lockout
The LT8580 monitors the V supply voltage in case V
sistorR
isoptional.R
canbeincludedtoreduce
UVLO2
UVLO2
IN
IN
the overall UVLO voltage variation caused by variations
drops below a minimum operating level (typically about
2.35V). When V is detected low, the power switch is
in SHDN pin current (see the Electrical Characteristics).
A good choice for R
value for R
of the following:
IN
is ≤10k 1%. After choosing a
can be determined from either
UVLO2
UVLO2 UVLO1
deactivated, and while sufficient V voltage persists, the
IN
, R
soft-start capacitor is discharged. After V is detected
IN
high, the power switch will be reactivated and the soft-
+
V
− 1.31V
start capacitor will begin charging.
IN
R
=
=
UVLO1
⎛
⎜
⎝
⎞
⎟
⎠
1.31V
+ 12µA
Thermal Considerations
R
UVLO2
For the LT8580 to deliver its full output power, it is impera-
tive that a good thermal path be provided to dissipate the
heat generated within the package. This is accomplished
bytakingadvantageofthethermalpadontheundersideof
the IC. It is recommended that multiple vias in the printed
circuit board be used to conduct heat away from the IC
and into a copper plane with as much area as possible.
or
−
V
− 1.27V
⎞
⎟
⎠
IN
R
UVLO1
⎛
⎜
⎝
1.27V
+ 12µA
R
UVLO2
–
+
where V and V are the V voltages when rising or
falling, respectively.
IN
IN
IN
ꢁ
ꢈꢉ
ꢁ
ꢈꢉ
ꢊꢒꢇꢈꢁꢓꢔ
ꢂꢃꢒꢕꢃꢀꢇ
ꢌ.ꢍꢁ
ꢙ
ꢚ
R
ꢀꢁꢂꢃꢌ
SHDN
ꢌꢄꢘꢊ
ꢊꢇ ꢌ.ꢍꢁ
R
ꢀꢁꢂꢃꢄ
ꢅꢃꢆꢇꢈꢃꢉꢊꢂꢋ
ꢖꢉꢗ
ꢎꢏꢎꢐ ꢑꢐꢎ
Figure 8. Configurable UVLO
Rev. B
16
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Thermal Lockout
P
P
P
P
= 117mW
= 169mW
= 44mW
= 30mW
SW
If the die temperature reaches approximately 165°C, the
part will go into thermal lockout, the power switch will be
turned off and the soft-start capacitor will be discharged.
The part will be enabled again when the die temperature
has dropped by ~5°C (nominal).
BAC
BDC
INP
Total LT8580 power dissipation (P ) = 361mW
TOT
ThermalresistancefortheLT8580isinfluencedbythepres-
ence of internal, topside or backside planes. To calculate
die temperature, use the appropriate thermal resistance
number and add in worst-case ambient temperature:
Thermal Calculations
Power dissipation in the LT8580 chip comes from four
primary sources: switch I R loss, NPN base drive (AC),
NPN base drive (DC), and additional input current. The
following formulas can be used to approximate the power
losses. These formulas assume continuous mode opera-
tion, so they should not be used for calculating efficiency
in discontinuous mode or at light load currents.
2
T = T + θ • P
TOT
J
A
JA
whereT =junctiontemperature,T =ambienttemperature,
J
A
and θ is the thermal resistance from the silicon junction
JA
to the ambient air.
V
• I
OUT OUT
The published θ value is 43°C/W for the 3mm × 3mm
JA
Average Input Current: I
=
IN
V • h
DFN package and 35°C/W to 40°C/W for the MSOP ex-
IN
posed pad package. In practice, lower θ values can be
JA
Switch Conduction Loss: P = (DC)(I )(V
)
IN
SW
SW
obtained if the board layout uses ground as a heat sink.
For instance, thermal resistances of 34.7°C/W for the
DFN package and 22.5°C/W for the MSOP package were
obtained on a board designed with large ground planes.
Base Drive Loss (AC): P
= 20ns(I )(V
)(f)
IN
BAC
OUT
(V )(I )(DC)
IN IN
Base Drive Loss (DC): P
=
BDC
40
V Ramp Rate
IN
Input Power Loss: P = 6mA (V )
INP
IN
While initially powering a switching converter application,
theV ramprateshouldbelimited.HighV rampratescan
where:
IN
IN
causeexcessiveinrushcurrentsinthepassivecomponents
of the converter. This can lead to current and/or voltage
overstress and may damage the passive components or
the chip. Ramp rates less than 500mV/µs, depending on
componentparameters,willgenerallypreventtheseissues.
Also,becarefultoavoidhot-plugging.Hot-pluggingoccurs
when an active voltage supply is “instantly” connected or
switchedtotheinputoftheconverter.Hot-pluggingresults
in very fast input ramp rates and is not recommended.
Finally, for more information, refer to Linear application
note AN88, which discusses voltage overstress that can
occurwhenaninductivesourceimpedanceishot-plugged
to an input pin bypassed by ceramic capacitors.
V
= switch on voltage (see Typical Performance
SW
Characteristics for Switch Saturation Voltage)
DC = duty cycle (see the Power Switch Duty Cycle sec-
tion for formulas)
h = power conversion efficiency (typically 85% at high
currents)
Example: boost configuration, V = 5V, V
OUT
= 12V,
IN
OUT
I
= 0.2A, f = 1.25MHz, V = 0.5V:
D
I = 0.56A
IN
DC = 62.0%
Rev. B
17
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Layout Hints
theboardreducesdietemperatureandincreasesthepower
capability of the LT8580. Provide as much copper area as
possible around this pad. Adding multiple feedthroughs
aroundthepadtothegroundplanewillalsohelp.Figure10
and Figure 11 show the recommended component place-
mentfortheboostandSEPICconfigurations,respectively.
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermal and noise performance. One will not get adver-
tised performance with a careless layout. For maximum
efficiency, switch rise and fall times are typically in the
10ns to 20ns range. To prevent noise, both radiated and
conducted,thehighspeedswitchingcurrentpath,shownin
Figure 9, must be kept as short as possible. This is imple-
mented in the suggested layout of a boost configuration in
Figure10.Shorteningthispathwillalsoreducetheparasitic
trace inductance. At switch-off, this parasitic inductance
produces a flyback spike across the LT8580 switch. When
operatingathighercurrentsandoutputvoltages,withpoor
layout,thisspikecangeneratevoltagesacrosstheLT8580
that may exceed its absolute maximum rating. A ground
plane should also be used under the switcher circuitry to
prevent interplane coupling and overall noise.
Layout Hints for Inverting Topology
Figure12showsrecommendedcomponentplacementfor
the dual inductor inverting topology. Input bypass capaci-
tor, C1, should be placed close to the LT8580, as shown.
The load should connect directly to the output capacitor,
C2, for best load regulation. The local ground may be tied
into the system ground plane at the C3 ground terminal.
The cut ground copper at D1’s cathode is essential to
obtain low noise. This important layout issue arises due
to the chopped nature of the currents flowing in Q1 and
D1. If they are both tied directly to the ground plane before
being combined, switching noise will be introduced into
the ground plane. It is almost impossible to get rid of this
noise, once present in the ground plane. The solution
is to tie D1’s cathode to the ground pin of the LT8580
before the combined currents are dumped in the ground
plane as drawn in Figure 2, Figure 13 and Figure 14. This
single layout technique can virtually eliminate high
frequency “spike” noise, so often present on switching
regulator outputs.
The VC and FBX components should be kept as far away
as practical from the switch node. The ground for these
components should be separated from the switch cur-
rent path. Failure to do so can result in poor stability or
subharmonic oscillation.
Board layout also has a significant effect on thermal re-
sistance. The exposed package ground pad is the copper
platethatrunsundertheLT8580die.Thisisagoodthermal
path for heat out of the package. Soldering the pad onto
DIFFERENCES FROM LT3580
ꢉꢊ
LT8580 is very similar to LT3580. However, LT8580 does
deviate from LT3580 in a few areas:
ꢏꢊ
ꢐꢊ
ꢅ
ꢆꢇꢈ
• 65V, 1A switch
ꢋꢌ
ꢉꢈꢀꢁꢀꢂ
• 40V V and SHDN absolute maximum rating
IN
ꢓꢒꢍꢓ
ꢃRꢔꢕꢇꢔꢎꢐꢖ
ꢋꢌꢒꢈꢐꢓꢒꢎꢍ
ꢗꢘꢈꢓ
ꢅ
ꢒꢎ
ꢐꢑ ꢉꢆꢘꢏ
• FB renamed to FBX
• 5V FBX absolute maximum rating
ꢍꢎꢏ
ꢀꢁꢀꢂ ꢃꢂꢄ
Figure 9. High Speed “Chopped” Switching
Path for Boost Topology
Rev. B
18
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
ꢗꢊꢔ
ꢗꢊꢎ
ꢑꢖꢊꢕ
ꢄ
ꢐ
ꢏ
ꢎ
ꢀ
ꢌ
ꢋ
ꢁ
ꢍ
ꢕꢄ
ꢔꢖꢊꢋ
ꢄ
ꢌ
ꢓ
ꢒ
ꢀ
ꢐ
ꢏ
ꢁ
ꢑ
ꢅ
ꢉꢊ
ꢋꢄ
SHDN
ꢅ
ꢉꢊ
ꢓꢄ
ꢓꢐ
SHDN
ꢑꢒ
ꢍꢄ
ꢔꢕ
ꢕꢐ
ꢅꢉꢘꢔ ꢈꢆ ꢗRꢆꢇꢊꢎ
ꢙꢍꢘꢊꢚ RꢚꢛꢇꢉRꢚꢎ
ꢈꢆ ꢉꢜꢙRꢆꢅꢚ
ꢎꢄ
ꢋꢌ
ꢅꢉꢘꢑ ꢈꢆ ꢗRꢆꢇꢊꢔ
ꢙꢓꢘꢊꢚ RꢚꢛꢇꢉRꢚꢔ
ꢈꢆ ꢉꢜꢙRꢆꢅꢚ
ꢔꢄ
ꢕꢏ
ꢈꢝꢚRꢜꢘꢍ
ꢙꢚRꢃꢆRꢜꢘꢊꢋꢚ
ꢀꢁꢀꢂ ꢃꢄꢂ
ꢈꢝꢚRꢜꢘꢓ
ꢅ
ꢆꢇꢈ
ꢙꢚRꢃꢆRꢜꢘꢊꢕꢚ
ꢀꢁꢀꢂ ꢃꢄꢄ
ꢅ
ꢆꢇꢈ
Figure 10. Suggested Component Placement for Boost Topology
(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
Figure 11. Suggested Component Placement for SEPIC Topology
(Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
ꢗꢋꢔ
ꢑꢖꢋꢓ
ꢄ
ꢅ
ꢐ
ꢏ
ꢀ
ꢎ
ꢓꢄ
ꢍ
ꢆ
ꢊꢋ
ꢌ
SHDN
ꢁ
ꢕꢄ
ꢑꢒ
ꢓꢅ
ꢔꢄ
ꢕꢅ
ꢆꢊꢘꢑ ꢉꢇ ꢗRꢇꢈꢋꢔ
ꢙꢕꢘꢋꢚ RꢚꢛꢈꢊRꢚꢔ
ꢉꢇ ꢊꢜꢙRꢇꢆꢚ
ꢓꢐ
ꢉꢝꢚRꢜꢘꢕ
ꢙꢚRꢃꢇRꢜꢘꢋꢓꢚ
ꢀꢁꢀꢂ ꢃꢄꢅ
ꢆ
ꢇꢈꢉ
Figure 12. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).
Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground Plane
for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance
Rev. B
19
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
ꢇ
ꢅꢆꢇ ꢀ ꢇ ꢍ
ꢈꢉ ꢊꢋꢌ
ꢄꢙꢎꢘꢌ
ꢄꢃ
ꢁꢂ
ꢁꢃ
ꢎꢏ
ꢎꢏꢐ
ꢇ
ꢈꢉ
ꢅꢇ
ꢊꢋꢌ
ꢑꢂ
ꢒꢂ
ꢀ
ꢄꢂ
ꢄꢗ
R
ꢁꢊꢘꢑ
ꢀ
ꢓꢔꢓꢕ ꢖꢂꢗ
Figure 13. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt
ꢅ
ꢀ ꢅ ꢀ ꢅ
ꢅ
ꢋ
ꢆꢇ
ꢈꢉꢊ
ꢋ
ꢄꢃ
ꢁꢂ
ꢁꢃ
ꢌꢍ
ꢌꢍꢎ
ꢅ
ꢆꢇ
ꢒꢅ
ꢈꢉꢊ
ꢋꢂ
ꢏꢂ
ꢀ
ꢄꢂ
ꢄꢐ
R
ꢁꢈꢑꢋ
ꢀ
ꢓꢔꢓꢕ ꢖꢂꢗ
Figure 14. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt
Rev. B
20
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
BOOST CONVERTER COMPONENT SELECTION
Table 4. Boost Design Equations
PARAMETERS/EQUATIONS
ꢎꢉ
ꢉꢏꢆꢐ
ꢑꢉ
Pick V , V , and f
to calculate equations below
Step 1:
Inputs
IN OUT
OSC
ꢈ
ꢁꢂꢃ
ꢈ
ꢕꢖ
ꢉꢊꢈ
ꢏꢈ
ꢊꢋꢋꢌꢍ
Step 2:
DC
V
– V
+ 0.5 V
ꢉꢋꢔ
OUT
IN(MIN)
DC
DC
=
MAX
MIN
=
V
+ 0.5 V – 0.4 V
OUT
ꢈ
ꢗꢘ
ꢇBꢒ
R
ꢕꢖ
ꢇBꢒ
ꢉꢓꢋꢔ
V
– V
+ 0.5 V
ꢀ
ꢄ.ꢅꢆꢇ
IN(MAX)
OUT
V
ꢁꢂꢃ
SHDN
=
ꢀ
+ 0.5 V – 0.4 V
ꢕꢖ
OUT
ꢎꢃꢙꢏꢙꢋ
ꢊ.ꢊꢆꢇ
Step 3:
L1
ꢗꢜꢖꢀ
Rꢃ
ꢈꢀ
(V
– 0.4V) • DC
• 0.3 A
IN(MIN)
f
MAX
(1)
(2)
L
R
ꢀ
TYP
ꢚ.ꢋꢄꢔ
OSC
ꢛꢖꢑ ꢗꢗ
ꢀ
ꢇ
ꢄꢅꢞꢇ
ꢀ
ꢀ
ꢀ
ꢓ.ꢓꢝꢇ
R
ꢏꢚ.ꢊꢔ
ꢗꢗ
ꢃ
(V
– 0.4V) • (2 • DC
– 1)
MAX
IN(MIN)
ꢋ.ꢊꢊꢆꢇ
L
=
MIN
ꢙꢏꢙꢋ ꢇꢉꢏ
1.25 • (DC
− 300ns • f
) • f
• (1– DC
)
MAX
MAX
OSC
OSC
(V
– 0.4V) • DC
IN(MIN)
MAX
(3)
(4)
L
L
=
MAX1
MAX2
Figure 15. Boost Converter: The Component Values and Voltages
Given Are Typical Values for a 1.5MHz, 5V to 12V Boost
f
• 0.08 A
OSC
(V
– 0.4V) • DC
MIN
IN(MAX)
=
The LT8580 can be configured as a boost converter as in
Figure15.Thistopologyallowsforpositiveoutputvoltages
that are higher than the input voltage. A single feedback
resistorsetstheoutputvoltage.Foroutputvoltageshigher
than 60V, see the Charge Pump Aided Regulators section.
f
• 0.08 A
OSC
• Solve equations 1 to 4 for a range of L values
• The minimum of the L value range is the higher of L and L
TYP
MIN
• The maximum of the L value range is the lower of L
and L
.
MAX1
MAX2
Step 4:
RIPPLE
(V
– 0.4V) • DC
MAX
IN(MIN)
I
=
I
RIPPLE(MIN)
f
• L
1
OSC
Table4isastep-by-stepsetofequationstocalculatecom-
ponent values for the LT8580 when operating as a boost
converter. Input parameters are input and output voltage,
(V
– 0.4V) • DC
MIN
IN(MAX)
I
=
RIPPLE(MAX)
f
• L
OSC
1
Step 5:
andswitchingfrequency(V ,V
andf
respectively).
⎛
⎞
I
IN OUT
OSC
RIPPLE(MIN)
2
I
I
I
= ⎜1A −
⎟ • (1− DC
)
MAX
OUT
OUT(MIN)
Refer to the Applications Information section for further
information on the design equations presented in Table 4.
⎝
⎠
⎛
⎞
I
RIPPLE(MAX)
= ⎜1A −
⎟ • (1− DC
)
MIN
OUT(MAX)
2
⎝
⎠
Variable Definitions:
V
> V ; I
> I
Step 6:
D1
R
OUT AVG OUT
V = Input Voltage
IN
Step 7:
I
• DC
MAX
OUT
C
≥
C
OUT
OUT
V
OUT
= Output Voltage
f
• 0.005 • V
OUT
OSC
Step 8:
IN
DC = Power Switch Duty Cycle
C
≥ C
+ C
≥
PWR
IN
VIN
C
I
1A • DC
RIPPLE(MAX)
f
I
I
= Switching Frequency
MAX
OSC
OUT
+
40 • f
• 0.005 • V
8 • f
• 0.005 • V
OSC
IN(MAX)
OSC
IN(MIN)
= Maximum Average Output Current
= Inductor Ripple Current
• Refer to the Capacitor Selection Section for definition of C and C
VIN
PWR
Step 9:
FBX
RIPPLE
V
− 1.204V
OUT
R
R
=
R
FBX
83.3µA
Step
10:
85.5
=
–1 ; f
in MHz and R in kΩ
T
OSC
T
f
OSC
R
T
Note 1: This table uses 1A for the peak switch current. Refer to the
Electrical Characteristics Table and Typical Performance Characteristics
plots for the peak switch current at an operating duty cycle.
Note 2: The final values for C
and C may deviate from the previous
IN
OUT
equations in order to obtain desired load transient performance.
Rev. B
21
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
Table 5. SEPIC Design Equations
PARAMETERS/EQUATIONS
SEPIC CONVERTER COMPONENT SELECTION
(COUPLED OR UNCOUPLED INDUCTORS)
Pick V , V
and f
to calculate equations below
Step 1:
Inputs
IN OUT
OSC
ꢀꢉ
ꢉꢆꢇ
ꢎꢉ
ꢊꢊꢆꢏ
ꢐꢉ
ꢈ
ꢁꢂꢃ
ꢈ
•
ꢔꢕ
Step 2:
DC
V
+ 0.5 V
ꢉꢊꢈ
OUT
ꢖꢈ ꢃꢁ ꢉꢗꢈ
DC
DC
=
MAX
ꢊꢄꢋꢌꢍ
V
+ V
+ 0.5 V – 0.4V
IN(MIN)
OUT
ꢎꢊ
ꢊꢊꢆꢏ
ꢄꢚꢅꢓ
V
+ 0.5 V
OUT
ꢈ
ꢘꢙ
ꢇBꢑ
R
=
ꢔꢕ
•
ꢇBꢑ
MIN
L
V
+ V
+ 0.5 V – 0.4V
ꢉꢒꢋꢓ
IN(MAX)
OUT
ꢀ
ꢄ.ꢅꢆꢇ
ꢁꢂꢃ
SHDN
ꢀ
Step 3:
L
ꢔꢕ
ꢎꢃꢚꢛꢚꢋ
(V
– 0.4V) • DC
• 0.3 A
IN(MIN)
MAX
ꢄ.ꢅꢆꢇ
(1)
(2)
(3)
=
TYP
ꢘꢝꢕꢀ
Rꢃ
ꢈꢀ
f
OSC
R
ꢀ
ꢉꢗ.ꢊꢓ
ꢜꢕꢐ ꢘꢘ
(V
– 0.4V) • (2 • DC
– 1)
MAX
ꢀ
ꢇ
IN(MIN)
L
L
=
ꢊꢊꢟꢇ
MIN
ꢀ
ꢘꢘ
ꢀ
ꢀ
ꢉꢞꢇ
R
ꢚꢄ.ꢛꢓ
ꢃ
1.25 • (DC
− 300ns • f
) • f
• (1– DC
)
MAX
MAX
OSC
OSC
ꢋ.ꢊꢊꢆꢇ
ꢚꢛꢚꢋ ꢇꢉꢗ
(V
– 0.4V) • DC
• 0.08 A
IN(MIN)
MAX
=
MAX
f
OSC
Figure 16. SEPIC Converter: The Component Values and Voltages
Given Are Typical Values for a 1MHz, 9V to 16V Input to 12V
Output SEPIC Converter
• Solve equations 1, 2 and 3 for a range of L values
• The minimum of the L value range is the higher of L and L
TYP
MIN
• The maximum of the L value range is L
• L = L1 = L2 for coupled inductors
• L = L1||L2 for uncoupled inductors
MAX
Step 4:
RIPPLE
(V
– 0.4V) • DC
MAX
The LT8580 can also be configured as a SEPIC, as shown
in Figure 16. This topology allows for positive output
voltages that are lower, equal or higher than the input volt-
age. Output disconnect is inherently built into the SEPIC
topology, meaning no DC path exists between the input
and output due to capacitor C1.
IN(MIN)
I
=
I
RIPPLE(MIN)
f
• L
OSC
(V
– 0.4V) • DC
MIN
IN(MAX)
I
I
I
=
RIPPLE(MAX)
f
• L
OSC
Step 5:
⎛
⎞
I
RIPPLE(MIN)
2
I
= ⎜1A −
⎟ • 1− DC
(
)
OUT
OUT(MIN)
OUT(MAX)
MAX
⎝
⎠
⎛
⎞
Table 5 is a step-by-step set of equations to calculate com-
ponent values for the LT8580 when operating as a SEPIC
converter. Input parameters are input and output voltage,
I
RIPPLE(MAX)
= ⎜1A −
⎟ • 1− DC
(
)
MIN
2
⎝
⎠
V
> V + V ; I
> I
Step 6:
D1
Step 7:
C1
R
IN
OUT AVG OUT
and switching frequency (V , V
and f , respectively).
IN OUT
OSC
C1 ≥ 1µF; V
≥ V
RATING
IN
Refer to the Applications Information section for further
information on the design equations presented in Table 5.
Step 8:
I
• DC
MAX
OUT(MIN)
C
C
≥
OUT
C
OUT
f
• 0.005 • V
OUT
OSC
Variable Definitions:
Step 9:
≥ C
+ C
≥
PWR
IN
VIN
C
IN
V = Input Voltage
IN
I
1A • DC
RIPPLE(MAX)
• 0.005 • V
MAX
+
V
OUT
= Output Voltage
40 • f
• 0.005 • V
8 • f
OSC
OSC
IN(MIN)
IN(MAX)
• Refer to the Capacitor Selection Section for definition of C and C
DC = Power Switch Duty Cycle
VIN
PWR
Step 10:
FBX
V
− 1.204V
OUT
f
I
I
= Switching Frequency
R
=
R
FBX
OSC
83.3µA
= Maximum Average Output Current
OUT
Step 11:
85.5
R
=
–1 ; f
in MHz and R in kΩ
T
OSC
T
R
T
f
OSC
= Inductor Ripple Current
RIPPLE
Note 1: This table uses 1A for the peak switch current. Refer to the
Electrical Characteristics Table and Typical Performance Characteristics
plots for the peak switch current at an operating duty cycle.
Note 2: The final values for C , C and C1 may deviate from the
OUT IN
previous equations in order to obtain desired load transient performance.
Rev. B
22
For more information www.analog.com
LT8580
APPLICATIONS INFORMATION
DUAL INDUCTOR INVERTING CONVERTER COMPONENT
SELECTION (COUPLED OR UNCOUPLED INDUCTORS)
Table 6. Dual Inductor Inverting Design Equations
PARAMETERS/EQUATIONS
Pick V , V
and f
to calculate equations below
Step 1:
Inputs
IN OUT
OSC
ꢀꢊ
ꢊꢆꢇ
ꢖꢊ
ꢕꢕꢆꢗ
ꢖꢕ
ꢕꢕꢆꢗ
Step 2:
DC
V
+ 0.5 V
OUT
ꢈ
ꢁꢂꢃ
ꢉꢊꢋꢈ
ꢌꢍꢎꢏ ꢐꢈ ꢓ ꢋꢈꢔ
ꢈ
DC
DC
=
•
•
ꢑꢒ
ꢋꢈ ꢃꢁ ꢄꢍꢈ
MAX
V
+ V
+ 0.5 V – 0.4 V
IN(MIN)
OUT
ꢑꢒ
ꢊꢍꢛ
ꢘꢊ
ꢕꢊꢍꢎꢏ ꢐꢈ ꢓ ꢊꢕꢈꢔ
ꢑꢒ
ꢄꢕꢍꢎꢏ ꢐꢈ ꢓ ꢄꢍꢈꢔ
ꢑꢒ
V
+ 0.5 V
OUT
=
MIN
L
ꢈ
ꢜꢝ
ꢇBꢙ
R
ꢑꢒ
ꢇBꢙ
ꢊꢚꢕꢛ
V
+ V
+ 0.5 V – 0.4 V
IN(MAX)
OUT
SHDN
Step 3:
L
ꢀ
ꢀ
ꢄ.ꢅꢆꢇ
ꢑꢒ
ꢄ.ꢅꢆꢇ
(V
– 0.4V) • DC
• 0.3 A
ꢁꢂꢃ
ꢖꢃꢚꢋꢚꢍ
IN(MIN)
MAX
(1)
=
TYP
ꢜꢠꢒꢀ
Rꢃ
ꢈꢀ
f
OSC
R
ꢀ
ꢊꢞ.ꢅꢛ
ꢟꢒꢘ ꢜꢜ
ꢀ
(V
– 0.4V) • (2 • DC
– 1)
MAX
ꢇ
IN(MIN)
(2)
(3)
L
L
=
ꢄꢅꢢꢇ
ꢀ
ꢀ
ꢀ
ꢊꢍꢡꢇ
MIN
R
ꢊꢊꢞꢛ
ꢜꢜ
ꢃ
1.25 • (DC
− 300ns • f
) • f
• (1– DC
)
MAX
MAX
OSC
OSC
ꢍ.ꢕꢕꢆꢇ
ꢚꢋꢚꢍ ꢇꢊꢅ
(V
– 0.4V) • DC
• 0.08 A
IN(MIN)
MAX
=
MAX
f
OSC
Figure 17. Dual Inductor Inverting Converter: The Component
Values and Voltages Given Are Typical Values for a 750kHz
Wide Input (5V to 40V) to –15V Inverting Topology Using
Coupled Inductors
• Solve equations 1, 2 and 3 for a range of L values
• The minimum of the L value range is the higher of L and L
TYP
MIN
• The maximum of the L value range is L
• L = L1 = L2 for coupled inductors
• L = L1||L2 for uncoupled inductors
MAX
Due to its unique FBX pin, the LT8580 can work in a dual
inductor inverting configuration as in Figure 17. Chang-
ing the connections of L2 and the Schottky diode in the
SEPIC topology results in generating negative output
voltages. This solution results in very low output voltage
ripple due to inductor L2 being in series with the output.
Output disconnect is inherently built into this topology
due to the capacitor C1.
Step 4:
RIPPLE
(V
– 0.4V) • DC
MAX
IN(MIN)
I
=
I
RIPPLE(MIN)
f
• L
OSC
(V
– 0.4V) • DC
MIN
IN(MAX)
I
I
I
=
RIPPLE(MAX)
f
• L
OSC
Step 5:
⎛
⎞
I
RIPPLE(MIN)
2
I
= ⎜1A −
⎟ • 1− DC
(
)
OUT
OUT(MIN)
OUT(MAX)
MAX
⎝
⎠
⎛
⎞
I
RIPPLE(MAX)
= ⎜1A −
⎟ • 1− DC
(
)
MIN
2
⎝
⎠
Table 6 is a step-by-step set of equations to calculate
component values for the LT8580 when operating as a
dual inductor inverting converter. Input parameters are
V
> V + |V |; I
> I
Step 6:
D1
R
IN
OUT AVG
OUT
C1 ≥ 1µF; V
≥ V
+ |V
|
Step 7:
C1
RATING
IN(MAX)
OUT
input and output voltage, and switching frequency (V ,
Step 8:
IN
I
RIPPLE(MAX)
C
C
≥
OUT
C
V
and f
respectively). Refer to the Applications
Information section for further information on the design
OUT
OUT
OSC
8 • f
(0.005 • V
)
OSC
OUT
Step 9:
≥ C
+ C
≥
PWR
IN
VIN
equations presented in Table 6.
C
IN
I
1A • DC
RIPPLE(MAX)
• 0.005 • V
IN(MAX)
MAX
+
Variable Definitions:
40 • f
• 0.005 • V
8 • f
OSC
OSC
IN(MIN)
• Refer to the Capacitor Selection Section for definition of C and C
VIN
PWR
V = Input Voltage
IN
Step 10:
FBX
V
+ 3mV
OUT
R
R
R
=
V
OUT
= Output Voltage
FBX
83.3µA
DC = Power Switch Duty Cycle
Step 11:
85.5
=
–1 ; f
in MHz and R in kΩ
OSC
T
R
T
T
f
OSC
f
I
I
= Switching Frequency
OSC
OUT
Note 1: This table uses 1A for the peak switch current. Refer to the
Electrical Characteristics Table and Typical Performance Characteristics
plots for the peak switch current at an operating duty cycle.
= Maximum Average Output Current
= Inductor Ripple Current
Note 2: The final values for C , C and C1 may deviate from the
RIPPLE
OUT IN
previous equations in order to obtain desired load transient performance.
Rev. B
23
For more information www.analog.com
LT8580
TYPICAL APPLICATIONS
1.5MHz, 5V to 12V Output Boost Converter
ꢎꢉ
ꢉꢏꢆꢐ
ꢑꢉ
ꢈ
ꢁꢂꢃ
ꢈ
ꢔꢕ
ꢉꢊꢈ
ꢏꢈ
ꢊꢋꢋꢌꢍ
ꢉꢋꢓ
ꢈ
ꢖꢗ
ꢇBꢜ
ꢈꢀ
ꢔꢕ
ꢉꢒꢋꢓ
ꢀ
ꢁꢂꢃ
SHDN
ꢄ.ꢅꢆꢇ
ꢀ
ꢔꢕ
ꢎꢃꢘꢏꢘꢋ
ꢊ.ꢊꢆꢇ
ꢖꢝꢕꢀ
Rꢃ
ꢚ.ꢋꢄꢓ
ꢒ.ꢒꢞꢇ
ꢛꢕꢑ ꢖꢖ
ꢄꢅꢟꢇ
ꢏꢚ.ꢊꢓ
ꢋ.ꢊꢊꢆꢇ
ꢘꢏꢘꢋ ꢃꢍꢋꢊꢙ
ꢎꢉꢠ ꢗꢡRꢃꢐ ꢉꢏꢆꢐ ꢗꢢꢣꢎꢤꢖ ꢅꢄꢄꢋꢄꢋꢏꢄꢉꢏꢋ
ꢑꢉꢠ ꢑꢔꢁꢑꢢꢖ ꢔꢕꢀ. ꢖBRꢉꢂꢄꢋꢎꢥ
ꢀ
ꢀ
ꢠ ꢊ.ꢊꢆ ꢦ ꢒꢏ ꢦ ꢋꢘꢋꢏꢦ ꢜꢅR
ꢁꢂꢃ
ꢔꢕ
ꢠ ꢄ.ꢅꢆ ꢦ ꢉꢚ ꢦ ꢋꢘꢋꢏꢦ ꢜꢅR
Efficiency and Power Loss
ꢘꢌꢌ
ꢕꢙꢌ
ꢕꢍꢌ
ꢛꢙꢌ
ꢛꢌꢌ
ꢍꢕꢌ
ꢘꢙꢌ
ꢘꢍꢌ
ꢗꢌ
ꢝꢌ
ꢙꢌ
ꢜꢌ
ꢗꢌ
ꢖꢌ
ꢕꢌ
ꢛꢌ
ꢍꢌ
ꢆꢎꢎꢏꢄꢏꢆꢇꢄꢐ
ꢒꢁꢓꢆR ꢀꢁꢔꢔ
ꢌ
ꢍꢌꢌ
ꢌ
ꢖꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢘꢌꢌ
ꢘꢖꢌ
ꢙꢖꢙꢌ ꢈꢂꢌꢍꢚ
50mA to 150mA to 50mA Output Load Step
ꢉ
ꢐꢃꢏꢍ
ꢑꢅꢅꢆꢊꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃ
ꢄꢅꢅꢆꢀꢇꢈꢉꢀ
ꢊꢋꢌꢋꢁꢂꢍꢎꢏꢈ
ꢉ
ꢎꢑ
ꢄꢅꢅꢆꢊꢇꢈꢉꢀ
ꢔꢄꢔꢅ ꢃꢊꢅꢕꢖ
ꢑꢅꢅꢒꢓꢇꢈꢉꢀ
Rev. B
24
For more information www.analog.com
LT8580
TYPICAL APPLICATIONS
750kHz, –15V Output Inverting Converter Accepts 5V to 40V Input
ꢀꢊ
ꢊꢆꢇ
ꢖꢊ
ꢕꢕꢆꢗ
ꢖꢕ
ꢕꢕꢆꢗ
ꢈ
ꢁꢂꢃ
ꢈ
•
•
ꢑꢒ
ꢉꢊꢋꢈ
ꢌꢍꢎꢏ ꢐꢈ ꢓ ꢋꢈꢔ
ꢋꢈ ꢃꢁ ꢄꢍꢈ
ꢑꢒ
ꢊꢍꢚ
ꢘꢊ
ꢕꢊꢍꢎꢏ ꢐꢈ ꢓ ꢊꢕꢈꢔ
ꢑꢒ
ꢄꢕꢍꢎꢏ ꢐꢈ ꢓ ꢄꢍꢈꢔ
ꢑꢒ
ꢈ
ꢛꢜ
ꢇBꢠ
ꢈꢀ
ꢑꢒ
ꢊꢙꢕꢚ
SHDN
ꢀ
ꢀ
ꢄ.ꢅꢆꢇ
ꢑꢒ
ꢁꢂꢃ
ꢖꢃꢙꢋꢙꢍ
ꢄ.ꢅꢆꢇ
ꢛꢡꢒꢀ
Rꢃ
ꢊꢝ.ꢅꢚ
ꢊꢍꢢꢇ
ꢟꢒꢘ ꢛꢛ
ꢄꢅꢣꢇ
ꢍ.ꢕꢕꢆꢇ
ꢊꢊꢝꢚ
ꢙꢋꢙꢍ ꢃꢏꢍꢝꢞ
ꢖꢊꢤ ꢖꢕꢥ ꢀꢁꢑꢖꢀRꢏꢇꢃ ꢕꢕꢆꢗ ꢦꢛꢘꢅꢝꢄꢕꢧꢕꢕꢝ
ꢘꢊꢥ ꢀꢨꢒꢃRꢏꢖ ꢛꢨꢦꢑ ꢀꢦꢦꢛꢗꢊꢧꢩꢍ
ꢀ
ꢀ
ꢥ ꢄ.ꢅꢆ ꢤ ꢋꢍ ꢤ ꢊꢕꢍꢩꢤ ꢠꢋR
ꢑꢒ
ꢥ ꢄ.ꢅꢆ ꢤ ꢕꢋ ꢤ ꢊꢕꢍꢩꢤ ꢠꢅR
ꢁꢂꢃ
ꢀꢊꢥ ꢊꢆ ꢤ ꢊꢍꢍ ꢤ ꢍꢙꢍꢋꢤ ꢠꢅꢛ
Efficiency and Power Loss (VIN = 12V)
ꢘꢌ
ꢜꢖꢌ
ꢙꢌ
ꢝꢌ
ꢜꢌ
ꢗꢌ
ꢖꢌ
ꢕꢌ
ꢛꢌ
ꢍꢌ
ꢗꢜꢌ
ꢖꢙꢌ
ꢖꢌꢌ
ꢕꢛꢌ
ꢛꢖꢌ
ꢍꢜꢌ
ꢙꢌ
ꢆꢎꢎꢏꢄꢏꢆꢇꢄꢐ
ꢒꢁꢓꢆR ꢀꢁꢔꢔ
ꢌ
ꢌ
ꢗꢌ
ꢛꢌꢌ
ꢍꢌꢌ
ꢍꢗꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢙꢗꢙꢌ ꢈꢂꢌꢕꢚ
60mA to 160mA to 60mA Output Load Step (VIN = 12V)
ꢉ
ꢐꢃꢏꢍ
ꢑꢅꢅꢆꢊꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃ
ꢄꢅꢅꢆꢀꢇꢈꢉꢀ
ꢊꢋꢌꢋꢁꢂꢍꢎꢏꢈ
ꢉ
ꢒ ꢉ
ꢎꢑ ꢎꢄ
ꢄꢅꢅꢆꢊꢇꢈꢉꢀ
ꢕꢖꢕꢅ ꢃꢊꢅꢗꢘ
ꢄꢅꢅꢓꢔꢇꢈꢉꢀ
Rev. B
25
For more information www.analog.com
LT8580
TYPICAL APPLICATIONS
1.2MHz Inverting Converter Generates –48V Output From 12V Input
C2
2.2µF
49.9Ω
C1
1µF
L1
150µH
L2
330µH
V
OUT
V
IN
–48V
12V
70mA
619k
D1
V
SW
FBX
VC
IN
576k
SHDN
C
C
IN
OUT
LT8580
1µF
2.2µF
SYNC
RT
20.5k
4.7nF
GND SS
47pF
0.33µF
69.8k
8580 TA04a
L1: COOPER 150µH DR74-151
L2: COOPER 330µH DR74-331
D1: DIODES, INC. DFLS1100
C
C
: 1µF, 50V, 0805, X7R
OUT
IN
: 2.2µF, 100V, 1206, X7R
C1: 1µF, 100V, 0805, X7S
C2: 2.2µF, 100V, 1206, X7S
Efficiency and Power Loss
ꢘꢌ
ꢜꢌꢖꢌ
ꢘꢍꢌ
ꢙꢌꢌ
ꢛꢙꢌ
ꢗꢛꢌ
ꢖꢖꢌ
ꢕꢍꢌ
ꢍꢌꢌ
ꢙꢌ
ꢝꢌ
ꢛꢌ
ꢗꢌ
ꢖꢌ
ꢕꢌ
ꢍꢌ
ꢆꢎꢎꢏꢄꢏꢆꢇꢄꢐ
ꢒꢁꢓꢆR ꢀꢁꢔꢔ
ꢌ
ꢜꢌ
ꢍꢌ
ꢕꢌ
ꢖꢌ
ꢗꢌ
ꢛꢌ
ꢝꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢙꢗꢙꢌ ꢈꢂꢌꢖꢚ
Switching Waveforms
Start-Up Waveforms
ꢀ
ꢀ
ꢉꢊ
ꢋꢅꢀꢆꢇꢈꢀ
ꢐꢑ
ꢄꢅꢀꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢄꢅꢆꢀꢇꢈꢉꢀ
ꢁꢂꢃ
ꢄꢅꢀꢆꢇꢈꢀ
ꢊꢋꢌꢋꢁꢂꢍꢎꢏꢈ
ꢉ
ꢓ ꢉ
ꢎꢒ ꢎꢄ
ꢄꢅꢅꢆꢊꢇꢈꢉꢀ
ꢈ
ꢍ ꢈ
ꢌꢄ ꢌꢋ
ꢋꢅꢅꢎꢏꢆꢇꢈꢀ
ꢖꢗꢖꢅ ꢃꢊꢅꢘꢙ
ꢒꢓꢒꢅ ꢃꢏꢅꢔꢕ
ꢄꢅꢅꢔꢕꢇꢈꢉꢀ
ꢋꢅꢅꢐꢑꢆꢇꢈꢀ
Rev. B
26
For more information www.analog.com
LT8580
TYPICAL APPLICATIONS
VFD (Vacuum Fluorescent Display) Power Supply Switches at 1MHz
Danger High Voltage! Operation by High Voltage Trained Personnel Only
D5
V
OUT3
180V
C5
1µF
D4
D2
20mA*
22Ω
C4
1µF
D3
D1
V
OUT2
120V
C3
1µF
30mA*
22Ω
L1
C2
1µF
68µH
V
OUT1
V
IN
60V
9V TO 16V
60mA*
487k
V
SW
FBX
VC
IN
698k
SHDN
C
C1
1µF
IN
LT8580
1µF
SYNC
RT
22.1k
4.7nF
GND SS
330pF
0.47µF
84.5k
8580 TA05a
*MAX TOTAL OUTPUT POWER 3.5W
L1: WÜRTH 68µH WE-LQS 74404084680
D1-D5: DIODES, INC. DFLS1100
C
: 1µF, 100V, 1206, X7R
IN
C1-C5: 1µF, 100V, 1206, X7S
Efficiency and Power Loss
(VIN = 12V with Load on VOUT3
)
Start-Up Waveforms
ꢖꢈ
ꢗꢈ
ꢜꢈ
ꢛꢈ
ꢕꢈ
ꢔꢈ
ꢓꢈ
ꢉꢈ
ꢖꢛꢈ
ꢗꢗꢈ
ꢗꢈꢈ
ꢜꢉꢈ
ꢛꢔꢈ
ꢕꢛꢈ
ꢔꢗꢈ
ꢔꢈꢈ
ꢀ
ꢁꢂꢃꢄ
ꢅꢆꢀꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃꢊ
ꢅꢆꢀꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃꢋ
ꢅꢆꢀꢇꢈꢉꢀ
ꢉ
ꢌꢋ
ꢊꢆꢆꢍꢎꢇꢈꢉꢀ
ꢅꢊꢊꢋꢌꢋꢅꢍꢌꢎ
ꢃꢀꢄꢅR ꢐꢀꢑꢑ
ꢐꢅꢐꢆ ꢃꢎꢆꢅꢑ
ꢊꢍꢏꢇꢈꢉꢀ
ꢈ
ꢈ.ꢕ
ꢚ
ꢚ.ꢕ
ꢉ
ꢉ.ꢕ
ꢓ
ꢓ.ꢕ
ꢀꢁꢂꢃꢁꢂ ꢃꢀꢄꢅR ꢆꢄꢇ
ꢗꢕꢗꢈ ꢂꢘꢈꢕꢙ
Rev. B
27
For more information www.analog.com
LT8580
TYPICAL APPLICATIONS
550kHz SEPIC Converter Generates 24V from 15V to 30V Input
ꢀꢊ
ꢊꢆꢇ
ꢖꢊ
ꢄꢅꢆꢗ
ꢘꢊ
ꢈ
ꢁꢂꢃ
ꢈ
•
ꢐꢑ
ꢉꢄꢈ
ꢊꢌꢈ ꢃꢁ ꢔꢕꢈ
ꢊꢋꢌꢍꢎ ꢏꢈ ꢒ ꢊꢌꢈꢓ
ꢔꢕꢕꢍꢎ ꢏꢈ ꢒ ꢉꢄꢈꢓ
ꢐꢑ
ꢐꢑ
ꢖꢉ
ꢄꢅꢆꢗ
ꢊꢟ
ꢈ
ꢚꢛ
ꢇBꢡ
ꢈꢀ
ꢐꢑ
ꢉꢅꢄꢙ
SHDN
ꢀ
ꢀ
ꢐꢑ
ꢁꢂꢃ
ꢖꢃꢜꢌꢜꢕ
ꢉ.ꢉꢆꢇ
ꢄ.ꢅꢆꢇ
ꢚꢢꢑꢀ
Rꢃ
ꢊꢉ.ꢅꢙ
ꢔ.ꢔꢣꢇ
ꢠꢑꢘ ꢚꢚ
ꢉꢉꢤꢇ
ꢕ.ꢊꢆꢇ
ꢊꢌꢄꢙ
ꢜꢌꢜꢕ ꢃꢎꢕꢝꢞ
ꢖꢊꢥ ꢖꢉꢦ ꢀꢁꢐꢖꢀRꢎꢇꢃ ꢄꢅꢆꢗ ꢟꢚꢘꢅꢔꢄꢉꢧꢄꢅꢔ
ꢘꢊꢦ ꢘꢐꢁꢘꢨꢚ ꢐꢑꢀ. ꢘꢇꢖꢚꢊꢊꢕꢕ
ꢀ
ꢀ
ꢦ ꢉ.ꢉꢆ ꢥ ꢔꢌ ꢥ ꢕꢜꢕꢌꢥ ꢡꢅR
ꢐꢑ
ꢦ ꢄ.ꢅꢆ ꢥ ꢔꢌ ꢥ ꢊꢉꢕꢝꢥ ꢡꢅR
ꢁꢂꢃ
ꢀꢊꢦ ꢊꢆ ꢥ ꢊꢕꢕ ꢥ ꢕꢜꢕꢌꢥ ꢡꢅꢚ
Efficiency and Power Loss
(VIN = 24V)
ꢙꢌ
ꢚꢌ
ꢝꢌ
ꢛꢌ
ꢘꢌ
ꢗꢌ
ꢕꢌ
ꢖꢌ
ꢍꢌ
ꢍꢗꢌꢌ
ꢍꢖꢘꢌ
ꢍꢍꢌꢌ
ꢙꢘꢌ
ꢚꢌꢌ
ꢛꢘꢌ
ꢘꢌꢌ
ꢕꢘꢌ
ꢖꢌꢌ
ꢆꢎꢎꢏꢄꢏꢆꢇꢄꢐ
ꢒꢁꢓꢆR ꢀꢁꢔꢔ
ꢌ
ꢘꢌ
ꢍꢌꢌ
ꢍꢘꢌ
ꢖꢌꢌ
ꢖꢘꢌ
ꢕꢌꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢚꢘꢚꢌ ꢈꢂꢌꢛꢜ
Transient Response with 100mA to 225mA
to 100mA Output Load Step (VIN = 24V)
ꢉ
ꢐꢃꢏꢍ
ꢑꢅꢅꢆꢊꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃ
ꢄꢅꢅꢆꢀꢇꢈꢉꢀ
ꢊꢋꢌꢋꢁꢂꢍꢎꢏꢈ
ꢉ
ꢒ ꢉ
ꢎꢑ ꢎꢓ
ꢄꢅꢅꢆꢊꢇꢈꢉꢀ
ꢖꢄꢖꢅ ꢃꢊꢅꢗꢘ
ꢑꢅꢅꢔꢕꢇꢈꢉꢀ
Rev. B
28
For more information www.analog.com
LT8580
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
ꢃReꢩeꢪeꢫꢬe ꢗꢌꢓ ꢇꢏꢐ ꢭ ꢁꢠꢘꢁꢧꢘꢂꢣꢚꢧ Rev ꢓꢉ
ꢁ.ꢥꢁ ±ꢁ.ꢁꢠ
ꢀ.ꢠ ±ꢁ.ꢁꢠ
ꢙ.ꢂꢁ ±ꢁ.ꢁꢠ ꢃꢙ ꢅꢆꢇꢈꢅꢉ
ꢂ.ꢣꢠ ±ꢁ.ꢁꢠ
ꢔꢎꢓꢕꢎꢐꢈ
ꢋꢖꢌꢗꢆꢊꢈ
ꢁ.ꢙꢠ ±ꢁ.ꢁꢠ
ꢁ.ꢠꢁ
Bꢅꢓ
ꢙ.ꢀꢧ ±ꢁ.ꢁꢠ
Rꢈꢓꢋꢑꢑꢈꢊꢇꢈꢇ ꢅꢋꢗꢇꢈR ꢔꢎꢇ ꢔꢆꢌꢓꢞ ꢎꢊꢇ ꢇꢆꢑꢈꢊꢅꢆꢋꢊꢅ
ꢎꢔꢔꢗꢢ ꢅꢋꢗꢇꢈR ꢑꢎꢅꢕ ꢌꢋ ꢎRꢈꢎꢅ ꢌꢞꢎꢌ ꢎRꢈ ꢊꢋꢌ ꢅꢋꢗꢇꢈRꢈꢇ
R ꢦ ꢁ.ꢂꢙꢠ
ꢁ.ꢄꢁ ±ꢁ.ꢂꢁ
ꢌꢢꢔ
ꢠ
ꢧ
ꢀ.ꢁꢁ ±ꢁ.ꢂꢁ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢂ.ꢣꢠ ±ꢁ.ꢂꢁ
ꢃꢙ ꢅꢆꢇꢈꢅꢉ
ꢔꢆꢊ ꢂ
ꢌꢋꢔ ꢑꢎRꢕ
ꢃꢊꢋꢌꢈ ꢣꢉ
ꢃꢇꢇꢧꢉ ꢇꢜꢊ ꢁꢠꢁꢚ Rꢈꢛ ꢓ
ꢄ
ꢂ
ꢁ.ꢙꢠ ±ꢁ.ꢁꢠ
ꢁ.ꢥꢠ ±ꢁ.ꢁꢠ
ꢁ.ꢙꢁꢁ Rꢈꢜ
ꢁ.ꢠꢁ Bꢅꢓ
ꢙ.ꢀꢧ ±ꢁ.ꢂꢁ
Bꢋꢌꢌꢋꢑ ꢛꢆꢈꢏꢤꢈꢝꢔꢋꢅꢈꢇ ꢔꢎꢇ
ꢁ.ꢁꢁ ꢨ ꢁ.ꢁꢠ
ꢊꢋꢌꢈꢍ
ꢂ. ꢇRꢎꢏꢆꢊꢐ ꢌꢋ Bꢈ ꢑꢎꢇꢈ ꢎ ꢒꢈꢇꢈꢓ ꢔꢎꢓꢕꢎꢐꢈ ꢋꢖꢌꢗꢆꢊꢈ ꢑꢁꢘꢙꢙꢚ ꢛꢎRꢆꢎꢌꢆꢋꢊ ꢋꢜ ꢃꢏꢈꢈꢇꢘꢂꢉ
ꢙ. ꢇRꢎꢏꢆꢊꢐ ꢊꢋꢌ ꢌꢋ ꢅꢓꢎꢗꢈ
ꢀ. ꢎꢗꢗ ꢇꢆꢑꢈꢊꢅꢆꢋꢊꢅ ꢎRꢈ ꢆꢊ ꢑꢆꢗꢗꢆꢑꢈꢌꢈRꢅ
ꢄ. ꢇꢆꢑꢈꢊꢅꢆꢋꢊꢅ ꢋꢜ ꢈꢝꢔꢋꢅꢈꢇ ꢔꢎꢇ ꢋꢊ Bꢋꢌꢌꢋꢑ ꢋꢜ ꢔꢎꢓꢕꢎꢐꢈ ꢇꢋ ꢊꢋꢌ ꢆꢊꢓꢗꢖꢇꢈ
ꢑꢋꢗꢇ ꢜꢗꢎꢅꢞ. ꢑꢋꢗꢇ ꢜꢗꢎꢅꢞꢟ ꢆꢜ ꢔRꢈꢅꢈꢊꢌꢟ ꢅꢞꢎꢗꢗ ꢊꢋꢌ ꢈꢝꢓꢈꢈꢇ ꢁ.ꢂꢠꢡꢡ ꢋꢊ ꢎꢊꢢ ꢅꢆꢇꢈ
ꢠ. ꢈꢝꢔꢋꢅꢈꢇ ꢔꢎꢇ ꢅꢞꢎꢗꢗ Bꢈ ꢅꢋꢗꢇꢈR ꢔꢗꢎꢌꢈꢇ
ꢣ. ꢅꢞꢎꢇꢈꢇ ꢎRꢈꢎ ꢆꢅ ꢋꢊꢗꢢ ꢎ RꢈꢜꢈRꢈꢊꢓꢈ ꢜꢋR ꢔꢆꢊ ꢂ ꢗꢋꢓꢎꢌꢆꢋꢊ
ꢋꢊ ꢌꢋꢔ ꢎꢊꢇ Bꢋꢌꢌꢋꢑ ꢋꢜ ꢔꢎꢓꢕꢎꢐꢈ
Rev. B
29
For more information www.analog.com
LT8580
PACKAGE DESCRIPTION
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
ꢄReꢪeꢫeꢬꢭe ꢕꢑꢙ ꢗꢛꢔ ꢮ ꢈꢎꢤꢈꢅꢤꢊꢏꢏꢉ Rev ꢍꢇ
Bꢂꢑꢑꢂꢀ ꢌꢒꢆꢛ ꢂꢝ
ꢆꢟꢃꢂꢁꢆꢗ ꢃꢐꢗ ꢂꢃꢑꢒꢂꢓ
ꢊ.ꢅꢅ
ꢄ.ꢈꢥꢢꢇ
ꢊ.ꢏꢅ
ꢊ
ꢈ.ꢉꢧ
Rꢆꢝ
ꢊ.ꢅꢅ ±ꢈ.ꢊꢈꢉ
ꢄ.ꢈꢥꢢ ±.ꢈꢈꢢꢇ
ꢈ.ꢅꢅꢧ ±ꢈ.ꢊꢉꢥ
ꢄ.ꢈꢋꢎ ±.ꢈꢈꢎꢇ
ꢄ.ꢈꢏꢏꢇ
ꢈ.ꢈꢎ Rꢆꢝ
ꢗꢆꢑꢐꢒꢕ ꢨBꢩ
ꢎ.ꢊꢈ
ꢄ.ꢉꢈꢊꢇ
ꢀꢒꢓ
ꢋ.ꢉꢈ ꢦ ꢋ.ꢢꢎ
ꢄ.ꢊꢉꢏ ꢦ .ꢊꢋꢏꢇ
ꢊ.ꢏꢅ ±ꢈ.ꢊꢈꢉ
ꢙꢂRꢓꢆR ꢑꢐꢒꢕ ꢒꢁ ꢃꢐRꢑ ꢂꢝ
ꢑꢚꢆ ꢕꢆꢐꢗꢝRꢐꢀꢆ ꢝꢆꢐꢑꢜRꢆ.
ꢝꢂR RꢆꢝꢆRꢆꢓꢙꢆ ꢂꢓꢕꢣ
ꢄ.ꢈꢏꢏ ±.ꢈꢈꢢꢇ
ꢗꢆꢑꢐꢒꢕ ꢨBꢩ
ꢅ
NO MEASUREMENT PURPOSE
ꢋ.ꢈꢈ ±ꢈ.ꢊꢈꢉ
ꢄ.ꢊꢊꢅ ±.ꢈꢈꢢꢇ
ꢄꢓꢂꢑꢆ ꢋꢇ
ꢈ.ꢏꢎ
ꢄ.ꢈꢉꢎꢏꢇ
Bꢁꢙ
ꢈ.ꢎꢉ
ꢄ.ꢈꢉꢈꢎꢇ
Rꢆꢝ
ꢈ.ꢢꢉ ±ꢈ.ꢈꢋꢅ
ꢄ.ꢈꢊꢏꢎ ±.ꢈꢈꢊꢎꢇ
ꢅ
ꢥ ꢏ ꢎ
ꢑꢣꢃ
Rꢆꢙꢂꢀꢀꢆꢓꢗꢆꢗ ꢁꢂꢕꢗꢆR ꢃꢐꢗ ꢕꢐꢣꢂꢜꢑ
ꢋ.ꢈꢈ ±ꢈ.ꢊꢈꢉ
ꢄ.ꢊꢊꢅ ±.ꢈꢈꢢꢇ
ꢄꢓꢂꢑꢆ ꢢꢇ
ꢢ.ꢧꢈ ±ꢈ.ꢊꢎꢉ
ꢄ.ꢊꢧꢋ ±.ꢈꢈꢏꢇ
ꢗꢆꢑꢐꢒꢕ ꢨꢐꢩ
ꢈ.ꢉꢎꢢ
ꢄ.ꢈꢊꢈꢇ
ꢈ° ꢦ ꢏ° ꢑꢣꢃ
ꢔꢐꢜꢔꢆ ꢃꢕꢐꢓꢆ
ꢊ
ꢉ
ꢋ
ꢢ
ꢈ.ꢎꢋ ±ꢈ.ꢊꢎꢉ
ꢄ.ꢈꢉꢊ ±.ꢈꢈꢏꢇ
ꢊ.ꢊꢈ
ꢄ.ꢈꢢꢋꢇ
ꢀꢐꢟ
ꢈ.ꢅꢏ
ꢄ.ꢈꢋꢢꢇ
Rꢆꢝ
ꢗꢆꢑꢐꢒꢕ ꢨꢐꢩ
ꢈ.ꢊꢅ
ꢄ.ꢈꢈꢥꢇ
ꢁꢆꢐꢑꢒꢓꢔ
ꢃꢕꢐꢓꢆ
ꢈ.ꢉꢉ ꢦ ꢈ.ꢋꢅ
ꢄ.ꢈꢈꢧ ꢦ .ꢈꢊꢎꢇ
ꢑꢣꢃ
ꢈ.ꢊꢈꢊꢏ ±ꢈ.ꢈꢎꢈꢅ
ꢄ.ꢈꢈꢢ ±.ꢈꢈꢉꢇ
ꢈ.ꢏꢎ
ꢄ.ꢈꢉꢎꢏꢇ
Bꢁꢙ
ꢀꢁꢂꢃ ꢄꢀꢁꢅꢆꢇ ꢈꢉꢊꢋ Rꢆꢌ ꢍ
ꢓꢂꢑꢆꢖ
ꢊ. ꢗꢒꢀꢆꢓꢁꢒꢂꢓꢁ ꢒꢓ ꢀꢒꢕꢕꢒꢀꢆꢑꢆRꢘꢄꢒꢓꢙꢚꢇ
ꢉ. ꢗRꢐꢛꢒꢓꢔ ꢓꢂꢑ ꢑꢂ ꢁꢙꢐꢕꢆ
ꢋ. ꢗꢒꢀꢆꢓꢁꢒꢂꢓ ꢗꢂꢆꢁ ꢓꢂꢑ ꢒꢓꢙꢕꢜꢗꢆ ꢀꢂꢕꢗ ꢝꢕꢐꢁꢚꢞ ꢃRꢂꢑRꢜꢁꢒꢂꢓꢁ ꢂR ꢔꢐꢑꢆ BꢜRRꢁ.
ꢀꢂꢕꢗ ꢝꢕꢐꢁꢚꢞ ꢃRꢂꢑRꢜꢁꢒꢂꢓꢁ ꢂR ꢔꢐꢑꢆ BꢜRRꢁ ꢁꢚꢐꢕꢕ ꢓꢂꢑ ꢆꢟꢙꢆꢆꢗ ꢈ.ꢊꢎꢉꢠꢠ ꢄ.ꢈꢈꢏꢡꢇ ꢃꢆR ꢁꢒꢗꢆ
ꢢ. ꢗꢒꢀꢆꢓꢁꢒꢂꢓ ꢗꢂꢆꢁ ꢓꢂꢑ ꢒꢓꢙꢕꢜꢗꢆ ꢒꢓꢑꢆRꢕꢆꢐꢗ ꢝꢕꢐꢁꢚ ꢂR ꢃRꢂꢑRꢜꢁꢒꢂꢓꢁ.
ꢒꢓꢑꢆRꢕꢆꢐꢗ ꢝꢕꢐꢁꢚ ꢂR ꢃRꢂꢑRꢜꢁꢒꢂꢓꢁ ꢁꢚꢐꢕꢕ ꢓꢂꢑ ꢆꢟꢙꢆꢆꢗ ꢈ.ꢊꢎꢉꢠꢠ ꢄ.ꢈꢈꢏꢡꢇ ꢃꢆR ꢁꢒꢗꢆ
ꢎ. ꢕꢆꢐꢗ ꢙꢂꢃꢕꢐꢓꢐRꢒꢑꢣ ꢄBꢂꢑꢑꢂꢀ ꢂꢝ ꢕꢆꢐꢗꢁ ꢐꢝꢑꢆR ꢝꢂRꢀꢒꢓꢔꢇ ꢁꢚꢐꢕꢕ Bꢆ ꢈ.ꢊꢈꢉꢠꢠ ꢄ.ꢈꢈꢢꢡꢇ ꢀꢐꢟ
ꢏ. ꢆꢟꢃꢂꢁꢆꢗ ꢃꢐꢗ ꢗꢒꢀꢆꢓꢁꢒꢂꢓ ꢗꢂꢆꢁ ꢒꢓꢙꢕꢜꢗꢆ ꢀꢂꢕꢗ ꢝꢕꢐꢁꢚ. ꢀꢂꢕꢗ ꢝꢕꢐꢁꢚ ꢂꢓ ꢆꢤꢃꢐꢗ
ꢁꢚꢐꢕꢕ ꢓꢂꢑ ꢆꢟꢙꢆꢆꢗ ꢈ.ꢉꢎꢢꢠꢠ ꢄ.ꢈꢊꢈꢡꢇ ꢃꢆR ꢁꢒꢗꢆ.
Rev. B
30
For more information www.analog.com
LT8580
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
09/16 Changed Minimum On-Time in the Electrical Characteristics table to typical room value instead of worst case.
Added Minimum On-Time vs Temperature graph.
3
5
Added text and equations explaining minimum on-time.
9
Clarified inductor paragraph in the Applications Information section.
10, 11
11, 14
Adjusted R , R , R , g and resultant gain and phase margin numbers and plot to better reflect applications and the
C
L
O
ma
Electrical Characteristics table.
Clarified Thermal Calculations section.
17
Corrected L
equation.
21, 22, 23
MIN
Clarified the Related Parts table.
11/19 Add AEC-Q100 Qualification in Progress
Add #W Part Numbers
32
1
B
2
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
31
LT8580
TYPICAL APPLICATION
12V Battery Stabilizer Survives 40V Transients
Efficiency and Power Loss
(VIN = 12V)
ꢀꢉ
ꢉꢆꢇ
ꢎꢉ
ꢊꢊꢆꢏ
ꢐꢉ
ꢚꢌ
ꢛꢌ
ꢜꢌ
ꢙꢌ
ꢘꢌ
ꢗꢌ
ꢕꢌ
ꢖꢌ
ꢍꢌ
ꢛꢌꢌ
ꢜꢌꢌ
ꢙꢌꢌ
ꢘꢌꢌ
ꢗꢌꢌ
ꢕꢌꢌ
ꢖꢌꢌ
ꢍꢌꢌ
ꢌ
ꢈ
ꢁꢂꢃ
ꢈ
•
ꢓꢔ
ꢉꢊꢈ
ꢕꢈ ꢃꢁ ꢉꢖꢈ
ꢂꢗ ꢃꢁ ꢄꢋꢈ
ꢃRꢍꢔꢘꢓꢙꢔꢃ
ꢊꢄꢋꢌꢍ
ꢎꢊ
ꢊꢊꢆꢏ
ꢄꢛꢅꢒ
ꢈ
ꢘꢚ
ꢇBꢟ
ꢈꢀ
ꢓꢔ
ꢉꢑꢋꢒ
SHDN
ꢀ
ꢀ
ꢄ.ꢅꢆꢇ
ꢓꢔ
ꢁꢂꢃ
ꢎꢃꢛꢜꢛꢋ
ꢄ.ꢅꢆꢇ
ꢘꢠꢔꢀ
Rꢃ
ꢉꢖ.ꢊꢒ
ꢉꢡꢇ
ꢞꢔꢐ ꢘꢘ
ꢊꢊꢢꢇ
ꢆꢎꢎꢏꢄꢏꢆꢇꢄꢐ
ꢒꢁꢓꢆR ꢀꢁꢔꢔ
ꢋ.ꢊꢊꢆꢇ
ꢛꢄ.ꢜꢒ
ꢛꢜꢛꢋ ꢃꢍꢋꢅꢝ
ꢌ
ꢗꢌ
ꢛꢌ
ꢍꢖꢌ
ꢍꢙꢌ
ꢖꢌꢌ
ꢖꢗꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢎꢉꢣ ꢎꢊꢤ ꢚꢥRꢃꢏ ꢊꢊꢆꢏ ꢚꢙꢦꢐꢐ ꢅꢄꢄꢛꢅꢅꢊꢊꢋ
ꢐꢉꢤ ꢐꢓꢁꢐꢙꢘ ꢓꢔꢀ. ꢐꢇꢎꢘꢉꢉꢋꢋ
ꢛꢘꢛꢌ ꢈꢂꢌꢜꢝ
ꢀ
ꢀ
ꢤ ꢄ.ꢅꢆ ꢣ ꢜꢋ ꢣ ꢉꢊꢋꢖꢣ ꢟꢅR
ꢓꢔ
ꢁꢂꢃ
ꢤ ꢄ.ꢅꢆ ꢣ ꢊꢜ ꢣ ꢉꢊꢋꢖꢣ ꢟꢅR
ꢀꢉꢤ ꢉꢆ ꢣ ꢉꢋꢋ ꢣ ꢋꢛꢋꢜꢣ ꢟꢅꢘ
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1613
550mA (I ), 1.4MHz High Efficiency Step-Up DC/DC Converter V : 0.9V to 10V, V
= 34V, I = 3mA, I < 1µA,
Q SD
SW
IN
OUT(MAX)
ThinSOT Package
LT1618
1.5A (I ), 1.4MHz High Efficiency Step-Up DC/DC Converter
V : 1.6V to 18V, V
= 35V, I = 1.8mA, I < 1µA,
Q SD
SW
IN
OUT(MAX)
MS10, 3mm × 3mm DFN Packages
LT1930/LT1930A 1A (I ), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC
V : 2.6V to 16V, V
= 34V, I = 4.2mA/5.5mA, I < 1µA,
Q SD
SW
Converter
IN
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
ThinSOT Package
LT1935
2A (I ), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter V : 2.3V to 16V, V
= 38V, I = 3mA, I < 1µA,
Q SD
SW
IN
ThinSOT Package
LT1944/LT1944-1 Dual Output 350mA (I ), Constant Off-Time, High Efficiency
V : 1.2V to 15V, V
= 34V, I = 20µA, I < 1µA,
Q SD
SW
IN
Step-Up DC/DC Converter
MS10 Package
LT1946/LT1946A 1.5A (I ), 1.2MHz/2.7MHz High Efficiency Step-Up DC/DC
V : 2.6V to 16V, V
= 34V, I = 3.2mA, I < 1µA,
Q SD
SW
IN
Converter
MS8E Package
LT3467
LT3477
LT3479
LT3580
LT3581
LT3579
LT8582
1.1A (I ), 1.3MHz High Efficiency Step-Up DC/DC Converter
V : 2.4V to 16V, V
= 40V, I = 1.2mA, I < 1µA,
Q SD
SW
IN
ThinSOT, 2mm × 3mm DFN Packages
42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver
V : 2.5V to 25V, V = 40V, Analog/PWM, I < 1µA,
IN
OUT(MAX)
SD
QFN, TSSOP-20E Packages
3A Full-Featured DC/DC Converter with Soft-Start and Inrush
Current Protection
V : 2.5V to 24V, V
= 40V, I = 5mA, I < 1µA,
Q SD
IN
OUT(MAX)
DFN, TSSOP Packages
2A (I ), 42V, 2.5MHz, High Efficiency Step-Up DC/DC
V : 2.5V to 32V, V
= 42V, I = 1mA, I = <1µA,
Q SD
SW
IN
OUT(MAX)
Converter
3mm × 3mm DFN-8, MSOP-8E
3.3A (I ), 42V, 2.5MHz, High Efficiency Step-Up DC/DC
V : 2.5V to 22V, V = 42V, I = 1.9mA, I = <1µA,
SW
IN
OUT(MAX)
Q
SD
Converter
4mm × 3mm DFN-14, MSOP-16E
6A (I ), 42V, 2.5MHz, High Efficiency, Step-Up DC/DC
V : 2.5V to 16V, V = 42V, I = 1.9mA, I = <1µA,
SW
IN
OUT(MAX)
Q
SD
Converter
4mm × 5mm QFN-20, TSSOP-20
Dual Channel, 3A (I ), 42V, 2.5MHz, High Efficiency Step-Up
V : 2.5V to 22V, V = 42V, I = 2.1mA, I = <1µA,
SW
IN
OUT(MAX)
Q
SD
DC/DC Converter
4mm × 7mm DFN-24
Rev. B
11/19
www.analog.com
ANALOG DEVICES, INC. 2014–2019
32
相关型号：
LT8580HMS8E#PBF
LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: MSOP; Pins: 8; Temperature Range: -40°C to 125°C
Linear
LT8580HMS8E#TRPBF
LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: MSOP; Pins: 8; Temperature Range: -40°C to 125°C
Linear
LT8580IDD#PBF
LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LT8580IDD#TRPBF
LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LT8580IMS8E#TRPBF
LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LT8582EDKD#PBF
LT8582 - Dual 3A Boost/Inverting/SEPIC DC/DC Converter with Fault Protection; Package: DFN; Pins: 24; Temperature Range: -40°C to 85°C
Linear
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