LT8711EFE#PBF [Linear]
LT8711 - Micropower Synchronous Multitopology Controller with 42V Input Capability; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LT8711EFE#PBF |
| 厂家： | 
Linear |
| 描述： | LT8711 - Micropower Synchronous Multitopology Controller with 42V Input Capability; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总38页 (文件大小：1309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT8711
Micropower Synchronous
Multitopology Controller
with 42V Input Capability
DescripTion
The LT®8711 is a multi-topology current mode PWM con-
trollerthatcaneasilybeconfiguredasasynchronousbuck,
boost, SEPIC, ZETA or as a nonsynchronous buck-boost
converter. Its dual gate drive voltage inputs optimize gate
driver efficiency.
FeaTures
n
Easily Configurable as a Synchronous Buck, Boost,
SEPIC, ZETA or Nonsynchronous Buck-Boost Converter
n
Wide Input Range: 4.5V to 42V (V Can Operate
IN
to 0V, when EXTV > 4.5V)
CC
Automatic Low Noise Burst Mode® Operation
n
n
n
n
n
n
n
n
n
Low I in Burst Mode Operation (15μA Operating)
Q
The15µAno-loadquiescentcurrentwiththeoutputvoltage
inregulationextendsoperatingrun-timeinbatterypowered
systems. Low ripple Burst Mode operation enables high
efficiency at very light loads while maintaining low output
voltageripple.TheLT8711'sfixedswitchingfrequencycan
be set from 100kHz to 750kHz or can be synchronized to
an external clock.
Input Voltage Regulation for High Impedance Source
100% Duty Cycle in Dropout (Buck Mode)
2A Gate Drivers (BG and TG)
Adjustable Soft-Start with One Capacitor
Frequency Programmable from 100kHz to 750kHz
Can Be Synchronized to External Clock
Available in 20-Lead TSSOP and 20-Lead 3mm×4mm
QFN Packages
The additional features include 100% duty cycle capability
wheninbuckmode,atopologyselectionpinandadjustable
soft-start. LT8711 is available in the 20-lead TSSOP and
20-lead 3mm × 4mm QFN packages.
applicaTions
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
of Analog Devices, Inc. All other trademarks are the property of their respective owners.
n
General Purpose DC/DC Conversion
n
Automotive Systems
n
Industrial Supplies
Solar Panel Power Converter
n
Typical applicaTion
400kHz 5V to 40V Input/12V Output Nonsynchronous Buck Boost
V
IN
Efficiency vs Load Current
5V TO
40V
10µF ×6
100
90
V
BIAS
IN
50V, X7R
2.2µF
EN/FBIN
EXTV
LT8711
OPMODE
INTV
V
CC
EE
OUT
80
100pF
TG
M1
L1
4.7µH
70
V
OUT
2.2µF
60
D1
D2
12V,
INTV
CC
3.5A (V >16V)
ISN
IN
50
2.5A (9V < V < 16V)
IN
60.4k
1.5A (V < 9V)
IN
40
30
20
10
0
4mΩ
1M
RT
100µF ×2
16V, X7R
SYNC
ISP
GND
V
V
V
V
= 5V
330nF
100pF
2.2nF
IN
IN
IN
IN
M2
69.8k
= 12V
= 24V
= 36V
SS
BG
CSP
CSN
4mΩ
0.001
0.01
0.1
1
4
110k
LOAD CURRENT (A)
V
C
8711 TA01b
FB
8711 TA01a
8711f
1
For more information www.linear.com/LT8711
LT8711
absoluTe MaxiMuM raTings
(Note 1)
V Voltage ................................................ –0.3V to 42V
CSN Voltage........................... CSP – 0.3V to CSP + 0.3V
ISP Voltage .............................. ISN – 0.3V to ISN + 0.3V
ISN Voltage ...............................................–0.3V to BIAS
IN
BIAS Voltage.............................................. –0.3V to 42V
EXTV Voltage ......................................... –0.3V to 42V
CC
BG, TG Voltage .....................................................Note 2
INTV Voltage ......................................... –0.3V to 5.5V
CC
FB Voltage................................................. –0.3V to 5.5V
RT Voltage ................................................ –0.3V to 5.5V
SS Voltage ............................................... –0.3V to 5.5V
Operating Junction Temperature Range
LT8711E............................................. –40°C to 125°C
LT8711I.............................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
V Voltage ................................................ –0.3V to 2.5V
C
EN/FBIN Voltage................. –0.3V to MAX(V , EXTV )
IN
CC
SYNC Voltage ........................................... –0.3V to 5.5V
OPMODE Voltage ...................................... –0.3V to 5.5V
INTV Voltage..................................................... Note 2
EE
CSP Voltage ............................................... –0.3V to 42V
pin conFiguraTion
TOP VIEW
TOP VIEW
EN/FBIN
FB
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
RT
SYNC
NC
20 19 18 17
V
C
V
1
2
3
4
5
6
16 CSP
15 CSN
14 EXTV
C
SS
OPMODE
ISP
CSP
CSN
EXTV
SS
OPMODE
ISP
21
GND
CC
21
GND
CC
13
V
IN
ISN
V
IN
ISN
12 INTV
11 NC
CC
INTV
EE
INTV
NC
CC
INTV
EE
BIAS
7
8
9 10
TG 10
BG
FE PACKAGE
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
20-LEAD PLASTIC TSSOP
T
JMAX
= 125°C, θ = 38°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 52°C/W, θ = 6.8°C/W
JA Jc
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
http://www.linear.com/product/LT8711#orderinfo
LEAD FREE FINISH
LT8711EFE#PBF
LT8711IFE#PBF
TAPE AND REEL
PART MARKING*
LT8711 FE
LT8711 FE
LGQJ
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8711EFE#TRPBF
LT8711IFE#TRPBF
LT8711EUDC#TRPBF
LT8711IUDC#TRPBF
20-Lead TSSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
20-Lead TSSOP
LT8711EUDC#PBF
LT8711IUDC#PBF
20-Lead 3mm × 4mm QFN
20-Lead 3mm × 4mm QFN
LGQJ
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
8711f
2
For more information www.linear.com/LT8711
LT8711
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VBIAS = 12V, unless otherwise noted (Note 3).
PARAMETER
Operating Voltage Range
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
V
V
= 0V
= 4.5V
4.5
0
42
42
V
V
IN
EXTVCC
EXTVCC
Quiescent Current in Normal Operation
(I + I + I
V
V
V
= 2.5V, Not Switching
2.0
15
1
2.5
25
2
mA
µA
µA
EN/FBIN
)
BIAS
VIN
EXTVCC
Quiescent Current in Burst Mode Operation
(I + I + I
= V
+ 3mV
FB_REG
FB
)
BIAS
VIN
EXTVCC
Quiescent Current in Shutdown
(I + I + I
= 0V
EN/FBIN
)
BIAS
VIN
EXTVCC
l
l
FB Output Regulation Voltage, V
784
795
800
800
816
805
mV
mV
FB_REG
FB Line Regulation
4.5V ≤ V ≤ 42V
0.01
0
0.05
50
%/V
nA
IN
FB Pin Input Bias Current
Error Amp Transconductance
Error Amp Voltage Gain
V
= 0.8V
–50
FB
∆I = 5µA
250
90
µmhos
dB
l
l
Maximum Current Sense Voltage,
– V
Minimum Duty Cycle
Maximum Duty Cycle
46
26
50
33
54
40
mV
mV
V
CSP
CSN
l
l
Switching Frequency, f
R = 30.3k
T
675
85
750
100
825
115
kHz
kHz
OSC
T
R = 247k
l
l
Switching Frequency Range
Free-Running
Synchronizing
85
140
825
750
kHz
kHz
l
l
SYNC Input Voltage High
SYNC Input Voltage Low
SYNC Clock Pulse Duty Cycle
1.3
V
V
0.4
80
V
= 0V to 2V, f
= 10mA
= 500kHz
20
0.8
%
SYNC
SYNC
Recommended SYNC Ratio f
/f
1.2
5.25
SYNC OSC
l
INTV Voltage
I
4.75
5
V
CC
INTVCC
INTV Line Regulation
6V ≤ V ≤ 42V, V
= 0, I = 10mA
INTVCC
VIN
–0.003
–0.003
–0.03
–0.03
%/V
%/V
CC
IN
EXTVCC
6V ≤ V
≤ 42V, V = 0, I
= 10mA
INTVCC
EXTVCC
INTV Load Regulation
I
= 0mA to 40mA
–1
10
–2
%
CC
INTVCC
INTV Maximum External Load Current
Internal Load Current = 40mA
mA
CC
l
l
INTV Undervoltage Lockout
INTV Rising
3.9
3.45
4.1
3.6
4.3
3.75
V
V
CC
CC
INTV Falling
CC
INTV Undervoltage Lockout Hysteresis
500
mV
V
CC
l
INTV Voltage, V
– V
I = 10mA
INTVEE
4.85
5.15
5.4
EE
BIAS
INTVEE
l
l
INTV Undervoltage Lockout, V
– V
V
BIAS
V
BIAS
– V
Rising
Falling
3.6
3.4
3.85
3.6
4.1
3.8
V
V
EE
BIAS
INTVEE
INTVEE
INTVEE
– V
INTV Undervoltage Lockout Hysteresis,
BIAS
250
mV
EE
V
– V
INTVEE
BG Rise Time
C
C
C
C
= 3.3nF (Note 4)
= 3.3nF (Note 4)
= 3.3nF (Note 4)
= 3.3nF (Note 4)
14
12
ns
ns
ns
ns
ns
ns
ns
BG
BG
TG
TG
BG Fall Time
TG Rise Time
11
TG Fall Time
14
BG and TG Non-Overlap Time
BG and TG Non-Overlap Time
Minimum On-Time
TG Rising to BG Rising, C = C = 3.3nF (Note 4)
70
BG
TG
BG Falling to TG Falling, C = C = 3.3nF (Note 4)
70
BG
TG
C
BG
= C = 3.3nF
100
TG
8711f
3
For more information www.linear.com/LT8711
LT8711
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VBIAS = 12V, unless otherwise noted (Note 3).
PARAMETER
CONDITIONS
V = 0V, Current Flows Out of SS pin
SS
MIN
6
TYP
10
MAX
15
UNITS
µA
l
l
l
SS Charge Current
SS Low Detection Voltage
EN/FBIN Active Mode
EN/FBIN Chip Enable
Part Exiting Undervoltage Lockout
EN/FBIN Rising
65
85
105
1.42
mV
V
1.28
1.35
l
l
EN/FBIN Rising
EN/FBIN Falling
0.97
0.94
1.03
1
1.11
1.08
V
V
EN/FBIN Chip Enable Hysteresis
EN/FBIN Input Voltage Low
30
mV
V
l
Shutdown Mode
0.2
l
l
EN/FBIN Current Limit Adjustment Voltage
Full Current Limit
1.27
V
V
Near Zero Current Limit
1.12
–50
l
EN/FBIN Pin Input Bias Current
EN/FBIN Amp Transconductance
EN/FBIN Amp Voltage Gain
V
V
V
= 12V
0
50
nA
µmhos
V/V
EN/FBIN
= 0.6V
40
FB
FB
= 0.6V
100
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not apply a positive or negative voltage or current source to
BG, TG and INTV pins, otherwise permanent damage may occur.
EE
Note 3: The LT8711E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8711I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
8711f
4
For more information www.linear.com/LT8711
LT8711
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Maximum Current Limit vs
Duty Cycle (CSP–CSN)
Maximum Current Limit vs SS
(CSP–CSN)
Output Voltage Regulation
(VFB_REG
)
55
48
41
34
27
20
60
50
40
30
20
10
0
805
804
803
802
801
800
799
798
797
796
795
0
10 20 30 40 50 60 70 80 90 100
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8 2.0
–50 –25
0
25
50
75 100 125
DUTY CYCLE (%)
SS (V)
TEMPERATURE (°C)
8711 G01
8711 G02
8711 G03
Input Voltage Regulation
(EN/FBIN)
EN/FBIN Chip Enable Threshold
EN/FBIN Active Mode Threshold
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
1.370
1.365
1.360
1.355
1.350
1.345
1.340
1.335
1.330
RISING
FALLING
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
8711 G04
8711 G05
8711 G06
Input Voltage Regulation vs FB
(EN/FBIN)
CSN Bias Current
ISN Bias Current
1.6
1.5
1.4
1.3
1.2
1.1
1.0
180
160
140
120
100
80
350
300
250
200
150
100
V
= V
= 12V
V
= V =12V
ISP ISN
CSP
CSN
60
0.60 0.65 0.70 0.75 0.80 0.85 0.90
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
FB (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
8711 G07
8711 G08
8711 G09
8711f
5
For more information www.linear.com/LT8711
LT8711
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Oscillator Frequency vs
Temperature
DCM Thresholds (ISP–ISN)
BG Transition Time vs Cap Load
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
800
700
600
500
400
300
200
100
0
60
50
40
30
20
10
0
R
T
= 30.3kΩ
V
= 0V
ISN
RISING
V
= 12V
ISN
FALLING
R
T
= 247kΩ
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
CAP LOAD (nF)
8711 G10
8711 G11
8711 G12
TG Transition Time vs Cap Load
Minimum Operating Input Voltage
INTVCC vs Temperature
60
50
40
30
20
10
0
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
I
= 10mA
INTVCC
RISING
RISING
FALLING
FALLING
0
1
2
3
4
5
6
7
8
9
10
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
CAP LOAD (nF)
TEMPERATURE (°C)
TEMPERATURE (°C)
8711 G13
8711 G14
8711 G15
INTVCC Current Limit vs
VIN or EXTVCC
INTVCC Dropout from
VIN or EXTVCC
INTVCC UVLO vs Temperature
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
70
60
50
40
30
20
10
0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
RISING
FALLING
–50 –25
0
25
50
75 100 125
5
10
15
20
25
30
35
40
0
10
20
30
40
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INTV LOAD CURRENT (mA)
CC
8711 G16
8711 G17
8711 G18
8711f
6
For more information www.linear.com/LT8711
LT8711
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
INTVEE vs Temperature
INTVEE UVLO vs Temperature
INTVEE Current Limit vs BIAS
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
3.9
3.8
3.7
3.6
3.5
80
70
60
50
40
30
20
10
0
I
= 10mA
INTVEE
RISING
FALLING
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
5
10
15
20
25
30
35
40
TEMPERATURE (°C)
TEMPERATURE (°C)
BIAS (V)
8711 G19
8711 G20
8711 G21
INTVEE Dropout (BIAS = 6V)
IQ_BURST vs VIN or EXTVCC
IQ_BURST vs Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
18
16
14
12
10
20.00
18.00
16.00
14.00
12.00
10.00
BIAS = 6V
0
10
20
30
40
50
60
5
10
15
20
25
30
35
40
–50 –25
0
25
50
75 100 125
INTV LOAD CURRENT (mA)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
EE
8711 G22
8711 G23
8711 G24
8711f
7
For more information www.linear.com/LT8711
LT8711
pin FuncTions (TSSOP/QFN)
EN/FBIN (Pin 1/Pin 19): Enable and Input Voltage Regu-
lation Pin. In conjunction with the UVLO (undervoltage
lockout) circuit, this pin is used to enable/disable the chip
and restart the soft-start sequence. The EN/FBIN pin is
also used to limit the switching regulator current to avoid
collapsingtheinputsupply.Drivebelow0.2Vtodisablethe
chip with very low quiescent current. Drive above 1.03V
(typical) to activate the chip. The commanded input cur-
rent will adjust when the EN/FBIN pin voltage is between
1.12V and 1.27V. Drive above 1.35V (typical) to activate
switchingwithnoreductionininputcurrentandrestartthe
soft-start sequence. See the Block Diagram and Applica-
tions section for more information. Do not float this pin.
TG (Pin 10/Pin 8): PFET Gate Drive Pin. Low and high
levels are INTV and BIAS respectively with a 2A drive
EE
capability.
BG (Pin 11/Pin 10): NFET Gate Drive Pin. Low and high
levels are GND and INTV respectively with a 2A drive
CC
capability.
NC (Pin 12/Pin 9): No Connection. Do not connect. Must
be floated.
INTV (Pin 13/Pin 12): 5V Dual Input LDO Regulator Pin.
CC
Must be locally bypassed with a minimum capacitance of
2.2µF to GND. Logic will choose to run INTV from the
CC
VIN or EXTV pins. A maximum 10mA external load can
CC
connect to the INTV pin. The undervoltage lockout on
FB (Pin 2/Pin 20): Feedback Input Pin. The LT8711 regu-
lates the FB pin to 0.8V. Connect the feedback resistor
divider tap to this pin.
CC
INTV is 3.6V (typical). The BG gate driver can begin
CC
switching when INTV exceeds 4.1V (typical).
CC
V
(Pin 14/Pin 13): Input Supply Pin. Must be locally
V (Pin 3/Pin 1): Error Amplifier Output Pin. Tie external
IN
C
bypassed. Can run down to 0V as long as EXTV > 4.5V.
compensation network to this pin.
CC
EXTV (Pin 15/Pin 14): Alternate Input Supply Pin.
SS (Pin 4/Pin 2): Soft Start Pin. Place a soft-start capaci-
tor here. Upon start-up, the SS pin will be charged by a
410k resistor to about 4.3V. During an overtemperature
or UVLO condition, the SS pin will be quickly discharged
to reset the part. Once those conditions are clear, the part
will attempt to restart.
CC
Must be locally bypassed. Can run down to 0V as long
as V > 4.5V.
IN
CSN & CSP (Pins 16 & 17/ Pins 15 & 16): Current Sense
Negative and Positive Input Pins Respectively. Kelvin
connect CSN and CSP pins to a sense resistor to limit
the input current. The maximum sense voltage at low
duty cycle is 50mV.
OPMODE (Pin 5/Pin 3): Topology Selection Pin. Tie this
pin to ground to select buck/ZETA mode. Tie to INTV
CC
to select SEPIC/boost mode. Tie to a 100pF capacitor to
NC (Pin 18/Pin 11): No Connection. Do not connect. Must
be floated.
GND to select nonsynchronous buck-boost mode.
ISP & ISN (Pins 6 & 7/ Pins 4 & 5): Current Sense Posi-
tive and Negative Input Pins respectively. Kelvin connect
ISP and ISN pins to a sense resistor.
SYNC (Pin 19/Pin 17): To synchronize the switching
frequency to an outside clock, simply drive this pin with
a clock. The high voltage level of the clock must exceed
1.3V, and the low level must be less than 0.4V. Drive this
pin to less than 0.4V to revert to the internal free running
clock. See the Applications Information section for more
information.
INTV (Pin 8/Pin 6): 5V Below BIAS LDO Regulator Pin.
EE
Must be locally bypassed with a minimum capacitance
of 2.2µF to BIAS. This pin sets the bottom rail for the TG
gate driver. The TG gate driver can begin switching when
BIAS – INTV exceeds 3.6V (typical).
EE
RT (Pin 20/Pin 18): Timing Resistor Pin. Adjusts the
LT8711’s switching frequency. Place a resistor from this
pin to ground to set the frequency to a fixed free running
level. Do not float this pin.
BIAS (Pin 9/Pin 7): Power Supply for the TG PFET Driver.
Must be locally bypassed with a minimum capacitance of
2.2µF to INTV . The BIAS pin sets the top rail for the TG
EE
gate driver.
GND (Pin 21/Pin 21): Ground. Must be soldered directly
to the local ground plane.
8711f
8
For more information www.linear.com/LT8711
LT8711
block DiagraM
C
INTVEE
V
IN
C
IN
V
IN
BIAS
LDO
UVLO
INTV
EE
BIAS
DRIVER
REV
COMP
TG
BG
LEVEL
SHIFT
M2
PFET
I
×
REC
+
–
BUCK/ZETA
BOOST/SEPIC
BUCK-BOOST
R
L1
R
SENSE
SENSE
CURRENT
SENSE
PROCESSOR
OPMODE
V
OUT
MODE
DETECTION
LOGIC
INTV
CC
DRIVER
I
× R
SW
SENSE
M1
NFET
IS CS
CSP
CSN
+
–
A1
A2
ISP
ISN
+
–
R
R
FB1
FB2
FB
+
–
R
R
IN1
EN/FBIN
C
OUT
0.88V
+
–
SS_L
1.35V
IN2
DIE
TEMP
165°C
+
–
UVLO
D1
D2
Q
LDO LOGIC
S
EXTV
R
CC
V
OUT
1.215V
REF
PWM
COMP
DISABLE
DRIVER
W3
W4
START-UP
AND
I
S
FAULT
LOGIC
C
INTVCC
LDO
INTV
CC
SYNC
RT
SYNC
RAMP
BLOCK
GENERATOR
ADJUSTABLE
OSCILLATOR
CLK
–
+
D6
D4
+
–
EN/FBIN
1.2V
R
T
EA2
EA1
0.8V
QUICK DISCHARGE
85mV
410k R CHARGE
+
–
SS_L
Q1
PNP
SS
V
C
8711 BD
C
SS
C
C
C
F
R
C
8711f
9
For more information www.linear.com/LT8711
LT8711
sTarT-up anD FaulT sequence
EN/FBIN < 1.0V (TYP) OR
AND EXTV < 4.5V OR
EN/FBIN > 1.0V (TYP) AND
V OR EXTV > 4.5V AND
IN
V
IN
CC
CC
T
> 165°C
T
< 160°C
JUNCTION
JUNCTION
CHIP OFF
• ALL SWITCHES OFF
INITIALIZE
• SS PULLED LOW
• INTV CHARGES UP
RESET
CC
EN/FBIN > 1.35V(TYP) AND
INTV > 4.1V (TYP) AND
CC
BIAS–INTV > 3.85V (TYP)
EE
(BUCK/BUCK-BOOST/ZETA)
RESET DETECTED
ACTIVE MODE
• SS CHARGES UP
RESET
RESET
• SS DISCHARGES QUICKLY
• SWITCHER DISABLED
SS < 50mV
BEGIN SWITCHING
RESET OVER
• NFET BEGINS SWITCHING
• PFET BEGINS SWITCHING
• NO RESET CONDITIONS
DETECTED
WHEN INTV REGULATOR
EE
IS OUT OF UVLO
RESET = UVLO ON V OR EXTV (<4.5V MAX)
IN
CC
UVLO ON INTV (<3.6V TYP)
CC
UVLO ON INTV (BUCK/BUCK-BOOST/ZETA) (<3.6V TYP)
EE
EN/FBIN < 1.35V (TYP) AT 1ST POWER-UP
EN/FBIN < 1.00V (TYP) AFTER ACTIVE MODE SET
STATUS CHANGE ON OPMODE PIN
OVERTEMPERATURE (T > 165°C)
J
8711 F01
Figure 1. State Diagram
8711f
10
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LT8711
operaTion
OPERATION—OVERVIEW
latched so that if EN/FBIN drops between 1.03V to 1.35V
(typical), the SS pin is not pulled low by the EN/FBIN pin.
The EN/FBIN pin is also used for input voltage regulation
which is at 1.200V (typical). Input voltage regulation is
explained in more detail in the Operation—Regulation
section. Taking the EN/FBIN pin below 0.2V shuts down
the chip, resulting in extremely low quiescent current.
See Figure 2 that illustrates the different EN/FBIN voltage
thresholds.
TheLT8711usesaconstantfrequency,currentmodecon-
trol scheme to provide excellent line and load regulation.
Thepart’sundervoltagelockout(UVLO)function,together
with soft-start, offers a controlled means of starting up.
Output voltage and input voltage have control over the
commanded peak current which allows a wide range of
applications to be built using the LT8711. Synchronous
switching makes high efficiency and high output cur-
rent applications possible. When operating at light load
condition, the LT8711 will enter burst mode to minimize
switching loss. Refer to the Block Diagram and the State
Diagram (Figure 1) for the following description of the
part’s operation.
ACTIVE MODE
(NORMAL OPERATION)
(MODE LATCHED UNTIL EN/FBIN DROPS BELOW
CHIP ENABLE TRESHOLD)
1.42V
ACTIVE MODE THRESHOLD
(TOLERANCE)
1.28V
NORMAL OPERATION IF ACTIVE MODE SET
1.27V
INPUT VOLTAGE REGULATION
(ONLY IF ACTIVE MODE SET)
OPERATION—TOPOLOGY SELECTING
1.12V
The8711canbeconfiguredasasynchronousbuck,boost,
SEPIC, ZETAornonsynchronousbuck-boostconverterby
configuration of the OPMODE pin.
SWITCH OFF, INTV AND INTV ENABLED, SS CAP
CC
EE
DISCHARGED IF ACTIVE MODE NOT SET
1.11V
0.94V
CHIP ENABLE THRESHOLD
(HYSTERSIS AND TOLERANCE)
WhentheOPMODEpinisconnectedtoGND,thecontroller
operates in buck/ZETA mode.
LOCKOUT
(SWITCH OFF, SS CAP DISCHARGED, INTV AND
CC
INTV DISABLED)
EE
When the OPMODE pin is connected to the INTV pin,
CC
0.2V
0V
the controller operates in SEPIC/boost mode.
SHUTDOWN
(LOW QUIESCENT CURRENT)
When the OPMODE pin is tied to a 100pF capacitor to
GND, the controller operates in nonsynchronous buck-
boost mode.
8711 F03
Figure 2. EN/FBIN Modes of Operation
Undervoltage Lockout (UVLO)
TheLT8711hasinternalUVLOcircuitrythatdisablesthechip
OPERATION—START-UP
when the greater of V or EXTV < 3.6V (typical). The EN/
IN
CC
Several functions are provided to enable a very clean
start-up of the LT8711.
FBIN pin can also be used to create a configurable UVLO.
Soft-Start of Switch Current
Precise Turn-On Voltages
The soft-start circuitry provides for a gradual ramp-up of
the switch current (refer to Max Current Limit vs SS in
Typical Performance Characteristics). When the part is
brought out of shutdown, the external SS capacitor is first
discharged which resets the states of the logic circuits in
the chip. Once the chip is in active mode, an integrated
410k resistor pulls the SS pin to ~4.3V at a ramp rate set
by the external capacitor connected to the pin. Typical
valuesforthesoft-startcapacitorrangefrom100nFto1μF.
The EN/FBIN pin has two voltage levels for activating the
part: one that enables the part and allows internal rails
to operate and a 2nd voltage threshold which activates
a soft-start cycle and switching can begin. To enable the
part, take the EN/FBIN pin above 1.03V (typical). This
comparator has 50mV of hysteresis to protect against
glitches and slow ramping. To activate a soft-start cycle
and allow switching, take EN/FBIN above 1.35V (typical).
When EN/FBIN exceeds 1.35V (typical), the logic state is
8711f
11
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LT8711
operaTion
OPERATION—REGULATION
Input Voltage Regulation
Use the Block Diagram when stepping through the follow-
ing description of the LT8711 operating in regulation. The
LT8711 has two modes of regulation:
A resistor divider from the converter’s input voltage to
the EN/FBIN pin sets the input voltage regulation point.
The EN/FBIN pin voltage connects to the positive input of
amplifier EA2. The V pin voltage is set by EA2, which is
C
1. Output Voltage (via FB pin)
the amplified difference between the EN/FBIN pin voltage
and an internal 1.200V reference voltage. In this manner,
the EN/FBIN error amplifier sets the correct peak current
level to maintain input voltage regulation.
2. Input Voltage (via EN/FBIN pin)
Both of these regulation loops control the peak com-
manded current. At the start of each oscillator cycle, the
SR latch is set, which first turns off the external rectifier
switch (NFET in Block Diagram), and then turns on the
external main switch (PFET in Block Diagram). The PFET’s
current flows through an external current sense resistor
(RSENSE) generating a voltage proportional to the PFET
switch current. This voltage is then amplified by A1 and
added to a stabilizing ramp. The resulting sum is fed into
the positive terminal of the PWM comparator. When the
voltage on the positive input of the PWM comparator ex-
OPERATION—RESET CONDITIONS
TheLT8711hasthreeresetcases.Whenthepartisinreset,
the SS pin is pulled low and both power switches, NFET
and PFET, are forced off. Once all of the reset conditions
are gone, the part is allowed to begin a soft-start sequence
andswitchingcancommence.Eachofthefollowingevents
can cause the LT8711 to be in reset:
1. UVLO
ceeds the voltage on the negative input (V pin), the SR
C
latch is reset, turning off the PFET and then turning on the
a. ThegreaterofV andEXTV is<4.5V(maximum)
IN
CC
NFET. The voltage on the V pin is controlled by one of the
C
b. UVLO on INTV . INTV < 3.6V (typical)
CC
CC
regulation loops, or a combination of regulation loops.
c. UVLO on INTV . V
– V
< 3.6V (typical)
INTVEE
EE BIAS
Slope compensation provides stability in constant fre-
quency current mode control architectures by preventing
subharmonic oscillations at high duty cycles. This is ac-
complished internally by adding a compensating ramp to
the positive terminal of the PWM comparator.
unless BOOST/SEPIC topology is selected
d. EN/FBIN < 1.35V (typical) at first power-up
e. EN/FBIN < 1.00V (typical) after active mode set
2. OPMODE pin status changes
Output Voltage Regulation
3. Die Temperature > 165°C
The error amplifier servos the V node by comparing the
C
voltage on the FB pin with an internal 0.800V reference.
When the load current increases it causes a reduction in
the feedback voltage relative to the reference causing the
OPERATION—POWER SWITCH CONTROL
The external PFET and NFET switches are never on at the
same time (except buck-boost mode), and there is a non-
overlap time of about 100ns to prevent cross conduction.
error amplifier to raise the V voltage. In this manner, the
C
FB error amplifier sets the correct peak current level to
maintain output voltage regulation.
8711f
12
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LT8711
operaTion
Light Load Operation Modes
OPERATION—LDO REGULATORS (INTV AND INTV )
CC EE
The SYNC pin can be used to tell the LT8711 to operate
in FCM regardless of load current, or operate in DCM and
Burst Mode at light loads.
The INTV LDO regulates at 5.0V (typical) and is used
CC
as the top rail for the BG gate driver. The INTV LDO can
CC
run from V or EXTV and will intelligently select to run
IN
CC
from the best rail to minimize power loss in the chip, but
SYNC = logic high: FCM
at the same time, select the proper input for maintaining
SYNC = logic low: DCM or Burst Mode operation
INTV as close to 5.0V as possible. The INTV regulator
CC
CC
also has safety features to limit the power dissipation in
theinternalpassdeviceandalsotopreventitfromdamage
if the pin is shorted to ground. The UVLO threshold on
IfaclockisappliedtotheSYNCpinthepartwillsynchronize
to an external clock frequency and operate in FCM mode.
INTV is 3.6V (typical), and the LT8711 will be in reset
CC
OPERATION—AUTOMATIC LOW NOISE Burst Mode
OPERATION
until the LDO comes out of UVLO.
The INTV regulator regulates to 5.15V (typical) below
EE
At no load or very light load condition, high FB voltage
the BIAS pin voltage. The BIAS and INTV voltages are
EE
causes V to decrease. When V voltage is lower than a
C
C
used for the top and bottom rails of the TG gate driver
threshold voltage, the controller operates in Burst Mode
to minimize switching loss. Between bursts, all circuitry
associated with controlling the output switch is shut
down, reducing the average input supply current to 15μA
in a typical application. Low standby power and higher
conversion efficiency is thus achieved. To optimize the
quiescent current performance at light loads, the current
in the feedback resistor divider must be minimized as it
appears to the output as load current.
respectively. Just like the INTV regulator, the INTV
CC
EE
regulatorhasasafetyfeaturetolimitthepowerdissipation
in the internal pass device. The TG pin can begin switch-
ing only after the INTV regulator comes out of UVLO
EE
(3.85V typical across the BIAS and INTV pins). When
EE
the INTV regulator is in UVLO, for the boost and SEPIC
EE
topologies, the bottom switch is allowed to switch. The
output current would flow through the body diode of the
PFET. To protect the PFET from thermal damage under this
condition, the peak commanded current is folded back to
25mV (maximum) across the CSP-CSN pins.
8711f
13
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LT8711
applicaTions inForMaTion
BUCK CONVERTER COMPONENT SELECTION
Table 1. Buck Design Equations
Parameters/Equations
The LT8711 can be configured as a buck converter as in
Figure 3.
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
Step 2: DC
For a desired output current and output voltage over a
given input voltage range, Table 1 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a buck converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 1.
MAX
VOUT
DCMAX
≅
V
IN MIN
(
)
Step 3: V
Step 4: R
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find V
CSPN
at DC
.
CSPN
MAX
SENSE
VCSPN
IOUT
R
SENSE ≤ 0.75 •
Step 5: L
Variable Definitions:
RSENSE • V
– VOUT
)
(
)
IN MIN
VOUT
(
LTYP
LMIN
LMAX
=
=
•
V
V
V
= Minimum Input Voltage
= Maximum Input Voltage
12.5m• f
VIN MIN
IN(MIN)
IN(MAX)
(
)
RSENSE • VIN MIN 2VOUT – V
IN MIN
(
)
(
)
•
40m• f
VOUT
= Output Voltage
OUT
OUT
RSENSE • V
– VOUT
(
)
IN MIN
VOUT
(
)
I
= Output Current of Converter
=
•
2.5m• f
VIN MIN
(
)
f = Switching Frequency
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
and L
DC
= Power Switch Duty Cycle at V
MAX
IN(MIN)
L
TYP
.
MIN
V
CSPN
= Current Limit Voltage at DC
MAX
Step 6: C
OUT
IN
1–DCMIN
8 •L • f2 • 0.005
V
IN
COUT ≥
5V TO
40V
C
IN
10µF
×5
V
IN
EN/FBIN
BIAS
Step 7: C
2.2µF
IOUT •DCMAX
CIN
≥
EXTV
CC
INTV
f • ∆V
V
EE
OUT
IN
LT8711
OPMODE
∆V is acceptable maximum input ripple voltage.
IN
TG
M1
L1
R
SENSE
2.2µF
Step 8: R /R
4.7µH 4.5mΩ
V
3.3V,
6.5A
FB1 FB2
OUT
⎛
⎜
⎝
⎞
VOUT
0.8V
INTV
CC
RFB1
=
– 1 •R
⎟
FB2
⎠
R 60.4k
T
M2
BG
RT
C
OUT
Step 9: R
T
SYNC
SS
GND
100µF
×2
25000
f
RT =
– 2: f is in kHz and RT is in kΩ
47nF
CSP
CSN
ISP
R
1M
FB1
68pF
NOTE: The final values for C
and C may deviate from the above
IN
OUT
equations in order to obtain desired load transient performance for a
particular application. The C and C equations assume zero ESR, so
1.5nF
R
316k
FB2
ISN
51k
OUT
IN
V
C
increase the capacitance accordingly based on the combined ESR.
FB
8711 F03
ADDITIONAL 470µF, 6.3V ELECTROLYTIC CAP ON V
OUT
47µF, 50V ELECTROLYTIC CAP ON V
IN
Figure 3. Buck Converter—The Component Values Given Are
Typical Values for a 400kHz, 5V–40V to 3.3V/6.5A Buck
8711f
14
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LT8711
applicaTions inForMaTion
BOOST CONVERTER COMPONENT SELECTION
Table 2. Boost Design Equations
Parameters/Equations
The LT8711 can be configured as a boost converter as
in Figure 4.
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
Step 2: DC
For a desired output current and output voltage over a
given input voltage range, Table 2 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a boost converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 2.
MAX
V
IN MIN
(
)
DCMAX ≅ 1–
VOUT
Step 3: V
Step 4: R
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find V
CSPN
at DC
.
CSPN
MAX
SENSE
VCSPN
IOUT
R
SENSE ≤ 0.63 •
1–DC
(
MAX
)
Step 5: L
Variable Definitions:
⎛
⎞
R
SENSE • VIN MIN
VIN MIN
(
)
(
)
⎜
⎟
LTYP
=
=
• 1–
⎜
⎝
⎟
12.5m• f
VOUT
V
V
V
I
= Minimum Input Voltage
= Maximum Input Voltage
⎠
IN(MIN)
IN(MAX)
⎛
⎜
⎞
⎟
⎟
V
RSENSE • VOUT
40m• f
IN MIN
(
)
LMIN
• 1–
⎜
⎝
VOUT – V
IN MIN
(
)
⎠
= Output Voltage
OUT
⎛
⎞
R
SENSE • VIN MIN
VIN MIN
(
)
(
)
= Output Current of Converter
⎜
⎟
OUT
LMAX1
=
=
• 1–
⎜
⎝
⎟
5m• f
VOUT
⎠
f = Switching Frequency
⎛
⎞
RSENSE • VIN MAX
VIN MAX
(
)
(
)
⎜
⎟
LMAX2
• 1–
DC
= Power Switch Duty Cycle at V
IN(MIN)
= Current Limit Voltage at DC
MAX
⎜
⎝
⎟
MAX
5m• f
VOUT
⎠
V
CSPN
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
and L . The maximum of the L value range
V
IN
10.8V TO
13.2V
L
TYP
MIN
C
10µF
×6
IN
is the lower of L
.
MAX
EN/FBIN
V
CSP
ISP
ISN
CSN
IN
R
Step 6: C
SENSE
4mΩ
OUT
IN
IOUT •DCMAX
f • 0.005 • VOUT
EXTV
CC
V
COUT
≥
OUT
LT8711
V
L1
8.2µH
OUT
2.2µF
OPMODE
Step 7: C
BIAS
DCMAX
V
24V,
3A
OUT
CIN
≥
M2
2.2µF
INTV
RT
8 •L • f2 • 0.005
CC
R
T
INTV
EE
60.4k
R
FB1
1M
Step 8: R /R
C
6.8µF
×4
FB1 FB2
OUT
⎛
⎜
⎝
⎞
VOUT
0.8V
SYNC
RFB1
=
– 1 •R
⎟
FB2
BG
GND
TG
M1
330nF
42pF
⎠
R
34k
FB2
SS
Step 9: R
T
25000
f
RT =
– 2: f is in kHz and RT is in kΩ
1nF
187k
NOTE: The final values for C
equations in order to obtain desired load transient performance for a
particular application. The C and C equations assume zero ESR, so
and C may deviate from the above
V
C
OUT
IN
FB
8711 F04
OUT
IN
ADDITIONAL 270µF, 50V ELECTROLYTIC CAP ON V
increase the capacitance accordingly based on the combined ESR.
OUT
47µF, 50V ELECTROLYTIC CAP ON V
IN
Figure 4. Boost Converter—The Component Values Given are
Typical Values for a 400kHz, 12V to 24V/3A Boost
8711f
15
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LT8711
applicaTions inForMaTion
SEPIC CONVERTER COMPONENT SELECTION
Table 3. SEPIC Design Equations
Parameters/Equations
The LT8711 can be configured as a SEPIC converter as
in Figure 5.
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
Step 2: DC
For a desired output current and output voltage over a
given input voltage range, Table 3 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a SEPIC converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 3.
MAX
VOUT
) + VOUT
DCMAX
≅
V
IN MIN
(
Step 3: V
Step 4: R
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find V
CSPN
at DC
.
CSPN
MAX
SENSE
VCSPN
R
SENSE ≤ 0.63 •
1–DC
MAX
(
)
IOUT
= R
R
= R
SENSE1
SENSE2
SENSE
Variable Definitions:
Step 5: L
VIN MIN
RSENSE • VOUT
12.5m• f
(
)
V
V
V
= Minimum Input Voltage
= Maximum Input Voltage
LTYP
=
=
•
IN(MIN)
IN(MAX)
VIN MIN + VOUT
(
)
2
⎛
⎞
⎟
⎟
⎟
⎛
⎞
V
RSENSE • VOUT
40m• f
IN MIN
(
)
⎜
= Output Voltage
⎜
⎟
⎟
LMIN
• 1–
OUT
OUT
⎜
⎜
⎜
VOUT
⎝
⎠
⎝
⎠
I
= Output Current of Converter
V
RSENSE • VOUT
5m• f
IN MIN
(
)
LMAX
=
•
f = Switching Frequency
VIN MIN + VOUT
(
)
DC
V
= Power Switch Duty Cycle at V
= Current Limit Voltage at DC
MAX
IN(MIN)
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
and L . The maximum of the L value range
CSPN
MAX
L
TYP
MIN
L1
8.2µH
is the lower of L
.
MAX
V
IN
4.5V TO
40V
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors.
C
10µF
×2
V
OUT
IN
EN/FBIN
V
BIAS
IN
C1
10µF
×3
2.2µF
Step 6: C1
C1 ≥ 10µF (Typical); V
> V
RATING IN
R
2mΩ
SENSE
EXTV
CC
INTV
V
EE
OUT
V
12V,
4A
OUT
M2
LT8711
Step 7: C
OUT
IOUT •DCMAX
f • 0.005 • VOUT
2.2µF
COUT
≥
R
OPMODE
BG
M1
FB1
1M
L2
C
22µF
×3
OUT
INTV
RT
CC
15µH
R
T
118k
R
71.5k
FB2
Step 8: C
IN
CSP
DCMAX
8 •L • f2 • 0.005
CIN
≥
SYNC
R
SENSE1
2mΩ
470nF
4.7nF
CSN
GND
SS
100pF
49.9k
Step 9: R /R
FB1 FB2
⎛
⎜
⎝
⎞
VOUT
0.8V
RFB1
=
– 1 •R
⎟
FB2
TG
ISP
ISN
⎠
V
C
Step 10: R
FB
T
25000
f
RT =
– 2: f is in kHz and RT is in kΩ
8711 F05
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON V
56µF, 50V ELECTROLYTIC CAP ON V
OUT
IN
NOTE: The final values for C
and C may deviate from the above
OUT
IN
equations in order to obtain desired load transient performance for a
particular application. The C and C equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
Figure 5. SEPIC Converter—The Component Values Given Are
Typical Values for a 200kHz, 4.5V–40V to 12V/4A SEPIC
OUT
IN
8711f
16
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ZETA CONVERTER COMPONENT SELECTION
Table 4. ZETA Design Equations
Parameters/Equations
The LT8711 can be configured as a ZETA converter as in
Figure 6.
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
Step 2: DC
For a desired output current and output voltage over a
given input voltage range, Table 4 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a ZETA converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 4.
MAX
VOUT
DCMAX
≅
V
) + VOUT
IN MIN
(
Step 3: V
Step 4: R
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find V
CSPN
at DC
.
CSPN
MAX
SENSE
VCSPN
R
SENSE ≤ 0.63 •
1–DC
MAX
(
)
IOUT
= R
R
= R
SENSE1
SENSE2
SENSE
Variable Definitions:
Step 5: L
VIN MIN
RSENSE • VOUT
12.5m• f
(
)
V
V
V
= Minimum Input Voltage
= Maximum Input Voltage
LTYP
=
=
•
IN(MIN)
IN(MAX)
VIN MIN + VOUT
(
)
2
⎛
⎞
⎟
⎛
⎞
V
RSENSE • VOUT
40m• f
IN MIN
(
)
⎜
= Output Voltage
⎜
⎟
⎟
LMIN
• 1–
OUT
OUT
⎜
⎜
⎜
⎟
⎟
VOUT
⎝
⎠
⎝
⎠
I
= Output Current of Converter
V
RSENSE • VOUT
5m• f
IN MIN
(
)
LMAX
=
•
f = Switching Frequency
VIN MIN + VOUT
(
)
DC
V
= Power Switch Duty Cycle at V
= Current Limit Voltage at DC
MAX
IN(MIN)
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
and L . The maximum of the L value range
CSPN
MAX
L
TYP
MIN
V
is the lower of L
.
IN
5V TO
40V
MAX
C
IN
CSP
CSN
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors.
10µF
×6
R
EN/FBIN
V
BIAS
SENSE1
3.5mΩ
IN
2.2µF
EXTV
CC
INTV
V
EE
OUT
Step 6: C1
C1 ≥ 10µF (Typical); V
> V
RATING IN
LT8711
OPMODE
TG
2.2µF
L1A 2.2µH
Step 7: C
OUT
IN
IOUT •DCMAX
f • 0.005 • VOUT
INTV
COUT
≥
CC
C1
10µF ×3
R
T
V
118k
OUT
RT
CSP
CSN
CSP
CSN
12V,
L1B 2.2µH
3.5A (V > 16V)
SYNC
SS
IN
Step 8: C
DCMAX
8 •L • f2 • 0.005
2.5A (9V < V < 16V)
IN
470nF
CIN
≥
BG
1.5A (V < 9V)
IN
R
ISN
FB1
100pF
1M
C
22µF
×4
OUT
R
SENSE2
3.5mΩ
Step 9: R /R
FB1 FB2
⎛
⎜
⎝
⎞
VOUT
0.8V
2.2nF
R
FB2
69.8k
ISP
GND
20k
RFB1
=
– 1 •R
⎟
FB2
V
C
⎠
FB
8711 F06
Step 10: R
T
25000
f
RT =
– 2: f is in kHz and RT is in kΩ
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON V
OUT
56µF, 50V ELECTROLYTIC CAP ON V
IN
NOTE: The final values for C
and C may deviate from the above
IN
OUT
equations in order to obtain desired load transient performance for a
particular application. The C and C equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
Figure 6. ZETA Converter—The Component Values Given Are
Typical Values for a 200kHz, 5V–40V to 12V/3.5A ZETA
OUT
IN
8711f
17
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BUCK-BOOST CONVERTER COMPONENT SELECTION
Table 5. Buck-Boost Design Equations
Parameters/Equations
The LT8711 can be configured as a buck-boost converter
as in Figure 7.
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
Step 2: DC
For a desired output current and output voltage over a
given input voltage range, Table 5 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a buck-boost converter. Refer to more
detail in this section and the Appendix for further informa-
tion on the design equations presented in Table 5.
MAX
VOUT
) + VOUT
DCMAX
≅
V
IN MIN
(
Step 3: V
Step 4: R
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find V
CSPN
at DC
.
CSPN
MAX
SENSE
VCSPN
R
SENSE ≤ 0.63 •
1–DC
MAX
(
)
IOUT
= R
R
= R
SENSE1
SENSE2
SENSE
Variable Definitions:
Step 5: L
VIN MIN
RSENSE • VOUT
12.5m• f
(
)
V
V
V
= Minimum Input Voltage
= Maximum Input Voltage
LTYP
=
=
•
IN(MIN)
IN(MAX)
VIN MIN + VOUT
(
)
2
⎛
⎞
⎟
⎟
⎟
⎛
⎞
V
RSENSE • VOUT
40m• f
IN MIN
(
)
⎜
= Output Voltage
⎜
⎟
⎟
LMIN
• 1–
OUT
OUT
⎜
⎜
⎜
VOUT
⎝
⎠
⎝
⎠
I
= Output Current of Converter
V
RSENSE • VOUT
5m• f
IN MIN
(
)
LMAX
=
•
f = Switching Frequency
VIN MIN + VOUT
(
)
DC
V
= Power Switch Duty Cycle at V
= Current Limit Voltage at DC
MAX
IN(MIN)
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
and L . The maximum of the L value range
CSPN
MAX
L
TYP
MIN
is the lower of L
.
MAX
V
IN
5V TO
40V
Step 6: C
Step 7: C
C
10µF
×6
OUT
IN
IOUT •DCMAX
f • 0.005 • VOUT
COUT ≥
EN/FBIN
V
BIAS
IN
2.2µF
EXTV
CC
LT8711
OPMODE
INTV
V
EE
OUT
100pF
IN
TG
DCMAX
8 •L • f2 • 0.005
M1
L1 4.7µH
V
OUT
12V,
CIN
≥
D2
2.2µF
3.5A (V >16V)
IN
INTV
2.5A (9V < V < 16V)
IN
CC
R
T
D1
R
1.5A (V < 9V)
IN
Step 8: R /R
FB1
FB1 FB2
60.4k
⎛
⎜
⎝
⎞
VOUT
0.8V
ISN
1M
RT
RFB1
=
– 1 •R
⎟
FB2
C
OUT
R
⎠
SENSE2
4mΩ
SYNC
SS
100µF
×2
330nF
100pF
2.2nF
R
FB2
ISP
GND
69.8k
Step 9: R
T
25000
f
M2
R
RT =
– 2: f is in kHz and RT is in kΩ
BG
CSP
CSN
10nF
10Ω
110k
SENSE1
NOTE: The final values for C
equations in order to obtain desired load transient performance for a
particular application. The C and C equations assume zero ESR, so
and C may deviate from the above
10Ω
10nF
OUT
IN
V
C
4mΩ
FB
OUT
IN
8711 F07
increase the capacitance accordingly based on the combined ESR.
Figure 7. Buck-Boost Converter—The Component Values
Given Are Typical Values for a 400kHz, 5V–40V to 12V/2.5A
Buck-Boost
8711f
18
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SETTING THE OUTPUT VOLTAGE REGULATION
The LT8711 output voltage is set by a resistor divider
FROM SYSTEM
V
OUT
LT8711
FB
R
FB1
between V , FB, and GND.
OUT
+
–
EA1
⎛
⎞
⎟
⎠
RFB1
RFB2
R
FB2
R2
0.8V
INTV
5V
VOUT = 0.8V • 1+
⎜
CC
⎝
V
C
R
NTC
where R and R are shown in the Block Diagram.
FB1
FB2
See the Electrical Characteristics for tolerances on the FB
regulation voltage.
R1
8711 F08
Figure 8. Temperature Dependent Output Using an
NTC Resistor Divider
SETTING THE INPUT VOLTAGE REGULATION OR
UNDERVOLTAGE LOCKOUT
TheFBvoltagesregulatesto0.8V(typical).Foranaccurate
room temperature output voltage, size the resistor divider
By connecting a resistor divider between V , EN/FBIN,
IN
and GND, the EN/FBIN pin provides a means to regulate
the input voltage or to create an undervoltage lockout
function. Referring to error amplifier EA2 in the block
diagram, when EN/FBIN is lower than the 1.2V reference,
offtheINTV pintogive0.8Vsuchthatthecurrentthrough
CC
R2 is ~0 at room temperature. Choose R
and use the equations below to calculate R1, R , and
at room temperature and R
change over temperature.
≤ 10kΩ
FB1
for a desired V
NTC(25)
V
OUT
FB2
OUT
V is pulled low. For example, if V is provided by a
C
IN
relatively high impedance source (e.g. a solar panel) and
0.8V
the current draw pulls V below a preset limit, V will be
IN
C
R1=R
NTC(25) 5.0V – 0.8V
reduced,thusreducingcurrentdrawfromtheinputsupply
and limiting the input voltage drop.
RFB1
R2
VOUT ≅ 0.8V+
To set the minimum or regulated input voltage use:
⎛
⎞
⎛
⎞
⎟
⎠
R1
RFB1
RFB2
RIN1
RIN2
⎜
⎟
• 0.8V – 5.0V •
+0.8V •
V
= 1.2V • 1+
⎜
⎜
⎝
⎟
IN MIN–REG
(
)
R1+RNTC(25)
⎠
⎝
⎛
⎞
where R and R are shown in the Block Diagram.
1
T
1
T
25
IN1
IN2
β•
–
⎜
⎝
⎟
⎠
R
NTC =RNTC 25) • e
(
Temperature Dependent Output Voltage Using NTC
Resistor
R
∆VOUT = –5.0V • FB1 •R1
R2
Itmaybedesirabletoregulatetheconverter’soutputbased
⎛
⎞
on the ambient temperature. The INTV LDO regulated
1
1
CC
⎜
⎟
•
–
voltage is 5.0V 4% (see Electrical Characteristics), and
a negative temperature coefficient (NTC) resistor can be
used to sum into the FB pin to create an output voltage
that decreases with temperature. See Figure 8 for the
necessary connections.
⎜
⎟
R1+RNTC(T(MAX)) R1+RNTC(T(MIN))
⎝
⎠
–5.0V
∆VOUT
R2 =
•RFB1 •R1
⎛
⎞
1
1
⎜
⎟
•
–
⎜
⎟
R1+RNTC(T(MAX)) R1+RNTC(T(MIN))
⎝
⎠
8711f
19
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where:
ISP-ISN CURRENT SENSING
R
ß
= Resistance of the NTC resistor at 25°C
CSP/CSN current sensing is used in switching regulator
peak current control.
NTC(25)
= Material-specific constant of NTC resistor.
Specified at two temperatures such as
ISP/ISN current sensing monitors the current of the rec-
tifier switch and helps protect the circuit from overload
conditions.
ß
. If more than two ßs are specified,
25/85
usethemostappropriatefortheapplication.
T
= Absolute temperature in Kelvin
TheISP-ISNcircuitrydelaysswitchingiftherectifierswitch
current goes too high. This mechanism also protects
the part during short-circuit and overload conditions by
keeping the current through the inductor under control.
T
25
= Room temperature in Kelvin (298.15K)
SWITCH CURRENT LIMIT (CSP-CSN CURRENT
SENSING)
Let’s see a buck mode example.
The external current sense resistor (R
) sets the maxi-
SENSE
C
V
EN/FBIN V BIAS
IN
IN
mum peak current. The maximum voltage across R
SENSE
is 50mV (typical) at very low switch duty cycles, and then
slope compensation decreases the current limit as the duty
cycle increases (see the Max Current Limit vs Duty Cycle
(CSP-CSN)plotintheTypicalPerformanceCharacteristics).
Theequationbelowgivestheswitchcurrentlimitforagiven
duty cycle and current sense resistor (find V
operating duty cycle in the plot mentioned).
EXTV
INTV
EE
CC
OUT
LT8711
TG
M1
M2
OPMODE
L1
R
SENSE
INTV
CC
R
T
BG
RT
at the
CSPN
SYNC
GND
SS
CSP
CSN
ISP
R
R
FB1
FB2
VCSPN
ISW LIMIT
=
C
OUT
(
)
RSENSE
Toprovideadesiredloadcurrentforanygivenapplication,
must be sized appropriately. The equation below
ISN
V
C
FB
8711 F09
R
SENSE
calculates R
for a desired output current:
SENSE
Figure 9. ISP-ISN Current Sensing Example
⎛
⎞
⎟
⎠
VCSPN
IOUT
iRIPPLE
RSENSE ≤0.74•η•
• 1–DC
(
• 1–
⎜
MAX
)
A potential controllability problem could occur under
short-circuit conditions without rectifier switch current
sensing. If the power supply output is short circuited, the
feedbackamplifier(EA)respondstothelowoutputvoltage
⎝
2
η
= Converter efficiency (assume ~90%)
V
= Max current limit voltage (see Max Current
Limit vs Duty Cycle (CSP-CSN) plot in the
Typical Performance Characteristics)
CSPN
by raising the control voltage, V , to its peak current limit
C
value. Ideally, the top switch would be turned on, and then
turned off as its current exceeded the value indicated by
I
= Converter load current
OUT
V . However, there is finite response time involved in both
C
DC
= Switching duty cycle at minimum V (see
Power Switch Duty Cycle in Appendix)
MAX
IN
thecurrentcomparatorandturnoffofthetopswitch.These
result in a minimum on time, t
. When combined
ON(MIN)
with high V , the potential exists for a loss of control.
i
= Peak-to-peak inductor ripple current percent-
IN
RIPPLE
age at minimum V (recommended to use
IN
25%)
8711f
20
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Expressed mathematically the requirement to maintain
control is:
as possible to the LT8711. Resistors greater than 10Ω
should be avoided as this can Increase the offset voltages
at the CSP/CSN and ISP/ISN pins.
V
R(SENSE)_L + VDS_NMOS +I•R
f • tON
≤
Table 6. CSP/CSN, ISP/ISN Bias Current:
V
IN
V
CM
= 0V
V
> 3V
CM
where:
f = switching frequency
= switch minimum on time
I_CSP (typ)
I_CSN (typ)
I_ISP (typ)
I_ISN (typ)
0µA
4µA ~ 25µA
110µA
–4µA ~ –25µA
0µA
4µA ~ 25µA
220µA
t
ON
–4µA ~ –25µA
V
V
= voltage drop on high side sense resistor
R(SENSE)_L
When V changes from 0V to 3V, bias current changes
gradually from low side values to high side values as
shown in Table 6.
CM
= voltage drop on high side PMOS switch
DS_NMOS
V = Input voltage
IN
I • R = inductor I • R voltage drop
CSN/ISN bias current at high side is proportional to tem-
perature (see the CSN/ISN Bias Current vs Temperature
plots in the Typical Performance Characteristics).
If this condition is not observed, the current will not be
limited at I , but will cycle-by-cycle ratchet up to some
PK
higher value. With rectifier switch current sensing, the
current through the inductor would be controlled under
thewholeclockcycle.Theswitchingwillonlyresumeonce
Positive bias currents flow into the pins. Negative bias
currents flow out of the pins.
Bias current of 4µA ~ 25µA and –4µA ~ –25µA in the
rectifier switch current has fallen below I .
PK
table changes according to the V voltage. 4µA (–4µA)
C
ISP-ISN current sensing is also used in reverse current
detecting for DCM operation.
corresponds to the minimum V voltage. 25µA (–25µA)
C
corresponds to the maximum V voltage.
C
5.1Ω
CURRENT SENSE FILTERING
CSP OR ISP
LT8711
Certain applications may require filtering of the current
sense signals due to excessive switching noise that can
R
, R
2.2nF
SENSE1 SENSE2
CSN OR ISN
5.1Ω
appear across R
and/or R
. Higher operating
SENSE1
SENSE2
8710 F10a
voltages,higherinductorcurrent,highervaluesofR
,
SENSE
andmorecapacitiveMOSFETswillallcontributeadditional
noise across R when MOSFETs transition. The CSP/
Figure 10a. Differential RC Filter on CSP/CSN and/or ISP/ISN Pins
SENSE
5.1Ω
CSN and/or the ISP/ISN sense signals can be filtered by
adding one of the RC networks shown in Figure 10. The
filter shown in Figure 10a filters out differential noise,
whereas the filter in Figure 10b filters out the differential
and common mode noise at the expense of an additional
capacitor and approximately twice the capacitance value.
It is recommended to Kelvin tie the ground connection
directly to the paddle of the LT8711 if using the filter in
Figure 10b. The filter network should be placed as close
CSP OR ISP
4.7nF
LT8711
R
, R
SENSE1 SENSE2
4.7nF
CSN OR ISN
5.1Ω
8711 F10b
Figure 10b. Differential and Common Mode RC Filter on CSP/
CSN and/or ISP/ISN Pins
8711f
21
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SWITCHING FREQUENCY
the SYNC pin is driven below 0.4V for a few free-running
clock periods. The LT8711 will operate in FCM mode with
internal free-running oscillator clock if driving SYNC high
for an extended period of time.
TheLT8711usesaconstantfrequencyarchitecturewhose
frequency can be between 100kHz and 750kHz. The fre-
quency can be set using the internal oscillator or can be
synchronized to an external clock source. Selection of
the switching frequency is a trade-off between efficiency
and component size. Low frequency operation increases
efficiency by reducing MOSFET switching losses, but
requires larger inductance and/or capacitance to maintain
low output ripple voltage. For high power applications,
consider operating at lower frequencies to minimize
MOSFET heating from switching losses. The switching
frequency can be set by placing an appropriate resistor
from the RT pin to ground and tying the SYNC pin low. The
frequency can also be synchronized to an external clock
source driven into the SYNC pin. The following sections
provide more details.
The duty cycle of the SYNC signal must be between 20%
and 80% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
1. SYNC may not toggle outside the frequency range of
140kHz to 750kHz unless it is stopped below 0.4V to
enable the free-running oscillator.
2. TheSYNCfrequencycanalwaysbehigherthanthefree-
running oscillator frequency (as set by the R resistor),
T
f
, but should not be less than 20% below f
.
OSC
OSC
LDO REGULATORS
The LT8711 has two linear regulators to run the BG and
TG gate drivers. The INTV LDO regulates 5V (typical)
CC
Oscillator Timing Resistor (RT)
above ground, and the INTV regulator regulates 5.15V
EE
The operating frequency of the LT8711 can be set by the
internal free-running oscillator. When the SYNC pin is
driven low (< 0.4V), the frequency of operation is set by a
resistorfromtheRTpintoground.Theoscillatorfrequency
is calculated using the following formula:
(typical) below the BIAS pin.
INTV LDO Regulator
CC
The INTV LDO is used as the top rail for the BG gate
CC
driver. An external capacitor greater than 2.2μF must be
25000
RT +2
placedfromtheINTV pintoground.Thecapacitorshould
CC
f =
have low ESR, such as a ceramic capacitor.
The INTV LDO can run off V or EXTV and will
where f is in kHz and R is in kΩ. Conversely, R can
CC
IN
CC
T
T
intelligently select to run off the best rail for minimizing
be calculated from the desired frequency using:
chip power loss, but at the same time, select the proper
25000
input for maintaining INTV as close to 5V as possible.
CC
RT =
– 2
For example, Figure 11 is a plot that shows how V or
f
IN
EXTV is selected.
CC
Clock Synchronization
Overcurrent protection circuitry typically limits the maxi-
mum current draw from the LDO to ~50mA. If the selected
inputvoltageisgreaterthan24V(typical), thenthecurrent
limit of the LDO reduces linearly with input voltage to limit
An external source can set the operating frequency of
the LT8711 by providing a digital clock signal into the
SYNC pin (RT resistor still required). The LT8711 will
operate at the SYNC clock frequency. The LT8711 will
revert to its internal free-running oscillator clock when
the maximum power in the INTV pass device. See the
CC
INTV Current Limit vs V or EXTV plot in the Typical
CC
IN
CC
Performance Characteristics.
8711f
22
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LT8711
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EXTV
CC
Overcurrent protection circuitry typically limits the maxi-
mum current draw from the regulator to ~80mA. If the
BIAS voltage is greater than15V (typical), then the current
limit of the regulator reduces linearly with input voltage
40V
to limit the maximum power in the INTV pass device.
EE
See the INTV Current Limit vs BIAS plot in the Typical
EE
POWERED BY V
IN
Performance Characteristics.
POWERED BY EXTV
CC
ThesamethermalguidelinesfromtheINTV LDORegula-
CC
tor section apply to the INTV regulator as well.
EE
5.5V
0
V
IN
NONSYNCHRONOUS CONVERTER
0
5.5V
40V
V
, EXTV POWER SELECTION
CC
8711 F11
IN
It may be desirable in some applications to replace the
external PFET with a Schottky diode to make a nonsyn-
chronous converter. One example would be a high output
voltage application because the voltage drop across the
rectifierhasasmalleffectontheefficiencyoftheconverter.
In fact, for high output voltage applications, replacing
the PFET with a Schottky may result in higher efficiency
because the LT8711 doesn’t have to supply gate drive to
the PFET. Figure 12 shows the recommended connec-
tions for using the LT8711 as a nonsynchronous boost
converter, however the same concept can be used for any
other converter topology.
Figure 11. INTVCC Input Voltage Selection
PowerdissipatedintheINTV LDOshouldbeminimizedto
CC
improveefficiencyandpreventoverheatingoftheLT8711.
The current limit reduction with input voltage circuit helps
prevent the part from overheating, but these guidelines
should be followed. The maximum current drawn through
the INTV LDO occurs under the following conditions:
CC
1. Large (capacitive) MOSFETs being driven at high
frequencies
2. The converter’s switch voltage (V for BUCK, V
V
IN
IN
OUT
for SEPIC
for BOOST and BUCK-BOOST, V + V
C
V
EN/FBIN V
CSP
ISP
ISN
CSN
IN
OUT
IN
IN
converters) is high, thus requiring more charge to
turn the MOSFET gates on and off.
R
SENSE
EXTV
CC
OUT
LT8711
OPMODE
V
OUT
L1
In general, use appropriately sized MOSFETs and lower
the switching frequency for higher voltage applications to
BIAS
V
C
OUT
INTV
INTV
CC
EE
keep the INTV current at a minimum.
CC
R
R
FB1
FB2
OUT
BG
GND
FB
M1
INTV LDO Regulator
EE
The BIAS and INTV voltages are used for the top and
EE
8711 F12
bottom rails of the TG gate driver respectively. An external
capacitor greater than 2.2μF must be placed between the
Figure 12. Simplified Schematic of a Nonsynchronous
Boost Converter
BIAS and INTV pins. The capacitor should have low
EE
ESR, such as ceramic capacitor.
8711f
23
For more information www.linear.com/LT8711
LT8711
applicaTions inForMaTion
LAYOUT GUIDELINES FOR BUCK, BOOST, SEPIC, ZETA
AND BUCK-BOOST TOPOLOGIES
BUCK Topology Specific Layout Guidelines
•
Keep length of loop (high speed switching path)
governing MN, MP, C , and ground return as short
IN
General Layout Guidelines
as possible to minimize parasitic inductive spikes at
the switch node during switching.
•
To optimize thermal performance, solder the ex-
posed pad of the LT8711 to the ground plane with
multiple vias around the pad connecting to additional
ground planes.
V
V
OUT
IN
L
•
•
High speed switching path (see specific topology
below for more information) must be kept as short
as possible.
PFET
R
SENSE
C
IN1
C
OUT1
NFET
The FB, V and RT components should be placed as
C
C
IN2
C
OUT2
GND
GND
close to the LT8711 as possible, while being far away
as practically possible from switching nodes. The
ground for these components should be separated
from the switch current path.
LT8711
•
•
Place bypass capacitors for the V and EXTV pins
IN CC
8711 F13
(1μF or greater) as close as possible to the LT8711.
Figure 13. Suggested Component Placement for Buck Topology
Place bypass capacitors for the INTV and INTV
CC
EE
(between BIAS and INTV ) pins (2.2μF or greater) as
EE
close as possible to the LT8711.
Boost Topology Specific Layout Guidelines
•
The load should connect directly to the positive and
negative terminals of the output capacitor for best
load regulation.
•
Keep length of loop (high speed switching path) gov-
erning MN, MP, C , and ground return as short as
OUT
possible to minimize parasitic inductive spikes at the
switch node during switching.
V
V
OUT
IN
R
SENSE
L
PFET
OUT2
C
IN1
C
OUT1
NFET
C
IN2
C
GND
GND
LT8711
8711 F13
Figure 14. Suggested Component Placement for Boost Topology
8711f
24
For more information www.linear.com/LT8711
LT8711
applicaTions inForMaTion
SEPIC Topology Specific Layout Guidelines
Buck-Boost Topology Specific Layout Guidelines
•
Keep length of loop (high speed switching path)
governing R , MN, C1, MP, R , C , and
•
Keep length of loop (high speed switching path)
governing R , DIO1, MP, C , and ground return
SENSE1
SENSE2 OUT
SENSE1
IN
groundreturnasshortaspossibletominimizeparasitic
as short as possible to minimize parasitic inductive
inductive spikes at the switch node during switching.
spikes at the switch node during switching.
•
Keep length of loop (high speed switching path) gov-
C1
L
V
V
OUT
IN
erning R
, MN, DIO2, C , and ground return
SENSE2
OUT
PFET
as short as possible to minimize parasitic inductive
spikes at the switch node during switching.
NFET
R
SENSE2
C
C
IN1
OUT1
L
V
V
OUT
IN
R
GND
GND
C
IN2
SENSE1
C
OUT2
PFET
DI01
DI02
NFET
C
IN1
C
OUT1
LT8711
R
R
C
IN2
C
OUT2
SENSE2 SENSE1
8711 F15
GND
GND
Figure 15. Suggested Component Placement for SEPIC Topology
LT8711
ZETA Topology Specific Layout Guidelines
8711 F17
•
Keep length of loop (high speed switching path)
governing R , MN, C1, MP, R , C , and
SENSE1
SENSE2 IN
Figure 17. Suggested Component Placement for Buck-Boost Topology
groundreturnasshortaspossibletominimizeparasitic
inductive spikes at the switch node during switching.
Current Sense Resistor Layout Guidelines
L
•
Route the CSP/CSN and ISP/ISN lines differentially
(close together) from the chip to the current sense
resistor as shown in Figure 17.
C
V
V
OUT
IN
PFET
•
Place the vias that connect the CSP/CSN and ISP/ISN
lines directly at the terminals of the current sense
resistor as shown in Figure 17.
R
NFET
SENSE2
C
C
IN1
OUT1
R
GND
GND
C
IN2
SENSE1
C
OUT2
R
SENSE1, 2
LT8711
TO
CURRENT
SENSE
PINS
8705 F20
8711 F16
Figure 18. Suggested Routing and Connections of
CSP/CSN and ISP/ISN Lines
Figure 16. Suggested Component Placement for ZETA Topology
8711f
25
For more information www.linear.com/LT8711
LT8711
applicaTions inForMaTion
THERMAL CONSIDERATIONS
The following applies for both the NFET and PFET power
switches. Below are the equations for the power loss in
MN and MP.
Overview
The primary components on the board that consume the
most power and produce the most heat are the power
switches, MN and MP, the power inductor, the Schottky
diodes in the nonsynchronous buck-boost converter and
the LT8711 IC. It is imperative that a good thermal path
be provided for these components to dissipate the heat
generated within the packages. This can be accomplished
by taking advantage of the thermal pads on the underside
of the packages. It is recommended that multiple vias in
the printed circuit board be used to conduct heat away
from each of these components and into a copper plane
with as much area as possible. For the case of the power
switches,thecopperareaofthedrainconnectionsshouldn’t
be too big as to create a large EMI surface that can radiate
noise around the board.
PMOSFET =P2 +P
SWITCHING
I R
2
P
MN =IN •RDS ON + VDS •IN • f • tRF +P
RR–N
(
)
⎛
⎞
⎟
⎠
IVY
1.6
2
PMP =IP •RDS ON + V • I +
• f •140nx+P
RR–N
⎜
BD
PK
(
)
⎝
i
iRIPPLE
IPK =ISW
+
RIPPLE ; IVY =ISW
–
2
2
VDS •IRR • tRR • f
P
≈
≈
RR–N
2
VDS •IRR • tRR • f
P
RR–P
2
where:
f
= Switching Frequency
= NFET RMS Current
= PFET RMS Current
Power MOSFET Loss and Thermal Calculations
I
I
t
N
The LT8711 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. Important parameters for estimating
the power dissipation in the MOSFETs are:
P
= Average of the rise and fall times of the NFET’s
drain voltage
RF
I
I
I
= Average switch current during its on-time
= Peak inductor current
SW
PK
VY
1. On-resistance (R
)
DS(ON)
2. Gate-to-drain charge (Q )
GD
= Valley inductor current
3. PFET body diode forward voltage (V )
BD
i
= Inductor ripple current
RIPPLE
4. V of the FETs during their Off-Time
DS
DC
= Switchdutycycle(seePowerSwitchDutyCycle
section in Appendix)
5. Switch current (I
)
SW
6. Switching frequency (f)
V
V
P
= PFET body diode forward voltage at I
= Voltage across the FET when it’s off.
BD
SW
The power loss in each power switch has a DC and AC
term. The DC term is when the power switch is fully on,
and the AC term is when the power switch is transitioning
from on-off or off-on.
DS
= PFET body diode reverse recovery power loss
in the NFET
RR-N
8711f
26
For more information www.linear.com/LT8711
LT8711
applicaTions inForMaTion
P
RR-P
= PFET body diode reverse recovery power loss
in the PFET
The INTV LDO primarily supplies voltage for the BG
CC
gate driver. The BIAS and INTV voltages supply the top
EE
and bottom rails of the TG gate driver respectively. The
I
t
= Current needed to remove the PFET body diode
charge
RR
chip Q current comes from INTV . Below are the chip
CC
power equations:
= Reverse recovery time of PFET body diode
RR
P
P
P
= Q • f • V
MN
INTVCC_BG
SELECT
Typical values for t are 10ns to 40ns depending on the
RF
= 2mA • V
INTVCC_Q
SELECT
MOSFET capacitance and drain voltage. In general, the
lower the QGD of the MOSFET, the faster the rise and fall
times of its drain voltage. For best calculations, measure
the rise and fall times in the application.
= Q • f • V
BIAS
INTVEE
MP
where:
f
= Switching frequency
PFET body diode reverse recovery power loss is depen-
dent on many factors and can be difficult to quantify in
an application. In general, this power loss increases with
Q
MN
= Total gate charge of NFET power switch (MN)
Q
MP
= Total gate charge of PFET power switch (MP)
higher V and/or higher switching frequency.
DS
V
= INTV LDO selected input
CC
SELECT
voltage, V or EXTV (see LDO Regulators
IN
CC
Chip Power and Thermal Calculations
section)
Power dissipation in the LT8711 chip comes from three
Thermal Lockout
primary sources: INTV and INTV LDOs providing gate
CC
EE
drive to the BG and TG pins and the chip quiescent cur-
rent. Theaveragecurrentthrough eachLDOisdetermined
by the gate charge of the power switches, MN and MP,
and the switching frequency. Below are the equations for
calculating the chip power loss.
If the die temperature reaches ~165°C, the part will go
into shutdown, so the power switches turn off and the
soft-start capacitor will be discharged. The LT8711 will
come out of shutdown when the die temperature drops
by ~5°C (typical).
8711f
27
For more information www.linear.com/LT8711
LT8711
appenDix
POWER SWITCH DUTY CYCLE
INDUCTOR SELECTION
The external power main switch (PFET in the Block Dia-
gram)cannotremainofffor100%ofeachclockcycle, and
will turn on for a minimum on time (MinOnTime) when in
regulation. This MinOnTime governs the minimum allow-
able duty cycle given by:
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses.
Additionally,chooseinductorswithmorevolumeforagiven
inductance. The inductor should have low DCR (copper-
2
wire resistance) to reduce I R losses, and must be able
to handle the peak inductor current without saturating.
Note that in some applications, the current handling
requirements of the inductor can be lower, such as in the
SEPIC topology where each inductor carries a fraction of
the total switch current. Molded chokes or chip inductors
do not have enough core area to support peak inductor
currents in the 5A to 15A range. To minimize radiated
noise, use a toroidal or shielded inductor. See Table 7 for
a list of inductor manufacturers.
(MinOnTime)
DCMIN
=
•100%
T
P
where TP is the clock period and MinOnTime (found in
the Electrical Characteristics) is 100ns (typ).
Theapplicationshouldbedesignedsuchthattheoperating
duty cycle is higher than DC
.
MIN
Duty cycle equations for different topologies are given
below.
Table 7. Inductor Manufacturers
For the Buck topology (see Figure 3):
VOUT
Coilcraft
MSS1278, XAL1010, and
MSD1278 Series
www.coilcraft.com
DCBUCK
≅
Cooper
DRQ127, DR127, and
www.cooperbussmann.com
V
Bussmann HCM1104 Series
IN
Vishay
Würth
IHLP Series
www.vishay.com
For the Boost topology (see Figure 4):
WE-DCT Series
WE-CFWI Series
www.we-online.com
V
IN
DCBOOST ≅ 1–
VOUT
For the SEPIC topology (see Figures 6):
VOUT
Minimum Inductance
Although there can be a trade-off with efficiency, it is
often desirable to minimize board space by choosing
smaller inductors. When choosing an inductor, there are
two conditions that limit the minimum inductance; (1)
providing adequate load current, and (2) avoidance of
subharmonic oscillation.
DCSEPIC
≅
V + V
IN
OUT
For the ZETA topology (see Figures 7):
VOUT
DCZETA
≅
V + V
IN
OUT
Adequate Load Current
For the Buck-Boost topology (see Figures 8):
Small value inductors result in increased ripple currents
and thus, due to the limited peak switch current, decrease
the average current that can be provided to the load.
VOUT
DCBUCK−BOOST
≅
V + V
IN
OUT
8711f
28
For more information www.linear.com/LT8711
LT8711
appenDix
Avoiding Subharmonic Oscillations
IfoperatingclosetotheBV
ratingoftheMOSFET,check
DSS
theleakagespecificationsontheMOSFETbecauseleakage
can decrease the efficiency of the converter.
The LT8711’s internal slope compensation circuit will
prevent subharmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the in-
ductance exceeds a minimum value. In applications that
operate with duty cycles greater than 50%, the inductance
must be at least:
The NFET and PFET gate-to-source drive is 5V typical.
The BG gate driver can begin switching when the INTV
CC
voltage exceeds ~4.1V, so ensure the selected NFET is in
the linear mode of operation with 4.1V of gate-to-source
drive to prevent possible damage to the NFET.
V •R
• 2 •DC – 1
(
)
IN
SENSE
LMIN
LMIN
where
≥
≥
, Buck Topology
The TG gate driver can begin switching when the BIAS-
40m•DC • f
INTV voltage exceeds ~3.85V, so it is optimal that the
EE
V •R
• 2 •DC – 1
(
)
IN
SENSE
PFET be in the linear mode of operation with 3.85V of
gate-to-source drive. Try to choose a PFET with a low body
diode reverse recovery time to minimize stored charge in
the PFET. The stored charge in the PFET body diode gets
removed when the NFET switch turns on and can lead to
, Other Topologies
40m•DC • f • 1–DC
(
)
L
= L1 for buck, boost and buck-boost topologies
= L1 = L2 for coupled dual inductor topologies
MIN
efficiency hits especially in applications where the V of
DS
L
MIN
thePFET(duringoff-time)ishigh.Fortheseapplications,it
may be beneficial to put a Schottky diode across the PFET
to reduce the amount of charge in the PFET body diode.
(SEPIC and ZETA)
L
= L1 || L2 for uncoupled dual inductor topologies
MIN
(SEPIC and ZETA)
Power MOSFET on-resistance and total gate charge go
hand-in-hand and are typically inversely proportional to
each other; the lower the on-resistance, the higher the
total gate charge. Choose MOSFETs with an on-resistance
to give a voltage drop to be less than 300mV at the peak
current. At the same time, choose MOSFETs with a lower
total gate charge to reduce LT8711 power dissipation and
MOSFET switching losses.
Inductor Current Rating
The inductor(s) must have a rating greater than its (their)
peak operating current to prevent inductor saturation,
which would result in efficiency losses.
POWER MOSFET SELECTION
The LT8711 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. It is important to select MOSFETs for
optimizing efficiency. For choosing an NFET and PFET, the
important device parameters are:
The turn-off delay time (t
) of available NFETs is
D(OFF)
generally smaller than the LT8711’s non-overlap time.
However, the turn-off time of the available PFETs should
be looked at before deciding on a PFET for a given applica-
tion. The turn-off time must be less than the non-overlap
time of the LT8711 or else the NFET and PFET could be
on at the same time and damage to external components
may occur. If the PFET turn-off delay time as specified in
the data sheet is less than the LT8711 non-overlap time,
then the PFET is good to use. If the turn-off delay time is
longer than the non-overlap time, it doesn’t necessarily
mean it can’t be used. It may be unclear how the PFET
1. Breakdown voltage (BV
)
DSS
2. Gate threshold voltage (V
)
GSTH
3. On-resistance (R
)
DS(ON)
4. Total gate charge (Q )
G
5. Turn-off delay time (t
)
D(OFF)
6. Package has exposed paddle
8711f
29
For more information www.linear.com/LT8711
LT8711
appenDix
manufacturer measures the turn-off delay time, so it is
best to measure the PFET turn-off delay time with respect
to the PFET gate voltage.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
noise. A minimum 1μF ceramic capacitor should also be
placed from V to GND and from EXTV to GND as close
IN
CC
Finally, both the NFET and PFET power MOSFETs should
be in a package with an exposed paddle for the drain
connection to be able to dissipate heat. The on-resistance
of MOSFETs is proportional to temperature, so it’s more
efficient if the MOSFETs are running cool with the help
of the exposed paddle. See Table 8 for a list of power
MOSFET manufacturers.
to the LT8711 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce ripple voltage and help reduce power loss in the
higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic ca-
pacitors,particularly0805or0603casesizes,havegreatly
reduced capacitance at the desired operating voltage.
Table 8. Power MOSFET (NFET and PFET) Manufacturers
Fairchild Semiconductor
On-Semiconductor
Vishay
www.fairchildsemi.com
www.onsemi.com
www.vishay.com
COMPENSATION – ADjUSTMENT
To compensate the feedback loop of the LT8711, a series
resistorcapacitornetworkinparallelwithanoptionalsingle
capacitorshouldbeconnectedfromtheV pintoGND.For
Diodes Inc.
www.diodes.com
C
INPUT AND OUTPUT CAPACITOR SELECTION
most applications, choose a series capacitor in the range
of 0.47nF to 10nF with 2.2nF being a good starting value.
The optional parallel capacitor should range in value from
47pF to 220pF with 100pF being a good starting value.
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out of the regulator. A parallel combination of
capacitorsistypicallyusedtoachievehighcapacitanceand
low ESR (equivalent series resistance). Tantalum, special
polymer,aluminumelectrolyticandceramiccapacitorsare
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
The compensation resistor, R , is usually in the range
C
of 10k to 100k. A good technique to compensate a new
application is to use a 100k potentiometer in place of the
series resistor RC. With the series and parallel capacitors
at 2.2nF and 100pF respectively, adjust the potentiometer
while observing the transient response and the optimum
value for RC can be found. The series capacitor can be
reducedorincreasedfrom2.2nFtospeeduptheconverter
or slow down the converter, respectively.
8711f
30
For more information www.linear.com/LT8711
LT8711
Typical applicaTions
400kHz, 5V–40V Input to 3.3V/6.5A Buck
V
IN
5V TO
40V
C
10µF
×5
IN
EN/FBIN
V
BIAS
IN
2.2µF
EXTV
CC
INTV
V
EE
OUT
LT8711
OPMODE
TG
M1
L1
4.7µH
R
SENSE
5mΩ
2.2µF
V
OUT
INTV
CC
3.3V, 6.5A
R
60.4k
T
M2
BG
RT
C
OUT
SYNC
SS
GND
100µF
×2
47nF
CSP
CSN
ISP
R
FB1
68pF
1M
1.5nF
R
316k
FB2
ISN
51k
V
C
FB
8711 TA02a
L1: COILCRAFT 4.7µH XAL7070-472
M1: ST STL42P6LLF6
M2: FAIRCHILD FDMC86520L
C : 10µF, 50V, X7R
IN
ADDITIONAL 47µF, 50V ELECTROLYTIC CAP ON V
IN
C
: 100µF, 6.3V, X7R
OUT
ADDITIONAL 470µF, 16V ELECTROLYTIC CAP ON V
OUT
Efficiency vs Load Current
Transient Response with 2A to 5.5A to 2A Output Load Step
100
90
80
70
60
50
40
30
20
10
0
LOAD STEP
5A/DIV
V
OUT
200mV/DIV
I
L1
5A/DIV
V
V
V
V
= 5V
IN
IN
IN
IN
= 12V
= 24V
= 36V
8711 TA02c
200µs/DIV
0.001
0.01
0.1
1
7
LOAD CURRENT (A)
8711 TA02b
8711f
31
For more information www.linear.com/LT8711
LT8711
Typical applicaTions
400kHz, 12V Input to 24V/3A Boost Converter
V
IN
10.8V TO
13.2V
C
10µF
×6
IN
EN/FBIN V
CSP
ISP
IN
R
SENSE
ISN
CSN
4mΩ
EXTV
CC
V
OUT
LT8711
V
L1
OUT
2.2µF
8.2µH
M2
OPMODE
BIAS
V
OUT
2.2µF
INTV
RT
CC
24V, 3A
R
T
INTV
EE
60.4k
R
FB1
1M
C
OUT
SYNC
6.8µF
×4
BG
GND
TG
M1
330nF
42pF
R
34k
FB2
SS
1nF
187k
V
C
FB
8711 TA03a
L1: WÜRTH 8.2µH WE-HCI 7443550820
M1: INFINEON BSC026N04
M2: ST STL60P4LLF6
C : 10µF, 50V, X7R
IN
ADDITIONAL 47µF, 50V ELECTROLYTIC CAP ON V
IN
C
: 6.8µF, 50V, X7R
OUT
ADDITIONAL 270µF, 50V ELECTROLYTIC CAP ON V
OUT
Efficiency vs Load Current
Transient Response with 1A to 2.5A to 1A
Output Load Step (VIN = 12V)
100
90
80
70
60
50
40
30
20
10
0
LOAD STEP
2A/DIV
V
OUT
500mV/DIV
I
L1
5A/DIV
V
V
V
= 5V
= 12V
= 20V
IN
IN
IN
8711 TA03c
500µs/DIV
0.001
0.01
0.1
1
3
LOAD CURRENT (A)
8711 TA03b
8711f
32
For more information www.linear.com/LT8711
LT8711
Typical applicaTions
200kHz, 4.5V–40V Input to 12V/4A SEPIC
V
IN
4.5V TO
40V
C
10µF
×2
V
OUT
IN
EN/FBIN V BIAS
IN
L1
2.2µF
8.2µH
EXTV
INTV
EE
LT8711
V
CC
OUT
C1
10µF ×3
R
SENSE2
2mΩ
V
M2
OUT
2.2µF
12V, 4A (V > 5V)
OPMODE
IN
R
INTV
CC
FB1
L2
15µH
BG
1M
M1
C
22µF
×3
OUT
R
118k
T
RT
SYNC
CSP
R
71.5k
FB2
R
SENSE1
470nF
4.7nF
2mΩ
CSN
GND
SS
100pF
49.9k
TG
ISP
ISN
V
C
FB
8711 TA04a
L1: COILCRAFT 8.2µH XAL1510-822ME
L2: COILCRAFT 15µH XAL1510-153ME
M1: VISHAY SiR826ADP
C : 10µF, 50V, X7R
IN
ADDITIONAL 56µF, 50V ELECTROLYTIC CAP ON V
IN
C
: 22µF, 25V, X7R
OUT
M2: ST STL42P6LLF6
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON V
OUT
Efficiency vs Load Current
Transient Response with 2A to 4A to 2A
Output Load Step (VIN = 12V)
100
90
80
70
60
50
40
30
20
10
0
V
OUT
500mV/DIV
LOAD STEP
2A/DIV
I
L1
V
V
V
V
= 5V
IN
IN
IN
IN
5A/DIV
= 12V
= 24V
= 36V
8711 TA04c
500µs/DIV
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
8711 TA04b
8711f
33
For more information www.linear.com/LT8711
LT8711
Typical applicaTions
200kHz, 5V–40V Input to 12V/3.5A ZETA Converter
V
IN
5V TO
40V
C
10µF
×6
IN
CSP
EN/FBIN V BIAS
R
IN
SENSE1
2.2µF
3.5mΩ
CSN
EXTV
INTV
EE
V
CC
OUT
LT8711
OPMODE
TG
CSP
CSN
M2
C1
10µF ×3
CSP
CSN
2.2µF
L1B
10µH
L1A
10µH
INTV
CC
V
OUT
R
T
12V, 3.5A (V > 16V)
IN
118k
2.5A (9V < V < 16V)
1.5A (V < 9V)
IN
RT
IN
M1
SYNC
SS
BG
330nF
ISN
R
FB1
R
SENSE2
1M
100pF
3.5mΩ
C
OUT
22µF ×4
ISP
GND
R
69.8k
FB2
1nF
62k
V
C
FB
8711 TA05a
L1: COILCRAFT 10µH MSD1583-103
M1: VISHAY SiR826ADP
M2: VISHAY Si7461DP
C : 10µF, 50V, X7R
IN
ADDITIONAL 56µF, 50V ELECTROLYTIC CAP ON V
IN
C
: 22µF, 25V, X7R
OUT
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON V
OUT
Efficiency vs Load Current
Transient Response with 1.5A to 3A to 1.5A
Output Load Step (VIN = 16V)
100
90
80
70
60
50
40
30
20
10
0
LOAD STEP
2A/DIV
V
OUT
200mV/DIV
I
L1
2A/DIV
V
V
V
= 6V
= 12V
= 24V
IN
IN
IN
8711 TA05c
400µs/DIV
0.001
0.01
0.1
1
4
LOAD CURRENT (A)
8711 TA05b
8711f
34
For more information www.linear.com/LT8711
LT8711
Typical applicaTions
400kHz, 5V–40V Input to 12V/3.5A Buck-Boost Converter
V
IN
5V TO
40V
C
IN
EN/FBIN V
BIAS
IN
10µF ×6
2.2µF
EXTV
CC
LT8711
OPMODE
INTV
V
EE
OUT
100pF
TG
M1
L1
4.7µH
2.2µF
D1
D2
V
OUT
INTV
CC
ISN
12V, 3.5A (V >16V)
IN
R
T
60.4k
R
R
SENSE2
FB1
2.5A (9V < V < 16V)
IN
1.5A (V < 9V)
IN
RT
4mΩ
1M
C
OUT
100µF ×2
SYNC
SS
ISP
GND
330nF
100pF
2.2nF
M2
R
69.8k
FB2
BG
CSP
10Ω
10Ω
10nF
R
SENSE1
4mΩ
CSN
110k
V
C
10nF
FB
8711 TA06a
L1: COILCRAFT 4.7µH XAL8080-472ME
M1: ST STL60P4LLF6
M2: FAIRCHILD FDMC86520L
D1, D2: VISHAY SS10P6M3
C : 10µF, 50V, X7R
IN
ADDITIONAL 47µF, 50V ELECTROLYTIC CAP ON V
IN
C
: 100µF, 16V, X7R
OUT
ADDITIONAL 390µF, 16V ELECTROLYTIC CAP ON V
OUT
Efficiency vs Load Current
Transient Response with 1.5A to 3A to 1.5A
Output Load Step (VIN = 9V)
100
90
80
70
60
50
40
30
20
10
0
LOAD STEP
2A/DIV
V
OUT
200mV/DIV
I
L1
V
V
V
V
= 5V
IN
IN
IN
IN
5A/DIV
= 12V
= 24V
= 36V
8711 TA06c
500µs/DIV
0.001
0.01
0.1
1
3
LOAD CURRENT (A)
8711 TA06b
8711f
35
For more information www.linear.com/LT8711
LT8711
package DescripTion
Please refer to http://www.linear.com/product/LT8711#packaging for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation CB
DETAIL A
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
0.60
(.024)
REF
3.86
(.152)
20 1918 17 16 15 14 1312 11
0.28
(.011)
REF
6.60 ±0.10
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
2.74
(.108)
DETAIL A
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
NO MEASUREMENT PURPOSE
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV K 0913
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
8711f
36
For more information www.linear.com/LT8711
LT8711
package DescripTion
Please refer to http://www.linear.com/product/LT8711#packaging for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.50 REF
2.65 ±0.05
1.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ±0.05
4.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
0.75 ±0.05
× 45° CHAMFER
1.50 REF
19 20
R = 0.05 TYP
3.00 ±0.10
0.40 ±0.10
1
PIN 1
TOP MARK
(NOTE 6)
2
2.65 ±0.10
1.65 ±0.10
4.00 ±0.10
2.50 REF
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
0.25 ±0.05
R = 0.115
TYP
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
8711f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
37
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT8711
Typical applicaTion
Boost Pre-Regulator for Automotive Stop-Start/Idle
V
IN
3V TO
36V
C
10µF
×6
IN
EN/FBIN
V
CSP
ISP
IN
R
SENSE
ISN
CSN
3.5mΩ
EXTV
CC
V
OUT
LT8711
D1
V
L1
5.6µH
OUT
2.2µF
OPMODE
BIAS
V
OUT
9V , 3A
M2
2.2µF
2Ω
INTV
RT
CC
MIN
R
T
INTV
EE
100k
R
FB1
560k
C
OUT
L1: WÜRTH 5.6µH WE-HCI 7443557560
M1: FAIRCHILD FDS8447
M2: FAIRCHILD FDD4141
D1: FAIRCHILD MBRS340
SYNC
22µF
×4
BG
GND
TG
M1
330nF
100pF
R
55k
FB2
SS
2Ω
C
: 10µF, 50V, X7R
IN
ADDITIONAL 56µF, 50V ELECTROLYTIC CAP ON V
IN
2.2nF
C
: 22µF, 25V, X7R
OUT
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON V
100k
OUT
V
C
FB
8711 TA07a
No-Load Supply Current
Transient VIN and VOUT Waveforms
150
120
90
60
30
0
V
OUT
5V/DIV
V
IN
5V/DIV
0V
8711 TA07c
10ms/DIV
0
5
10
15
20
25
30
35
INPUT VOLTAGE (V)
8711 TA07b
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LT3757A
LT3758A
LT3957A
LT3958
LT8705A
LT8709
LT8710
LT8714
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E
Boost, Flyback, SEPIC and Inverting Controller
5.5V ≤ V ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E
Boost, Flyback, SEPIC and Inverting Converter
with 5A, 40V Switch
3V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
IN
5mm × 6mm QFN
Boost, Flyback, SEPIC and Inverting Converter
with 3.3A, 84V Switch
5V ≤ V ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency,
IN
5mm × 6mm QFN
80V V and V
Synchronous 4-Switch Buck-Boost 2.8V ≤ V ≤ 80V, 100kHz to 400kHz Programmable Operating Frequency,
IN
OUT
IN
DC/DC Controller
5mm × 7mm QFN-38 and TSSOP-38
Negative Input Synchronous Multitopology DC/DC
Control
–80V ≤ V ≤ –4.5V, Up to 400kHz Programmable Operating Frequency,
IN
TSSOP-20
Synchronous SEPIC/Inverting/Boost Controller with
Output Current Control
4.5V ≤ V ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency,
IN
TSSOP-20
Bipolar Output Synchronous Controller with
Seamless Four Quadrant Operation
4.5V ≤ V ≤ 80V, Output Can Source or Sink Current for Any Output Voltage,
IN
Switching Frequency Up to 750kHz, 20-Lead TSSOP
8711f
LT 0817 • PRINTED IN USA
www.linear.com/LT8711
38
LINEAR TECHNOLOGY CORPORATION 2016
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