LTC1040CSW [Linear]
Dual Micropower Comparator; 双通道微功率比较器
| 型号： | LTC1040CSW |
| 厂家： | 
Linear |
| 描述： | Dual Micropower Comparator |
| 文件： | 总12页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1040
Dual Micropower
Comparator
U
FEATURES
DESCRIPTIO
The LTC®1040 is a monolithic CMOS dual comparator
manufactured using Linear Technology’s enhanced
LTCMOSTM silicon gate process. Extremely low operating
power levels are achieved by internally switching the
comparator ON for short periods of time. The CMOS
output logic holds the output information continuously
while not consuming any power.
■
Micropower
1.5µW (1 Sample/Second)
■
Power Supply Flexibility
Single Supply 2.8V to 16V
Split Supply ±2.8V to ±8V
Guaranteed Max Offset 0.75mV
Guaranteed Max Tracking Error Between Input
Pairs ± 0.1%
■
■
In addition to switching power ON, a switched output is
provided to drive external loads during the comparator’s
active time. This allows not only low comparator power,
but low total system power.
■
■
Input Common Mode Range to Both Supply Rails
TTL/CMOS Compatible with ±5V or Single 5V
Supply
■
Input Errors are Stable with Time and Temperature
Sampling is controlled by an external strobe input or an
internal oscillator. The oscillator frequency is set by an
external RC network.
U
APPLICATIO S
■
Battery-Powered Systems
Each comparator has a unique input structure, giving two
differential inputs. The output of the comparator will be
high if the algebraic sum of the inputs is positive and low
if the algebraic sum of the inputs is negative.
■
Remote Sensing
■
Window Comparator
BANG-BANG Controllers
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS™ is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
Window Comparator with Symmetric Window Limits
Typical LTC1040 Supply Current
vs Sampling Frequency
1000
V
= ±5V
S
LTC1040
100
10
V
+
–
IN
A
V
= “1” WHEN
> V + ∆
C
OUT
IN
COMP A
+
–
A + B = “1” WHEN
1
R
= 10M
EXT
V
– ∆ ≤ V ≤ V + ∆
C
IN C
V
+
–
+
–
C
0.10
EXTERNALLY STROBED
B
V
= “1” WHEN
< V – ∆
C
OUT
IN
COMP B
∆
0.01
0.1
1
10
100
1,000 10,000
SAMPLING FREQUENCY, f (Hz)
S
LTC1040 • TA02
LTC1040 • TA01
1040fa
1
LTC1040
W W
U W
U W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Total Supply Voltage (V+ to V–) ............................... 18V
lnput Voltage ........................ (V+ + 0.3V) to (V– – 0.3V)
Operating Temperature Range
LTC1040C..................................... –40°C ≤ TA ≤ 85°C
LTC1040M (OBSOLETE) .................... –55°C to 125°C
Storage Temperature Range ................. –55°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Output Short-Circuit Duration.......................Continuous
ORDER PART
NUMBER
+
1
2
3
4
5
6
7
8
9
V
V
18
17
16
15
14
13
12
11
10
STROBE
ON/OFF
A + B
P-P
LTC1040CN
LTC1040CSW
OSC
B
OUT
A
OUT
+
+
B1
A1
–
–
B1
A1
+
+
B2
A2
–
–
B2
A2
–
V
GND
N PACKAGE
18-LEAD PDIP
SW PACKAGE
18-LEAD PLASTIC SO WIDE
T
= 110°C, θ = 120°C/W (N)
JA
JMAX
T
= 125°C, θ = 85°C/W (SW)
JMAX
JA
J PACKAGE
LTC1040MJ
LTC1040CJ
18-LEAD CERDIP
= 150°C, θ = 80°C/W
T
JMAX
JA
OBSOLETE PACKAGE
Consider the N18 Package as an Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions: V+ = 5V, V– = –5V, unless otherwise noted.
LTC1040M/LTC1040C
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Offset Voltage (Note 2)
Split Supplies ±2.8V to ±6V
●
●
●
±0.3
± 0.75
mV
OS
–
Single Supply (V = GND) 2.8V to 6V
Split Supplies ±6V to ±8V
±1
±4.5
mV
%
–
Single Supply (V = GND) 6V to 15V
Tracking Error Between
Input Pairs (Notes 2 and 3)
Split Supplies ±2.8V to ±8V
0.05
0.1
–
Single Supplies (V = GND) 2.8 to 16V
I
Input Bias Current
OSC = GND
±0.3
nA
MΩ
V
BIAS
R
Average Input Resistance
Common Mode Range
Power Supply Range
f = 1kHz (Note 4)
S
●
●
●
●
●
20
30
IN
–
+
CMR
PSR
V
V
Split Supplies
±2.8
±8
16
3
V
–
Single Supplies (V = GND)
2.8
V
+
I
I
Power Supply ON Current (Note 5)
Power Supply OFF Current (Note 5)
V = 5V, V On
1.2
mA
S(ON)
P-P
+
V = 5V, V Off
LTC1040C
LTC1040M
●
●
0.001
0.001
0.5
5
µA
µA
S(OFF)
P-P
t
Response Time (Note 6)
60
80
100
µs
D
A, B, A + B and
ON/OFF Outputs (Note 7)
Logic “1” Output Voltage
Logic “0” Output Voltage
+
+
V
V
V = 4.75V, l
= –360µA
= 1.6mA
●
●
2.4
4.4
0.25
V
V
OH
OL
OUT
OUT
V = 4.75V, l
0.4
1040fa
2
LTC1040
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range otherwise specifications are at TA = 25°C. Test conditions: V+ = 5V, V– = –5V, unless otherwise specified
LTC1040M/LTC1040C
SYMBOL PARAMETER
CONDITIONS
MIN
2.0
TYP
MAX
UNITS
STROBE Input (Note 7)
Logic “1” Input Voltage
Logic “0” Input Voltage
+
V
V
V = 5.25V
●
●
1.6
1.0
V
V
IH
IL
+
V = 4.75V
0.8
+
R
External Timing Resistor
Sampling Frequency
Resistor Tied Between V and OSC Pin
= 1M, C = 0.1µF
100
10,000
kΩ
EXT
f
R
EXT
5
Hz
S
EXT
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 5: Average supply current = t • l
• f + (1 – t x f ) • l
.
S(OFF)
D
S(ON)
S
D
S
of a device may be impaired.
Note 6: Response time is set by an internal oscillator and is independent
Note 2: Applies over input voltage range limit and includes gain
of overdrive voltage.
uncertainty.
Note 7: Inputs and outputs also capable of meeting EIA/JEDEC B series
Note 3: Tracking error = (V – V )/ V .
IN1
CMOS specifications.
IN1
IN2
Note 4: R is guaranteed by design and is not tested.
IN
R
IN
= 1/(f • 33pF).
S
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Peak Supply Current
vs Supply Voltage
Normalized Sampling Frequency
vs Supply Voltage and Temperature
Sampling Rate vs REXT, CEXT
3
2
20
18
16
14
12
10
8
10
10
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
R = 1M
C = 0.1µF
C
EXT
= 1000pF
C
EXT
= 0.01µF
T
A
= 125°C
C
EXT
= 0.05µF
25°C
10
1
–55°C
C
EXT
= 0.1µF
6
T
A
= 25°C
125°C
4
C
= 1µF
EXT
2
T
= –55°C
A
0.1
0
2
6
8
10
12
+
14
16
4
100k
1M
(Ω)
10M
8
10
0
2
4
6
12 14 16
+
SUPPLY VOLTAGE, V (V)
R
SUPPLY VOLTAGE, V (V)
EXT
LT1040 • TPC03
LTC1040 • TPC01
LTC1040 • TPC02
Response Time
Input Resistance
VP-P Output Voltage
vs Load Current
vs Supply Voltage
vs Sampling Frequency
11
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
10
300
250
200
150
T
A
= 25°C
10
10
+
V
= 10V
+
V
= 16V
9
+
10
V
= 2.8V
100
50
0
+
8
V
= 5V
10
7
10
2
3
4
0
1
2
3
4
5
6
7
8
9
10
1
10
10
10
10
10
14
16
2
4
6
8
12
+
SAMPLING FREQUENCY, f (Hz)
LOAD CURRENT, I (mA)
L
S
SUPPLY VOLTAGE, V (V)
LTC1040 • TPC05
LTC1040 • TPC06
LTL1040 • TPC04
1040fa
3
LTC1040
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TYPICAL PERFOR A CE CHARACTERISTICS
Quick Hookup Guide
Response Time
vs Temperature
Self-Oscillating
External Strobe
130
+
+
+
V
V
= 5V
V
EXTERNAL
STROBE
INPUT
1
18
17
16
1
18
17
16
120
110
100
90
R
EXT
C
EXT
LTC1040
LTC1040
80
70
60
9
10
9
10
50
40
–50 –25
0
25
125
50
75 100
LTC1040 • TPC08
AMBIENT TEMPERATURE, T (°C)
A
LTC1040 • TPC07
TEST CIRCUIT
+
V
(18)
+
–
+
–
V
IN
OUTPUT
GND (9)
–
V
(10)
LTC1040 • TA01
ALL INPUTS ON OPPOSITE COMPARATOR AT GROUND
W
BLOCK DIAGRA
+
V
18
+
A1
A1
A2
A2
5
6
7
8
V
V
IN1
+
–
+
–
–
+
–
COMP A
4
2
A
OUT
IN2
ON/OFF
4
+
–
+
–
B1
B1
B2
B2
14
13
12
11
1
V
V
IN1
3
A + B
+
–
COMP B
4
15
B
OUT
+
–
IN2
+
V
STROBE
OSC
TIMING
GENERATOR TIMING
SWITCH
V
P-P
CIRCUIT
16
17
10
V
P-P
POWER ON
9
GND
–
V
80µs
LTC1040 • BD01
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4
LTC1040
W U U
APPLICATIO S I FOR ATIO
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The LTC1040 uses sampled data techniques to achieve its
unique characteristics. Some of the experience acquired
using classic linear comparators does not apply to this
circuit, so a brief description of internal operation is
essential to proper application.
For RS > 1OkΩ
For RS greater than 10kΩ, CIN cannot fully charge and a
bypass capacitor, CS, is needed. When switch S1 closes,
charge is shared between CS and CIN. The change in
voltage on CS because of this charge sharing is:
The most obvious difference between the LTC1040 and
other comparators is the dual differential input structure.
Functionally, when the sum of inputs is positive, the
comparator output is high and when the sum of the inputs
is negative, the output is low. This unique input structure
is achieved with CMOS switches and a precision capacitor
array. Because of the switching nature of the inputs, the
concept of input current and input impedance needs to be
examined.
CIN
∆V = VIN •
CIN + CS
This represents an error and can be made arbitrarily small
by increasing CS.
With the addition of CS, a second error term caused by the
finiteinputresistanceoftheLTC1040mustbeconsidered.
Switches S1 and S2 alternately open and close, charging
and discharging CIN between VIN and ground. The
alternate charge and discharge of CIN causes a current to
flow into the positive input and out of the negative input.
The magnitude of this current is:
The equivalent input circuit is shown in Figure 1. Here, the
input is being driven by a resistive source, RS, with a
bypass capacitor, CS. The bypass capacitor may or may
not be needed, depending on the size of the source
resistance and the magnitude of the input voltage, VIN.
IIN = q • fS = VIN CIN fS
where fS is the sampling frequency. Because the input
currentisdirectlyproportionaltoinputvoltage,theLTC1040
can be said to have an average input resistance of:
C
IN
≈ 33pF
S1
S2
R
S
+
–
VIN
1
1
RIN =
=
=
IIN fS CIN fS • 33pF
V
C
S
IN
–
V
(see typical curve of Input Resistance vs Sampling Fre-
quency). A voltage divider is set up between RS and RIN
causing error.
LTC1040 DIFFERENTIAL INPUT
LTC1040 • AI01
Figure 1. Equivalent Input Circuit
The input voltage error caused by these two effects is:
C
R
IN
S
+
V
= V
IN
ERROR
(
)
For RS < 1Ok
C + C R + R
IN IN
S
S
Assuming CS is zero, the input capacitor, CIN, charges to
VIN with a time constant of RS CIN. When RS is too large,
CIN does not have a chance to fully charge during the
sampling interval (≈ 80µs) and errors will result. If RS
exceeds 10kΩ, a bypass capacitor is necessary to mini-
mize errors.
Example: f = 10Hz, R = 1MΩ,
S
S
C = 1µF, V = 1V
S
IN
–12
33 • 10
–6
1 • 10
6
10
+
V
= 1V
ERROR
(
)
6
9
10 + 3 • 10
= 33µV + 330µV = 363µV.
Notice that most of the error is caused by RIN. If the
sampling frequency is reduced to 1Hz, the voltage error is
reduced to 66µV.
1040fa
5
LTC1040
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APPLICATIO S I FOR ATIO
Minimizing Comparison Errors
Tracking Error
The two differential input voltages, V1 and V2, are con- Tracking error is caused by the ratio error between CIN1
verted to charge by the input capacitors CIN1 and CIN2 (see and CIN2 and is expressed as a percentage. For example,
Figure 2). The charge is summed at the virtual ground consider Figure 3a with VREF = 1V. Then at null,
point; if the net charge is positive, the comparator output
C
CIN2
VIN = VREF IN1 = 1V ± 1mV
is high and if negative, it is low. There is an optimum way
to connect these inputs, in a specific application, to
minimize error.
because CIN1 is guaranteed to equal CIN2 to within 0.1%.
C
VIRTUAL
GROUND
IN1
S1
+
–
+
–
V
V
REF
V1
V2
REF
+
–
+
–
V
S2
IN
+
–
+
–
V
IN
C
IN2
(a) OK
(b) Optimum
Figure 3. Two Ways to Do It
LTC1040 • TA03
LTC1040 DUAL DIFFERENTIAL INPUT
LTC1040 • AI02
Figure 2. Dual Differential Equivalent Input Circuit
Common Mode Range
The input switches of the LTC1040 are capable of
switchingtoeithertheV+orV– supply.Thismeansthatthe
input common mode range includes both supply rails.
Many applications, not feasible with conventional com-
parators, are possible with the LTC1040. In the load
current detector shown in Figure 4, a 0.1Ω resistor is used
to sense the current in the V+ supply. This application
requires the dual differential input and common mode
capabilities of the LTC1040.
Ignoring internal offset, the LTC1040 will be at its switch-
ing point when:
V1 • CIN1 + V2 • CIN2 = 0.
Optimum error will be achieved when the differential
voltages, V1 and V2, are individually minimized. Figure 3
shows two ways to connect the LTC1040 to compare an
input voltage, VIN, to a reference voltage, VREF. Using the
above equation, each method will be at null when:
(a) (VREF – 0V) CIN1 – (0V – VIN) CIN2 = 0
I
L
or VIN = VREF (CIN1/CIN2
)
0.1Ω
(b) (VREF – VIN) CIN1 – (0V – 0V) CIN2 = 0
or VIN = VREF
R
L
–
+
–
+
.
1/2
LTC1040
OUT
Notice that in method (a) the null point depends on the
ratio of CIN1/CIN2, but method (b) is independent of this
ratio. Also, because method (b) has zero differential input
voltage, the errors due to finite input resistance are
negligible. The LTC1040 has a high accuracy capacitor
array and even the non-optimum connection will only
result in ± 0.1% more error, worst-case compared to the
optimum connection.
+
V
100mV
S
OUT = HI IF I > 1A
L
OUT = LO IF I < 1A
L
LTC1040 • AI04
Figure 4. Load Current Detector
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6
LTC1040
W U U
APPLICATIO S I FOR ATIO
U
Offset Voltage Error
The VP-P output voltage is not precise (see VP-P Output
Voltage versus Load Current curve). There are two ways
VP-P can be used to power external networks without
excessive errors: (1) ratiometric networks and (2) fast
settling references.
The errors due to offset, common mode, power supply
variation, gain and temperature are all included in the
offsetvoltagespecification. Thismakesiteasytocompute
the error when using the LTC1040.
In a ratiometric network, the inputs are all proportional to
VP-P (see Figure 6). Consequently, for small changes, the
absolute value of VP-P does not affect accuracy.
Example: error computation for Figure 4.
Assume: 2.8V ≤ VS ≤ 6V.
Then total worst-case error is:
1A
It is critical that the inputs to the LTC1040 completely
settle within 4µs of the start of the comparison cycle and
that they do not change during the 80µs ON time. When
driving resistive networks with VP-P, capacitive loading on
= ±6mA
I
= ± (100mV • 0.001 + 0.5mV) •
L (ERROR)
100mV
↑
Tracking Error
6mA
↑
VOS
V
OUTPUT
P-P
IL (ERROR)% =
• 100 = ± 0.6%.
1A
V
–
+
IN
+
–
+
–
Note: If source resistance exceeds 10k, bypass
capacitors should be used and the associated errors must
be included.
1/2
LTC1040
OUTPUT
V
TRIP
LTC1040 • AI06
Pulsed Power (VP-P) Output
Figure 6. Ratiometric Network Driven by VP-P
It is often desirable to use comparators with resistive
networks such as bridges. Because of the extremely low
powerconsumptionoftheLTC1040,thepowerconsumed
by these resistive networks can far exceed that of the
device itself.
the network should be minimized to meet the 4µs settling
timerequirement.ItisnotrecommendedthatVP-P beused
to drive networks with source impedances, as seen by the
inputs, of greater than 10kΩ.
At low sample rates the LTC1040 spends most of its time
off.Totakeadvantageofthis,apulsedpower(VP-P)output
is provided. VP-P is switched to V+ when the comparator
is on and to a high impedance (open circuit) when the
comparator is off. The ON time is nominally 80µs.
Figure 5 shows the VP-P output circuit.
In applications where an absolute reference is required,
the VP-P output can be used to drive a fast settling
reference. The LT1009 2.5V reference, ideal in this
application, settles in approximately 2µs (see Figure 7).
The current through R1 must be large enough to supply
the LT1009 minimum bias current (≈1mA) and the load
current, IL.
+
V
18
V
OUTPUT
P-P
R1
+
–
+
–
V
Q1 P1
IN
1/2
LTC1040
R2
80µs
I
L
R3
LT1009
COMPARATOR ON TIME
9
17
GND
V
P-P
LTC1040 • AI07
LTC1040 • AI05
Figure 5. VP-P Output Switch
Figure 7. Driving Reference with VP-P Output
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7
LTC1040
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APPLICATIO S I FOR ATIO
Output Logic
Because of the sampling nature of the LTC1040, some
sensitivity exists between the offset voltage and the falling
edge of the input strobe. When the falling edge of the
strobe signal falls within the comparator’s active time
(80µsafterrisingedge),offsetchangesofasmuchas2mV
canoccur.Toeliminatethisproblem,makesurethestrobe
pulse width is greater than the response time, tD.
In addition to the normal outputs (AOUT and BOUT), two
additional outputs, A + B and ON/0FF, are provided (see
Figure 8 and Table 1). All logic is powered from V+ and
ground, thusinputandoutputlogiclevelsareindependent
of the V– supply. The LTC1040 is directly compatible with
CMOS logic and is TTL compatible for 4.75V≤ V + ≤ 5.25V.
No external pull-up resistors are required.
Using Internal Strobe
Table 1. Output Logic Truth Table
An internal oscillator allows the LTC1040 to strobe itself.
The frequency of oscillation, and hence sampling rate, is
set by an external RC network (see typical curve of
Sampling Rate vs REXT, CEXT).
ΣA INPUTS
ΣB INPUTS
A
OUT
B
A + B
ON/OFF
OUT
+
+
–
+
–
+
H
H
L
H
L
H
L
L
L
L
L
H
For self-oscillation, the STROBE pin must be tied to
ground. The external RC network is connected as shown
in Figure 9.
–
–
L
L
H
I*
*I = indeterminate. When both A and B outputs are low, the ON/OFF output
remains in the state it was in prior to entering A
= B
= L.
OUT
OUT
To assure oscillation, REXT must be between 100k and
Using External Strobe
10M. There is no limit to the size of CEXT
.
Apositivepulseonthestrobeinput,withthe0SCinputtied
to ground, will initiate a comparison cycle. The STROBE
input is edge-sensitive and pulse widths of 50ns will
typically trigger the device.
REXT is very important in determining the power
consumption. The average voltage at the oscillator pin is
approximatelyV+/2.ThepowerconsumedbyREXT isthen:
PREXT = (V+/2)2/REXT
.
+
V
1
18
17
16
2
ON/OFF
R
EXT
C
EXT
LTC1040
COMPARATOR A
OUTPUT
D
C
4
3
A
Q
Q
OUT
10
9
A + B
COMPARATOR B
OUTPUT
D
C
B
15
OUT
LTC1040 • AI09
Figure 9. External RC Connection
STROBE
Example: REXT = 1M, V+ 5V, PREXT = (2.5)2/106 =
6.25 • 10–6W.
80µs
LTC1040 • AI08
This is about four times the power consumed by the
LTC1040 at V+ = 5V and fS = 1 sample/second. Where
power is a premium REXT should be made as large as
possible. Note that the power consumed by REXT is not a
Figure 8. LTC1040 Logic Diagram
function of fS or CEXT
.
1040fa
8
LTC1040
U
TYPICAL APPLICATIO S
Complete Heating/Cooling Automatic Thermostat
5V AT 0.85µA
17
18
20M
LTC1040
4.32k
4.99k
5
6
7
8
+
–
+
–
4
3
COMP A
†
82k*
HEAT
COOL
5k
TEMP
ADJUST
14
13
12
11
+
–
+
–
15
16
6.81k
COMP B
10M
82k*
† THERMISTOR # 44007
YELLOW SPRINGS INSTRUMENT CO., INC.
0.1µF
9
10
82k
20M
SEPARATION
(20mV)
*
LTC1040 • TA03
HYSTERESIS = 5V •
= 20mV
20M
AIRCONDITIONING ON
HYSTERESIS
AIRCONDITIONING OFF
HEATER OFF
HYSTERESIS
HEATER ON
28°C
SEPARATION
27°C
HEAT
COOL
LTC1040 • TA04
TIME
Window Comparator with Independent Window Limits and
Fully Floating Differential Input
Hysteresis Comparator with Fully Floating Differential Input
+
V
LTC1040
+
V
IN
–
+
–
1/2 LTC1040
OUT
V
IN
V
V
TRIP
+
–
A
V
= “1” WHEN
OUT
IN
COMP A
COMP B
R1
10k
> V
*
+
–
U
U
A+B = “1” WHEN
R2
2.49MΩ
R2 + (5V) R1
V
≥ V ≥ V
IN L
U
+
–
+
–
V
TRIP
OUT = “0” WHEN V > V
=
= 0.996 V
+ 20mV
B
V
= “1” WHEN
L
IN
U
TRIP
OUT
IN
R1 + R2
R2
< V
V
L
V
TRIP
R1 + R2
OUT = “1” WHEN V < V1 =
= 0.996V
TRIP
IN
LTC1040 • TA05
*
TO CENTER HYSTERESIS ABOUT V
HYSTERESIS/2 (10mV)
, FORCE THIS INPUT TO
TRIP
LTC1040 • TA06
1040fa
9
LTC1040
U
TYPICAL APPLICATIO S
The LTC1040 as a Linear Amplifier
With a simple RC filter, the LTC1040 can be made to
function as a linear amplifier. By filtering the logic output
and feeding it back to the negative input, the loop forces
the output duty cycle [tON/(tON + tOFF)] so that VOUT equals
VIN (Figure 10).
should be set to 0.5mV to 1mV for best results. Notice that
thehigherthesamplingfrequency,fS,thelowerRCcanbe.
This is important because the RC filter also sets the loop
response. A convenient way to keep fS as high as possible
under all conditions is to connect a 100k resistor to pin 16
(OSC) with no capacitance to ground.
TheRCtimeconstantissettokeeptherippleontheoutput
small. The maximum output ripple is: ∆V = V+/fSRC and
+
V
+
+
V
R
–
1/2 LTC1040
V
OUT
V
IN
+
0V
t
ON
+
= V
–
C
t
V
OFF
OUT
t
+ t
ON OFF
t
ON
LTC1040 • TA08
LTC1040 • TA07
Figure 10. The LTC1040 as a Linear Amplifier
2-Wire 0°C to 100°C Temperature Transducer with 4mA to 20mA Output
12V TO 40V
0°C = 4mA
100°C = 20mA
+
V
R
LM134
–
V
43
1N914
430Ω
1k
ZERO
ADJUST
3200
6250
100k
16
6
4
6
–
5
LT1019-5
18
1M
4
+
7
1/2
LTC1040
2N6657
†
†
–
8
9
+
+
+
1µF
10
18k
50Ω
10µF
5k
182Ω
† YELLOW SPRINGS INSTRUMENT
PART NO. 44201
RETURN
FULL-SCALE
ADJUST
ACCURACY =
±0.1°C
CIRCUIT ERROR
+
±0.2°C
TRANSDUCER
ERROR
= ±0.3°C
LTC1040 • TA09
AT 25°C
1040fa
10
LTC1040
U
PACKAGE DESCRIPTIO
J Package
18-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.960
(24.384)
MAX
CORNER LEADS OPTION
(4 PLCS)
.005
(0.127)
MIN
17
16
18
15
14
11
13
12
10
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
.220 – .310
(5.590 – 7.870)
.025
(0.635)
RAD TYP
.045 – .065
(1.143 – 1.650)
FULL LEAD
OPTION
3
1
2
4
5
6
7
8
9
.200
(5.080)
MAX
.300 BSC
(7.62 BSC)
.015 – .060
(0.380 – 1.520)
.008 – .018
(0.203 – 0.457)
0° – 15°
.045 – .065
(1.143 – 1.651)
.100
(2.54)
BSC
.125
(3.175)
MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.014 – .026
J18 0801
(0.360 – 0.660)
OBSOLETE PACKAGE
N Package
18-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.900*
(22.860)
MAX
18
17
16
15
14
13
12
11
10
.255 ± .015*
(6.477 ± 0.381)
1
2
3
5
6
9
4
7
8
.300 – .325
(7.620 – 8.255)
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.020
(0.508)
MIN
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
+.035
–.015
.325
.120
(3.048)
MIN
.018 ± .003
(0.457 ± 0.076)
.005
(0.127)
MIN
.100
(2.54)
BSC
+0.889
8.255
(
)
–0.381
NOTE:
INCHES
N18 1002
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1040fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1040
U
TYPICAL APPLICATIO S
Analog Multiplier/Divider
Single + 5V Voltage-to-Frequency Converter
5V
V
(5V)
REF
4
5
6
7
8
18
+
–
+
–
1/4 74C00
1/2
LTC1040
4
15
3
18
V
V
IN
C
f
f
OUT
1
100k
16
1/4 74C00
10
9
10k
V
OUT
+
+
5
6
7
8
100k
V1
V2
+
–
+
–
10µF
18
10
1/2
LTC1040
16
13
4
LTC1043
IN
V
A
+
1µF
14
12
9
V *
B
V
IN
f
(AVERAGE) = f
IN
±0.1% FS
OUT
10k
V
REF
LTC1040 • TA11
10µF
17
(V + V1 – V2) • V
A
ACCURACY = ±10mV NO TRIM
C
V
OUT =
*
V
B
MUST BE > V + (V1 – V2)
V
B
A
LTC1040 • TA10
U
PACKAGE DESCRIPTIO
SW Package
18-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.447 – .463
(11.354 – 11.760)
NOTE 4
N
14 13
11
15
12
10
18 17 16
N
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
9
RECOMMENDED SOLDER PAD LAYOUT
.291 – .299
(7.391 – 7.595)
NOTE 4
2
3
5
7
8
1
4
6
.037 – .045
(0.940 – 1.143)
.093 – .104
.010 – .029
(0.254 – 0.737)
× 45°
(2.362 – 2.642)
.005
(0.127)
RAD MIN
0° – 8° TYP
.050
(1.270)
BSC
.004 – .012
.009 – .013
(0.102 – 0.305)
NOTE 3
(0.229 – 0.330)
.014 – .019
.016 – .050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
S18 (WIDE) 0502
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
1040fa
LW/TP 1202 1K REV A • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 1991
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