LTC1041_09 [Linear]
BANG-BANG Controller; Bang-Bang控制
| 型号： | LTC1041_09 |
| 厂家： | 
Linear |
| 描述： | BANG-BANG Controller |
| 文件： | 总8页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1041
BANG-BANG Controller
U
FEATURES
DESCRIPTIO
The LTC®1041 is a monolithic CMOS BANG-BANG
controller manufactured using Linear Technology’s
enhanced LTCMOS™ silicon gate process. BANG-BANG
loops are characterized by turning the control element
fully ON or fully OFF to regulate the average value of
the parameter to be controlled. The SET POINT input
determines the average control value and the DELTA input
sets the deadband. The deadband is always 2 x DELTA and
is centered around the SET POINT. Independent control
of the SET POINT and deadband, with no interaction, is
made possible by the unique sampling input structure of
the LTC1041.
■
Micropower 1.5µW (1 Sample/Second)
■
Wide Supply Range 2.8V to 16V
■
High Accuracy
Guaranteed SET POINT Error ±0.5mV Max
Guaranteed Deadband ±0.1% of Value Max
Wide Input Voltage Range V+ to Ground
■
■
TTL Outputs with 5V Supply
■
Two Independent Ground-Referred Control Inputs
■
Small Size 8-Pin SO
U
APPLICATIO S
AnexternalRCconnectedtotheOSCpinsetsthesampling
rate. At the start of each sample, internal power to the
analog section is switched on for ≈ 80µs. During this time,
the analog inputs are sampled and compared. After the
comparison is complete, power is switched off. This
achieves extremely low average power consumption
at low sampling rates. CMOS logic holds the output
continuously while consuming virtually no power.
■
Temperature Control (Thermostats)
■
Motor Speed Control
■
Battery Charger
Any ON-OFF Control Loop
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
Tokeepsystempoweratanabsoluteminimum,aswitched
power output (VP-P) is provided. External loads, such as
bridge networks and resistive dividers, can be driven by
this switched output.
The output logic sense (i.e., ON = V+) can be reversed
(i.e., ON = GND) by interchanging the VIN and SET POINT
inputs. This has no other effect on the operation of
the LTC1041.
U
TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
10000
Ultralow Power 50°F to 100°F (2.4µW) Thermostat
V
S
= 6V
26V AC 2-WIRE THERMOSTAT
1000
0.1µF
4.32k
4.99k
56Ω
1
2
3
4
8
7
6
5
100
10
TOTAL SUPPLY
CURRENT
10M
5k
I
S
LTC1041
400nA
+
2N6660
†
6.81k
1
0.1
6V
LTC1041 SUPPLY
CURRENT
1N4002
(4)
1µF
DELTA = 0.5°F
49.9Ω
LTC1041 • TA01
0.01
ALL RESISTORS 1%. †YELLOW SPRINGS INSTRUMENT CO., INC. P/N 44007.
DRIVING THERMISTOR WITH V ELIMINATES 3.8°F ERROR DUE TO SELF-HEATING
0.1
1
10
100
1000
10000
P-P
SAMPLING FREQUENCY, f (Hz)
LTC1041 • TA02
S
1041fa
1
LTC1041
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Total Supply Voltage (V+ to V–) .............................. 18V
Input Voltage ........................ (V+ + 0.3V) to (V– – 0.3V)
Operating Temperature Range
LTC1041C......................................... –40°C to 85°C
LTC1041M (OBSOLETE) .................. –55°C to125°C
Storage Temperature Range ................. –55°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Output Short Circuit Duration .......................Continuous
+
1
2
3
4
8
7
6
5
V
V
ON / OFF
V
IN
P-P
LTC1041CN8
LTC1041CS8
SET POINT
GND
OSC
DELTA
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PDIP
T
JMAX
T
JMAX
= 110°C, θ = 150°C/W (N8)
JA
= 150°C, θ = 150°C/W (S8)
JA
J8 PACKAGE
8-LEAD CERDIP
LTC1041MJ8
T
= 150°C, θ = 100°C/W
JMAX
JA
OBSOLETE PACKAGE
Consider the N8 Package as an Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test Conditions: V+ = 5V, unless otherwise specified.
TC1041M/LTC1041C
SYMBOL PARAMETER
SET POINT Error (Note 3)
CONDITIONS
V = 2.8V to 6V (Note 2)
MIN
TYP
MAX
UNITS
+
±0.3
+
±0.05
±0.5
+
±0.1
mV
●
●
●
●
% of DELTA
mV
+
V = 6V to 15V (Note 2)
±1
+
±0.05
±3
+
±0.1
% of DELTA
mV
+
Deadband Error (Note 4)
Input Current
V = 2.8V to 6V (Note 2)
±0.6
+
±0.1
±1
+
±0.2
% of DELTA
+
V = 6V to 15V (Note 2)
±2
+
±0.1
±6
+
±0.2
% of DELTA
nA
+
I
V = 5V, T = 25°C, OSC = GND
±0.3
OS
A
(V , SET POINT and DELTA Inputs)
IN
R
Equivalent Input Resistance
Input Voltage Range
f = 1kHz (Note 5)
●
●
●
●
10
GND
2.8
15
MΩ
V
IN
S
+
V
P
Power Supply Range
16
3
V
SR
+
I
I
t
Power Supply ON
Current (Note 6)
V = 5V, V ON
1.2
mA
S(ON)
P-P
+
Power Supply OFF
Current (Note 6)
V = 5V, V OFF
LTC1041C
LTC1041M
●
●
0.001
0.001
0.5
5
µA
µA
S(OFF)
D
P-P
+
Response Time (Note 7)
V = 5V
60
2.4
100
80
100
µs
ON/OFF Output (Note 8)
Logical “1” Output Voltage
Logical “0” Output Voltage
+
+
V
V
V = 4.75V, I
= –360µA
= 1.6mA
●
●
4.4
0.25
V
V
OH
OL
OUT
OUT
V = 4.75V, I
0.4
+
R
EXT
External Timing Resistor
Sampling Frequency
Resistor Connected between V and OSC Pin
10,000
kΩ
+
f
V = 5V, T = 25°C,
5
Hz
S
A
R
= 1M C = 0.1µF
EXT
EXT
Note 2: Applies over input voltage range limit and includes gain
uncertainty.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
1041fa
2
LTC1041
ELECTRICAL CHARACTERISTICS
Note 5: R is guaranteed by design and is not tested.
V + V
IN
U
L
Note 3: SET POINT error ≡
– SET POINT
(
)
R
IN
= 1/(f x 66pF).
2
S
Note 6: Average supply current = t • I
• f + (1 – t • f ) l
S
.
S(OFF)
where V = upper band limit and V = lower band limit.
D
S(ON)
D
S
U
L
Note 7: Response time is set by an internal oscillator and is independent
Note 4: Deadband error ≡ (V – V ) – 2 • DELTA where V = upper band
U
L
U
of overdrive voltage. t = V pulse width.
D
P-P
limit and V = lower band limit.
L
Note 8: Output also capable of meeting EIA/JEDEC standard B series
CMOS drive specifications.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Normalized Sampling
IS(ON) vs V+
Frequency vs V+, Temperature
Sampling Rate vs REXT, CEXT
3
2
10
20
18
16
14
12
10
8
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
R = 1M, C = 0.1µF
C
EXT = 1000pF
10
CEXT = 0.01
µF
TA = 125°C
25°C
CEXT = 0.05
µF
10
1
–55°C
CEXT = 0.1
µF
6
T
A = 25°C
125°C
4
CEXT = 1µ
F
2
T
A = –55°C
0.1
0
8
10
0
2
4
6
12 14 16
100k
1M
10M
2
6
8
10
12
+
14
16
4
+
R
EXT
(Ω)
SUPPLY VOLTAGE, V (V)
SUPPLY VOLTAGE, V (V)
LTC1041 • TPC03
LTC1041 • TPC02
LTC1041 • TPC01
Response Time
vs Supply Voltage
Response Time
vs Temperature
300
250
200
150
130
120
110
100
90
+
T
= 25°C
V
= 5V
A
80
100
50
0
70
60
50
40
10
SUPPLY VOLTAGE, V (V)
14
16
2
4
6
8
12
–50 –25
0
25
125
50
75 100
+
AMBIENT TEMPERATURE, T (°C)
A
LTC1041 • TPC04
LTC1041 • TPC05
1041fa
3
LTC1041
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VP-P Output Voltage
vs Load Current
RIN vs Sampling Frequency
11
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
10
+
10
9
V
= 16V
10
+
V
= 10V
10
+
V
= 2.8V
8
7
+
10
V
= 5V
7
10
2
3
4
0
1
2
3
4
5
6
8
9
10
1
10
10
10
10
SAMPLING FREQUENCY fS (Hz)
LOAD CURRENT, IL (mA)
LTC1041 • TPC07
LTC1041 • TPC06
W U U
U
APPLICATIO S I FOR ATIO
The LTC1041 uses sampled data techniques to achieve
its unique characteristics. It consists of two comparators,
each of which has two differential inputs (Figure 1a).
When the sum of the voltages on a comparator’s inputs is
positive, the output is high and when the sum is negative,
the output is low. The inputs are interconnected such that
the RS flip-flop is reset (ON/OFF = GND) when
VIN > (SET POINT + DELTA) and is set (ON/OFF = V+) when
VIN < (SET POINT – DELTA). This makes a very precise
hysteresis loop of 2 • DELTA centered around the
SET POINT. (See Figure 1b.)
For RS < 10kΩ
+
The dual differential input structure is made with CMOS
switches and a precision capacitor array. Input
impedance characteristics of the LTC1041 can be
determined from the equivalent circuit shown in Figure 2.
The input capacitance will charge with a time constant of
V
VIN
(2)
(8)
+
–
+
–
COMP A
ON/OFF
(1)
4
SET POINT
SET POINT
(3)
DELTA – +DELTA
+
–
+
–
V+
COMP B
DELTA
(5)
DEADBAND
+
V
GND
(4)
4
+
V
REXT
OSC
(6)
TIMING
GENERATOR
VP-P
(7)
V
P-P
CIRCUIT
GND
0V
VL
VU
CEXT
POWER ON
INPUT VOLTAGE, VIN
80µs
LTC1041 • AI01a
LTC1041 • AI01b
(a)
(b)
Figure 1. LTC1041 Block Diagram
1041fa
4
LTC1041
W U U
APPLICATIO S I FOR ATIO
U
Input Voltage Range
CIN
(≈ 33pF)
S1
RS
The input switches of the LTC1041 are capable of
switchingeithertotheV+ supplyorground.Consequently,
the input voltage range includes both supply rails. This is
a further benefit of the sampling input structure.
+
–
VIN
CS
S2
V–
LTC1041 DIFFERENTIAL INPUT
LTC1041 • AI01
Error Specifications
Figure 2. Equivalent Input Circuit
The only measurable errors on the LTC1041 are the
deviations from “ideal” of the upper and lower switching
levels (Figure 1b). From a control standpoint, the error in
the SET POINT and deadband is critical. These errors may
be defined in terms of VU and VL.
RS • CIN. The ability to fully charge CIN from the signal
source during the controller’s active time is critical in
determining errors caused by the input charging current.
For source resistances less than 10kΩ, CIN fully charges
and no error is caused by the charging current.
VU + VL
SET POINT error ≡
– SET POINT
2
For RS > 10kΩ
deadband error ≡ V – V – 2 •DELTA
(
)
U
L
Forsourceresistancesgreaterthan10kΩ, CIN cannotfully
charge, causing voltage errors. To minimize these errors,
an input bypass capacitor, CS, should be used. Charge is
shared between CIN and CS, causing a small voltage error.
ThemagnitudeofthiserrorisAV =VIN •CIN (CIN +CS). This
error can be made arbitrarily small by increasing CS.
The specified error limits (see electrical characteristics)
include error due to offset, power supply variation, gain,
time and temperature.
Pulsed Power (VP-P) Output
It is often desirable to use the LTC1041 with resistive
networks such as bridges and voltage dividers. The power
consumed by these resistive networks can far exceed that
of the LTC1041 itself.
The averaging effect of the bypass capacitor, CS, causes
another error term. Each time the input switches cycle
between the plus and minus inputs, CIN is charged and
discharged. The average input current due to this is
IAVG = VIN • CIN • fS, where fS is the sampling frequency.
Because the input current is directly proportional to the
differential input voltage, the LTC1041 can be said to have
an average input resistance of RIN = VIN/IAVG = I/(fS • CIN).
At low sample rates the LTC1041 spends most of its time
off. Aswitchedpoweroutput, VP-P, isprovidedtodrivethe
input network, reducing its average power as well. VP-P is
switched to V+ during the controller’s active time (≈ 80µs)
and to a high impedance (open circuit) when internal
power is switched off.
Sincetwocomparatorinputsareconnectedinparallel, RIN
is one half of this value (see typical curve of RIN versus
Sampling Frequency). This finite input resistance causes
an error due to the voltage divider between RS and RIN.
Figure 3 shows the VP-P output circuit. The VP-P output
voltage is not precisely controlled when driving a load
(seetypicalcurveofVP-P OutputVoltagevsLoadCurrent).
Inspiteofthis,highprecisioncanbeachievedintwoways:
(1) driving ratiometric networks and (2) driving fast set-
tling references.
The input voltage error caused by both of these effects is
VERROR = VIN [2CIN/(2CIN + CS) + RS/(RS + RIN)].
Example: assume fS = 10Hz, RS = 1M, CS = 1µF, VIN = 1V,
VERROR = 1V(66µV + 660µV) = 726µV. Notice that most of
the error is caused by RIN. If the sampling frequency is
reduced to 1Hz, the voltage error from the input
impedance effects is reduced to 136µV.
In ratiometric networks all the inputs are proportional to
VP-P (Figure 4). Consequently, the absolute value of VP-P
does not affect accuracy.
1041fa
5
LTC1041
W U U
U
APPLICATIO S I FOR ATIO
+
V
In applications where an absolute reference is required,
the VP-P output can be used to drive a fast settling
reference. The LTC1009 2.5V reference settles in ≈ 2µs
and is ideal for this application (Figure 5). The current
through R1 must be large enough to supply the LT1009
minimum bias current (≈ 1mA) and the load current, IL.
8
Q1
P1
80µs
COMPARATOR ON TIME
4
7
GND
VP-P
LTC1041 • AI03
Internal Oscillator
Figure 3. VP-P Output Switch
An internal oscillator allows the LTC1041 to strobe itself.
The frequency of the oscillation, and hence the sampling
rate, is set with an external RC network (see typical curve,
Sampling Rate REXT, CEXT). REXT and CEXT are connected
as shown in Figure 1. To assure oscillation, REXT must be
between 100kΩ and 10MΩ. There is no limit to the size of
+
V
R1
R2
1
8
R3
R4
R5
R6
V
V
IN
SET POINT
GND
2
3
4
7
6
5
P-P
LTC1041
CEXT.
DELTA
At low sampling rates, REXT is very important in
determining the power consumption. REXT consumes
power continuously. The average voltage at the OSC pin
is approximately V+/2, giving a power dissipation of
LTC1041 • AI04
PREXT = (V+/ 2)2/REXT
.
Figure 4. Ratiometric Network Driven by VP-P
Example: assume REXT = 1MΩ, V+ = 5V, PREXT
=
(2.5)2/106 =6.25/µW. Thisisapproximatelyfourtimesthe
power consumed by the LTC1041 at V+ = 5V and
fS = 1 sample/second. Where power is a premium,
REXT should be made as large as possible. Note that the
+
V
R1
8
7
6
5
1
2
3
4
I
V
R2
L
IN
LTC1041
SET POINT
power dissipated by REXT is not a function of fS or CEXT
.
DELTA
R3
R4
If high sampling rates are needed and power consumption
is of secondary importance, a convenient way to get the
maximumpossiblesamplingrateistomakeREXT =100kΩ
and CEXT = 0. The sampling rate, set by the controller’s
active time, will nominally be ≈ 10kHz.
LT1009-2.5
LTC1041 • AI05
Figure 5. Driving Reference with VP-P Output
To synchronize the Sampling of the LTC1041 to an
external frequency source, the OSC pin can be driven by a
CMOS gate. A CMOS gate is necessary because the input
trip points of the oscillator are close to the supply rails and
TTLdoesnothaveenoughoutputswing.Externallydriven,
there will be a delay from the rising edge of the OSC input
and the start of the sampling cycle of approximately 5µs.
If the best possible performance is needed, the inputs to
the LTC1041 must completely settle within 4µs of the start
of the comparison cycle (VP-P high impedance to V+
transition). Also, it is critical that the input voltages do not
changeduringthe80µsactivetime.Whendrivingresistive
input networks with VP-P, capacitive loading should be
minimized to meet the 4µs settling time requirement.
Further, care should be exercised in layout when driving
networkswithsourceimpedances,asseenbytheLTC1041,
of greater than 10kΩ (see For RS > 10kΩ).
1041fa
6
LTC1041
U
TYPICAL APPLICATIO S
Motor Speed Controller
+
V
100k
10k
1N4002
MOTOR*
TACH
+
V
1.1k
1
2
3
4
8
2N6387
LT1009
7
320k
24k
20k
6
5
LTC1041
3k
SPEED
320pF
500Ω
DEADBAND DEMAND
LTC1041 • TA03
*CANNON CKT26-T5-3SAE
Battery Charger
1N4002
IN
89
GE 106B†
OUT
LT1019-5
5V
24V
1A
74C00
+
74C00
100µF
115VAC
60 Hz
UTC D0T20
+
V
12V
LEAD
ACID
100k
36.5k
1
2
3
4
8
7
6
5
1N4002
1N4022
40k
10k
74C00
2kΩ
LTC1041
2.21k
0.1µF
13Ω
†SCR FIRES AT ZERO CROSSING.
*
SET BATTERY VOLTAGE. BATTERY IS
MEASURED WITH ZERO CHARGE CURRENT
LTC1041 • TA04
1041fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
7
LTC1041
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.405
(10.287)
MAX
CORNER LEADS OPTION
(4 PLCS)
.005
(0.127)
MIN
.200
(5.080)
MAX
.300 BSC
(7.62 BSC)
6
5
4
8
7
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
.015 – .060
(0.381 – 1.524)
.025
(0.635)
RAD TYP
.220 – .310
(5.588 – 7.874)
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.008 – .018
(0.203 – 0.457)
0° – 15°
J8 0801
1
2
3
.045 – .065
(1.143 – 1.651)
.125
3.175
MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.014 – .026
(0.360 – 0.660)
.100
(2.54)
BSC
OBSOLETE PACKAGE
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
.130 ± .005
.300 – .325
.045 – .065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
8
1
7
6
5
4
.065
(1.651)
TYP
.255 ± .015*
(6.477 ± 0.381)
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
–.015
2
3
.325
.018 ± .003
(0.457 ± 0.076)
.100
(2.54)
BSC
N8 1002
+0.889
8.255
(
)
–0.381
NOTE:
INCHES
MILLIMETERS
1. DIMENSIONS ARE
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.160 ±.005
.050 BSC
.010 – .020
(0.254 – 0.508)
7
5
8
6
× 45°
.053 – .069
(1.346 – 1.752)
N
1
.004 – .010
(0.101 – 0.254)
.008 – .010
N
0°– 8° TYP
(0.203 – 0.254)
.245
MIN
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
N/2
4
NOTE:
2
3
N/2
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.030 ±.005
TYP
1
2
3
RECOMMENDED SOLDER PAD LAYOUT
SO8 0502
1041fa
LW/TP 1202 1K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
8
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 1985
相关型号：
LTC1042CN8#PBF
LTC1042 - Window Comparator; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC1043CD
IC SPECIALTY ANALOG CIRCUIT, CDIP18, HERMETIC SEALED, SIDE BRAZED, DIP-18, Analog IC:Other
Linear
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