LTC1067C [Linear]
Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; 轨到轨，极低噪声的通用双滤波器积木
| 型号： | LTC1067C |
| 厂家： | 
Linear |
| 描述： | Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block |
| 文件： | 总20页 (文件大小：480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1067/LTC1067-50
Rail-to-Rail, Very Low Noise
Universal Dual Filter Building Block
U
FEATURES
DESCRIPTION
The LTC®1067/LTC1067-50 consist of two identical rail-
to-rail, high accuracy and very wide dynamic range 2nd
order switched-capacitor building blocks. Each building
block, together with three to five resistors, provides 2nd
orderfilterfunctionssuchasbandpass,highpass,lowpass,
notch and allpass. High precision 4th order filters are
easily designed.
■
Rail-to-Rail Input and Output Operation
Operates from a Single 3V to ±5V Supply
Dual 2nd Order Filter in a 16-Lead SSOP Package
> 80dB Dynamic Range on Single 3.3V Supply
Clock-to-Center Frequency Ratio of 100:1 for the
LTC1067 and 50:1 for the LTC1067-50
Internal Sampling-to-Center Frequency Ratio of
200:1 for the LTC1067 and 100:1 for the LTC1067-50
Center Frequency Error < ±0.2% Typ
Low Noise: < 40µVRMS, Q ≤ 5
Customizable with Internal Resistors
■
■
■
■
■
Thecenterfrequencyofeach2ndordersectionistunedby
the external clock frequency. The internal clock-to-center
frequency ratio (100:1 for the LTC1067 and 50:1 for the
LTC1067-50) can be modified by the external resistors.
These devices have a double sampled architecture which
placesaliasingandimagingcomponentsattwicetheclock
frequency. The LTC1067-50 is a low power device con-
suming about one half the current of the LTC1067. The
LTC1067-50’s typical supply current is about 1mA from a
3.3V supply.
■
■
■
U
APPLICATIONS
■
Notch Filters
■
Narrowband Bandpass Filters
■
Tone Detection
■
Noise Reduction Systems
The LTC1067 and LTC1067-50 are available in 16-pin
narrow SSOP and SO packages.
Mask programmable versions of the LTC1067 and
LTC1067-50, with thin film resistors on-chip and custom
clock-to-cutoff frequency ratios, can be designed in an
SO-8 package to realize application specific monolithic
filters. Please contact LTC Marketing for more details.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATION
Frequency Response
Single 3.3V Supply Rail-to-Rail,
4th Order, 10kHz Bandpass Filter
0
1
2
3
4
16
15
14
13
+
f
= 500kHz
V
CLK
CLK
–10
–20
–30
–40
NC
AGND
1µF
+
–
3.3V
V
V
0.1µF
SA
SB
LTC1067-50
5
6
7
8
12
11
10
9
LPA
LPB
OUT
R32, 200k
R22, 10k
R31, 200k
R21, 10k
BPA
BPB
HPA/NA
INV A
HPB/NB
INV B
R11
200k
IN
10
11
8
12
9
TOTAL OUTPUT NOISE: 90µV
RMS
RB1, 200k
FREQUENCY (kHz)
S/N RATIO: 80dB
1067 TA01
1067 • TA02
1
LTC1067/LTC1067-50
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
Total Voltage Supply (V+ to V–) .............................. 12V
Input Voltage ........................ (V+ + 0.3V) to (V– – 0.3V)
Output Short-Circuit Duration.......................... Indefinite
Power Dissipation............................................... 500mV
Operating Temperature Range
TOP VIEW
ORDER PART
NUMBER
+
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
NC
+
AGND
LTC1067CGN
LTC1067-50CGN
LTC1067IGN
LTC1067-50IGN
LTC1067CS
LTC1067-50CS
LTC1067IS
LTC1067-50IS
–
V
V
SA
LPA
SB
LTC1067C................................................ 0°C to 70°C
LTC1067I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LPB
BPA
BPB
HPA/NA
INV A
HPB/NB
INV B
GN PACKAGE
S PACKAGE
16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
TJMAX = 110°C, θJA = 135°C/ W (GN)
T
JMAX = 110°C, θJA = 115°C/ W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS LTC1067 (internal op amps) VS = 4.75V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Range
Positive Output Voltage Swing
3
11
V
V = 3V, R = 10k
●
●
●
2.65
4.25
4.15
2.80
4.50
4.50
V
V
V
S
L
V = 4.75V, R = 10k
S
L
V = ±5V, R = 10k
S
L
Negative Output Voltage Swing
V = 3V, R = 10k
●
●
●
0.020
0.025
–4.96
0.200
0.225
–4.80
V
V
V
S
L
V = 4.75V, R = 10k
S
L
V = ±5V, R = 10k
S
L
Output Short-Circuit Current
(Source/Sink)
V = 3V
16/1.0
33/2.2
70/7.2
mA
mA
mA
S
V = 4.75V
S
V = ±5V
S
DC Open-Loop Gain
GBW Product
Slew Rate
R = 10k
90
2.8
2.25
dB
MHz
V/µs
L
R = 10k
L
R = 10k
L
LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25°C, unless otherwise noted.
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
kHz
MHz
Center Frequency Range, f (Note 1)
0.001 to 20
0 to 1
O
Input Frequency Range
Clock-to-Center Frequency, f /f
V = 3V, f
R1 = R3 = 49.9k, R2 = 10k
= 250kHz, Mode 1, f = 2.5kHz, Q = 5
100:1 ±0.2
%
%
%
%
%
%
CLK
O
S
CLK
O
●
●
●
±0.70
±0.70
±0.70
V = 4.75V, f = 250kHz, Mode 1, f = 2.5kHz, Q = 5
100:1 ±0.2
100:1 ±0.2
S
CLK
O
R1 = R3 = 49.9k, R2 = 10k
V = ±5V, f = 500kHz, Mode 1, f = 5kHz, Q = 5
S
CLK
O
R1 = R3 = 49.9k, R2 = 10k
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
V = 3V, f = 250kHz, Q = 5
●
●
●
±0.1
±0.1
±0.1
±0.35
±0.35
±0.35
%
%
%
S
CLK
V = 4.75V, f
= 250kHz, Q = 5
= 500kHz, Q = 5
S
CLK
V = ±5V, f
S
CLK
2
LTC1067/LTC1067-50
ELECTRICAL CHARACTERISTICS
LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
V = 3V, f
MIN
TYP
MAX
UNITS
Q Accuracy
= 250kHz, Q = 5
CLK
●
●
●
±0.5
±0.5
±0.5
±2
±2
±2
%
%
%
S
V = 4.75V, f
S
= 250kHz, Q = 5
= 500kHz, Q = 5
CLK
V = ±5V, f
S
CLK
f Temperature Coefficient
Q Temperature Coefficient
±1
±5
ppm/°C
ppm/°C
O
DC Offset Voltage (See Table 2)
V
OS1
V
OS2
V
OS3
(DC Offset of Input Inverter)
(DC Offset of First Integrator)
(DC Offset of Second Integrator)
●
●
●
±3
±4
±4
±12.5
±15.0
±15.0
mV
mV
mV
Clock Feedthrough
Maximum Clock Frequency
Power Supply Current
150
2.0
2.50
3.00
4.35
µV
RMS
MHz
Q < 2.5, V = ±5V
S
V = 3V, f
V = 4.75V, f
S
= 250kHz
= 250kHz
CLK
●
●
●
4.5
5.5
7.5
mA
mA
mA
S
CLK
V = ±5V, f
= 500kHz
S
CLK
LTC1067-50 (internal op amps) VS = 4.75V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Range
Positive Output Voltage Swing
2.7
11
V
V = 3V, R = 10k
●
●
●
2.65
4.25
4.15
2.80
4.50
4.50
V
V
V
S
L
V = 4.75V, R = 10k
S
L
V = ±5V, R = 10k
S
L
Negative Output Voltage Swing
V = 3V, R = 10k
●
●
●
0.020
0.025
–4.96
0.200
0.225
– 4.80
V
V
V
S
L
V = 4.75V, R = 10k
S
L
V = ±5V, R = 10k
S
L
Output Short-Circuit Current
(Source/Sink)
V = 3V
16/0.6
33/1.2
70/5.7
mA
mA
mA
S
V = 4.75V
S
V = ±5V
S
DC Open-Loop Gain
GBW Product
Slew Rate
R = 10k
90
1.9
0.8
dB
MHz
V/µs
L
R = 10k
L
R = 10k
L
LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25°C, unless otherwise noted.
PARAMETER CONDITIONS
MIN
TYP
0.001 to 40
0 to 1
MAX
UNITS
kHz
MHz
Center Frequency Range, f (Note 1)
O
Input Frequency Range
Clock-to-Center Frequency, f /f
V = 3V, f
R1 = R3 = 49.9k, R2 = 10k
= 125kHz, Mode 1, f = 2.5kHz, Q = 5
50:1 ±0.2
%
%
%
%
%
%
CLK
O
S
CLK
O
●
●
●
±0.75
±0.75
±0.75
V = 4.75V, f = 125kHz, Mode 1, f = 2.5kHz, Q = 5
50:1 ±0.2
50:1 ±0.3
S
CLK
O
R1 = R3 = 49.9k, R2 = 10k
V = ±5V, f = 250kHz, Mode 1, f = 5kHz, Q = 5
S
CLK
O
R1 = R3 = 49.9k, R2 = 10k
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
V = 3V, f = 125kHz, Q = 5
●
●
●
±0.2
±0.2
±0.2
±0.55
±0.55
±0.55
%
%
%
S
CLK
V = 4.75V, f
= 125kHz, Q = 5
= 250kHz, Q = 5
S
CLK
V = ±5V, f
S
CLK
Q Accuracy
V = 3V, f
= 125kHz, Q = 5
= 125kHz, Q = 5
CLK
●
●
●
±0.5
±0.5
±0.5
±2
±2
±2
%
%
%
S
CLK
V = 4.75V, f
S
V = ±5V, f
S
= 250kHz, Q = 5
CLK
3
LTC1067/LTC1067-50
ELECTRICAL CHARACTERISTICS
LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
±1
±5
MAX
UNITS
ppm/°C
ppm/°C
f Temperature Coefficient
O
Q Temperature Coefficient
DC Offset Voltage (See Table 2)
V
V
V
(DC Offset of Input Inverter)
(DC Offset of First Integrator)
(DC Offset of Second Integrator)
●
●
●
±3
±4
±4
±12.5
±15.0
±15.0
mV
mV
mV
OS1
OS2
OS3
Clock Feedthrough
Maximum Clock Frequency
Power Supply Current
150
2.0
1.00
1.45
2.35
µV
RMS
MHz
Q < 2.5, V = ±5V
S
V = 3V, f
V = 4.75V, f
S
= 125kHz
●
●
●
2.5
3.0
4.0
mA
mA
mA
S
CLK
= 125kHz
CLK
V = ±5V, f
= 250kHz
S
CLK
Note 1: See Typical Performance Characteristics.
The
● denotes the specifications which apply over the full operating
temperature range.
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067 Maximum Q vs
Center Frequency
(Modes 1, 1B, 2 where R4 ≥ 10R2)
LTC1067 Maximum Q vs
Center Frequency
(Modes 2 where R4 < 10R2, 3)
LTC1067
Noise + THD vs Input Voltage
50
40
30
20
10
0
50
40
30
20
10
0
–20
–30
–40
–50
–60
–70
–80
–90
–100
4TH ORDER BUTTERWORTH LPF
V
f
= ±5V
CLK(MAX)
S
V
f
= SINGLE 3.3V, f = 1kHz
S
IN
= 2MHz
V
= ±5V
S
= 400kHz, f
= 4kHz
–3dB
CLK
f
= 2MHz
CLK(MAX)
R
L
= 20k
V
f
= 5V
CLK(MAX)
S
V
= 5V
= 1.5MHz
S
f
= 1.5MHz
CLK(MAX)
V
= 3.3V
S
V
= 3.3V
f
= 1MHz
S
CLK(MAX)
f
= 1MHz
CLK(MAX)
MODE 1
MODE 3
10
15
0
5
10
15
20
0
5
20
0.1
1
2
INPUT VOLTAGE (V
)
CENTER FREQUENCY, f (kHz)
CENTER FREQUENCY, f (kHz)
RMS
O
O
1067 G03
1067 G02
1067 G01
LTC1067
Noise + THD vs Input Voltage
LTC1067
Noise + THD vs Input Frequency
LTC1067
Noise + THD vs Input Voltage
–20
–30
–40
–50
–60
–70
–80
–90
–100
–60
–65
–70
–75
–80
–85
–90
–20
–30
–40
–50
–60
–70
–80
–90
–100
4TH ORDER BUTTERWORTH LPF
4TH ORDER BUTTERWORTH LPF
V
f
= SINGLE 5V, f = 1kHz
V
f
= ±5V, f = 1kHz
S
IN
S
IN
= 500kHz, f
= 5kHz
–3dB
= 500kHz, f
= 5kHz
CLK
CLK
–3dB
MODE 1
R
L
= 20k
R
L
= 20k
MODE 2
MODE 1
MODE 1
MODE 3
MODE 3
4TH ORDER BUTTERWORTH LPF
V
f
–3dB
= SINGLE 3.3V
S
CLK
MODE 3
= 400kHz, V = 0.36V
IN
RMS
f
= 4kHz, R = 20k
L
1
2
3
4
5
0.1
1
INPUT VOLTAGE (V
5
0.1
1
)
2
INPUT FREQUENCY (kHz)
)
INPUT VOLTAGE (V
RMS
RMS
1067 G05
1067 G06
1067 G04
4
LTC1067/LTC1067-50
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067
LTC1067
LTC1067
Noise vs Q
220
Noise + THD vs Input Frequency
Noise + THD vs Input Frequency
–75
–80
–85
–90
–75
–80
–85
–90
4TH ORDER LOWPASS
BUTTERWORTH
200
±5V
180
160
140
120
100
80
V
CLK
R
= ±5V, V = 1V
S
IN RMS
f
= 1MHz, f = 10kHz
–3dB
MODE 1
MODE 3
= 20k
L
5V
3V
MODE 1
MODE 3
60
4TH ORDER BUTTERWORTH LPF
40
V
V
= SINGLE 5V, f
IN
= 500kHz
= 5kHz, R = 20k
L
S
CLK
RMS, –3dB
20
= 0.5V
f
0
1
2
3
4
5
0
10
20
30
40
50
1
3
6
9 10
7 8
2
4
5
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (MHz)
Q
1067 G07
1067 G08
1067 G09
LTC1067
LTC1067
Output Voltage Swing vs Load
Resistance, Single Supply Voltage
LTC1067
Power Supply Current
vs Power Supply
Output Voltage Swing vs Load
Resistance, ±5V Supply Voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0
10.0
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
V
= ±5V
S
V
= 5V
S
70°C
V
S
= 3.3V
–20°C
25°C
0
2
4
6
8
10 12 14 16 18 20
3
4
5
6
7
8
9
10
0
2
4
6
8
10 12 14 16 18 20
–
LOAD RESISTANCE (kΩ TO GND)
LOAD RESISTANCE (kΩ TO V )
TOTAL POWER SUPPLY (V)
1067 G10
1067 G11
1067 G12
LTC1067-50
Maximum Q vs Center Frequency
(Modes 2 Where R4 < 10R2, 3)
LTC1067-50
Maximum Q vs Center Frequency
LTC1067-50
Noise + THD vs Input Voltage
(Modes 1, 1B, 2 Where R4 ≥ 10R2)
–20
–30
–40
–50
–60
–70
–80
–90
–100
50
40
30
20
10
0
50
40
30
20
10
0
4TH ORDER BUTTERWORTH LPF
V
= SINGLE 3V, f = 1kHz
V
f
= ±5V
CLK(MAX)
S
CLK
IN
V
f
= ±5V
CLK(MAX)
S
S
f
= 200kHz, f
= 4kHz
–3dB
= 2MHz
= 2MHz
V
= 5V
S
V
f
= 5V
CLK(MAX)
S
f
= 1.5MHz
CLK(MAX)
= 1.5MHz
V
= 3.3V
S
V
= 3.3V
S
f
= 800kHz
CLK(MAX)
f
= 800kHz
CLK(MAX)
MODE 1
MODE 3
V
= 3V
S
V
f
= 3V
S
f
= 600kHz
CLK(MAX)
= 600kHz
CLK(MAX)
0.1
1
2
0
10
20
30
0
10
20
30
40
40
INPUT VOLTAGE (V
)
RMS
CENTER FREQUENCY, f (kHz)
CENTER FREQUENCY, f (kHz)
O
O
1067 G15
1067 G13
1067 G14
5
LTC1067/LTC1067-50
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067-50
Noise + THD vs Input Voltage
LTC1067-50
Noise + THD vs Input Voltage
LTC1067-50
Noise + THD vs Input Frequency
–20
–30
–40
–50
–60
–70
–80
–90
–100
–60
–65
–70
–75
–80
–85
–90
–20
–30
–40
–50
–60
–70
–80
–90
–100
4TH ORDER BUTTERWORTH LPF
4TH ORDER BUTTERWORTH LPF
MODE 1
V
f
–3dB
= ±5V, f = 1kHz
V
f
= SINGLE 5V, f = 1kHz
S
CLK
IN
S
IN
= 250kHz (225kHz FOR MODE 2)
= 250kHz, f
= 5kHz
–3dB
CLK
f
= 10kHz, R = 20k
R
L
= 20k
L
MODE 3
MODE 3
MODE 2
MODE 1
MODE 1
4TH ORDER BUTTERWORTH LPF
V
V
= SINGLE 3V, f
IN
= 200kHz
= 4kHz, R = 20k
S
CLK
RMS, –3dB
MODE 3
1
= 0.34V
f
L
0.1
2
0.1
1
5
1
2
3
4
5
INPUT VOLTAGE (V
)
INPUT VOLTAGE (V
)
RMS
INPUT FREQUENCY (kHz)
RMS
1067 G16
1067 G17
1067 G18
LTC1067-50
Noise + THD vs Input Frequency
LTC1067-50
Noise vs Q
LTC1067-50
Noise + THD vs Input Frequency
400
350
300
250
200
150
100
50
–60
–65
–70
–75
–80
–85
–90
–60
–65
–70
–75
–80
–85
–90
4TH ORDER BUTTERWORTH LPF
4TH ORDER BUTTERWORTH LPF
V
V
= SINGLE 5V, f
= 250kHz
V
V
= ±5V, f
= 250kHz
S
IN
CLK
RMS, –3dB
S
IN
CLK
, f
= 0.5V
f
= 5kHz, R = 20k
L
= 1V
= 20k
= 5kHz
±5V
RMS –3dB
R
L
5V
3V
MODE 1
MODE 3
MODE 1
MODE 3
0
0
5
10 15 20 25 30 35 40 45 50
1
2
3
4
5
1
2
3
4
5
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Q
1067 G19
1067 G20
1067 G21
LTC1067-50
Output Voltage Swing vs Load
Resistance, ±5V Supply Voltage
LTC1067-50
Output Voltage Swing vs Load
Resistance, Single Supply Voltage
LTC1067-50
Power Supply Current
vs Power Supply
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
10.0
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
V
= ±5V
S
V
S
= 5V
70°C
V
S
= 3V
20°C
25°C
0
2
4
6
8
10 12 14 16 18 20
–
3
4
5
6
7
8
9
10
0
2
4
6
8
10 12 14 16 18 20
LOAD RESISTANCE (kΩ TO GND)
LOAD RESISTANCE (kΩ TO V )
TOTAL POWER SUPPLY (V)
1067 G22
1067 G23
1067 G24
6
LTC1067/LTC1067-50
W
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067/LTC1067-50 Mode 1B
Noise Increase vs R5/R6 Ratio
2.0
LTC1067/LTC1067-50 Mode 3
Noise Increase vs R2/R4 Ratio
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.6
R2/R4 RATIO
0.7
0.8 0.9 1.0
0.2 0.3 0.4 0.5
2.0
2.5
3.0 3.5
0
0.5
1.0 1.5
R5/R6 RATIO
1067 G26
1067 G25
U
U
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PIN FUNCTIONS
V+, V– (Pins 1, 3,14): The V+ (Pins 1, 3) and the V– (Pin
14) should each be bypassed with a 0.1µF capacitor to an
adequateanalogground.Thefilter’spowersuppliesshould
be isolated from other digital or high voltage analog
supplies. A low noise linear supply is recommended.
Using a switching power supply will lower the signal-to-
noise ratio of the filter. The supply’s power-up slew rate
shouldbelessthan1V/µs.WhenV+ isappliedbeforeV–, and
V– isallowedtogoaboveground,adiodeshouldclampV–
to prevent latch-up. Figures 1 and 2 show typical connec-
tions for dual and single supply operation.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
+
V
CLK
V
CLK
NC
AGND
NC
AGND
1µF
+
–
+
+
–
+
–
V
V
V
V
V
V
V
0.1µF
0.1µF
SA
LTC1067
LTC1067-50
SB
LPB
BPB
SA
SB
LPB
BPB
0.1µF
LTC1067
LTC1067-50
LPA
LPA
BPA
BPA
HPA/NA
INV A
HPB/NB
INV B
HPA/NA
INV A
HPB/NB
INV B
DIGITAL
GROUND
PLANE
DIGITAL
GROUND
PLANE
200Ω
STAR
SYSTEM
GROUND
STAR
SYSTEM
GROUND
200Ω
CLOCK
SOURCE
CLOCK
SOURCE
106 7 F02
FOR MODE 3, THE SA AND SB SUMMING NODE PINS
ARE TIED TO THE AGND PIN
1067 F01
Figure 2. Single Supply Ground Plane Connections
Figure 1. Dual Supply Ground Plane Connections
7
LTC1067/LTC1067-50
U
U
U
PIN FUNCTIONS
SA, SB (Pins 4, 13):Summing Inputs. The summing pins’
connection, along with the other resistor connections,
determine the circuit topology (mode) of each 2nd order
section. These pins should never be left floating.
plane with at least a 1µF capacitor. An on-chip resistive
voltage divider sets the bias at one-half of the supply.
CLK (Pin 16): Clock Input. Any CMOS logic clock source
with a square-wave output and a 50% duty cycle (±10%)
is an adequate clock source for the device. The power
supplyfortheclocksourceshouldnotbethefilter’spower
supply. The analog ground for the filter should be con-
nected to the clock’s ground at a single point only. Table
1showstheclock’slowandhighlevelthresholdvaluesfor
dual supply or single supply operation. Logic low level
signals must be greater than the negative supply voltage.
With a ±5V power supply, the clock levels may be either
±5V or 0V to 5V. Logic high level signals should be less
than the positive supply voltage. However, when the
positive supply voltage is either 3V or 3.3V, the clock
signal can be as high as 5.5V.
LPA, BPA, HPA/NA, HPB/NB, BPB, LPB (Pins 5, 6, 7, 10,
11, 12): Output Pins. Each 2nd order section of the
LTC1067 has three outputs which typically source 33mA
and sink 2mA. Driving coaxial cable, capacitive loads or
resistive loads less than 10k will degrade the total har-
monic distortion performance ofany filter design. Referto
OutputLoadingintheApplicationsInformationsectionfor
more details. When evaluating the distortion or noise
performance of a filter, the output should be buffered with
a wideband amplifier.
INV A, INV B (Pins 8, 9): Inverting Input. These pins are
the high impedance inverting inputs of internal op amps.
They are susceptible to stray capacitance coupling to low
impedance nodes such as signal outputs and power
supply lines. Resistors that are connected from a signal
outputto theinverting inputpin should be locatedas close
to the inverting input as possible.
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY
±5V
HIGH LEVEL
≥ 2.2V
LOW LEVEL
≤ 0.50V
Single 5V
≥ 2.2V
≤ 0.50V
Single 3V, 3.3V
≥ 2V
≤ 0.40V
Sine waves are not recommended for the clock input. The
clock signal should be routed from the right side of the IC
package to avoid coupling to any power supply lines or
input or output signal paths. A 200Ω resistor between the
clock source and Pin 16 will slow down the rise and fall
times of the clock to reduce charge coupling of the clock.
This will result in less clock feedthrough noise on the
output signal.
AGND (Pin 15): Analog Ground. The filter performance
depends on the quality of the analog signal ground. For
either dual or single supply operation, an analog ground
plane surrounding the package is recommended. The
analog ground plane should be connected to any digital
ground at a single point. For dual supply operation Pin 15
is connected to the analog ground plane. For single supply
operationPin15shouldbebypassedtotheanalogground
W
BLOCK DIAGRA
+
1
V
V
HPA/NA
LPA
5
BPA
6
INV A
8
7
–
+
+
∑
+
3
–
4
15k
15k
AGND
15
SA
BPB
11
LPB
12
HPB/NB
10
+
–
+
∑
–
INV B
9
–
14
1067 BD
V
13
16
CLK
SB
8
LTC1067/LTC1067-50
W
U
ODES OF OPERATIO
Linear Technology’s universal switched-capacitor filters
are designed with a fixed internal, nominal fCLK/fO ratio.
The LTC1067 has a 100:1 fCLK/fO ratio and the
LTC1067-50 has a 50:1 fCLK/fO ratio. Filter designs often
requirethefCLK/fO ratioofeachsectiontobedifferentfrom
the nominal ratio and in most cases different from each
other. Ratios other than the nominal value are possible
with external resistors. Operating modes use external
resistors, connected in different arrangements to realize
different fCLK/fO ratios. By choosing the proper mode, the
Mode 1
In Mode 1, the ratio of the external clock frequency to the
center frequency of each 2nd order section is internally
fixed at the part’s nominal ratio. Figure 3 illustrates Mode
1 providing 2nd order notch, lowpass and bandpass
outputs. Mode 1 can be used to make high order Butter-
worth lowpass filters; it can also be used to make low Q
notches and for cascading 2nd order bandpass functions
tuned at the same center frequency. Mode 1 is faster than
Mode 3.
f
CLK/fO ratio canbeincreasedordecreasedfromthe part’s
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
nominal ratio.
The choice of operating mode also effects the transfer
function at the HP/N pins. The LP and BP pins always give
thelowpassandbandpasstransferfunctionsrespectively,
regardless of the mode utilized. The HP/N pins have a
different transfer function depending on the mode used.
Mode 1 yields a notch transfer function. Mode 3 yields a
highpass transfer function. Mode 2 yields a highpass-
notch transfer function (i.e., a highpass with a stopband
notch). More complex transfer functions, such as low-
pass-notch, allpass or complex zeros, are achieved by
summing two or more of the LP, BP or HP/N outputs. This
is illustrated in sections Mode 2n and Mode 3a.
C
C
R3
R2
N
S
LP
BP
R1
V
–
IN
–
+
Σ
∫
∫
1067 F03
+
f
CLK
f
=
; f = f
n O
O
RATIO
R3
R2
= H
R2
R1
R3
R1
AGND
Q = ; H = – ; H
= –
ON
OBP
H
OLP
ON
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
Choosing the proper mode(s) for a particular application
is not trivial and involves much more than just adjusting
the fCLK/fO ratio. Listed here are six of the nearly twenty
modes available. To make the design process simpler and
quicker, Linear Technology has developed the FilterCADTM
for Windows® design software. FilterCAD is an easy-to-
use, powerful and interactive filter design program. The
designer can enter a few filter specifications and the
program produces a full schematic. FilterCAD allows the
designer to concentrate on the filter’s transfer function
and not get bogged down in the details of the design.
Alternatively, those who have experience with the Linear
Technology family of parts can control all of the details
themselves. For a complete listing of all the operating
modes, consult the appendices of the FilterCAD manual or
the Help files in FilterCAD. FilterCAD can be obtained free
of charge on the Linear Technology web site (http://
www.linear-tech.com) or you can order the FilterCAD
CD-ROM by contacting Linear Technology’s marketing
department.
Figure 3. Mode 1, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
Mode 1b
Mode 1b is derived from Mode 1. In Mode 1b (Figure 4)
two additional resistors R5 and R6 are added to lower the
amount of voltage fed back from the lowpass output into
the input of the SA (or SB) switched-capacitor summer.
This allows the filter’s clock-to-center frequency ratio to
be adjusted beyond the part’s nominal ratio. Mode 1b
maintains the speed advantages of Mode 1 and should be
consideredanoptimummodeforhighQdesignswithfCLK
to fCUTOFF (or fCENTER) ratios greater than the part’s
nominal ratio.
FilterCAD is a trademark of Linear Technology Corporation.
Windows is a registered trademark of Microsoft Corporation.
9
LTC1067/LTC1067-50
W
U
ODES OF OPERATIO
C
C
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
R6
N
R5
C
C
R3
R2
R4
R3
R2
S
LP
BP
R1
V
–
IN
–
HP
S
LP
BP
+
Σ
∫
∫
R1
1067 F04
+
V
IN
–
+
–
f
+
R6
(R6 + R5)
CLK
f
=
;=f f
n
O
O
Σ
∫
∫
RATIO
R3
R2 (R6 + R5)
√
R6
AGND
1067 F05
R2
R3
R1
Q =
; H = – ; H
= –
OBP
ON
R1
√
R2 R6 + R5
f
1
CLK
R2
R4
R2
R4
R3
H
OLP
= –
f
=
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
; Q = 1.005
AGND
O
(
)
(
)
R1
R6
RATIO
R2
√
R3
√
1 –
(
)
(RATIO)(0.32)(R4)
R3
R1
1
R2
= – ; H
R4
R1
H
= –
OBP
;
H
OLP
= –
Figure 4. Mode 1b, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
OHP
R1
R3
1 –
(
)
(RATIO)(0.32)(R4)
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
The parallel combination of R5 and R6 should be kept
below 5k.
Figure 5. Mode 3, 2nd Order Section Providing
Highpass, Bandpass and Lowpass Outputs
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
C
C
Mode 3
R4
R3
In Mode 3, the ratio of the external clock frequency to the
center frequency of each 2nd order section can be ad-
justed above or below the part’s nominal ratio. Figure 5
illustrates Mode 3, the classical state variable configura-
tion, providing highpass, bandpass and lowpass 2nd
orderfilterfunctions. Mode3isslowerthanMode1. Mode
3 can be used to make high order all-pole bandpass,
lowpass and highpass filters.
R2
HPN
S
LP
BP
R1
V
IN
–
+
–
+
Σ
∫
∫
1067 F06
AGND
f
R2
R4
f
CLK
RATIO
CLK
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
1 +
f
=
; f =
n
O
√
)
RATIO
R2
R4
1
R3
1 +
Q = 1.005
(
R2
√
R3
1 –
(
)
(RATIO)(0.32)(R4)
Mode 2
R2
R1
R2
1
R2
R4
H
OHPN
= –
(AC GAIN, f >> f ); H
= –
OHPN
(DC GAIN)
O
R1
Mode 2 is a combination of Mode 1 and Mode 3, shown in
Figure6.WithMode2,theclock-to-centerfrequencyratio,
fCLK/fO, is always less than the part’s nominal ratio. The
advantage of Mode 2 is that it provides less sensitivity to
resistor tolerances than does Mode 3. Mode 2 has a
highpass-notch output where the notch frequency
depends solely on the clock frequency and is therefore
less than the center frequency, fO.
1 +
(
)
1
1
R2
R4
R3
R1
R2
R1
H
= –
; H
= –
OBP
OLP
R3
1 +
1 –
(
)
(
)
(RATIO)(0.32)(R4)
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
Figure 6. Mode 2, 2nd Order Filter Providing Highpass
Notch, Bandpass and Lowpass Outputs
10
LTC1067/LTC1067-50
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ODES OF OPERATIO
Mode 3a
Mode 2n
This is an extension of Mode 3 where the highpass and
lowpass outputs are summed through two external resis-
tors, RH and RL, to create a notch (see Figure 7). Mode 3a
is more versatile than Mode 2 because the notch fre-
quency can be higher or lower than the center frequency
of the 2nd order section. The external op amp of Figure 7
isnotalwaysrequired. Whencascadingthesectionsofthe
LTC1067, the highpass and lowpass outputs can be
summed directly into the inverting input of the next
section.
This mode extends the circuit topology of Mode 3a to
Mode 2 (Figure 8) where the highpass-notch and lowpass
outputs are summed through two external resistors, RH
and RL, to create a lowpass output with a notch higher in
frequency than the notch in Mode 2. This mode, shown in
Figure 8, is most useful in lowpass elliptic designs. When
cascading the sections of the LTC1067, the highpass-
notch and lowpass outputs can be summed directly into
the inverting input of the next section.
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
C
C
f
f
CLK
RATIO
R2
R4
R
H
CLK
f
=
f =
; n
O
√
√
R
L
RATIO
R4
R3
R2
1
R2
R4
R3
Q = 1.005
(
)
R2
R3
√
1 –
(
)
(RATIO)(0.32)(R4)
R
G
R
R2
R1
R4
R1
G
H
(f = ∞) =
; H (f = 0) =
OLPn
OHPn
(
)
(
)
(
)
(
)
HP
S
R
H
R
L
LP
R
BP
NOTE: RATIO = 100 FOR LTC1067
R1
V
= 50 FOR LTC1067-50
–
IN
–
+
Σ
∫
∫
R
G
L
+
–
+
HIGHPASS
OR LOWPASS
NOTCH OUTPUT
R
H
AGND
EXTERNAL OP AMP OR INPUT OP
1067 F07
AMP OF THE LTC1067, SIDES A OR B
Figure 7. Mode 3a, 2nd Order Filter Providing a Highpass Notch or Lowpass Notch Output
f
CLK
R2
R4
f
f
=
=
1 +
1 +
O
RATIO
√
√
f
C
C
CLK
R
H
n
RATIO
R
L
R
R
R
G
1
R2
R1
G
H
H
(f = 0)=
+
OLPn
R4
R3
R2
(
)
(
)
R
R2
R4
L
1 +
(
)
R2
R4
1
R3
1 +
Q = 1.005
(
)
√
R2
R3
1 –
(
)
(RATIO)(0.32)(R4)
HP
S
LP
R
BP
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
R1
V
–
IN
–
+
Σ
∫
∫
R
G
L
+
–
+
LOWPASS
NOTCH
OUTPUT
R
H
AGND
EXTERNAL OP AMP OR INPUT OP AMP
OF THE LTC1067, SIDES A OR B
1067 F08
Figure 8. Mode 2n, 2nd Order Filter Providing a Lowpass Notch Output
11
LTC1067/LTC1067-50
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APPLICATIONS INFORMATION
Aswitched-capacitorintegratorgenerallyexhibitsahigher
input offset than a discrete RC integrator. The larger offset
is mainly due to the charge injection from the CMOS
switches into the integrated capacitor. The integrator’s op
amp offset, typically a couple of millivolts, also adds to the
overall offset value. Figure 9 shows the input offsets from
a single 2nd order section. Table 2 lists the formula for the
output offset voltage for various modes and output pins.
limits defined by the Typical Performance Characteristics
graphs, passband gain variations of 2dB or more should be
expected.
Clock Feedthrough
ClockfeedthroughisdefinedastheRMSvalueoftheclock
frequency and its harmonics that are present at the filter’s
output pins. The clock feedthrough is tested with the
filter’s input grounded and depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
HP/N
BP
LP
INV
V
OS1
–
+
+
∑
V
OS2
V
OS3
–
1067 F09
Any parasitic switching transients during the rising and
fallingedgesoftheincomingclockarenotpartoftheclock
feedthroughspecifications. Switchingtransientshavefre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, can be greatly reduced by adding a
simple RC lowpass network at the final filter output. This
RC will completely eliminate any switching transients.
S
Figure 9. Block Diagram of a 2nd Order Section
Showing the Input Offsets
Operating Limits
The Maximum Q vs Frequency (fO) graphs, under Typical
Performance Characteristics, define an upper limit of
operating Q for each LTC1067 (or LTC1067-50) 2nd order
section. These graphs indicate the power supply, fO and Q
value conditions under which a filter implemented with an
LTC1067 will remain stable when operated at tempera-
tures of 70°C or less. For a 2nd order section, a bandpass
gainerrorof3dBorlessisarbitrarilydefinedasacondition
for stability.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and is used to deter-
mine the operating signal-to-noise ratio. Most of its fre-
quency contents lie within the filter passband and cannot
be reduced with post filtering. For a notch filter the noise
of the filter is centered at the notch frequency.
When the passband gain error begins to exceed 1dB, the use
of capacitor CC will reduce the gain error (capacitor CC is
connected from the lowpass node to the inverting node of a
2nd order section). Please refer to Figures 3 through 8. The
value of CC can be best determined experimentally, and as a
guide it should be about 5pF for each 1dB of gain error and
not to exceed 15pF. When operating the LTC1067 near the
Thetotalwidebandnoise(µVRMS)isnearlyindependentof
the value of the clock. The clock feedthrough specifica-
tions are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence.
Table 2. Output DC Offsets for a Second Order Section
MODE
V
V
V
V
V
V
OSLP
OSHP/N
OSBP
OS3
OS3
OS3
1
1b
2
V
V
V
[1 + (R2/R3) + (R2/R1)] – (V )(R2/R3)
V
– V
OSHP/N OS2
OS1
OS1
OS1
OS3
[1 + (R2/R3) + (R2/R1)] – (V )(R2/R3)
(V
– V )[1 + (R5/R6)]
OSHP/N OS2
OS3
[1 + (R2/R3) + (R2/R1) + (R2/R4) – (V
(R2/R3)](R4/R2 + R4) + (V )(R2/R2 + R4)
)
V
– V
OSHP/N OS2
OS3
OS2
3
V
V
V
[1 + (R4/R1) + (R4/R2) + (R4/R3)] – (V
)
OS2
OS2
OS3
OS1
(R4/R2) – (V )(R4/R3)
OS3
12
LTC1067/LTC1067-50
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APPLICATIONS INFORMATION
Aliasing
LTC1067-50, always use a 10× probe. Never use a 1×
probe. A standard 10× probe has a capacitance of 10pF to
15pF while a 1× probe’s capacitance can be as high as
150pF. The 1× probe will probably cause oscillation.
Aliasingisaninherentphenomenonofswitched-capacitor
filters and occurs when the frequency of the input signals
that produce the strongest aliased components have a
frequency, fIN, such as (fSAMPLING – fIN) that falls into the
filter’s passband. For both the LTC1067 and the
LTC1067-50, the sampling frequency is twice fCLK. If the
input signal spectrum is not band limited, aliasing may
occur.
What to Do with an Unused Section
If the LTC1067 or LTC1067-50 is used as a single 2nd
order filter, the other 2nd order section is not used. Do not
leave this section unconnected. If the section is uncon-
nected,inputsandoutputsarelefttofloattoundetermined
levels and oscillation may occur. The unused section
should be connected as shown in Figure 10.
Output Loading
The op amps on the LTC1067/LTC1067-50 have a rail-to-
rail output stage. The output loading issues can be divided
into resistive loading effects and capacitive loading ef-
fects.
+
V
INV
–
∑
Resistiveloadingeffectsthemaximumoutputsignalswing.
This effect is shown in the typical performance curves.
Note that the load on the output must include both the
feedback resistor and any external load resistor. For
example, consider the following situation: the part is
running on split power supplies, the section is configured
in Mode 3, the R4 resistor is 20k and an external 20k load
is connected from the LP node to ground. The load on the
LP output is 20k in parallel with 20k, or 10k. All testing on
the LTC1067/LTC1067-50 is done with a 10k load. For the
best results, the load resistance on all output pins should
be at least 10k.
+
HP
BP
LP
1067 F10
Figure 10. Connections for an Unused Section
Output Voltage Swing on a Single Supply Voltage
The typical performance curves show the output voltage
swing limitations. The curves show the output signal
swing, in volts peak-to-peak, versus the output load resis-
tance. The peak-to-peak swing is limited by the following
three considerations: the op amp’s output swings closer
to the negative supply than the positive supply, the AGND
pin is biased at the midpoint of the supplies and all
operating modes are inverting.
Capacitive loading reduces the stability of the op amps.
The signal at the output of a switched-capacitor filter is
composed of a series of very small steps. The op amp
mustrespondtoastepandfullysettlebeforethenextstep.
As the stability of the op amp is decreased, the output step
responsehasincreasedringingandamuchlongersettling
time. This longer settling time drastically lowers the maxi-
mum usable clock speed and introduces errors. If the
capacitive loading is sufficiently high, the stability will be
decreased to the point of oscillation at the output.
The op amps in the LTC1067/LTC1067-50 swing closer to
the negative supply rail than the positive supply rail. The
positive output voltage swing for single supply operation
isshowninFigures11and12. Thenegativeoutputvoltage
swing is about 15mV for the LTC1067 and 10mV for the
LTC1067-50. The negative output voltage swing is nearly
independent of load resistance since the load in this case
is connected to the V– supply rail.
TheLTC1067/LTC1067-50aresensitivetocapacitiveload-
ing. Capacitive loading should be kept below 20pF. Good,
tight layout techniques should be maintained at all times.
These parts should not drive long traces and never drive
a long coaxial cable. When probing the LTC1067 or
Forsinglesupplyapplications, theon-chipresistordivider
sets the voltage at the AGND pin to the midpoint of the V+
and V– potentials. The AGND voltage is the reference for
all internal op amps. If the input to the filter is at the V– rail,
13
LTC1067/LTC1067-50
U
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APPLICATIONS INFORMATION
5.0
Many applications are more concerned with the negative
outputswingthanthepositiveoutputswing.Interfacingto
an ADC running on a single 5V supply with a 4.096
reference voltage is a standard example. The LTC1067 or
LTC1067-50 will easily reach the 4.096V level for a full-
scale reading. The issue is how close does the output go
toground. Thefurthertheoutputisfromground, themore
codes that are essentially lost. The previous example
demonstrated that the lowest output voltage would be
about 250mV, although, as is shown below, 15mV is
achievable.
4.5
LTC1067
4.0
LTC1067-50
3.5
3.0
2.5
0
2
4
6
8
10 12 14 16 18 20
–
LOAD RESISTANCE (kΩ TO V )
1067 F11
To achieve a lower negative output swing voltage, the
AGNDvoltagemustbeadjusteddownbelowthemidpoint.
The AGND voltage is determined by two equal, on-chip
resistors. These resistors are typically 15k each. While the
ratioofthesetworesistorsistightlymatched, theabsolute
value of the resistors is not tightly controlled. Adjusting
the AGND voltage by simply adding an external resistor
can be done, but caution must be exercised.
Figure 11. LTC1067/LTC1067-50 Positive Output Voltage
Swing vs Load Resistance, 5V Supply
3.3
LTC1067
S
3.0
2.7
2.4
2.1
1.8
1.5
V
= 3.3V
LTC1067-50
V
= 3V
S
In Figure 13, a resistor is used to adjust the AGND voltage
for use with a 5V powered ADC with a full-scale input of
4.096V. The resistor value was chosen carefully to assure
that a 4.096V input signal to the filter yields a full-scale
reading from the ADC and a 0V input signal gives the
lowest possible value (15mV for the LTC1067 and 10mV
forthe LTC1067-50). The circuit works wellover tempera-
tureandpartvariations. Forthisapplication, the5Vsupply
must be above 4.75V.
0
2
4
6
8
10 12 14 16 18 20
–
LOAD RESISTANCE (kΩ TO V )
1067 F12
Figure 12. LTC1067/LTC1067-50 Positive Output Voltage
Swing vs Load Resistance, 3.3V/3V Supplies
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
64.9k
1%
V
CLK
the output of the first section is near the positive rail
(operating modes invert the signal). The output of the first
stage will saturate at about 250mV (typical for 5V supply)
from positive supply. The output from the second stage
will be 250mV from the negative supply rail (assuming
inversion again) even though the op amp’s output is
capable of swinging to within 15mV.
NC
AGND
1µF
5V
MIN
0.1µF
+
–
V
V
(4.75V
)
SA
LTC1067
LTC1067-50
SB
LPB
BPB
LPA
BPA
HPA/NA
INV A
HPB/NB
INV B
1067 F13
The positive output voltage swing being less than the
negative swing, coupled with the AGND potential set at the
midpoint of the supplies and inverting of the signal, yields
the following equation for peak-to-peak output swing:
Figure 13. Power and AGND Connections for
5V ADC with 4.096V Full Scale
VP-P Swing = (V+ – V–) – 2(V+ – VPOSITIVE SWING
)
14
LTC1067/LTC1067-50
U
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APPLICATIONS INFORMATION
Figure 14 illustrates how a resistor adjusts the AGND
voltage for use with a 3V/3.3V powered ADC with a full-
scale input of 2.048V. As in the previous circuit, the
resistorvaluewaschosencarefullytoassurethata2.048V
input signal to the filter yields a full-scale reading from the
ADC and a 0V input signal gives the lowest possible value.
For this application, the power supply must be above 2.7V
for an LTC1067-50 filter and above 3V for an LTC1067
filter.
obtain a demonstration board, call your local representa-
tive or Linear Technology’s marketing department.
The demonstration board has all integrated circuits, con-
nectors and decoupling capacitors installed. The board is
ready to be configured with the appropriate resistors and
jumper connections.
Therearetwosetsofpowersupplyconnections. Oneisfor
the LTC1067/LTC1067-50 and the other is for the buffer-
ing op amp on the board. Having separate connections
gives the board the most flexibility. The two sets of
supplies can be connected together if a common supply is
desired.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
33.2k
1%
V
CLK
NC
AGND
3V TO 3.6V
(LTC1067)
2.7V TO 3.6V
(LTC1067-50)
1µF
+
–
V
V
SA
LTC1067
LTC1067-50
SB
LPB
BPB
When configuring the board for split supply operation, a
jumper wire must be installed in the JPAGND position.
This connects the AGND pin of the device to the ground
plane of the board. The JPVNEG jumper must be left open.
The power supply is then connected to V+, V– and GND
turrets (all of the GND turrets on the board are the same).
For single supply operation, insert a wire in the JPVNEG
jumperandleavetheJPAGNDjumperopen.Thisconnects
the V– pin to the board’s ground plane. The JPAGND
jumper must be left open so that the on-chip resistor
network can set the AGND potential at the midpoint of the
supply. Connect the power supply to V+ and any GND
turret. The V– turret can be left open or shorted to the
adjacent GND turret. If the buffering op amp is run on the
same single voltage supply, the VOA+ turret and the V+
turrets must be connected together and the VOA– turret
must be shorted to the adjacent GND turret.
0.1µF
LPA
BPA
HPA/NA
INV A
HPB/NB
INV B
1067 F14
Figure 14. Power and AGND Connections for
3V/3.3V ADC with 2.048V Full Scale
Semi-Custom Filter Program
Linear Technology has in place a program to deliver fully
integratedfilters, customdesignedforanyspecifiedappli-
cation. Thesesemi-customfilters arebasedonanexisting
universal filter product with integrated, on-chip resistors.
The final filter is then tested to the exact parameters
defined for the application. The final result is a fully
integrated, accurately tested solution in a smaller pack-
age. For the LTC1067 or LTC1067-50 parts, a semi-
customfiltercomesintheSO-8packageandrequiresonly
aclockandadecouplingcapacitor. Formoredetailsonthe
semi-custom filter program, contact Linear Technology’s
marketing department.
The J1 BNC connector is the clock input. There is a 200Ω
series resistor connected between the connector and the
CLK pin of the part. This resistor, coupled with the CLK
pin’s input capacitance, slows down the rise and fall times
oftheclocksignalanddecreaseshighfrequencycoupling.
The clock input is not terminated to 50Ω or 75Ω. An
external terminator should be used.
Demonstration Board
Jumpers JP51 and JP61 are connected in parallel with
R51andR61respectively. JumperJP51connectstheLPA
pin of the part with the SA pin. This can be used for
operating modes 1 or 2. Alternatively, a 0Ω resistor in the
R51 position fulfills the same requirement. The JP61
jumper connects the SA pin of the part to the AGND pin.
There is a demonstration board available for the LTC1067/
LTC1067-50.Demonstrationboard150AhastheLTC1067
part installed and the board 150B has the LTC1067-50
installed. The schematic for the board is shown in Figure
15 and the assembly drawing is shown in Figure 16. To
15
LTC1067/LTC1067-50
U
W U U
APPLICATIONS INFORMATION
This would be used for operating Mode 3. Here, a 0Ω
resistorintheR61positionalsoworks. JumpersJP52and
JP62 perform the same functions on the B side of the part.
Several other jumpers should be connected as follows:
JP1: Install a jumper wire from position 1 to position 2,
leave the other positions open.
The buffering amplifier can be configured for inverting or
noninverting operation. For inverting applications, con-
nect jumper JP2 positions 1 and 2. Additionally, connect
jumper JP4 for split supply applications or JP8 for a single
supply. For a noninverting application, connect jumper
JP2 positions 2 and 3.
JP5: Install a jumper wire if split supply, leave open if
single supply.
JP6: Leave open.
JP7: Install a jumper wire.
JP9: Install a jumper wire if single supply, leave open if
split supply.
CONNECT THIS JUMPER
FOR DUAL SUPPLIES
JPAGND
C1
CONNECT THIS JUMPER
FOR SINGLE SUPPLIES.
THE LTC1067 HAS ON-CHIP
RESISTORS TO GENERATE
1/2 SUPPLY FOR AGND
10µF, 6.3V
+
C2, 0.1µF
J1
CLOCK
D2
IN
R1
200Ω
1%
JP3
C5
TP1
TP2
MBR0630T1
–
+
V
V
JP62
R62
C4
JPVNEG
JP61
C6, 0.1µF
+
C3
10µF
1
2
3
4
5
6
7
8
16
D1
+
+
10µF
V
CLK
16V
MBR0630T1
R61
JP51
R51
C7
0.1µF
16V
15
14
13
12
11
10
9
R3
R2
JP8
JP4
NC
AGND
JP52
TP8
+
–
TP9
V
V
LTC1067
OR
LTC1067-50
TP3
VOA
R52
+
SA
SB
C8
0.1µF
R
+
C9
10µF
36V
R41
R31
R21
L2
B2
H2
LPA
LPB
BPB
JP2
3
2
R
R
BPA
1
8
1
3
2
+
–
TP5
HPA/NA
INV A
HPB/NB
INV B
R11
2
TP4
IN
TP10
JP1
V
OUT
1
3
V
1/2
LT1498
TP6
C13
4
4
R42
R32 R22
R
R
R
B1
L1
H1
TP7
–
VOA
C11
10µF
36V
C10
0.1µF
+
TP11
JP9
R4
JP6
JP5
+
–
5
6
7
1/2
LT1498
JP7
C12
1067 F15
Figure 15. Schematic for the LTC1067/LTC1067-50 Demo Board
16
LTC1067/LTC1067-50
U
W U U
APPLICATIONS INFORMATION
Figure 16. Silkscreen for the LTC1067/LTC1067-50 Demo Board
U
TYPICAL APPLICATIONS
5th Order Lowpass with Input RC (Fixed Frequency)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
f
V
CLK
5V
CLK
0.1µF
–5V
NC
AGND
0.1µF
+
–
V
V
SA
SB
LTC1067
R42, 47.5k
R41, 20k
LPA
LPB
BPB
R32, 29.4k
R22, 45.3k
R31, 47.5k
R21, 22.6k
V
V
f
C
f
±5V
20k
750pF 1000pF
2MHz 1.5MHz
5V
10k
1500pF
1MHz
3V
S
IN
BPA
15k
5k
CUTOFF
R
IN1
16.9k
3000pF
500kHz
IN1
R
22.6k
HPA/NA HPB/NB
IN2
CLK
INV A
INV B
, 118k
C
IN1
1500pF
5%
1067 TA05a
R
H1
V
OUT
R
L1
, 24.3k
Frequency Response (fCUTOFF = 10kHz)
Passband Gain Variation Due to CIN
10
1.00
0
0.75
0.50
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.25
C
= 1500pF – 5%
IN1
C
= 1500pF
0
IN1
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
C
= 1500pF + 5%
IN1
1
10
100
1
2
4
6
8 10
20
FREQUENCY (kHz)
FREQUENCY (kHz)
1067 TA05b
1067 TA05c
17
LTC1067/LTC1067-50
U
TYPICAL APPLICATIONS
1kHz Linear Phase Bandpass Filter
16
1
2
3
4
5
6
7
8
+
100kHz
V
CLK
5V
0.1µF
15
14
13
12
11
10
9
R61
–5V
NC
AGND
40.2k
0.1µF
+
–
V
V
R51
4.99k
SA
SB
LTC1067
R42, 80.6k
LPA
BPA
LPB
BPB
R32, 53.6k
R22, 10k
R31, 56.2k
V
S
±5V
5V (OR±2.5V) 3V (OR±1.5V)
R21, 10k
MAXIMUM
FREQUENCY
CENTER
HPA/NA HPB/NB
R11
60.4k
5kHz
2.5kHz
2.2kHz
INV A
R
INV B
, 36.5k
V
IN
1067 TA06a
B1
V
OUT
Gain and Group Delay vs Frequency
10
Sine Burst Response
5
0
GAIN
INPUT
(500mV/DIV)
–5
–10
–15
–20
–25
–30
–35
–40
3.0
DELAY
2.5
2.0
1.5
1.0
0.5
0
OUTPUT
(50mV/DIV)
600
760
920
1080
1240
1400
5ms/DIV
FREQUENCY (Hz)
1067 TA06c
1067 TA06b
Single Supply, 4th Order Bandpass Filter
fCENTER = fCLK/64, –3dB BW = fCENTER/20
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
64kHz
V
CLK
5V
0.1µF
R61
7.32k
NC
AGND
+
–
V
V
1µF
R51
4.99k
V
S
MAXIMUM f
CENTER
R62
SA
SB
R52
4.99k
8.66k
SINGLE 5V
SINGLE 3.3V
SINGLE 3V
12kHz
7.5kHz
5.5kHz
LTC1067-50
LPA
LPB
R32, 255k
R22, 4.99k
R31, 255k
R21, 4.99k
BPA
BPB
NOISE
(FILTER INPUT AT V/2)
+
HPA/NA
INV A
HPB/NB
INV B
R11
267k
V
S
SINGLE 5V
SINGLE 3.3V
SINGLE 3V
42µ6V
3µ3V3
RMS
RMS
RMS
V
IN
2µ9V0
R
, 115k
B1
V
OUT
1067 TA07a
18
LTC1067/LTC1067-50
U
TYPICAL APPLICATIONS
Single Supply, 4th Order Bandpass Filter
VS = 5V, fCLK = 64kHz
Gain vs Frequency
Gain vs Frequency
Sine Burst Response
–5
1
0
5
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
V
IN
(500mV/DIV)
10
15
20
25
30
35
40
45
V
OUT
(50mV/DIV)
500
700
900
1100
1300
1500
960
980
1000
1020
1040
5ms/DIV
FREQUENCY (kHz)
FREQUENCY (kHz)
1067 TA07d
1067 TA07b
1067 TA07b
LTC1067 Dual Bandpass Filters
VS = ±5V, fCLK = 150kHz (fCENTER1 =1.3kHz, fCENTER2 = 2.1kHz)
Frequency Response
5
0
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
V
V
OUT2
5V
150kHz
V
CLK
OUT1
0.1µF
–5V
0.1µF
NC
AGND
–5
R61
15k
+
–
V
V
–10
–15
–20
–25
–30
–35
–40
–45
R51
4.99k
SA
SB
LTC1067
R42, 5.23k
R32, 75k
LPA
BPA
LPB
BPB
R31, 232k
R21, 4.99k
R22, 4.99k
HPA/NA HPB/NB
INV A INV B
R11
232k
V
IN1
R12,140k
1
2
3
4
5
V
V
V
IN2
OUT2
OUT1
1067 TA08a
FREQUENCY (kHz)
1067 TA08b
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.015 ± 0.004
× 45°
16 15 14 13 12 11 10
9
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.025
(0.635)
BSC
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
GN16 (SSOP) 1197
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1067/LTC1067-50
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
16
15
14
13
12
11
10
9
0.004 – 0.010
(0.101 – 0.254)
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S16 0695
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
U
TYPICAL APPLICATION
1.02kHz Notch Filter for Telecom System
Frequency Response
0
200Ω
1µF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
+
f
= 125kHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5V
CLK
V
CLK
0.1µF
AGND
NC
–
+
V
V
R61, 9.88k*
R62, 10k*
SB
SA
LTC1067
R52, 4.99k*
R32, 464k
R51, 4.99k*
LPB
BPB
LPA
R31, 61.9k
BPA
V
OUT
R21, 10k
R22, 75k
C22, 30pF**
10
9
HPA/NA
INV A
HPB/NB
INV B
C21, 300pF**
800
900
1000
1100
1200
RH1, 40.2k
V
***
IN
FREQUENCY (kHz)
R11, 18.7k
1067 TA04
R51, R61, R52, R62 ARE 0.1% TOLERANCE RESISTORS
*
C21 AND C22 IMPROVE THE NOTCH DEPTH WHERE
**
1
(30)(f
) <
< (75)(f
)
NOTCH
NOTCH
2π(R2x)(C2X)
WITHOUT C21 AND C22 THE NOTCH DEPTH IS LIMITED TO –35dB
≤ 1.25V
V
1067 TA03
***
IN
P-P
RELATED PARTS
PART NUMBER
LTC1068-25
LTC1068-50
LTC1068-200
LTC1068
DESCRIPTION
COMMENTS
25:1 Clock-to-f Ratio
High Speed Quad Universal Building Block Filter
Low Power Quad Universal Building Block Filter
O
50:1 Clock-to-f Ratio
O
Low Noise, Oversampled Quad Universal Building Block Filter
Quad Universal Building Block Filter
200:1 Clock-to-f Ratio
O
100:1 Clock-to-f Ratio
O
LTC1562
Quad, Universal, Continuous Time Building Block
10kHz < f < 150kHz
C
10675f LT/TP 0698 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1997
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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