LTC1096LCS8#TR [Linear]
LTC1096 - Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC1096LCS8#TR |
| 厂家： | 
Linear |
| 描述： | LTC1096 - Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1096/LTC1096L
LTC1098/LTC1098L
Micropower Sampling
8-Bit Serial I/O A/D Converters
U
DESCRIPTIO
EATURE
S
F
The LTC®1096/LTC1096L/LTC1098/LTC1098L are
micropower, 8-bit A/D converters that draw only 80µA of
supplycurrentwhenconverting.Theyautomaticallypower
down to 1nA typical supply current whenever they are not
performing conversions. They are packaged in 8-pin SO
packages and have both 3V (L) and 5V versions. These
8-bit,switched-capacitor,successiveapproximationADCs
include sample-and-hold. The LTC1096/LTC1096L have a
single differential analog input. The LTC1098/LTC1098L
offer a software selectable 2-channel MUX.
■
■
■
■
■
■
■
■
■
■
80µA Maximum Supply Current
1nA Typical Supply Current in Shutdown
8-Pin SO Plastic Package
5V Operation (LTC1096/LTC1098)
3V Operation (LTC1096L/LTC1098L)(2.65V Min)
Sample-and-Hold
16µs Conversion Time
33kHz Sample Rate
±0.5LSB Total Unadjusted Error Over Temp
Direct 3-Wire Interface to Most MPU Serial Ports and
All MPU Parallel I/O Ports
On-chip serial ports allow efficient data transfer to a wide
rangeofmicroprocessorsandmicrocontrollersoverthree
wires.This,coupledwithmicropowerconsumption,makes
remote location possible and facilitates transmitting data
through isolation barriers.
O U
PPLICATI
S
A
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Battery-Operated Systems
Remote Data Acquisition
Battery Monitoring
Battery Gas Gauges
Temperature Measurement
Isolated Data Acquisition
These circuits can be used in ratiometric applications or
with an external reference. The high impedance analog
inputs and the ability to operate with reduced spans
(below 1V full scale) allow direct connection to sensors
and transducers in many applications, eliminating the
need for gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Supply Current vs Sample Rate
10µW, S8 Package, 8-Bit A/D
Samples at 200Hz and Runs Off a 5V Battery
1000
T
= 25°C
= V
A
V
= 5V
CC
REF
1µF
5V
100
10
1
MPU
(e.g., 8051)
CS/
V
P1.4
P1.3
P1.2
CC
SHUTDOWN
+IN
CLK
ANALOG INPUT
0V TO 5V RANGE
LTC1096
–IN
D
OUT
GND
V
REF
LTC1096/8 • TA01
0.1
1
SAMPLE FREQUENCY, f
10
100
(kHz)
SMPL
LTC1096/98 • TPC03
1
LTC1096/LTC1096L
LTC1098/LTC1098L
W W W
U
ABSOLUTE AXI U RATI GS
(Notes 1 and 2)
Operating Temperature
Supply Voltage (VCC) to GND................................... 12V
Voltage
LTC1096AC/LTC1096C/LTC1096LC/
LTC1098AC/LTC1098C/LTC1098LC ....... 0°C to 70°C
LTC1096AI/LTC1096I/LTC1096LI/
LTC1098AI/LTC1098I/LTC1098LI ..... –40°C to 85°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
Analog and Reference ................ –0.3V to VCC + 0.3V
Digital Inputs.........................................–0.3V to 12V
Digital Outputs ........................... –0.3V to VCC + 0.3V
Power Dissipation.............................................. 500mW
Storage Temperature Range ................. –65°C to 150°C
W
U
/O
PACKAGE RDER I FOR ATIO
(Notes 3)
TOP VIEW
TOP VIEW
ORDER PART
ORDER PART
NUMBER
CS/
SHUTDOWN
+IN
CS/
NUMBER
1
2
3
4
V
V
(V
CC REF)
8
7
6
5
1
2
3
4
8
7
6
5
CC
SHUTDOWN
CLK
D
CH0
CH1
GND
CLK
D
LTC1098ACN8
LTC1098ACS8
LTC1098AIN8
LTC1098AIS8
LTC1098CN8
LTC1098CS8
LTC1098IN8
LTC1098IS8
LTC1098LCS8
LTC1098LIS8
LTC1096ACN8
LTC1096ACS8
LTC1096AIN8
LTC1096AIS8
LTC1096CN8
LTC1096CS8
LTC1096IN8
LTC1096IS8
LTC1096LCS8
LTC1096LIS8
–IN
OUT
OUT
V
GND
D
IN
REF
N8 PACKAGE
S8 PACKAGE
N8 PACKAGE
8-LEAD PLASTIC DIP
S8 PACKAGE
8-LEAD PLASTIC DIP
8-LEAD PLASTIC SOIC
8-LEAD PLASTIC SOIC
TJMAX = 150°C, θJA = 130°C/W (N8)
TJMAX = 150°C, θJA = 175°C/W (S8)
TJMAX = 150°C, θJA = 130°C/W (N8)
TJMAX = 150°C, θJA = 175°C/W (S8)
S8 PART MARKING
S8 PART MARKING
1098
1098A
1098I
1098IA 1098LI
1098L
1096
1096A
1096I
1096IA
1096L
1096LI
Consult factory for Military grade parts.
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
LTC1096
LTC1098
3.0
3.0
9
6
V
V
CC
V
= 5V Operation
CC
f
Clock Frequency
Total Cycle Time
V
= 5V
25
500
kHz
CC
CLK
CYC
t
LTC1096, f
LTC1098, f
= 500kHz
= 500kHz
29
29
µs
µs
CLK
CLK
t
t
Hold Time, D After CLK↑
V
= 5V
150
ns
IN
CC
hDI
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
V
V
= 5V, LTC1096
= 5V, LTC1098
500
500
ns
ns
CC
CC
suCS
t
Wake-Up Time CS↓ Before First CLK↓ After First CLK↑
(See Figure 1 LTC1096 Operating Sequence)
V
= 5V, LTC1096
10
µs
WAKEUP
CC
Wake-Up Time CS↓ Before MSBF Bit CLK↓
V
= 5V, LTC1098
10
µs
CC
(See Figure 2 LTC1098 Operating Sequence)
t
t
Setup Time, D Stable Before CLK↑
V
V
= 5V
= 5V
400
0.8
ns
suDI
IN
CC
CC
CLK High Time
µs
WHCLK
2
LTC1096/LTC1096L
LTC1098/LTC1098L
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
MIN
0.8
1
TYP
MAX
UNITS
µs
t
t
t
CLK Low Time
V
V
= 5V
= 5V
WLCLK
WHCS
WLCS
CC
CC
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
µs
LTC1096, f
LTC1098, f
= 500kHz
= 500kHz
28
28
µs
µs
CLK
CLK
V
= 3V Operation
CC
f
t
Clock Frequency
Total Cycle Time
V
= 3V
CC
25
250
kHz
CLK
CYC
LTC1096, f
LTC1098, f
= 250kHz
= 250kHz
58
58
µs
µs
CLK
CLK
t
t
Hold Time, D After CLK↑
V
= 3V
450
ns
IN
hDI
CC
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
V
V
= 3V, LTC1096
= 3V, LTC1098
1
1
µs
µs
suCS
CC
CC
t
Wake-Up Time CS↓ Before First CLK↓ After First CLK↑
(See Figure 1 LTC1096 Operating Sequence)
V
= 3V, LTC1096
10
µs
WAKEUP
CC
Wake-Up Time CS↓ Before MSBF Bit CLK↓
V
= 3V, LTC1098
10
µs
CC
(See Figure 2 LTC1098 Operating Sequence)
t
t
t
t
t
Setup Time, D Stable Before CLK↑
V
V
V
V
= 3V
= 3V
= 3V
= 3V
1
1.6
1.6
2
µs
µs
µs
µs
suDI
IN
CC
CC
CC
CC
CLK High Time
WHCLK
WLCLK
WHCS
WLCS
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
LTC1096, f
LTC1098, f
= 250kHz
= 250kHz
56
56
µs
µs
CLK
CLK
LTC1096L/LTC1098L
SYMBOL
PARAMETER
CONDITIONS
MIN
2.65
25
TYP
MAX
4.0
UNITS
V
V
f
Supply Voltage
Clock Frequency
Total Cycle Time
CC
V
= 2.65V
250
kHz
CC
CLK
CYC
t
LTC1096L, f
LTC1098L, f
= 250kHz
= 250kHz
58
58
µs
µs
CLK
CLK
t
t
Hold Time, D After CLK↑
V
= 2.65V
450
ns
IN
CC
hDI
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
V
V
= 2.65V, LTC1096L
= 2.65V, LTC1098L
1
1
µs
µs
CC
CC
suCS
t
Wake-Up Time CS↓ Before First CLK↓ After First CLK↑
(See Figure 1, LTC1096L Operating Sequence)
V
= 2.65V, LTC1096L
10
µs
WAKEUP
CC
Wake-Up Time CS↓ Before MSBF Bit CLK↓
V
= 2.65V, LTC1098L
10
µs
CC
(See Figure 2, LTC1098L Operating Sequence)
t
t
t
t
t
Setup Time, D Stable Before CLK↑
V
V
V
V
= 2.65V
= 2.65V
= 2.65V
= 2.65V
1
µs
µs
µs
µs
suDI
IN
CC
CC
CC
CC
CLK High Time
1.6
1.6
2
WHCLK
WLCLK
WHCS
WLCS
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
LTC1096L, f
LTC1098L, f
= 250kHz
= 250kHz
56
56
µs
µs
CLK
CLK
3
LTC1096/LTC1096L
LTC1098/LTC1098L
U
U W
CO VERTER A D ULTIPLEXER CHARACTERISTICS
LTC1096/LTC1098
VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.
LTC1096A/LTC1098A
LTC1096/LTC1098
MIN TYP MAX
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
V
Resolution (No Missing Code)
Offset Error
●
●
●
●
●
8
8
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±1.0
±1.0
Linearity Error
(Note 4)
Full Scale Error
Total Unadjusted Error (Note 5)
Analog Input Range
REF Input Range (Notes 6, 7)
V
REF
= 5.000V
(Notes 6, 7)
–0.05V to V + 0.05V
–0.05V to V + 0.05V
CC
4.5 ≤ V ≤ 6V
V
V
CC
CC
6V < V ≤ 9V, LTC1096
–0.05V to 6V
CC
Analog Input Leakage Current
(Note 8)
●
±1.0
±1.0
µA
LTC1096/LTC1098
VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
LTC1096A/LTC1098A
LTC1096/LTC1098
MIN TYP MAX
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
V
Resolution (No Missing Code)
Offset Error
●
●
●
●
●
8
8
±0.75
±0.5
±1.0
±1.0
±1.0
±1.0
±1.0
±1.5
Linearity Error
(Notes 4, 9)
Full-Scale Error
Total Unadjusted Error (Notes 5, 9)
Analog Input Range
V
= 2.500V
REF
–0.05V to V + 0.05V
(Notes 6, 7)
3V ≤ V ≤ 6V
CC
REF Input Range (Notes 6, 7, 9)
Analog Input Leakage Current
–0.05V to V + 0.05V
V
CC
CC
(
Notes 8, 9
)
●
±1.0
±1.0
µA
LTC1096L/LTC1098L
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
LTC1096L/LTC1098L
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
V
Resolution (No Missing Code)
Offset Error
●
●
●
●
●
8
±1.0
±1.0
±1.0
±1.5
Linearity Error
(Note 4)
Full-Scale Error
Total Unadjusted Error (Notes 5)
Analog Input Range
REF Input Range (Note 6)
Analog Input Leakage Current
V
REF
= 2.5V
(Notes 6, 7)
–0.05V to V + 0.05V
CC
2.65V ≤ V ≤ 4.0V
–0.05V to V + 0.05V
V
CC
CC
(Note 8)
●
±1.0
µA
4
LTC1096/LTC1096L
LTC1098/LTC1098L
U
DIGITAL ANDDCELECTRICALCHARACTERISTICS
LTC1096/LTC1098
VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.0
IH
IL
CC
CC
IN
0.8
2.5
V
I
I
= V
µA
IH
IL
CC
= 0V
–2.5
µA
IN
V
V
V
= 4.75V, I = 10µA
= 4.75V, I = 360µA
●
●
4.5
2.4
4.74
4.72
V
V
OH
CC
CC
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Current
V
= 4.75V, I = 1.6mA
●
●
0.4
V
µA
OL
CC
O
I
I
I
I
CS ≥ V
±3.0
OZ
IH
V
V
= 0V
–25
45
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
CS = V
●
●
●
0.001
3.500
2.5
7.5
µA
µA
µA
REF
CC
t
t
≥ 200µs, f
≤ 50kHz
CLK
= 500kHz
CYC
CYC
= 29µs, f
35.000 50.0
CLK
I
Supply Current
CS = V
●
0.001
3.0
µA
CC
CC
LTC1096, t
LTC1096, t
≥ 200µs, f
≤ 50kHz
CLK
= 500kHz
●
●
40
120
80
180
µA
µA
CYC
CYC
= 29µs, f
CLK
LTC1098, t
LTC1098, t
≥ 200µs, f
≤ 50kHz
CLK
= 500kHz
●
●
44
155
88
230
µA
µA
CYC
CYC
= 29µs, f
CLK
LTC1096/LTC1098
VCC = 3V, VREF = 2.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (Note 9)
Low Level Input Current (Note 9)
High Level Output Voltage
V
V
V
V
= 3.6V
= 3V
●
●
●
●
1.9
IH
IL
CC
CC
IN
0.45
2.5
V
I
I
= V
µA
IH
IL
CC
= 0V
–2.5
µA
IN
V
V
V
= 3V, I = 10µA
●
●
2.3
2.1
2.69
2.64
V
V
OH
CC
CC
O
= 3V, I = 360µA
O
V
Low Level Output Voltage
V
= 3V, I = 400µA
●
●
0.3
V
µA
OL
CC
O
I
I
I
I
Hi-Z Output Leakage (Note 9)
Output Source Current (Note 9)
Output Sink Current (Note 9)
Reference Current (Note 9)
CS ≥ V
±3.0
OZ
IH
V
V
= 0V
–10
15
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
CS = V
●
●
●
0.001
3.500
2.5
7.5
µA
µA
µA
REF
CC
t
t
≥ 200µs, f
≤ 50kHz
CLK
= 250kHz
CYC
CYC
= 58µs, f
35.000 50.0
CLK
I
Supply Current (Note 9)
CS = V
●
0.001
3.0
µA
CC
CC
LTC1096, t
LTC1096, t
≥ 200µs, f
≤ 50kHz
CLK
= 250kHz
●
●
40
120
80
180
µA
µA
CYC
CYC
= 58µs, f
CLK
LTC1098, t
LTC1098, t
≥ 200µs, f
≤ 50kHz
CLK
= 250kHz
●
●
44
155
88
230
µA
µA
CYC
CYC
= 58µs, f
CLK
5
LTC1096/LTC1096L
LTC1098/LTC1098L
U
DIGITAL ANDDCELECTRICALCHARACTERISTICS
LTC1096L/LTC1098L
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.6V
●
●
●
●
1.9
CC
CC
IN
= 2.65V
0.45
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
OH
V
V
= 2.65V, I = 10µA
= 2.65V, I = 360µA
●
●
2.3
2.1
2.64
2.50
V
V
CC
CC
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Current
V
= 2.65V, I = 400µA
●
●
0.3
V
µA
OL
CC
O
I
I
I
I
CS = High
±3.0
OZ
V
V
= 0V
–10
15
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
CS = V
●
●
●
0.001
3.500
2.5
7.5
µA
µA
µA
REF
CC
t
t
≥ 200µs, f
≤ 50kHz
CLK
= 250kHz
CYC
CYC
= 58µs, f
35.000 50.0
CLK
I
Supply Current
CS = V
●
0.001
3.0
µA
CC
CC
LTC1096L, t
LTC1096L, t
≥ 200µs, f
≤ 50kHz
CLK
= 250kHz
●
●
40
120
80
180
µA
µA
CYC
CYC
= 58µs, f
CLK
LTC1098L, t
LTC1098L, t
≥ 200µs, f
≤ 50kHz
CLK
= 250kHz
●
●
44
155
88
230
µA
µA
CYC
CYC
= 58µs, f
CLK
AC CHARACTERISTICS
LTC1096/LTC1098
VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
t
t
t
t
t
t
t
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
1.5
CLK Cycles
SMPL
●
33
kHz
SMPL(MAX)
See Operating Sequence
See Test Circuits
8
CLK Cycles
CONV
dDO
dis
en
Delay Time, CLK↓ to D
Data Valid
●
●
●
200
170
60
450
450
250
ns
ns
ns
ns
ns
ns
OUT
Delay Time, CS↑ to D
Hi-Z
See Test Circuits
OUT
Delay Time, CLK↓ to D
Enable
See Test Circuits
OUT
Time Output Data Remains Valid After CLK↓
C
LOAD
= 100pF
180
70
hDO
f
D
D
Fall Time
See Test Circuits
See Test Circuits
●
●
250
100
OUT
OUT
Rise Time
25
r
C
IN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
6
LTC1096/LTC1096L
LTC1098/LTC1098L
AC CHARACTERISTICS
LTC1096/LTC1098
VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
t
t
t
t
t
t
t
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
1.5
CLK Cycles
SMPL
●
16.5
kHz
SMPL(MAX)
See Operating Sequence
See Test Circuits (Note 9)
See Test Circuits (Note 9)
See Test Circuits (Note 9)
8
CLK Cycles
CONV
dDO
dis
en
Delay Time, CLK↓ to D
Data Valid
●
●
●
500
220
160
400
70
1000
800
ns
ns
ns
ns
ns
ns
OUT
Delay Time, CS↑ to D
Hi-Z
OUT
Delay Time, CLK↓ to D
Enable
480
OUT
Time Output Data Remains Valid After CLK↓
C
LOAD
= 100pF
hDO
f
D
D
Fall Time
See Test Circuits (Note 9)
See Test Circuits (Note 9)
●
●
250
150
OUT
OUT
Rise Time
50
r
C
IN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
LTC1096L/LTC1098L
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
t
t
t
t
t
t
t
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
1.5
CLK Cycles
SMPL
●
16.5
kHz
SMPL(MAX)
See Operating Sequence
See Test Circuits
8
CLK Cycles
CONV
dDO
dis
en
Delay Time, CLK↓ to D
Data Valid
●
●
●
500
220
160
400
70
1000
800
ns
ns
ns
ns
ns
ns
OUT
Delay Time, CS↑ to D
Hi-Z
See Test Circuits
OUT
Delay Time, CLK↓ to D
Enable
See Test Circuits
480
OUT
Time Output Data Remains Valid After CLK↓
C
= 100pF
LOAD
hDO
f
D
D
Fall Time
See Test Circuits
See Test Circuits
●
●
250
200
OUT
OUT
Rise Time
50
r
C
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
IN
Digital Input
5
pF
The
● denotes specifications which apply over the operating temperature
input does not exceed the supply voltage by more than 50mV, the output
code will be correct. To achieve an absolute 0V to 5V input voltage range
will therefore require a minimum supply voltage of 4.950V over initial
range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: For the 8-lead PDIP, consult the factory.
Note 4: Linearity error is specified between the actual and points of the
A/D transfer curve.
tolerance, temperature variations and loading. For 5.5V < V ≤ 9V,
CC
reference and analog input range cannot exceed 5.55V. If reference and
analog input range are greater than 5.55V, the output code will not be
guaranteed to be correct.
Note 7: The supply voltage range for the LTC1096L/LTC1098L is from
2.65V to 4V. The supply voltage range for the LTC1096 is from 3V to 9V,
but the supply voltage range for the LTC1098 is only from 3V to 6V.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: These specifications are either correlated from 5V specifications or
guaranteed by design.
Note 5: Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
Note 6: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above V . This spec allows 50mV forward
CC
bias of either diode. This means that as long as the reference or analog
7
LTC1096/LTC1096L
LTC1098/LTC1098L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Clock Rate
for Active and Shutdown Modes
Supply Current vs Supply Voltage
Active and Shutdown Modes
Supply Current vs Sample
Frequency LTC1096
250
200
150
100
50
1000
100
10
100
80
T
= 25°C
T
= 25°C
REF
A
T
= 25°C
= V
A
A
CS = 0V
V
= 2.5V
V
= 5V
REF
CC
V
= 9V
V
CC
= 5V
CC
60
40
“ACTIVE” MODE CS = 0
10
20
0.001
0
0.002
“SHUTDOWN” MODE CS = V
CS = V
CC
CC
1
0
0.1
1
SAMPLE FREQUENCY, f
10
100
1
10
100
1000
0
1
2
3
4
5
6
7
8
9
(kHz)
SMPL
FREQUENCY (kHz)
SUPPLY VOLTAGE,V (V)
CC
LTC1096/98 • TPC01
LTC1096/98 • TPC03
LTC1096/98 • TPC02
Change in Offset vs
Reference Voltage LTC1096
Change in Offset vs
Supply Voltage
Change in Linearity vs
Reference Voltage LTC1096
0.50
0.25
0
0.50
0.25
0
0.5
0.4
T
= 25°C
T
= 25°C
= 2.5V
REF
T
= 25°C
A
A
A
V
F
= 5V
V
F
V
F
= 5V
CC
CC
= 500kHz
= 100kHz
= 500kHz
CLK
CLK
CLK
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.25
–0.50
–0.25
–O.50
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
SUPPLY VOLTAGE, V (V)
CC
LTC1096/98 • TPC04
LTC1096/98 • TPC06
LTC1096/98 • TPC05
Change in Linearity vs
Supply Voltage
Change in Gain vs
Reference Voltage LTC1096
Change in Gain vs Supply Voltage
0.5
0.4
0.5
0.4
0.50
0.25
0
T
V
F
= 25°C
T
= 25°C
T
V
F
= 25°C
CC
A
A
A
= 2.5V
V
F
= 2.5V
= 5V
REF
REF
= 100kHz
= 100kHz
CLK
= 500kHz
CLK
0.3
0.3
CLK
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
–0.25
–O.50
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
SUPPLY VOLTAGE, V (V)
SUPPLY VOLTAGE, V (V)
VOLTAGE REFERENCE (V)
CC
CC
LTC1096/98 • TPC08
LTC1096/98 • TPC07
LTC1096/98 • TPC09
8
LTC1096/LTC1096L
LTC1098/LTC1098L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Digital Input Logic Threshold
Maximum Clock Frequency vs
Source Resistance
Maximum Clock Frequency vs
Supply Voltage
vs Supply Voltage
1.5
5
1
0.75
0.50
0.25
0
T
= 25°C
REF
T
= 25°C
A
T
= 25°C
= V
A
A
CC
V
IN
+ INPUT
– INPUT
V
= 2.5V
V
= 5V
REF
1.25
4
3
2
1
0
–
R
1.0
SOURCE
0.75
0.5
0.25
0
0
2
4
6
8
10
0
2
6
8
10
4
1
10
100
–
SUPPLY VOLTAGE (V)
R
(kΩ)
SUPPLY VOLTAGE, V (V)
SOURCE
CC
LTC1096/98 • TPC11
LTC1096/98 • TPC12
LTC1096/98 • TPC10
Minimum Wake-Up Time
vs Source Resistance
Input Channel Leakage Current
vs Temperature
Wake-Up Time vs Supply Voltage
4
10
7.5
5.0
2.5
0
1000
100
10
T
= 25°C
REF
T
= 25°C
REF
V
V
= 5V
A
A
REF
CC
V
= 2.5V
V
= 5V
= 5V
3
2
1
0
ON CHANNEL
1
0.1
+
OFF CHANNEL
R
SOURCE
V
+
–
IN
0.01
0
2
4
6
8
10
1
10
100
–60 –40 –20
0
20
60 80 100 120 140
40
R
(kΩ)
SUPPLY VOLTAGE, V (V)
CC
SOURCE
TEMPERATURE (°C)
LTC1096/98 • TPC13
LTC1096/98 • TPC14
LTC1096/98 • TPC15
Minimum Clock Frequency for
0.1LSB Error† vs Temperature
FFT Plot
ENOBs vs Frequency
0
200
180
160
140
120
10
9
T
= 25°C
V
V
= 5V
A
REF
= 5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= V
= 5V
CC
REF
= 31.25kHz
CC
f
f
8
SMPL
IN
= 5.8kHz
7
6
5
4
3
2
1
0
100
80
60
T
= 25°C
40
20
A
V
= V
= 5V
CC
REF
= 31.25kHz
f
SMPL
0
–60 –40 –20
0
20
60 80 100 120 140
40
1
10
FREQUENCY (kHz)
100
0
4
6
8
10 12
14
16
2
TEMPERATURE (°C)
FREQUENCY (kHz)
LTC1096/98 • TPC16
LTC1096/98 • TPC17
LTC1096/98 • TPC18
*Maximum CLK frequency represents the clock frequency at which a 0.1LSB shift in the error at any code
transition from its 0.75MHz value is first detected.
† As the CLK frequency is decreased from 500kHz, minimum CLK frequency (∆error ≤ 0.1LSB) represents
the frequency at which a 0.1LSB shift in any code transition from its 500kHz value is first detected.
9
LTC1096/LTC1096L
LTC1098/LTC1098L
U
U
U
PI FU CTIO S
LTC1096/LTC1096L
LTC1098/LTC1098L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
inputenablestheLTC1096/LTC1096L. Alogichighonthis
input disables the LTC1096/LTC1096L and disconnects
the power to the LTC1096/LTC1096L.
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
inputenablestheLTC1098/LTC1098L. Alogichighonthis
input disables the LTC1098/LTC1098L and disconnects
the power to the LTC1098/LTC1098L.
IN+ (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
CH0(Pin2): AnalogInput. Thisinputmustbefreeofnoise
with respect to GND.
IN– (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
CH1(Pin3): AnalogInput. Thisinputmustbefreeofnoise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
REF (Pin 5): Reference Input. The reference input defines
DIN (Pin 5): Digital Data Input. The multiplexer address is
the span of the A/D converter and must be kept free of
noise with respect to GND.
shifted into this pin.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer.
VCC (VREF)(Pin 8): Power Supply Voltage. This pin pro-
vides power and defines the span of the A/D converter. It
must be free of noise and ripple by bypassing directly to
the analog ground plane.
VCC (Pin 8): Power Supply Voltage. This pin provides
power to the A/D converter. It must be free of noise and
ripple by bypassing directly to the analog ground plane.
W
LTC1096/LTC1096L
BLOCK DIAGRA
V
(V /V
)
CS (D ) CLK
IN
CC CC REF
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
D
OUT
+
IN (CH0)
C
SAMPLE
–
+
SAR
–
IN (CH1)
MICROPOWER
COMPARATOR
CAPACITIVE DAC
GND
PIN NAMES IN PARENTHESES
REFER TO THE LTC1098/LTC1098L
V
REF
10
LTC1096/LTC1096L
LTC1098/LTC1098L
TEST CIRCUITS
On and Off Channel Leakage Current
Load Circuit for tdDO, tr and tf
5V
1.4V
I
ON
A
ON CHANNEL
3kΩ
I
OFF
A
D
OUT
TEST POINT
100pF
OFF
CHANNEL
•
•
•
•
LTC1096/98 • TC02
POLARITY
LTC1096/98 • TC1
Voltage Waveforms for DOUT Delay Time, tdDO
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
CLK
V
IL
V
OH
D
OUT
V
OL
t
dDO
V
V
OH
t
r
t
f
LTC1096/98 • TC04
D
OUT
OL
LTC1096/98 • TC03
Load Circuit for tdis and ten
Voltage Waveforms for tdis
TEST POINT
3k
2.0V
CS
5V t WAVEFORM 2, t
dis
en
D
D
OUT
OUT
WAVEFORM 1
(SEE NOTE 1)
90%
10%
t
dis
WAVEFORM 1
100pF
t
dis
LTC1096/98 • TC05
D
OUT
WAVEFORM 2
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1096/98 • TC06
11
LTC1096/LTC1096L
LTC1098/LTC1098L
TEST CIRCUITS
Voltage Waveforms for ten
LTC1096/LTC1096L
CS
t
WAKEUP
1
CLK
B7
D
OUT
CS
V
OL
t
LTC1098/LTC1098L
en
LTC1096/98 • TC07
START
D
IN
1
2
3
4
5
CLK
B7
D
OUT
V
OL
t
en
LTC1096/98 • TC08
O U
W
U
PPLICATI
A
S I FOR ATIO
OVERVIEW
a serial port (see Block Diagram). Although they share the
samebasicdesign,theLTC1096(L)andLTC1098(L)differ
in some respects. The LTC1096(L) has a differential input
and has an external reference input pin. It can measure
signals floating on a DC common mode voltage and can
operatewithreducedspansdownto250mV.Reducingthe
span allows it to achieve 1mV resolution. The LTC1098(L)
has a 2-channel input multiplexer and can convert either
channel with respect to ground or the difference between
the two.
The LTC1096/LTC1096L/LTC1098/LTC1098L are 8-bit
micropower, switched-capacitor A/D converters. These
sampling ADCs typically draw 120µA of supply current
when sampling up to 33kHz. Supply current drops linearly
as the sample rate is reduced (see Supply Current vs
SampleRateonthefirstpageofthisdatasheet). TheADCs
automatically power down when not performing conver-
sion, drawing only leakage current. They are packaged in
8-pin SO packages. The LTC1096L/LTC1098L operate on
a single supply ranging from 2.65V to 4V. The LTC1096
operates on a single supply ranging from 3V to 9V while
the LTC1098 operates from 3V to 6V supplies.
SERIAL INTERFACE
The LTC1098(L) communicates with microprocessors
andotherexternalcircuitryviaasynchronous,halfduplex,
4-wire serial interface while the LTC1096(L) uses a 3-wire
interface (see Operating Sequence in Figures 1 and 2).
The LTC1096/LTC1096L/LTC1098/LTC1098L comprise
an 8-bit, switched-capacitor ADC, a sample-and-hold and
12
LTC1096/LTC1096L
LTC1098/LTC1098L
O U
W
U
PPLICATI
S I FOR ATIO
A
t
WAKEUP
Power Down and Wake-Up Time
CS
TheLTC1096(L)/LTC1098(L)drawpowerwhentheCSpin
is low and shut themselves down when that pin is high. In
order to have a correct conversion result, a 10µs wake-up
time must be provided from CS falling to the first falling
clock (CLK) after the first rising CLK for the LTC1096(L)
and from CS falling to the MSBF bit CLK falling for the
LTC1098(L)(seeOperatingSequence).IftheLTC1096(L)/
LTC1098(L) are running with clock frequency less than or
equal to 100kHz, the wake-up time is inherently provided.
t
su
CLK
D
OUT
NULL BIT
B7
Case 1. Timing Diagram
t
WAKEUP
CS
t
su
10µs
CLK
Example
D
OUT
Two cases are shown at right to illustrate the relationship
among wake-up time, setup time and CLK frequency for
the LT1096(L).
LTC1096/98 • AI Ex.
Case 2. Timing Diagram
In Case 1 the clock frequency is 100kHz. One clock cycle
is 10µs which can be the wake-up time, while half of that
can be the setup time. In Case 2 the clock frequency is
50kHz, half of the clock cycle plus the setup time (=1µs)
can be the wake-up time. If the CLK frequency is higher
than 100kHz, Figure 1 shows the relationship between the
wake-up time and setup time.
Thewake-uptimeisinherentlyprovidedfortheLTC1098(L)
with setup time = 1µs (see Figure 2).
t
CYC
CS
POWER
DOWN
CLK
t
suCS
NULL
BIT
t
WAKEUP
Hi-Z
D
OUT
B5
B4 B3
B2 B1 B0
B7
(MSB)
B6
HI-Z
t
CONV
t
CYC
CS
POWER
DOWN
CLK
t
suCS
NULL
BIT
t
WAKEUP
Hi-Z
B0
B7
B5
B4 B3
B2 B1
B1
B2
B3
B5 B6 B7*
B6
B4
D
OUT
Hi-Z
(MSB)
LTC1096/98 F01
t
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Figure 1. LTC1096(L) Operating Sequence
13
LTC1096/LTC1096L
LTC1098/LTC1098L
O U
W
U
PPLICATI
S I FOR ATIO
A
MSB-FIRST DATA (MSBF = 1)
t
CYC
CS
POWER
DOWN
t
WAKEUP
CLK
t
suCS
ODD/
SIGN
START
D
D
DON'T CARE
IN
MSBF
SGL/
DIFF
NULL
HI-Z
Hi-Z
OUT
B5
t
B4 B3
B2 B1 B0*
BIT B7
B6
(MSB)
t
SMPL
CONV
MSB-FIRST DATA (MSBF = 0)
t
CYC
CS
POWER
DOWN
t
WAKEUP
CLK
t
suCS
ODD/
SIGN
START
D
D
DON'T CARE
B1 B2
IN
MSBF
SGL/
DIFF
NULL
HI-Z
Hi-Z
B6
B0
BIT B7
B5
t
B4 B3
B2 B1
B3
B5 B6 B7*
OUT
B4
(MSB)
t
LTC1096/98 F02
SMPL
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Figure 2. LTC1098(L) Operating Sequence Example: Differential Inputs (CH+, CH–)
Data Transfer
CS
D
1
D
2
IN
TheCLKsynchronizesthedatatransferwitheachbitbeing
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving sys-
tems. The LTC1098(L) first receives input data and then
transmits back the A/D conversion result (half duplex).
Becauseofthehalfduplexoperation, DIN andDOUT maybe
tied together allowing transmission over just three wires:
CS, CLK and DATA (DIN/DOUT).
IN
D
1
D
2
OUT
OUT
SHIFT MUX
ADDRESS IN
1 NULL BIT SHIFT A/D CONVERSION
RESULT OUT
LTC1096/98 • AI01
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the LTC1098(L) in
preparation for the next data exchange.
Datatransferisinitiatedbyafallingchipselect(CS)signal.
After CS falls the LTC1098(L) looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the LTC1098(L) and starts the
conversion. After one null bit, the result of the conversion
The LTC1096(L) does not require a configuration input
word and has no DIN pin. A falling CS initiatesdata transfer
as shown in the LTC1096(L) operating sequence. After CS
falls, the first CLK pulse enables DOUT. After one null bit,
14
LTC1096/LTC1096L
LTC1098/LTC1098L
O U
W
U
PPLICATI
A
S I FOR ATIO
the A/D conversion result is output on the DOUT line. MSB-First/LSB-First (MSBF)
Bringing CS high resets the LTC1096(L) for the next data
exchange.
The output data of the LTC1098(L) is programmed for
MSB-first or LSB-first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
Input Data Word
the D
line in MSB-first format. Logical zeros will be
OUT
The LTC1096(L) requires no DIN word. It is permanently
configured to have a single differential input. The conver-
sion result, in which output on the DOUT line is MSB-first
sequence, followedbyLSBsequenceprovidingeasyinter-
face to MSB- or LSB-first serial ports.
filled in indefinitely following the last data bit. When the
MSBF bit is a logical zero, LSB-first data will follow the
normal MSB-first data on the D
Sequence)
line. (see Operating
OUT
Unipolar Transfer Curve
TheLTC1098(L)clocksdataintotheDIN inputontherising
edge of the clock. The input data words are defined as The LTC1096(L)/LTC1098(L) are permanently config-
follows:
ured for unipolar only. The input span and code assign-
ment for this conversion type are shown in the follow-
ing figures for a 5V reference.
SGL/ ODD/
DIFF SIGN
START
MSBF
MUX MSB-FIRST/
Unipolar Transfer Curve
ADDRESS LSB-FIRST
LTC1096/8 • AI02
Start Bit
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1098(L) will ignore all leading zeros
which precede this logical one. After the start bit is
received, the remaining bits of the input word will be
clocked in. Further inputs on the DIN pin are then ignored
until the next CS cycle.
•
•
•
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V
IN
LTC1096/8 • AI04
Multiplexer (MUX) Address
Unipolar Output Code
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the followintg tables. In
single-ended mode, all input channels are measured with
respect to GND.
INPUT VOLTAGE
(V = 5.000V)
OUTPUT CODE
INPUT VOLTAGE
REF
4.9805V
1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
4.9609V
1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
•
0.0195V
0V
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1LSB
0V
LTC1096/8 • AI05
Operation with DIN and DOUT Tied Together
LTC1098(L) Channel Selection
The LTC1098(L) can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to
communicatetothemicroprocessor(MPU).Dataistrans-
mitted in both directions on a single wire. The processor
pin connected to this data line should be configurable as
either an input or an output. The LTC1098(L) will take
control of the data line and drive it low on the 4th falling
MUX ADDRESS
SGL/DIFF ODD/SIGN
CHANNEL #
0
1
GND
–
–
1
1
0
0
0
1
0
1
+
SINGLE-ENDED MUX MODE
DIFFERENTIAL MUX MODE
+
–
+
+
–
LTC1096/8 • AI03
15
LTC1096/LTC1096L
LTC1098/LTC1098L
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A
MSBF BIT LATCHED
BY LTC1098(L)
CS
1
2
3
4
CLK
DATA (D /D
)
START
SGL/DIFF
ODD/SIGN
MSBF
B7
B6
• • •
IN OUT
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1098(L)
LTC1098(L) CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1098(L) TAKES CONTROL OF
DATA LINE ON 4TH FALLING CLK
LTC1-96/8 • F03
Figure 3. LTC1098(L) Operation with DIN and DOUT Tied Together
CLK edge after the start bit is received (see Figure 3).
Therefore the processor port line must be switched to an
input before this happens, to avoid a conflict.
normal operating power continuously. Figure 5 shows
that the typical current varies from 40µA at clock rates
below 50kHz to 100µA at 500kHz. Several things must
be taken into account to achieve such a low power
consumption.
In the Typical Applications section, there is an example of
interfacing the LTC1098(L) with DIN and DOUT tied to-
gether to the Intel 8051 MPU.
140
T
= 25°C
CC
A
120
100
80
V
= 5V
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 40µA and automatic
shutdown between conversions, the LTC1096/LTC1098
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). In systems that
convert continuously, the LTC1096/LTC1098 will draw its
60
ACTIVE (CS LOW)
40
20
0.002
SHUTDOWN (CS HIGH)
1000
0
100
T
= 25°C
A
1k
10k
100k
1M
V
= V
= 5V
CC
REF
CLOCK FREQUENCY (Hz)
LTC1096/98 • F05
100
10
1
Figure 5. After a Conversion, When the Microprocessor
Drives CS High, the ADC Automatically Shuts Down Until the
Next Conversion. The Supply Current, Which Is Very Low
During cConversions, Drops to Zero in Shutdown
Shutdown
Figures 1 and 2 show the operating sequence of the
LTC1096/LTC1098. The converter draws power when the
CS pin is low and powers itself down when that pin is high.
If the CS pin is not taken to ground when it is low and not
taken to supply voltage when it is high, the input buffers of
0.1
1
SAMPLE FREQUENCY, f
10
100
(kHz)
SMPL
LTC1096/98 • TPC03
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
16
LTC1096/LTC1096L
LTC1098/LTC1098L
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the converter will draw current. This current may be larger
thanthetypicalsupplycurrent.Itisworthwhiletobringthe
CS pin all the way to ground when it is low and all the way
to supply voltage when it is high to obtain the lowest
supply current.
Wake-Up Time
A 10µs wake-up time must be provided for the ADCs to
convert correctly on a 5V supply. The wake-up time is
typically less than 3µs over the supply voltage range (see
typical curve of Wake-Up Time vs Supply Voltage). With
10µs wake-up time provided over the supply range, the
ADCswillhaveadequatetimetowakeupandacquireinput
signals.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK input have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high, except the MPU may benefit.
Input Logic Levels
The input logic levels of CS, CLK and DIN are made to meet
TTL on 5V supply. When the supply voltage varies, the
input logic levels also change. For the LTC1096/LTC1098
to sample and convert correctly, the digital inputs have to
meet logic low and high levels relative to the operating
supply voltage (see typical curve of Digital Input Logic
Threshold vs Supply Voltage). If achieving micropower
consumption is desirable, the digital inputs must go rail-
to-rail between supply voltage and ground (see ACHIEV-
ING MICROPOWER PERFORMANCE section).
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, waiting 10µs for the wake-up
time, transferring data as quickly as possible, and then
bringing it back high will result in the lowest current drain.
This minimizes the amount of time the device draws
power. Even though the device draws more power at high
clock rates, the net power is less because the device is on
for a shorter time.
Clock Frequency
DOUT Loading
The maximum recommended clock frequency is 500kHz
for the LTC1096/LTC1098 running off a 5V supply. With
the supply voltage changing, the maximum clock fre-
quency for the devices also changes (see the typical curve
of Maximum Clock Rate vs Supply Voltage). If the maxi-
mum clock frequency is used, care must be taken to
ensure that the device converts correctly.
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can more than double the 100µA supply current drain at a
500kHz clock frequency. An extra 100µA or so of current
goesintocharginganddischargingtheloadcapacitor.The
same goes for digital lines driven at a high frequency by
any logic. The CxVxf currents must be evaluated and the
troublesome ones minimized.
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1096/LTC1098
operating on 3V or 9V supplies. The requirement to
achievethisisthattheoutputsofCS, CLKandDIN fromthe
MPU have to be able to trip the equivalent inputs of the
ADCs and the output of DOUT from the ADCs must be able
totoggletheequivalentinputoftheMPU(seetypicalcurve
of Digital Input Logic Threshold vs Supply Voltage). With
the LTC1096 operating on a 9V supply, the output of DOUT
may go between 0V and 9V. The 9V output may damage
the MPU running off a 5V supply. The way to get around
this possibility is to have a resistor divider on DOUT
Lower Supply Voltage
For lower supply voltages, LTC offers the LTC1096L/
LTC1098L. These pin compatible devices offer specified
performance to 2.65VMIN supply.
OPERATING ON OTHER THAN 5V SUPPLIES
The LTC1096 operates from 3V to 9V supplies and the
LTC1098 operates from 3V to 6V supplies. To operate the
LTC1096/LTC1098onotherthan5Vsupplies,afewthings
must be kept in mind.
17
LTC1096/LTC1096L
LTC1098/LTC1098L
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A
(Figure 6) and connect the center point to the MPU input.
It should be noted that to get full shutdown, the CS input
of the LTC1096/LTC1098 must be driven to the VCC
voltage. This would require adding a level shift circuit to
The VCC pin should be bypassed to the ground plane with
a 1µF tantalum with leads as short as possible. If power
supply is clean, the LTC1096(L)/LTC1098(L) can also
operate with smaller 0.1µF surface mount or ceramic
bypass capacitors. All analog inputs should be referenced
directly to the single point ground. Digital inputs and
outputs should be shielded from and/or routed away from
the reference and analog circuitry.
the CS signal in Figure 6.
9V
OPTIONAL
LEVEL SHIFT
4.7µF
9V
SAMPLE-AND-HOLD
MPU
(e.g. 8051)
5V
Both the LTC1096(L) and the LTC1098(L) provide a built-
in sample-and-hold (S&H) function to acquire signals.
The S&H of the LTC1096(L) acquires input signals from
“+” input relative to “–” input during the tWAKEUP time (see
Figure 1). However, the S&H of the LTC1098(L) can
sample input signals in the single-ended mode or in the
differential inputs during the tSMPL time (see Figure 7).
CS
V
P1.4
CC
DIFFERENTIAL INPUTS
+IN
–IN
GND
CLK
P1.3
P1.2
50k
6V
COMMON MODE RANGE
0V TO 6V
D
OUT
V
REF
50k
LTC1096
LTC1096/98 • F06
Figure 6. Interfacing a 9V Powered LTC1096 to a 5V System
Single-Ended Inputs
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The sample-and-hold of the LTC1098(L) allows conver-
sionofrapidlyvaryingsignals.Theinputvoltageissampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
The LTC1096(L)/LTC1098(L) should be used with an ana-
log ground plane and single point grounding techniques.
The GND pin should be tied directly to the ground plane.
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
CS
t
t
CONV
SMPL
CLK
D
START
SGL/DIFF
MSBF
DON'T CARE
IN
D
OUT
B7
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
"+" INPUT
"–" INPUT
LTC1096/8 • F07
Figure 7. LTC1098(L) “+” and “–” Input Settling Windows
18
LTC1096/LTC1096L
LTC1098/LTC1098L
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in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
S I FOR ATIO
A
tWAKEUP or tSMPL for the LTC1096(L) or the LTC1098(L)
+
respectively. Minimizing RSOURCE and C1 will improve
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
using a slower CLK frequency.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
ageontheselected“–”inputmustremainconstantand be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 8 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
“–” Input Settling
At the end of the tWAKEUP or tSMPL, the input capacitor
switches to the “–” input and conversion starts (see
Figures 1 and 7). During the conversion the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. However, it is critical
that the “–” input voltage settles completely during the
first CLK cycle of the conversion time and be free of noise.
Minimizing RSOURCE– and C2 will improve settling time. If
a large “–” input source resistance must be used, the time
allowedforsettlingcanbeextendedbyusingaslowerCLK
frequency.
V
ERROR (MAX) = VPEAK • 2 • π • f(“–”) • 8/fCLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
CLK. In most cases VERROR will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
(5mV) with the converter running at CLK = 500kHz, its
peak value would have to be 750mV.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(seeFigure7). Again, the“+”and“–”inputsamplingtimes
can be extended as described above to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 3µs (“+”
input) which occur at the maximum clock rate of 500kHz.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1096(L)/
LTC1098(L)havecapacitiveswitchinginputcurrentspikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to ensure that the transients caused by the current
spikes settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1096/LTC1098 look like a
25pF capacitor (CIN) in series with a 500Ω resistor (RON)
as shown in Figure 8. CIN gets switched between the
selected “+” and “–” inputs once during each conversion
“+”
“+” Input Settling
+
INPUT
R
SOURCE
LTC1096
LTC1098
V
+
–
IN
The input capacitor of the LTC1096(L) is switched onto
“+” input during the wake-up time (see Figure 1) and
samples the input signal within that time. However, the
input capacitor of the LTC1098(L) is switched onto “+”
input during the sample phase (tSMPL, see Figure 7). The
sample phase is 1.5 CLK cycles before conversion starts.
The voltage on the “+” input must settle completely within
C1
R
ON
= 500Ω
“–”
INPUT
C
IN
= 25pF
–
R
SOURCE
V
IN
C2
LTC1096/8 • F8
Figure 8. Analog Input Equivalent Circuit
19
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A
cycle. Large external source resistors and capacitances
will slow the settling of the inputs. It is important that the
overall RC time constants be short enough to allow the
analog inputs to completely settle within the allowed time.
tive current spike will be generated on the reference pin by
the ADC. These current spikes settle quickly and do not
cause a problem.
Using a slower CLK will allow more time for the reference
to settle. Even at the maximum CLK rate of 500kHz most
references and op amps can be made to settle within the
2µs bit time.
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 9. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 25pF(VIN/tCYC) and is roughly pro-
portional to VIN. When running at the minimum cycle time
of 29µs, the input current equals 4.3µA at VIN = 5V. In this
case, a filter resistor of 390Ω will cause 0.1LSB of full-
scale error. If a larger filter resistor must be used, errors
can be eliminated by increasing the cycle time.
+
REF
LTC1096
5
EVERY CLK CYCLE
R
OUT
R
ON
V
5pF TO 30pF
REF
GND
4
LTC1096/8 • F10
Figure 10. Reference Input Equivalent Circuit
Reduced Reference Operation
The minimum reference voltage of the LTC1098 is limited
to 3V because the VCC supply and reference are internally
tied together. However, the LTC1096 can operate with
reference voltages below 1V.
I
DC
R
FILTER
“+”
LTC1098
“–”
V
IN
C
FILTER
The effective resolution of the LTC1096 can be increased
by reducing the input span of the converter. The LTC1096
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Linearity and Full
Scale Error vs Reference Voltage). However, care must be
taken when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. The following fac-
tors must be considered when operating at low VREF
values.
LTC1096/8 • F9
Figure 9. RC Input Filtering
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 1µA (at 125°C) flowing
through a source resistance of 3.9k will cause a voltage
drop of 3.9mV or 0.2LSB. This error will be much reduced
at lower temperatures because leakage drops rapidly (see
typical curve of Input Channel Leakage Current vs Tem-
perature).
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced VREF
REFERENCE INPUTS
The offset of the LTC1096 has a larger effect on the output
code when the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Unadjusted Offset Error vs
Reference Voltage shows how offset in LSBs is related to
The voltage on the reference input of the LTC1096 defines
the voltage span of the A/D converter. The reference input
transientcapacitiveswitchingcurrentsduetotheswitched-
capacitor conversion technique (see Figure 10). During
each bit test of the conversion (every CLK cycle), a capaci-
20
LTC1096/LTC1096L
LTC1098/LTC1098L
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reference voltage for a typical value of VOS. For example,
aVOS of2mVwhichis0.1LSBwitha5Vreferencebecomes
0.5LSB with a 1V reference and 2.5LSBs with a 0.2V
reference. If this offset is unacceptable, it can be corrected
digitally by the receiving system or by offsetting the “–”
input of the LTC1096.
settle within the bit time at which the clock is running.
Whenusingalargervalueresistordivideronthereference
input the “–” input should be matched with an equivalent
resistance.
Bypassing Reference Input with Divider
Bypassing the reference input with a divider is also pos-
sible. However, care must be taken to make sure that the
DC voltage on the reference input will not drop too much
below the intended reference voltage.
Noise with Reduced VREF
The total input referred noise of the LTC1096 can be
reducedtoapproximately1mVpeak-to-peakusingaground
plane, good bypassing, good layout techniques and mini-
mizing noise on the reference inputs. This noise is insig-
nificant with a 5V reference but will become a larger
fraction of an LSB as the size of the LSB is reduced.
AC PERFORMANCE
Two commonly used figures of merit for specifying the
dynamic performance of the ADCs in digital signal pro-
cessing applications are the signal-to-noise ratio (SNR)
and the effective number of bits (ENOBs).
For operation with a 5V reference, the 1mV noise is only
0.05LSB peak-to-peak. In this case, the LTC1096 noise
will contribute virtually no uncertainty to the output
code. However, for reduced references, the noise may
become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with a
1V reference, this same 1mV noise is 0.25LSB peak-to-
peak. This will reduce the range of input voltages over
which a stable output code can be achieved by 1LSB. If
the reference is further reduced to 200mV, the 1mV
noise becomes equal to 1.25LSBs and a stable code may
be difficult to achieve. In this case averaging readings
may be necessary.
Signal-to-Noise Ratio
T
he signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other frequency components at
the A/D output. This includes distortion as well as noise
products and for this reason it is sometimes referred to
as signal-to-noise + distortion [S/(N + D)]. The output is
band limited to frequencies from DC to one half the
sampling frequency. Figure 11 shows spectral content
from DC to 15.625kHz which is 1/2 the 31.25kHz sam-
pling rate.
This noise data was taken in a very clean setup. Any setup-
induced noise (noise or ripple on VCC, VREF or VIN) will add
to the internal noise. The lower the reference voltage to be
used,themorecriticalitbecomestohaveaclean,noisefree
setup.
0
–10
–20
f
f
= 31.25kHz
SAMPLE
IN
= 11.8kHz
–30
–40
–50
Conversion Speed with Reduced VREF
–60
–70
With reduced reference voltages the LSB step size is
reduced and the LTC1096 internal comparator over-
drive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values
–80
–90
–100
–110
–120
8
10
0
2
4
6
12 14 16
of V
are used.
REF
FREQUENCY (kHz)
LTC1096/8 • F11
Input Divider
Figure 11. This Clean FFT of an 11.8kHz Input Shows
Remarkable Performance for an ADC That Draws Only 100µA
When Sampling at the 31.25kHz Rate
It is OK to use an input divider on the reference input of the
LTC1096 as long as the reference input can be made to
21
LTC1096/LTC1096L
LTC1098/LTC1098L
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A
8
7
6
5
Effective Number of Bits
f
= 31.25kHz
SAMPLE
The effective number of bits (ENOBs) is a measurement of
the resolution of an A/D and is directly related to the
S/(N + D) by the equation:
4
3
ENOB = [S/(N + D) –1.76]/6.02
2
1
0
where S/(N + D) is expressed in dB. At the maximum
samplingrateof33kHztheLTC1096 maintains7.5 ENOBs
or better to 40kHz. Above 40kHz the ENOBs gradually
decline, as shown in Figure 12, due to increasing second
harmonic distortion. The noise floor remains approxi-
mately 70dB.
0
20
40
INPUT FREQUENCY (kHz)
LTC1096/8 • F12
Figure 12. Dynamic Accuracy Is Maintained Up to an Input
Frequency of 40kHz
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O
TYPICAL APPLICATI S
MICROPROCESSOR INTERFACES
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1096(L)/LTC1098(L)
The LTC1096(L)/LTC1098(L) can interface directly (with-
out external hardware to most popular microprocessor
(MPU) synchronous serial formats (see Table 1). If an
MPU without a dedicated serial port is used, then three or
four of the MPU’s parallel port lines can be programmed
to form the serial link to the LTC1096(L)/LTC1098(L).
Included here is one serial interface example and one
example showing a parallel port programmed to form the
serial interface.
PART NUMBER
Motorola
TYPE OF INTERFACE
MC6805S2,S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
Hitachi
SPI
HD6305
HD63705
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O
Motorola SPI (MC68HC05C4,CM68HC11)
The MC68HC05C4 has been chosen as an example of
an MPU with a dedicated serial port. This MPU transfer
data MSB-first and in 8-bit increments. With two 8-bit
transfers, the A/D result is read into the MPU. The first
National Semiconductor
COP400 Family
COP800 Family
NS8050U
MICROWIRETM
MICROWIRE/PLUSTM
MICROWIRE/PLUS
MICROWIR/PLUS
8-bit transfer sends the D word to the LTC1098(L)
IN
HPC16000 Family
and clocks into the processor. The second 8-bit trans-
fer clocks the A/D conversion result, B7 through B0,
into the MPU.
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
ANDing the first MUP received byte with 00Hex clears the
first byte. Notice how the position of the start bit in the first
MPU transmit word is used to position the A/D result
right-justified in two memory locations.
*
Requires external hardware
MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
22
LTC1096/LTC1096L
LTC1098/LTC1098L
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TYPICAL APPLICATI S
Data Exchange Between LTC1098(L) and MC68HC05C4
START
BIT
BYTE 1
MSBF
BYTE 2 (DUMMY)
MPU TRANSMIT
WORD
SGL/ ODD/
DIFF SIGN
0
0
0
1
X
X
X
X
X
X
X
X
X
X = DON'T CARE
CS
START
SGL/
DIFF
ODD/
SIGN
D
IN
DON'T CARE
MSBF
CLK
D
B7
B7
B6
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
OUT
MPU RECEIVED
WORD
?
?
?
?
?
?
?
0
1ST TRANSFER
2ND TRANSFER
LTC1096/8 • TA03
Hardware and Software Interface to Motorola MC68HC05C4
LABEL
MNEMONIC
COMMENTS
Bit 0 Port C goes low (CS goes low)
Load LTC1098(L) D word into Acc.
START
BCLRn
LDA
STA
C0
IN
CS
Load LTC1098(L) D word into SPI from Acc.
IN
SCK
MC68HC05C4
MISO
CLK
Transfer begins.
ANALOG
INPUTS
LTC1098
TST
BPL
Test status of SPIF
Loop to previous instruction if not done
with transfer
D
IN
D
MOSI
OUT
LDA
Load contents of SPI data register
into Acc. (D
Start next SPI cycle
Clear the first D
Store in memory location A (MSBs)
Test status of SPIF
Loop to previous instruction if not done
with transfer
Set B0 of Port C (CS goes high)
Load contents of SPI data register into
MSBs)
LTC1096/8 • TA04
OUT
STA
AND
STA
TST
BPL
word
OUT
DOUT from LTC1098(L) Stored in MC68HC05C4
LOCATION A
0
0
0
0
0
0
0
0
BYTE 1
BYTE 2
BSETn
LDA
LSB
B0
Acc. (D
LSBs)
OUT
LOCATION A + 1
B7
B6
B5
B4
B3
B2
B1
STA
Store in memory location A + 1 (LSBs)
LTC1096/8 • TA05
23
LTC1096/LTC1096L
LTC1098/LTC1098L
U
O
TYPICAL APPLICATI S
Interfacing to the Parallel Port of the
Intel 8051 Family
LABEL
MNEMONIC
OPERAND
COMMENTS
word for LTC1098(L)
Make sure CS is high
CS goes low
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
SETB
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
D
IN
The Intel 8051 has been chosen to demonstrate the
interfacebetweentheLTC1098(L)andparallelportmicro-
processors. Normally the CS, CLK and DIN signals would
be generated on three port lines and the DOUT signal read
on a fourth port line. This works very well. However, we
will demonstrate here an interface with the DIN and DOUT
of the LTC1098(L) tied together as described in the
SERIAL INTERFACE section. This saves one wire.
Load counter
LOOP 1
Rotate D bit into Carry
IN
CLK goes low
Output D bit to LTC1098(L)
IN
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into Acc.
CLK goes high
CLK goes low
Next bit
Store MSBs in R2
CS goes high
LOOP
The 8051 first sends the start bit and MUX address to the
LTC1098(L) over the data line connected to P1.2. Then
P1.2 is reconfigured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
P1.3
P1.3
R4, LOOP
R2, A
P1.4
DOUT from LTC1098(L) Stored in 8051 RAM
CS
CLK
P1.4
P1.3
P1.2
ANALOG
INPUTS
LTC1098(L)
8051
MSB
LSB
B0
D
OUT
D
MUX ADDRESS
A/D RESULT
IN
R2 B7
B6
B5
B4
B3
B2
B1
LTC1096/8 • TA07
LTC1096/8 • TA06
MSBF BIT LATCHED
BY LTC1098(L)
CS
CLK
)
1
2
3
4
SGL/
DIFF
ODD/
SIGN
DATA (D /D
B7
B6
B5
B4
B3
B2
B1
B0
START
MSBF
IN OUT
8051 P1.2 OUTPUTS DATA
TO LTC1098(L)
LTC1096/8 • TA08
LTC1098(L) SENDS A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND BEFORE THE 4TH FALLING CLK
LTC1098(L) TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
24
LTC1096/LTC1096L
LTC1098/LTC1098L
U
O
TYPICAL APPLICATI S
A “Quick Look” Circuit for the LTC1096
CS
Users can get a quick look at the function and timing of the
LT1096 by using the following simple circuit (Figure 13).
V
REF is tied to VCC. VIN is applied to the +IN input and the
CLK
–IN input is tied to the ground. CS is driven at 1/16 the
clock rate by the 74C161 and DOUT outputs the data. The
output data from the DOUT pin can be viewed on an
oscilloscope that is set up to trigger on the falling edge of
CS (Figure 14). Note the LSB data is partially clocked out
before CS goes high.
DOUT
LSB LSB DATA
(B0) (B1)
MSB
(B7)
NULL
BIT
VERTICAL: 5V/DIV
HORIZONTAL: 10µs/DIV
5V
4.7µF
+
Figure 14. Scope Trace the LTC1096 “Quick Look” Circuit
CLR
CLK
A
V
5V
CC
RC
Showing A/D Output 10101010 (AAHEX
)
CS
V
CC
QA
QB
QC
QD
T
V
CH0
CH1
GND
CLK
B
C
IN
74C161
LTC1096
D
D
P
GND
OUT
3V
V
REF
LOAD
0.1µF
LM134
75k
CLOCK IN 150kHz MAX
TO OSCILLOSCOPE
678Ω
V
CC
LTC1096/8 • F13
+IN
CS
13.5k
TO µP
–IN LTC1096 CLK
Figure 13. “Quick Look” Circuit for the LTC1096
182k
V
REF
D
OUT
GND
LT1004-1.2
Figure 15 shows a temperature measurement system.
The LTC1096 is connected directly to the low cost silicon
temperature sensor. The voltage applied to the VREF pin
adjusts the full scale of the A/D to the output range of the
sensor. The zero point of the converter is matched to the
zero output voltage of the sensor by the voltage on the
LTC1096’s negative input.
0.01µF
0.01µF
63.4k
LTC1096/8 • F15
Figure 15. The LTC1096’s High Impedance Input Connects
Directly to This Temperature Sensor, Eliminating Signal
Conditioning Circuitry in This 0°C to 70°C Thermometer
25
LTC1096/LTC1096L
LTC1098/LTC1098L
U
O
TYPICAL APPLICATI S
conversions and the optoisolators draw power only when
data is being transferred. The system consumes only
50µAatasamplerateof10Hz(1mson-timeand99msoff-
time). This is easily within the current supplied by the
charge pump running at 5MHz. If a truly isolated system
is required, the system’s low power simplifies generating
an isolated supply or powering the system from a battery.
Remote or Isolated Systems
Figure 16 shows a floating system that sends data to a
grounded host system. The floating circuitry is isolated by
two optoisolators and powered by a simple capacitor
diode charge pump. The system has very low power
requirements because the LTC1096 shuts down between
FLOATING SYSTEM
1N5817
+
0.001µF
0.1µF
47µF
2kV
2N3904
75k
1N5817
V
V
CC
REF
0.022µF
100k
20k
LT1004-2.5
CS
5MHz
300Ω
LTC1096
+IN
–IN
ANALOG
INPUT
1N5817
CLK
D
OUT
100k
GND
CLK
1k
10k
500k
DATA
LTC1096/8 • F16
Figure 16. Power for This Floating A/D System Is Provided by a Simple Capacitor Diode Charge Pump. The Two Optoisolators
Draw No Current Between Samples, Turning On Only to Send the Clock and Receive Data
26
LTC1096/LTC1096L
LTC1098/LTC1098L
U
Dimensions in inches (millimeters), unless otherwise noted.
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
*THESE DIMENSIONS DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL
NOT EXCEED 0.010 INCH (0.254mm)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.015
+0.025
–0.015
(0.380)
MIN
0.325
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
N8 0695
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0695
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1096/LTC1096L
LTC1098/LTC1098L
U
O
TYPICAL APPLICATI
A/D Conversion for 3V Systems
LT1004 provides the full-scale reference for the ADC. The
other half of the LTC1178 is used to provide low battery
detection. The circuit’s 70µA supply current is dominated
by the op amps and the reference. The circuit can be
located near the battery and data transmitted serially to
the microprocessor.
TheLTC1096/LTC1098areidealfor3Vsystems. Figure17
shows a 3V to 6V battery current monitor that draws only
70µA from the battery it monitors. The battery current is
sensed with the 0.02Ω resistor and amplified by the
LT1178. The LTC1096 digitizes the amplifier output and
sends it to the microprocessor in serial format. The
0.1µF
0.1µF
3V TO 6V
73.2k
470k
750k
24.9k
+
CS
+
V
CC
CLK
L
O
A
D
1/2 LT1178
0.02Ω FOR 2A FULL SCALE
0.2Ω FOR 0.2A FULL SCALE
LTC1096
D
–
OUT
–
TO µP
GND
V
REF
20M
+
LO BATTERY
1/2 LT1178
470k
LT1004-1.2
–
LTC1096/8 • F17
Figure 17. This 0A to 2A Battery Current Monitor Draws Only 70µA from a 3V Battery
RELATED PARTS
PART NUMBER
LTC1196/LTC1198
LTC1286/LTC1298
LTC1285/LTC1298
LTC1400
DESCRIPTION
COMMENTS
8-Pin SO, 1Msps, 8-Bit ADCs
Low Power, Small Size, Low Cost
1- or 2-Channel, Auto Shutdown
1- or 2-Channel, Auto Shutdown
8-Pin SO, 5V Micropower, 12-Bit ADCs
8-Pin SO, 3V Micropower, 12-Bit ADCs
5V High Speed,Serial 12-Bit ADC
400ksps, Complete with V , CLK, Sample-and-Hold
REF
LTC1594/LTC1598
4- and 8-Channel, 5V Micropower, 12-Bit ADCs
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
LTC1594L/LTC1598L 4- and 8-Channel, 3V Micropower, 12-Bit ADCs
10968fb LT/TP 0397 5K REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1994
Linear Technology Corporation
●
1630McCarthyBlvd.,Milpitas, CA95035-7417 (408)432-1900
28
●
●
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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