LTC1099CSW#PBF [Linear]
LTC1099 - High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C;
| 型号： | LTC1099CSW#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1099 - High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1099
High Speed 8-Bit A/D
Converter with Built-In
Sample-and-Hold
U
FEATURES
DESCRIPTIO
TheLTC®1099isahighspeedmicroprocessorcompatible
8-bitanalog-to-digitalconverter(A/D).Aninternalsample-
and-hold (S/H) allows the A/D to convert inputs up to the
full Nyquist limit. With a conversion rate of 2.5µs, this
allows 156kHz 5VP-P input signals or slew rates as high as
2.5V/µs, to be digitized without the need for an external
S/H.
■
Built-In Sample-and-Hold
■
No Missing Codes
■
No User Trims Required
■
All Timing Inputs Edge Sensitive for Easy Processor
Interface
■
Fast Conversion Time: 2.5µs
■
Latched Three-State Outputs
■
Single 5V Operation
No External Clock
Twomodesofoperation,Read(RD)modeandWrite-Read
(WR-RD) mode, allow easy interface with processors. All
timing is internal and edge sensitive which eliminates the
need for external pulse shaping circuits. The Stand-Alone
(SA) mode is convenient for those applications not involv-
ing a processor.
■
■
Overflow Output Allows Cascading
■
TC Input Allows User Adjustable Conversion Time
■
0.3" Wide 20-Pin PDIP
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KEY SPECIFICATIO S
Data outputs are latched with three-state control to allow
easy interface to a processor data bus or I/O port. An
overflow output (OFL) is provided to allow cascading for
higher resolution.
■
Resolution: 8-Bits
Conversion Time: 2.5µs (RD Mode)
■
2.5µs (WR/RD Mode)
■
Slew Rate Limit (Internal S/H): 2.5V/µs
■
Low Power: 75mW Max
■
Total Unadjusted Error
LTC1099: ±1 LSB
LTC1099A: ±0.75 LSB
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Infinite Hold Time Sample-and-Hold (TACQ = 240ns)
Signal-to-Noise Ratio (SNR) vs Input Frequency
5V
15V
–36
10k
T
T
= 25°C
= 2.5µs
A
C
–38
–40
–42
–44
–46
–48
–50
–52
12
+
20
V
CC
14
+
20
+
REF
2.5k
LTC1099
REF
V
7
1
6
1
17
16
15
14
5
4
3
2
MODE
DB7
DB6
DB5
DB4
B1
2
3
4
5
6
7
8
B2
B3
B4
B5
B6
B7
B8
2
3
18
19
7
V
IN
V
+
IN
I
O
6
SAMPLE
HOLD
V
OUT
AM6012
LT1022
4
WR/RDY DB3
DB2
I
O
–
8
RD
DB1
DB0
13
CS
–
–
REF
V
–
GND
REF
15
17
1
10
INPUT FREQUENCY (kHz)
100
10k
10
11
1099 G08
1099 TA01
–15V
1
LTC1099
W W
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ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Supply Voltage (VCC) to GND Voltage ...................... 12V
Analog and Reference Inputs... –0.3V to (VCC + 0.3V)
Digital Inputs .........................................–0.3V to 12V
Digital Outputs ........................ –0.3V to (VCC + 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1099C/LTC1099AC............................ 0°C to 70°C
LTC1099I/LTC1099AI ..........................–40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
V
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
IN
1
2
V
T
20
19
18
17
16
15
14
13
12
11
V
CC
NUMBER
IN
DB0
DB1
TC
DB0
DB1
C
OFL
DB7
DB6
DB5
DB4
CS
3
OFL
LTC1099CN
LTC1099ACN
LTC1099AIN
LTC1099CSW
DB2
4
DB7
DB6
DB5
DB4
CS
DB2
DB3
5
DB3
WR/RDY
MODE
RD
6
WR/RDY
MODE
RD
7
8
+
+
INT
REF
REF
9
REF
REF
INT
–
–
GND 10
10
GND
SW PACKAGE
20-LEAD PLASTIC SO
N PACKAGE
20-LEAD PDIP
TJMAX = 150°C, θJA = 130°C/W
TJMAX = 150°C, θJA = 100°C/W
Consult factory for parts specified with wider operating temperature ranges.
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CONVERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise
noted.
LTC1099AI/LTC1099I
LTC1099AC/LTC1099C
PARAMETER
Accuracy
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Total Unadjusted Error
LTC1099A
(Note 3)
●
●
±0.75
±1
±0.75
±1
LSB
LSB
LTC1099
Minimum Resolution (No Missing Codes)
Reference Input
●
8
8
Bits
Input Resistance
●
●
●
1
3.2
60
6
2
3.2
60
4.5
kΩ
V
+
–
–
REF Input Voltage Range
(Note 4)
(Note 4)
REF
V
REF
V
CC
CC
–
+
+
REF Input Voltage Range
GND
GND
REF
GND
GND
REF
V
Analog Input
Input Voltage Range
Input Leakage Current
Input Capacitance
Sample-and-Hold
Acquisition Time
Aperture Time
●
●
V
V
V
µA
pF
CC
CC
CS = V , V = V , GND
±3
±3
CC IN
CC
240
110
2.5
240
110
2.5
ns
ns
Tracking Rate
V/µs
2
LTC1099
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DIGITAL ANDDCELECTRICALCHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise noted.
LTC1099AI/LTC1099I
LTC1099AC/LTC1099C
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage All Digital Inputs, V = 5.25V
●
●
2.0
2.0
V
V
IH
IL
CC
Low Level Input Voltage
High Level Input Current
All Digital Inputs, V = 4.75V
0.8
0.0001
0.8
CC
I
V
V
= 5V; CS, RD, Mode
= 5V; WR
●
●
0.0001
0.0005
1
3
1
3
µA
µA
IH
IH
IH
0.0005
I
Low Level Input Current
V
= 0V; All Digital Inputs
●
–0.0001
–1
–0.0001
–1
µA
IL
IL
V
High Level Output Voltage DB0-DB7, OFL, INT; V = 4.75V
CC
OH
I
I
= 360µA
=10µA
●
2.4
4.0
4.7
2.4
4.0
4.7
V
V
OUT
OUT
V
Low Level Output Voltage DB0-DB7, OFL, INT, RDY; V = 4.75V
OL
CC
I
=1.6mA
●
0.4
0.4
V
OUT
I
Hi-Z Output Leakage
DB0-DB7, RDY; V
DB0-DB7, RDY; V
= 5V
= 0V
●
●
0.1
–0.1
3
–3
0.1
–0.1
3
–3
µA
µA
OZ
OUT
OUT
I
I
I
Output Source Current
Output Sink Current
Supply Current
DB0-DB7, OFL, INT; V
= 0V
OUT
●
●
●
–11
14
–6
7
–11
14
–7
9
mA
mA
mA
SOURCE
SINK
CC
DB0-DB7, OFL, INT, RDY; V
= 5V
OUT
CS = WR = RD = V
11
20
11
15
CC
The ● denotes the specifications which apply over the full operating temperature range,
AC CHARACTERISTICS
otherwise specifications are at TA = 25°C. VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise noted.
LTC1099AI/LTC1099I LTC1099AC/LTC1099C
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RD Mode (Figure 2) Pin 7 = GND
t
Conversion Time
T = 25°C
2.2
2.5
70
2.8
5.0
2.2
2.5
70
2.8
3.75
µs
µs
CRD
A
●
t
t
t
t
t
t
Delay From CS↓ to RDY↓
C = 100pF
L
ns
ns
ns
ns
ns
ns
RDY
Delay From RD↓ to Output Data Valid
Delay From RD↑ to INT↑
C = 100pF
L
t
+ 35
t
+ 35
CRD
ACC0
INTH
CRD
C = 100pF
L
70
70
70
70
, t
1H 0H
Delay From RD↑ to Hi-Z State on Outputs
Delay Time Between Conversions
Delay Time From RD↓ to Output Data Valid
Test Circuit Figure 1
700
70
700
70
P
ACC2
WR/RD Mode (Figures 3 and 4) Pin 7 = V
CC
t
Conversion Time
T = 25°C
A
2.2
2.5
2.8
5.0
2.2
2.5
2.8
3.75
µs
µs
CWR
●
t
t
t
t
t
t
t
Delay Time From WR↓ to Output Data Valid C = 100pF
t
+ 40
t + 40
CWR
ns
ns
ns
ns
ns
ns
ns
ACC0
ACC2
INTH
IHWR
L
CWR
Delay From RD↓ to Output Data Valid
Delay From RD↑ to INT↑
C = 100pF
70
70
70
70
L
C = 100pF
L
Delay From WR↓ to INT↑
C = 100pF
L
240
70
240
70
, t
1H 0H
Delay From RD↑ to Hi-Z State on Outputs
Delay Time Between Conversions
Minimum WR Pulse Width
Test Circuit Figure 1
700
55
700
55
P
WR
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: Total unadjusted error includes offset, gain, linearity and hold step
errors.
Note 2: All voltages are with respect to GND (Pin 10) unless otherwise
noted.
Note 4: Reference input voltage range is guaranteed but is not tested.
3
LTC1099
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TYPICAL PERFOR A CE CHARACTERISTICS
Linearity Error vs Reference
Voltage
Supply Current vs Temperature
VOS Error vs Reference Voltage
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
18
16
14
12
10
8
4
3
2
1
0
T
T
= 25°C
= 2.5µs
T
A
T
C
= 25°C
= 2.5µs
A
C
6
4
2
0
0
1
2
3
4
5
25
AMBIENT TEMPERATURE, T (°C)
–50 –25
0
50
75 100 125
0
4
5
1
2
3
REFERENCE VOLTAGE, V
(V)
REFERENCE VOLTAGE, V
(V)
REF
A
REF
1099 G03
1099 G01
1099 G02
Total Error vs Reference Voltage
Accuracy vs Conversion Time
Conversion Time vs REXT
4
3
2
1
0
100
10
1.0
0.8
T
= 25°C
T
T
= 25°C
= 2.5µs
A
A
C
T = 25°C
A
RESISTOR BETWEEN
PIN 19 AND V
CC
0.6
0.4
0.2
0
RESISTOR BETWEEN
PIN 19 AND GND
1.0
0.1
0
4
5
1
2
3
10
100
1000
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5
REFERENCE VOLTAGE, V
(V)
RESISTANCE (kΩ)
CONVERSION TIME (µs)
REF
1099 G05
1099 G06
1099 G04
Signal-to-Noise Ratio (SNR) vs
Input Frequency
Conversion Time vs Temperature
1.8
1.6
1.4
1.2
1.0
0.8
0.6
4.5
4.0
3.5
3.0
2.5
2.0
1.5
–36
T
T
= 25°C
= 2.5µs
A
C
–38
–40
–42
–44
–46
–48
–50
–52
50
100 125
–50 –25
0
25
75
1
10
INPUT FREQUENCY (kHz)
100
AMBIENT TEMPERATURE, T (°C)
A
1099 G08
1099 G07
4
LTC1099
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PIN FUNCTIONS
VIN (Pin 1): Analog Input.
INT (Pin 9): Output that goes low when the conversion in
process is complete and goes high after data is read.
DB0 to DB3 (Pins 2 to 5): Data Outputs. DB0 = LSB.
GND (Pin 10): Ground Connection.
REF– (Pin 11): Low Reference Potential (Analog Ground).
WR/RDY (Pin 6): WR/RDY is an input when M0DE = VCC.
Falling edge of WR switches internal S/H to hold then
startsconversion.WR/RDYisanopendrainoutput(active
pull-down) when M0DE = GND. RDY goes low at start of
conversion and pull-down is turned off when conversion
iscomplete. Resistivepull-upisusuallyusedinthismode.
REF+ (Pin 12): High Reference Potential. VREF = Full Scale
= (REF+) – (REF–).
CS(Pin13):ChipSelect. Whenhigh, dataoutputsarehigh
impedance and all inputs are ignored.
MODE (Pin 7): WR-RD when MODE = VCC. RD when
M0DE = GND. No internal pull-down.
DB4 to DB7 (Pins 14 to 17): Data Outputs. DB7 = MSB.
OFL(Pin18): OverflowOutput. GoeslowwhenVIN >VREF
TC (Pin 19): User Adjustable Conversion Time.
.
RD (Pin 8): A Low on RD with CS Low Activates Three-
State Outputs. With MODE = GND and CS low, the falling
edge of RD switches internal S/H to hold and starts
conversion.
VCC (Pin 20): Positive Supply. 4.75V ≤ VCC ≤ 5.25V.
TEST CIRCUITS
t
1H
t = 20ns, C = 10pF
r
L
t
r
V
CC
V
90%
50%
CC
RD
10%
GND
RD
CS
t
1H
DATA
OUT
V
0H
90%
C
1k
L
DATA OUT
GND
t
0H
t = 20ns, C = 10pF
r
L
t
r
V
V
CC
CC
V
CC
90%
50%
1k
RD
RD
CS
10%
GND
DATA
OUT
t
0H
C
L
V
CC
DATA OUT
10%
V
0L
1099 F01
Figure 1. Three-State Test Circuit
5
LTC1099
W U
W
TI I G DIAGRA S
CS
RD
t
P
t
RDY
WR/RDY
INT
t
t
INTH
CRD
t
t , t
1H 0H
ACC0
NEW DATA
DB0-DB7
OLD DATA
t
ACC2
1099 F02
Figure 2. RD Mode (Pin 7 Is GND)
CS
CS
WR/RDY
WR/RDY
t
t
t
P
t
P
CWR
CWR
RD
INT
RD
t
t
INTH
INTH
INT
t
t
, t
1H 0H
t
, t
1H 0H
ACC2
DB0-DB7
OLD DATA
NEW DATA
DB0-DB7
t
t
ACC2
1099 F03B
1099 F03A
ACC0
Figure 3a. WR-RD Mode (Pin 7 Is HIGH and tRD > tCWR
)
Figure 3b. WR-RD Mode (Pin 7 Is HIGH and tRD< tCWR
)
CS (GND)
RD (GND)
WR/RDY
t
t
P
IHWR
INT
t
CWR
OLD DATA
NEW DATA
DB0-DB7
t
1099 F04
ACC0
Figure 4. WR-RD Mode (Pin 7 Is HIGH) Standalone Operation
6
LTC1099
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FUNCTIONAL DESCRIPTIO
V
REF
Figure 5 shows the functional block diagram for the
LTC1099 2-step flash ADC. It consists of two 4-bit flash
converters, a 4-bit DAC and a differencing circuit. The
conversion process proceeds as follows:
B7
B6
B5
B4
MS
4-BIT
FLASH
V
IN
1. At the start of the conversion, the on-board sample-
and-hold switches from the sample to the hold mode.
This is a true sample-and-hold with an acquisition time
of 240ns, an aperture time of 110ns and a tracking rate
of 2.5V/µs.
4-BIT
DAC
2. The held input voltage is converted by the 4-bit MS-
FlashADC. Thisgeneratestheupperormostsignificant
4-bits of the 8-bit output.
+
–
∑
3. A 4-bit approximation, from the DAC output, is sub-
tracted from the held input voltage.
REMAINDER
V
/16
REF
B3
B2
B1
B0
4. The LS-Flash ADC converts the difference between the
held input voltage and the DAC approximation. This
generates the lower or least significant (LS) 4-bits of
the 8-bit output. The LS-Flash reference is one six-
teenth of the MS-Flash reference. This effectively mul-
tiplies the difference by 16.
LS
4-BIT
FLASH
1099 F05
Figure 5. 8-Bit 2-Step Semiflash A/D
5. Upon the completion of the LS 4-bit flash the eight
outputlatchesareupdatedsimultaneously. Atthesame
time, the sample-and-hold is switched from the hold
mode to the acquire mode in preparation for the next
conversion.
accomplishthisfunctioninasimple, althoughnotstraight
forward, manner.
Figure 6 shows the six input switched capacitor compara-
tor. Intuitively, the comparator is easy to understand by
notingthatthecommonconnectionbetweenthetwoinput
capacitors, C1 and C2, acts like a virtual ground. In
operational amplifier circuits, current is summed at the
virtual ground node. Input voltage is converted to current
by the input resistors. In the switched capacitor compara-
tor, input voltage is converted to charge by the input
capacitors and these charges are summed at the virtual
ground node.
The advantage of this approach is the reduction in the
amount of hardware required. A full flash converter re-
quires 255 comparators while this approach requires only
31. The price paid for this reduction in hardware is an
increase in conversion time. A full flash converter requires
only one comparison cycle while this approach requires
two comparison cycles, hence 2-step flash.
This architecture is further simplified in the LTC1099 by
reusing the MS-Flash hardware to do the LS-Flash. This
reduces the number of comparators from 31 to 16. This is
possible because the MS and LS conversions are done at
different times.
A major advantage of this technique is that the switch-on
impedance has no affect on accuracy as long as sufficient
time exists to fully charge and discharge the capacitors.
During the first time period the T+ and TZ switches are
closed. This forces the common node between C1 and C2
to an arbitrary bias voltage. Since the capacitors subtract
out this voltage, it may be considered, for the sake of this
discussion, to be exactly zero (i.e., virtual ground). Note
TotakethesimpleblockdiagramofFigure5andreconfigure
it to reuse the MS-Flash to do the LS-Flash is conceptually
simple, but from a hardware point of view is not practical.
A new six input switched capacitor comparator is used to
7
LTC1099
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FUNCTIONAL DESCRIPTIO
T+
T
–2
T
–1
T
Z
T
Z
(+)
V
IN
C1
(–)
(–)
(+)
(–)
(–)
MS TAP
DAC
VIRTUAL
GROUND
0.5 LSB
C2
C1 = C2
HOLD
0V
LS TAP
T
SAMPLE
SAMPLE
Z
T+
T
–1
T
–2
STROBE
1099 F06
Figure 6. Six Input Switched Capacitor Comparator
also that variations in the bias voltage with time and
temperature will also be rejected. In this state, C1 charges
to VIN. When TZ opens, VIN is held on C1.
ThisholdstheDACoutputconstantforthenextstep—the
LS conversion. The LS conversion is started when T–1 is
opened and T–2 is closed. Capacitor C1 subtracts the 4-bit
DAC approximation from VIN and inputs the difference
charge to the virtual ground node. The equation for each
comparator is:
The next step is the first comparison — the MS-Flash. TZ
andT+areopenedandT–1 isclosed. Theequationforeach
comparator is:
VIN + 0.5LSB – VDAC – LSTAP = 0V
VIN + 0.5LSB – MSTAP = 0V
The 4-bit DAC approximation is input to all 16 compara-
tors. The LS tap voltages are converted to charge by
capacitorC2. LStapsvaryfromVREF/16Vto0Vin16equal
steps of VREF/256. The comparators look at the net charge
on the virtual ground node to perform the LS-Flash con-
version. When this conversion is complete, the four LSBs
along with the four MSBs are transferred to the output
latches. In this way, all eight outputs will change
simultaneously.
There are 16 identical comparators each tied to the tap on
a 16 resistor ladder. The MS tap voltages vary from VREF
to 0V in 16 equal steps of VREF/16.
Notice that capacitor C2 adds 0.5LSB to VIN. This offsets
the converter transfer function by 0.5LSB, equally distrib-
uting the 1LSB quantization error to ±0.5LSB.
Theoutputsofthe16comparatorsaretemporarilylatched
and drive the 4-bit DAC directly without need of decoding.
8
LTC1099
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DIGITAL I TERFACE
When RD goes low, with CS low, the result of the previous
conversion is output. This data stays there until the
ongoing conversion is complete (INT goes low). At this
time the outputs are updated with new data.
The digital interface to the LTC1099 entails either control-
ling the conversion timing or reading data. There are two
basic modes for controlling and reading the A/D — the
Write-Read(WR-RD) mode and the Read (RD) mode.
As long as CS and RD stay low long enough, the receiving
device will get the right data. Remember, the receiving
device reads data in on the rising edge of RD. The RDY
output facilitates making RD long enough.
WR-RD Mode (Pin 7 = High)
In the WR-RD mode, a conversion sequence starts on the
falling edge of WR with CS low (Figures 3a and 3b). This
is an edge-sensitive control function. The width of the WR
input is not important. All timing functions are internal to
the A/D.
In the RD mode, the WR input becomes the RDY output.
On the falling edge of RD, the RDY goes low. It is an open
drain output to allow a wired OR function so it requires a
pull-up resistor. At the end of conversion, the active pull-
down is released and RDY goes high.
The first thing to happen after the falling edge of WR is the
internal S/H is switched to hold. This typically takes 110ns
after WR falls and is the aperture time of the S/H.
The RDY output is designed to interface to the Ready In
(RDYIN) function on many popular processors. RDYIN
allows these processors to work with slow memory by
stretching the RD strobe coming from the processor. RD
will remain low as long as RDY is low. In the case of the
LTC1099, RDY stays low until the conversion is complete
and new data is available on the outputs. This greatly
simplifies the programmers task. Each time data is re-
quired from the A/D a simple read is executed. The
hardware interface makes sure the RD strobe is long
enough.
Next, the A/D conversion takes place. The conversion time
is internally set at 2.5µs, but is user adjustable (see
Adjusting the Conversion Time). The end of conversion is
signaled by the high to low transition of INT. The S/H is
switched back to the acquire state as soon as the conver-
sion is complete.
After the conversion is complete, the 8-bit result is avail-
ableonthethree-stateoutputs.Theoutputsareactivewith
RD and CS low. Output data is latched and, if no new
conversion is initiated, is available indefinitely as long as
the power is not turned off.
Adjusting the Conversion Time
The WR-RD mode is also used for stand-alone operation.
By tying CS and RD low the data outputs will be continu-
ously active (Figure 4). The falling edge of WR starts the
conversion sequence and when done new data will appear
ontheoutputs.Alloutputswillbeupdatedsimultaneously.
In stand-alone operation, the outputs will never be in a
high impedance state.
The conversion time of the LTC1099 is internally set at
2.5µs. If desired, it can be adjusted by forcing a voltage on
Pin 19. With Pin 19 left open, the conversion time runs
2.5µs. A convenient way to force the voltage is with the
circuit shown in Figure 7. To preset the conversion time to
a fixed amount, a resistor may be tied from Pin 19 to VCC
or GND. Tying it to VCC slows down the conversion and
tying it to GND will speed it up (see Typical Performance
RD Mode (Pin 7 = Low)
Characteristics).
5V
In the RD mode, a conversion sequence is initiated by the
falling edge of RD when CS is low (Figure 2). The S/H is
switched to the hold state 110ns after the falling edge of
RD. It is switched back to the acquire state at the end of
conversion.
1
2
20
19
10k
1099 F07
Figure 7. Adjusting the Conversion Time
9
LTC1099
U
U
ANALOG INTERFACE
The inclusion of a high quality sample-and-hold (S/H)
simplifies the analog interface to the LTC1099. All of the
error terms normally associated with an S/H (hold step,
offset, gain and droop errors) are included in the error
specifications for the A/D. This makes it easy for the
designer since all the error terms need not be taken into
account individually.
excellentamplifierinthisregard.Italsoworkswithasingle
supply which fits nicely with the LTC1099.
Reference Inputs
Sixteen equal valued resistors are internally connected
between REF+ and REF–. Each resistor is nominally 200Ω
giving a total resistance of 3.2k between the reference
terminals. When VIN equals REF+, the output code will be
all ones. When VIN equals REF–, the output code will be all
zeros.
Although it is most common to connect REF+ to a 5V
reference and REF– to ground, any voltages can be used.
The only restrictions are REF+ >REF– and REF+ and REF–
must be within the supply rails. As the reference voltage is
reduced the A/D will eventually lose accuracy. Accuracy is
quite good for references down to 1V.
S/H Timing
AfallingedgeontheRDorWRinputswitchestheS/Hfrom
acquire to hold and starts the conversion. The aperture
time is the delay from the falling edge to the actual instant
when the S/H switches to hold. It is typically 110ns.
As soon as a conversion is complete (2.5µs typ), the S/H
switches back to the sample mode. Even though the
acquisition time is only 240ns, a new conversion cannot
be started for (700ns typ) after a conversion is completed.
Even though the reference drives a resistive ladder, a lot of
capacitive switching is taking place internally. For this
reason, driving the reference has the same characteristics
as driving VIN. A fast low impedance source is necessary.
The reference has the additional problem of presenting a
DC load to the driving source. This requires the DC as well
as the AC source impedance to be low.
Analog Input
The input to the A/D looks like a 60pF capacitor in series
with 550Ω (Figure 8).
550Ω
V
TO A/D
60pF
IN
1099 F08
Good Grounding
Figure 8. Equivalent Input Circuit
As with any precise analog system care must be taken to
followgoodgroundingpracticeswhenusingtheLTC1099.
The most noise free environment is obtained by using a
ground plane with GND (Pin 10) and REF– (Pin 11) tied to
it. Bypass capacitors from REF+ (Pin 12) and VCC (Pin 20)
with short leads are also required to prevent spurious
switching noise from affecting the conversion accuracy.
With this high input capacitance care must be taken when
driving the inputs from a source amplifier. When the input
switch closes, an instantaneous capacitive load is applied
to the amplifier output. This acts like an impulse into the
amplifier and if it has poor phase margin the resulting
ringing can cause a considerable loss of accuracy. If the
amplifier is too slow the resulting settling tail will also
cause a loss of accuracy. The amplifier should also have
low open circuit output impedance. The LT1006 is an
If a ground plane is not practical, single point grounding
techniques should be used. Ground for the A/D should not
be mixed in with other noisy grounds.
10
LTC1099
U
U
ANALOG INTERFACE
APPLICATIONS
Note that since this is only a two quadrant multiplier, a
carrier component (the input to the LTC1099) will appear
in the output spectrum. Figure 11 shows the frequency
spectrum of a 42.5kHz sine wave multiplied by a 5kHz sine
wave. The depth of modulation is about 30dB. Figure 12
shows a 42.375kHz sine wave multiplied by a 30.875kHz
sinewave. Notethatatthesehigherfrequencies, thedepth
ofmodulationisstillabout30dB. Thecarrierfeed-through
is seen in Figure 12.
Analog Multiplier
The schematic Figure 9 shows the LTC1099 configured
with a DAC to form a two quadrant analog multiplier. An
input waveform is applied to the LTC1099 where it is
digitized at a 300kHz rate. The digitized signal is fed to the
DACin“flow-through”modewhereanothersignalisinput
to the DAC reference input. In this way, the two analog
signalsaremultipliedtoproduceadoublesidebandampli-
tude modulated output. Figure 10 shows a 3kHz sine wave
multiplied by a 100Hz triangle.
(V ) 0V TO 5V
IN1
(V ) +10V TO –10V
IN2
ANALOG
INPUT
ANALOG
INPUT
12V
MICROLINEAR
4
MP1208 DAC
CS AND RD LOW
DB0-DB3
8
8
5V
1
CS
2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
20
19
18
17
16
15
14
13
12
11
V
N/C
5V
CC
4
LTC1099
DB0
BYTE 1/
BYTE 2
WR2
XFER
DI6
DB4-DB7
WR1
3
10µF
10µF
3MHz
OSC
3
GND
4
DB1
DB2
DB3
4
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
DI5
5
DB7
DB6
CLK
N/C
5
DI4
6
74LS90
÷ 10 = 300kHz
6
DI7
DI3
7
WR/RDY DB5
7
DI8
DI2
8
MODE
RD
DB4
CS
50k
OFFSET NULL
8
DI9
4.7µF
DI1
9
5V
9
+
DI10
DI11
15V
DI0
10
INT
REF
N/C
8
10
–
1
V
GND
REF
REF
15V
0.01µF
5
11
I
RFB
12
+
–
OUT2
I
OUT1
LT1056
–15V
5V
REF
LT1019-5
= ANALOG GROUND
= DIGITAL GROUND
OUT
10pF
15V
IN
IN
25k
TRIM
GND
AGND
Figure 9
V
IN1
0V TO 5V
TRIANGLE INTO LTC1099
~100Hz
V
±4.8V SINE
IN2
INTO DAC ~ 3kHz
1099 F10
Figure 10
11
LTC1099
U
U
ANALOG INTERFACE
0
–70
32.5
34.5
36.5
38.5
40.5
42.5
44.5
46.5
48.5
50.5
52.5
1099 F11
37500Hz
42500Hz
47500Hz
Figure 11. Two Quadrant Multiplier Output Spectrum with 0V to
4.5V at 42.5kHz into LTC1099 and ±2V at 5kHz into DAC
0
–70
5
15
25
35
45
55
65
75
85
95
105
1099 F12
11500Hz
30875Hz 42375Hz
73250Hz
Figure 12. Two Quadrant Multiplier Output Spectrum with 0V to
4.5V at 42.375kHz into LTC1099 and ±2V at 30.875kHz into DAC
12
LTC1099
U
TYPICAL APPLICATIONS
TMS320C25 Interface Using RD Mode
5V
(A10, B11, H2, L6)
(B1, K11, L2)
74AS138
(K1)
(K2)
(L3)
(J11)
(K3)
V
V
SS
CC
A
V
CC
A0
A1
A2
IS
B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
C
G2A
G2B
G1
Y7
GND
A3
5V
TMS320C25
(D1)
(C2)
(C1)
(B2)
D4
D5
D6
D7
LTC1099
ANALOG
INPUT
VOLTAGE
V
V
IN
CC
(F1)
(E2)
(E1)
(D2)
+
DB0
TC
D0
D1
D2
D3
C1
C2
DB1
OFL
DB7
DB6
DB5
DB4
CS
DB2
DB3
MSC
READY
STRB
WR/RDY
MODE
RD
(B8)
(C10)
(H10)
+
INT
REF
5V
C2
(4)
(5)
(1)
(2)
(6)
(3)
–
GND
REF
+
C1
10k
1/2 74AS00
C1 = 4.7µF TANTALUM
C2 = 0.1µF CERAMIC
1099 TA03
5V
TMS320C25 Assembly Code for RD Mode Interface to LTC1099
0001 0000
0002 0032
AORG >32
DINT
0003 0032 CE01
0004 0033 C800
Disable Interrupts
LDPK >00 Data Page Pointer Is 0
0005 0034 8064 LOOP IN 100,PAO Input 1099 Data to Address 100
0006 0035 CB13
0007 0036 5500
0008 0037 FF80
RPTK
NOP
B
12
Repeat Next Instruction 12 Times
Don’t Convert Again Too Soon
LOOP Go for Another Conversion
13
LTC1099
U
TYPICAL APPLICATIONS
TMS320C25 Interface Using WR/RD Mode
5V
(A10, B11, H2, L6)
(K1)
74F138
V
V
SS
CC
A
V
CC
A0
A1
A2
IS
(K2)
(L3)
(J11)
(K3)
+
C5
0.1µF
B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
C7
C6
C
G2A
G2B
G1
Y7
GND
A3
5V
TMS320C25
LTC1099
ANALOG
INPUT
VOLTAGE
V
V
5V
C4
IN
CC
(F1)
(E2)
(E1)
(D2)
+
DB0
T
C
D0
D1
D2
D3
C3
DB1
OFL
DB7
DB6
DB5
DB4
CS
DB2
D7(B2)
D6(C1)
D5(C2)
D4(D1)
DB3
WR/RDY
MODE
RD
5V
+
INT
REF
5V
C2
+
–
C1
GND
REF
MSC
(C10)
READY
(B8)
R/W
(H11)
STRB
(H10)
74F00
IN1
V
5V
CC
C8
0.1µF
IN1
IN4
IN4
OUT1
IN2
OUT4
IN3
1N2
OUT2
GND
IN3
OUT3
C1, C3, C6 = 4.7µF TANTALUM
C2, C4, C5, C7, C8 = 0.1µF CERAMIC
1099 TA04
TMS320C25 Assembly Code for WR/RD Mode Interface to
LTC1099
0001 0032
AORG >32
DINT
0002 0032 CE01
0003 0033 C800
Disable Interrupts
LDPK
>0
Data Page Pointer Is 0
0004 0034 E064 LOOP OUT >64.PAO Start LTC1099 Conversion
0005 0035 CB20
0006 0036 5500
0007 0037 8064
0008 0038 FF80
RPTK >12 Wait for Conversion to Finish
NOP
IN >64.PAO Read LTC1099 Data; Store in >64
B
LOOP Do Again
14
LTC1099
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N Package
20-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.040*
(26.416)
MAX
20
19
18
17
16
15
14
13
12
11
10
0.255 ± 0.015*
(6.477 ± 0.381)
3
4
5
6
7
8
9
1
2
0.300 – 0.325
0.045 – 0.065
0.130 ± 0.005
(7.620 – 8.255)
(1.143 – 1.651)
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
0.005
(0.127)
MIN
0.100
(2.54)
BSC
–0.015
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N20 1098
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.496 – 0.512*
(12.598 – 13.005)
19 18
16
14 13 12 11
20
17
15
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
BSC
0.004 – 0.012
0.009 – 0.013
(0.102 – 0.305)
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
S20 (WIDE) 1098
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1099
U
TYPICAL APPLICATIO S
Cascading for 9-Bit Resolution
20
1
CS
13
LTC1099
5V
5V
CS
V
CC
WR
RD
8
V
WR/RDY
V
IN
IN
6
RD
7
B0
B1
2
3
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
MODE
12
+
5V
V
REF
REF
B2
B3
B4
B5
B6
B7
B8
OFL
4
µP
BUS
4.7µF
5
14
15
16
17
11
10
–
V
4.7µF
1k
18
OFL
GND
5k
1k
LTC1099
13
8
20
1
5V
5V
CS
V
CC
WR/RDY
V
IN
6
RD
2
3
7
MODE
12
+
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OFL
V
REF
REF
4
5
4.7µF
14
15
16
17
18
11
10
–
V
GND
1099 TA02
RELATED PARTS
PART NUMBER
LTC1274/LTC1277
LTC1279
DESCRIPTION
COMMENTS
12-Bit, 100ksps Parallel/2-Byte ADC
12-Bit, 600ksps Parallel ADC
8-Bit, 20Msps Parallel ADC
5V or ± 5V, 10mW with 1µA Shutdown
5V, 60mW, 70dB SINAD
LTC1406
5V, 150mW, 48.5dB SINAD
±5V, 80mW, 72.5dB SINAD
±5V, 150mW, 81.5dB SINAD
LTC1409
12-Bit, 800ksps Parallel ADC
14-Bit, 800ksps Parallel ADC
LTC1419
sn1099 1099fas LT/TP 1100 2K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1989
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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