LTC1149-3.3 [Linear]
High Efficiency Synchronous Step-Down Switching Regulators; 高效率同步降压型开关稳压器
| 型号： | LTC1149-3.3 |
| 厂家： | 
Linear |
| 描述： | High Efficiency Synchronous Step-Down Switching Regulators |
| 文件： | 总20页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1149
LTC1149-3.3/LTC1149-5
High Efficiency Synchronous
Step-Down Switching Regulators
U
DESCRIPTIO
EATURE
S
F
■
■
■
Operation to 48V Input Voltage
The LTC®1149 series is a family of synchronous step-
down switching regulator controllers featuring automatic
Burst ModeTM operation to maintain high efficiencies at
low output currents. These devices drive external comple-
mentary power MOSFETs at switching frequencies up
to 250kHz using a constant off-time current-mode archi-
tecture.
Ultrahigh Efficiency: Up to 95%
Current Mode Operation for Excellent Line and
Load Transient Response
High Efficiency Maintained over Wide Current Range
Logic-Controlled Micropower Shutdown
Short-Circuit Protection
■
■
■
■
■
■
■
Very Low Dropout Operation: 100% Duty Cycle
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
Special onboard regulation and level-shift circuitry allow
operation at input voltages from dropout to 48V (60V
absolute max). The constant off-time architecture main-
tains constant ripple current in the inductor, easing the
design of wide input range converters. Current mode
operation provides excellent line and load transient
response. The operating current level is user-program-
mable via an external current sense resistor.
Available in 16-Pin Narrow SO Package
O U
PPLICATI
A
S
■
■
■
■
■
■
Notebook and Palmtop Computers
Portable Instruments
Battery-Operated Digital Devices
Industrial Power Distribution
Avionics Systems
The LTC1149 series incorporates automatic power saving
Burst Modeoperation when load currents drop below the
level required for continuous operation. Standby power is
reduced to only about 8mW at VIN = 12V. In shutdown,
both MOSFETs are turned off.
Telecom Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Modeis a trademark of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
V
IN
LTC1149-5 Efficiency
C
+
IN
1N4148
1N4148
100
90
80
70
60
100µF
V
IN
FIGURE 1 CIRCUIT
100V
CAP
P-CHANNEL
IRFR9024
PGATE
V
= 12V
IN
0.068µF
V
V
0.047µF
D1
1N5819
CC
+
PDRIVE
3.3µF
L*
62µH
R
**
CC
SENSE
0.05Ω
V
= 24V
V
IN
OUT
LTC1149-5
5V/2A
+
–
SHDN1
SHDN2
SENSE
SENSE
0V = NORMAL
>2V = SHUTDOWN
1000pF
I
TH
+
N-CHANNEL
IRFR024
C
OUT
220µF
3300µF
C
NGATE
SGND P, RGNDS
T
C
T
1k
470pF
0.02
0.2
LOAD CURRENT (A)
2
*COILTRONICS CTX62-2-MP
**KRL SL-1-C1-0R050J
1149 F01
1149 TA01
Figure 1. High Efficiency Step-Down Regulator
1
LTC1149
LTC1149-3.3/LTC1149-5
W W W
U
ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
Input Supply Voltage (Pin 2)...................... –15V to 60V
TOP VIEW
ORDER PART
V
CC Output Current (Pin 3) .................................. 50mA
NUMBER
1
2
3
4
5
6
7
8
CAP
16
15
14
13
12
11
10
9
PGATE
VCC Input Voltage (Pin 5)........................................ 16V
Continuous Output Current (Pins 4, 13) .............. 50mA
Sense Voltages (Pins 8, 9)
SHDN2
RGND
NGATE
PGND
SGND
V
IN
V
CC
LTC1149CN
PDRIVE
LTC1149CN-3.3
LTC1149CN-5
LTC1149CS
VIN ≥ 12.7V .......................................... 13V to –0.3V
VIN < 12.7V............................. (VCC + 0.3V) to –0.3V
Shutdown Voltages (Pins 10, 15) ............................. 7V
Operating Temperature Range .................... 0°C to 70°C
Extended Commercial
Temperature Range ............................... –40°C to 85°C
Junction Temperature (Note 1)............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
V
CC
C
T
V
/
FB
I
TH
–
SHDN1*
LTC1149CS-3.3
LTC1149CS-5
+
SENSE
SENSE
N PACKAGE
S PACKAGE
16-LEAD PDIP
16-LEAD PLASTIC SO
*FIXED OUTPUT VERSIONS
TJMAX = 125°C, θJA = 70°C/ W (N)
TJMAX = 125°C, θJA = 110°C/ W (S)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.25
0.2
MAX
1.29
1
UNITS
V
V
10
Feedback Voltage (LTC1149 Only)
Feedback Current (LTC1149 Only)
V
IN
= 9V
●
●
1.21
I
µA
10
V
OUT
Regulated Output Voltage
LTC1149-3.3
LTC1149-5
V
= 9V
= 700mA
= 700mA
IN
I
I
●
●
3.23
4.9
3.33
5.05
3.43
5.2
V
V
LOAD
LOAD
∆V
OUT
Output Voltage Line Regulation
V
IN
= 9V to 48V, I = 50mA
LOAD
–40
0
40
mV
Output Voltage Load Regulation
LTC1149-3.3
LTC1149-5
5mA < I
5mA < I
< 2A
< 2A
●
●
40
60
65
100
mV
mV
LOAD
LOAD
Burst ModeOutput Ripple
I
= 0A
50
mV
P-P
LOAD
I
Input DC Supply Current (Note 3)
Normal Mode
2
V
IN
V
IN
= 12V
= 48V
2.0
2.2
2.8
3.0
mA
mA
Burst Mode
Shutdown
V
V
= 12V
= 48V
0.6
0.8
0.9
1.1
mA
mA
IN
IN
V
IN
V
IN
= 12V, V = 2V
= 48V, V = 2V
135
300
170
390
µA
µA
15
15
V
CC
Internal Regulator Voltage
(Sets MOSFET Gate Drive Levels)
V
3
= 12V to 48V
●
9.75
10.25
11
V
IN
I = 20mA
V – V
2
V
CC
Dropout Voltage
V
IN
= 5V, I = 10mA
200
250
mV
3
3
V
IN
– V
P-Gate to Source Voltage (Off)
V
IN
V
IN
= 12V
= 48V
●
●
–0.2
–0.2
0
0
V
V
1
2
LTC1149
LTC1149-3.3/LTC1149-5
ELECTRICAL CHARACTERISTICS TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
SYMBOL
V – V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense Threshold Voltage
LTC1149
9
8
V = 5V, V = 1.32V (Forced)
25
150
mV
mV
8
10
V = V
– 100mV
●
●
●
130
130
130
170
170
170
8
OUT
LTC1149-3.3
LTC1149-5
V = 3.5V (Forced)
25
mV
mV
8
V = V
– 100mV
150
8
OUT
V = 5.3V (Forced)
25
150
mV
mV
8
V = V
8
– 100mV
OUT
V
V
Shutdown 1 Threshold
10
15
LTC1149-3.3, LTC1149-5
0.5
0.8
0.8
1.4
18
2
2
V
V
Shutdown 2 Threshold
I
I
Shutdown 2 Input Current
V
= 5V
25
µA
15
15
–
C Pin Discharge Current
T
V
V
In Regulation, V
= 0V
= V
OUT
50
4
70
2
90
10
µA
µA
6
OUT
OUT
SENSE
t
Off-Time (Note 4)
C = 390pF, I = 700mA
LOAD
5
6
µs
OFF
T
t , t
r
Driver Output Transition Times
C = 3000pF (Pins 4, 13), V = 6V
100
200
ns
f
L
IN
–40°C ≤ TA ≤ 85°C (Note 5), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Feedback Voltage LTC1149 Only
1.2
1.25
1.3
V
10
Regulated Output Voltage
LTC1149-3.3
LTC1149-5
V = 9V
IN
OUT
I
I
= 700mA
= 700mA
3.17
4.85
3.33
5.05
3.43
5.2
V
V
LOAD
LOAD
I
Input DC Supply Current (Note 3)
Normal Mode
2
V
V
= 12V
= 48V
2.0
2.2
3.2
3.5
mA
mA
IN
IN
Burst Mode
Shutdown
V
V
= 12V
= 48V
0.6
0.8
1.05
1.30
mA
mA
IN
IN
V
V
= 12V, V = 2V
= 48V, V = 2V
135
300
230
520
µA
µA
IN
IN
15
15
V
Internal Regulator Voltage
(Sets MOSFET Gate Drive Levels)
V
3
= 12V to 48V
9.75
10.25
11
V
CC
IN
I = 20mA
V – V
Current Sense Threshold Voltage
Low Threshold (Forced)
High Threshold (Forced)
25
mV
mV
9
8
125
0.8
3.8
150
175
2
V
Shutdown 2 Threshold
Off-Time (Note 4)
1.4
5
V
15
t
C = 390pF, I
= 700mA, V = 10V
6
µs
OFF
T
LOAD
IN
The
temperature range.
Note 1: T is calculated from the ambient temperature T and power
● denotes specifications which apply over the full operating
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. The allowable operating frequency
may be limited by power dissipation at high input voltages. See Typical
Performance Characteristics and Applications Information.
J
A
dissipation P according to the following formulas:
D
LTC1149CN, LTC1149CN-3.3, LTC1149CN-5: T = T + (P )(70°C/W)
Note 4: In applications where R
time increases approximately 40%.
is placed at ground potential, the off-
J
A
D
SENSE
LTC1149CS, LTC1149CS-3.3, LTC1149CS-5: T = T + (P )(110°C/W)
J
A
D
Note 2: Pin 10 is a shutdown pin on the LTC1149-3.3 and LTC1149-5
fixed output voltage versions and must be at ground potential for testing.
Note 5: The LTC1149, LTC1149-3.3, and LTC1149-5 are not tested and
not quality assurance sampled at –40°C and 85°C. These specifications
are guaranteed by design and/or correlation.
3
LTC1149
LTC1149-3.3/LTC1149-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Line Regulation
Load Regulation
Efficiency vs Input Voltage
100
95
90
85
80
20
0
60
40
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
= 24V
FIGURE 1 CIRCUIT
I
= 1A
V
IN
I
= 1A
LOAD
LOAD
–20
–40
20
0
–60
–80
–20
–40
–60
–100
0
10
20
30
40
50
0
0.5
1.0
1.5
2.0
2.5
0
10
20
30
40
50
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1149 G01
1149 G03
1149 G02
Operating Frequency
DC Supply Current
Supply Current in Shutdown
vs (VIN – VOUT
)
3.0
2.5
400
300
200
100
0
2.0
1.5
1.0
0.5
0
V
= 2V
V
= 5V
SD2
OUT
T = 0°C
ACTIVE MODE
2.0
1.5
T = 25°C
T = 70°C
1.0
0.5
0
SLEEP MODE
0
10
20
30
40
50
0
10
20
30
40
50
0
5
10
15
20
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
(V – V ) VOLTAGE (V)
IN
OUT
1149 G04
1149 G05
1149 G06
Gate Charge Supply Current
Current Sense Threshold Voltage
Off-Time vs VOUT
30
25
160
140
120
100
80
80
70
60
50
40
30
20
10
0
MAXIMUM
THRESHOLD
20
15
Q
P
+ Q = 100nC
N
60
10
5
40
MINIMUM
THRESHOLD
Q
P
+ Q = 50nC
N
LTC1149-5
4
20
LTC1149-3.3
0
0
60
TEMPERATURE (°C)
80
0
20
40
100
50
100
150
200
250
3
0
1
2
5
OPERATING FREQUENCY (kHz)
OUTPUT VOLTAGE (V)
1149 G09
1149 G07
1149 G08
4
LTC1149
LTC1149-3.3/LTC1149-5
U
U
U
PI FU CTIO S
PGATE (Pin 1): Level-Shifted Gate Drive Signal for Top
P-ChannelMOSFET. ThevoltageswingatPin1isfromVIN
to VIN – VCC.
SHDN1/VFB (Pin 10): In fixed output voltage versions, Pin
10 serves as a shutdown pin for the control circuitry only
(VCC is not affected). Taking Pin 10 of the LTC1149-3.3 or
LTC1149-5 high holds both MOSFETs off. Must be at
ground potential for normal operation.
VIN (Pin 2): Main Supply Input Pin.
VCC (Pin3):OutputPinofLowDropout10VRegulator.Pin
3 is not protected against DC short circuits.
For the LTC1149 adjustable version, Pin 10 serves as the
feedback pin from an external resistive divider used to set
the output voltage.
PDRIVE (Pin 4): High Current Gate Drive for Top
P-ChannelMOSFET.ThevoltageswingatPin4isfromVCC
to ground.
SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of COUT
.
VCC (Pin 5): Regulated 10V Input for Driver and Control
Supplies. Must be closely decoupled to power ground.
PGND (Pin 12): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of CIN.
CT (Pin 6): External capacitor CT from Pin 6 to ground sets
theoperatingfrequency. (Thefrequencyisalsodependent
on the ratio VOUT/VIN.)
NGATE (Pin 13): High Current Drive for Bottom
N-channel MOSFET. The voltage swing at Pin 13 is from
ground to VCC.
ITH (Pin 7): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 7 voltage.
SENSE– (Pin 8): Connects to internal resistive divider
which sets the output voltage in LTC1149-3.3 and
LTC1149-5 versions. Pin 8 is also the (–) input for the
current comparator.
RGND (Pin 14): Low Dropout Regulator Ground. Con-
nects to power ground.
SHDN2 (Pin 15): Master Shutdown Pin. Taking Pin 15
high shuts down VCC and all control circuitry; requires a
logic signal with tr, tf < 1µs.
CAP(Pin16):ChargeCompensationPin. Acapacitorfrom
Pin 16 to VCC provides the charge required by the P-drive
level-shift capacitor during supply transitions. The Pin 16
capacitor must be larger than the Pin 4 capacitor.
SENSE+ (Pin9):The(+) Inputforthe CurrentComparator.
A built-in offset between Pins 8 and 9 in conjunction with
RSENSE sets the current trip threshold.
U
OPERATIO
(Refer to Functional Diagram)
The LTC1149 series uses a current mode, constant off-
time architecture to synchronously switch an external pair
of complementary power MOSFETs. Operating frequency
is set by an external capacitor at the timing capacitor,
Pin 6.
A low dropout 10V regulator provides the operating volt-
age VCC for the MOSFET drivers and control circuitry. The
driver outputs at Pins 4 and 13 are referenced to ground,
which fulfills the N-channel MOSFET gate drive require-
ment. The P-channel gate drive at Pin 1 must be refer-
encedtothemainsupplyinputVIN, whichisaccomplished
by level-shifting the Pin 4 signal via an internal 500k
resistor and external capacitor.
The output voltage is sensed either by an internal voltage
divider connected to SENSE–, Pin 8 (LTC1149-3.3 and
LTC1149-5) or an external divider returned to VFB Pin 10
(LTC1149). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference
voltage of 1.25V. To optimize efficiency, the LTC1149
series automatically switches between two modes of
operation, burst and continuous. The voltage comparator
is the primary control element for Burst Mode operation,
whilethegainblockcontrolstheoutputvoltageincontinu-
ous mode.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 8 and 9
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the PGATE output is switched to VIN,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 6 is now allowed to discharge at a rate
determined by the off-time controller. The discharge
5
LTC1149
LTC1149-3.3/LTC1149-5
U
OPERATIO (Refer to Functional Diagram)
current is made proportional to the output voltage (mea-
sured by Pin 8) to model the inductor current, which
decays at a rate which is also proportional to the output
voltage. While the timing capacitor is discharging, the
NGATE output is high, turning on the N-channel MOSFET.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, much of the circuitry
is turned off, dropping the supply current from several
milliamperes (with the MOSFETs switching) to 600µA.
When the output capacitor has discharged by the amount
of hysteresis in comparator V, the P-channel MOSFET is
again turned on and this process repeats. To avoid the
operation of the current loop interfering with Burst Mode
operation, a built-in offset is incorporated in the gain
stage. This prevents the current comparator threshold
from increasing until the output voltage has dropped
below a minimum threshold.
When the voltage on the timing capacitor has discharged
past VTH1, comparator T trips, setting the flip-flop. This
causes the NGATE output to go low (turning off the
N-channel MOSFET) and the PGATE output to also go low
(turning the P-channel MOSFET back on). The cycle then
repeats.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain
stage to increase the current comparator threshold, thus
tracking the load current.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the N-gate
output can go high, the P-drive output must also be high.
Likewise, the P-drive output is prevented from going low
when the N-gate output is high.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
orabovethedesiredregulatedvalue,theP-channelMOSFET
is held off by comparator V and the timing capacitor
continues to discharge below VTH1. When the timing
capacitor discharges past VTH2, voltage comparator S
trips, causing the internal SLEEP line to go low and the
N-channel MOSFET to turn off.
Using constant off-time architecture, the operating fre-
quency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-
time controller increases the discharge current as VIN
drops below VOUT + 1.5V. In dropout the P-channel
MOSFET is turned on continuously.
U
U
W
Pin 10 connection shown for LTC1149-3.3 and LTC1149-5; changes create LTC1149.
FU CTIO AL DIAGRA
V
IN
2
PGATE
1
4
CAP
16
5
V
CC
500k
PDRIVE
LOW
DROPOUT
10V
V
CC
SHDN2
15
500k
3
REGULATOR
NGATE
13
9
14 RGND
+
–
12
8
SENSE
PGND
SENSE
–
+
V
R
S
–
+
Q
SLEEP
C
25mV TO 150mV
–
–
+
V
OS
V
TH1
T
13k
G
+
100k
+
S
1.25V
V
–
TH2
V
IN
OFF-TIME
CONTROL
–
REFERENCE
7
10
11
SGND
SENSE
6
I
SHDN1
TH
C
T
(V
)
FB
1149 FD
6
LTC1149
LTC1149-3.3/LTC1149-5
TEST CIRCUIT
+
+
220µF
100V
IRF9Z34
0.1µF
V
IN
0.068µF
MBR380
IRFZ34
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
PGATE
CAP
SHDN2
RGND
NGATE
PGND
V
15
V
V
IN
0.047µF
CC
+
PDRIVE
1µF
50µH
LTC1149
V
CC
C
T
SGND
+
V
V
10
V
FB
/
I
25k
TH
SHDN1
+
390pF
3300pF
–
SENSE
SENSE
+
220µF
+
+
1k
75k
0.05Ω
V
8
V
9
– V
8
1000pF
OUT
1149 TC
U U
W
U
APPLICATIO S I FOR ATIO
Typical Application Circuit
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing a
margin for variations in the LTC1149 series and external
component values yields:
The basic LTC1149 series application circuit is shown in
Figure 1. External component selection is driven by the
input voltage and output load requirement, and begins
with the selection of RSENSE. Once RSENSE is known, CT
and L can be chosen. Next, the power MOSFETs and D1
are selected. Finally, CIN and COUT are selected and the
loop is compensated. The circuit shown in Figure 1 can be
configured for operation up to an input voltage of 48V. If
the application does not require greater than 15V opera-
tion, then the LTC1148 should be used.
100mV
MAX
R
=
SENSE
I
A graph for selecting RSENSE versus maximum output
currentisgiveninFigure2.TheLTC1149seriesworkswell
with values of RSENSE from 0.02Ω to 0.2Ω.
RSENSE Selection for Output Current
The load current below which Burst Mode operation
commences, IBURST, and the peak short-circuit current,
ISC(PK), both track IMAX. Once RSENSE has been chosen,
IBURST and ISC(PK) can be predicted from the following
equations:
RSENSE is chosen based on the required output current.
The LTC1149 series current comparator has a threshold
range which extends from a minimum of 25mV/RSENSE to
a maximum of 150mV/RSENSE. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. For proper
Burst Mode operation, IRIPPLE(P-P) must be less than or
equal to the minimum current comparator threshold.
15mV
SENSE
I
≈
BURST
R
150mV
SENSE
I
=
SC(PK)
R
7
LTC1149
LTC1149-3.3/LTC1149-5
U U
W
U
APPLICATIO S I FOR ATIO
The LTC1149 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
V
V
1
OFF
OUT
f =
1 –
)
)
t
IN
where:
ISC(AVG) to be reduced to approximately IMAX
.
V
V
REG
OUT
4
t
= (1.3)(10 )(C )
T
OFF
)
)
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
VREG is the desired output voltage (i.e., 5V, 3.3V), while
VOUT is the actual output voltage. Thus VREG/VOUT = 1
when in regulation.
Note that as VIN decreases, the frequency decreases.
When the input to output voltage differential drops below
1.5V, the LTC1149 series reduces tOFF by increasing the
discharge current in CT. This prevents audible operation
prior to dropout.
0
1
2
3
4
5
OncethefrequencyhasbeensetbyCT,theinductorLmust
be chosen to provide no more than 25mV/RSENSE of peak-
to-peak inductor ripple current. This results in a minimum
required inductor value of:
MAXIMUM OUTPUT CURRENT (A)
1149 F02
Figure 2. RSENSE vs Maximum Output Current
LMIN =( 5.1)(105)(RSENSE)(CT)(VREG
)
L and CT Selection for Operating Frequency
The LTC1149 series uses a constant off-time architecture
with tOFF determined by an external timing capacitor CT.
Each time the P-channel MOSFET switch turns on, the
voltage on CT is reset to approximately 3.3V. During the
off-time, CT is discharged by a current which is propor-
tional to VOUT. The voltage on CT is analogous to the
current in inductor L, which likewise decays at a rate
proportional to VOUT. Thus the inductor value must track
the timing capacitor value.
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor are
eased at the expense of efficiency. If too small an inductor
is used, the inductor current will decrease past zero and
changepolarity.AconsequenceofthisisthattheLTC1149
series may not enter Burst Modeoperation and efficiency
will be severely degraded at low currents.
1400
V
= 5V
OUT
1200
1000
800
600
400
200
0
The value of CT is calculated from the desired continuous
mode operating frequency, f:
–5
V
V
(7.8)(10 )
OUT
V
= 48V
C =
1 –
IN
T
)
)
f
IN
V
= 24V
IN
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
V
IN
= 12V
200
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency is given by:
0
50
100
150
250
FREQUENCY (kHz)
1149 F03
Figure 3. Timing Capacitor Selection
8
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LTC1149-3.3/LTC1149-5
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Inductor Core Selection
Selection criteria for the P-channel MOSFET include the
on-resistanceRDS(ON), reversetransfercapacitanceCRSS
,
Once the minimum value for L is known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ® cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
input voltage and maximum output current. When the
LTC1149 is operating in continuous mode, the duty cycle
for the P-channel MOSFET is given by:
V
V
OUT
P-Ch Duty Cycle =
IN
The P-channel MOSFET dissipation at maximum output
current is given by:
V
V
OUT
P-Ch P =
(I
MAX
)2(1 + ∂ ) R
D
P
DS(ON)
Ferrite designs have very low core loss, so design goals
canconcentrateoncopperlossandpreventingsaturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Modeoperation to be falsely
triggered in the LTC1149 series. Do not allow the core to
saturate!
IN
+ K(V )2(I
)(C )(f)
MAX RSS
IN
where ∂ is the temperature dependency of RDS(ON) and K
is a constant related to the gate drive current. Note the two
distinct terms in the equation. The first gives the I2R
losses, which are highest at low input voltages, while the
second gives the transition losses, which are highest at
high input voltages. For VIN < 24V, the high current
efficiency generally improves with larger MOSFETs
(although gate charge losses begin eating into the gains.
See Efficiency Considerations). For VIN > 24V, the transi-
tion losses rapidly increase to the point that the use of a
higher RDS(ON) device with lower CRSS actually provides
higher efficiency. This is illustrated in the Design Example
section.
Molypermalloy (from Magnetics, Inc.) is a very good, low
losscorematerialfortoroids,butitismoreexpensivethan
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, new surface mount designs available
from Coiltronics do not increase the height significantly.
The term (1 + ∂) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
∂ = 0.007/°C can be used as an approximation for low
voltageMOSFETs.CRSS isusuallyspecifiedintheMOSFET
electricalcharacteristics.TheconstantKismuchharderto
pin down, but K = 5 can be used for the LTC1149 series to
estimate the relative contributions of the two terms in the
P-channel dissipation equation.
P-Channel MOSFET Selection
Two external power MOSFETs must be selected for use
with the LTC1149 series: a P-channel MOSFET for the
main switch, and an N-channel MOSFET for the synchro-
nous switch.
The minimum input voltage determines whether standard
thresholdorlogic-levelthresholdMOSFETsmustbeused.
For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V)
may be used. If VIN is expected to drop below 8V, logic-
level threshold MOSFETs (VGS(TH) < 2.5V) are strongly
recommended. When logic-level MOSFETs are used, the
absolute maximum VGS rating for the MOSFETs must be
greater than the LTC1149 series internal regulator
voltage VCC.
N-Channel MOSFET and D1 Selection
The same input voltage constraints apply to the N-channel
MOSFET as to the P-channel with regard to when logic-
level devices are required. However, the dissipation calcu-
lation is quite different. The duty cycle and dissipation for
Kool Mµ is a registered trademark of Magnetics, Inc.
9
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the N-channel MOSFET operating in continuous mode are
given by:
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. An additional 0.1µF ceramic capacitor may also be
required on VIN for high frequency decoupling.
V – V
IN
OUT
N-Ch Duty Cycle =
V – V
V
IN
)2(1 + ∂ )R
MAX N DS(ON)
IN
OUT
N-Ch P =
(I
D
V
IN
The selection of COUT is driven by the required effective
series resistance (ESR). The ESR of COUT must be less
than twice the value of RSENSE for proper operation of the
LTC1149 series:
where ∂ is the temperature dependency of RDS(ON). Note
that there is no transition loss term in the N-channel
dissipation equation because the drain-to-source voltage
is always low when the N-channel MOSFET is turning on
or off. The remaining I2R losses are the greatest at high
input voltage or during a short circuit, when the N-channel
duty cycle is nearly 100%. Fortunately, low RDS(ON)
N-channel MOSFETs are readily available which reduce
losses to the point that heat sinking is not required, even
during continuous short-circuit operation.
C
OUT Required ESR < 2RSENSE
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RSENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RSENSE, the voltage ripple on the output capacitor
willprematurelytriggerBurstModeoperation, resultingin
disruption of continuous mode and an efficiency hit which
can be several percent.
The Schottky diode D1 shown in Figure 1 only conducts
during the dead-time between the conduction of the two
powerMOSFETs. D1’ssolepurposeinlifeistopreventthe
body diode of the N-channel MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
Manufacturers such as Nichicon, Chemicon and Sprague
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR for its size, at a somewhat
higher price. Once the ESR requirement for COUT has been
met, the RMS current rating generally far exceeds the
IRIPPLE(P-P) requirement.
conducting IMAX
.
In surface mount applications multiple capacitors may
havetobeparalleledtomeetthecapacitance,ESR,orRMS
current handling requirements of the application. Alumi-
num electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. For example,
if 200µF/10V is called for in an application requiring 3mm
height,twoAVX100µF/10V(P/NTPSD107K010)couldbe
used. Consult the manufacturer for other specific recom-
mendations.
Finally, both MOSFETs and D1 must be selected for
breakdown voltages higher than the maximum VIN.
CIN and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT/VIN. To
preventlargevoltagetransients, alowESRinputcapacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
I
[V
(V – V )]1/2
MAX OUT IN OUT
C Required I
≈
RMS
IN
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IMAX/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturer’s
At low supply voltages, a minimum value of COUT is
suggested to prevent an abnormal low frequency operat-
ing mode (see Figure 4). When COUT is too small, the
10
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LTC1149-3.3/LTC1149-5
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regulator loop adapts to the current change and returns
VOUT to its steady state value. During this recovery time
VOUT can be monitored for overshoot or ringing which
would indicate a stability problem. The Pin 7 external
components shown in the Figure 1 circuit will prove
adequate compensation for most applications.
outputrippleatlowfrequencieswillbelargeenoughtotrip
the voltage comparator. This causes the Burst Mode
operation to be activated when the LTC1149 series would
normally be in continuous operation. The effect is most
pronounced with low values of RSENSE and can be
improved by operating at higher frequencies with lower
values of L. The output remains in regulation at all times.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Checking Transient Response
Switching regulators take several cycles to respond to a
step in DC (resistive) load current. When a load step
occurs, VOUT shifts by an amount equal to (∆ILOAD)(ESR),
where ESR is the effective series resistance of COUT
.
∆ILOAD also begins to charge or discharge COUT until the
1000
L = 50µH
SENSE
R
= 0.02Ω
800
600
LTC1149 Adjustable Applications
L = 25µH
SENSE
When an output voltage other than 3.3V or 5V is required,
the LTC1149 adjustable version is used with an external
resistive divider from VOUT to VFB Pin 10. The regulated
voltage is determined:
R
= 0.02Ω
400
200
0
L = 50µH
= 0.05Ω
R
SENSE
R2
V
= 1.25 1 +
OUT
)
)
R1
0
1
2
3
4
5
(V – V ) VOLTAGE (V)
IN
OUT
In applications where VOUT is greater than the LTC1149
internallyregulatedVCC voltage, RSENSE mustbemovedto
1149 F04
Figure 4. Minimum Suggested COUT
V
IN
+
150µF
1N4148
1N4148
V
IN
50V
CAP
PGATE
IRF9Z34
0.068µF
100µH
V
V
0.047µF
CC
+
PDRIVE
NGATE
1µF
CC
R2
1N5819
IRFZ34
215k
1%
+
150µF
16V
LTC1149
V
LOAD
OUT
0V = NORMAL
V
SHDN2
FB
OS-CON
>2V = SHUTDOWN
R1
25k
1%
100pF
+
SENSE
SENSE
I
TH
1000pF
R
–
SENSE
0.05Ω
C
3300pF
1k
T
OUTPUT
GROUND
CONNECTION
GNDS
C
T
200pF
R2
R1
V
OUT
= 1.25 1 +
(
)
1149 F05
VALUES SHOWN FOR V
= 12V
OUT
Figure 5. High Efficiency Step-Down Regulator with VOUT > VCC
11
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the ground side of the output to prevent the absolute
maximum voltage ratings of the sense pins from being
exceeded. This is shown in Figure 5. When the current
sense comparator is operating at 0V common mode, the
off-time increases approximately 40%, requiring the use
of a smaller timing capacitor CT.
mode, IGATECHG = f (QN + QP). The typical gate charge
for a 0.1Ω N-channel power MOSFET is 25nC, and for
a P-channel about twice that value. This results in
IGATECHG = 7.5mA in 100kHz continuous operation, for
a 5% to 10% typical mid-current loss with VIN = 24V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it
argues against using larger MOSFETs than necessary
to control I2R losses, since overkill can cost efficiency
as well as money!
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
3. I2R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continu-
ous mode all of the output current flows through L and
RSENSE, but is “chopped” between the P-channel and
N-channel MOSFETs. If the two MOSFETs have
approximately the same RDS(ON), then the resistance of
one MOSFET can simply be summed with the resis-
tances of L and RSENSE to obtain I2R losses. For
example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω and
RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I2R losses cause the
efficiency to roll-off at high output currents.
%Efficiency = 100 – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1149 series circuits: 1) LTC1149 DC supply
current, 2)MOSFETgatechargecurrent, 3)I2Rlossesand
4) P-channel transition losses.
1. The DC supply current is the current which flows into
VIN Pin 2 less the gate charge current. For VIN = 12V the
LTC1149 DC supply current is 0.6mA for no load, and
increases proportionally with load up to 2mA after the
LTC1149 series has entered continuous mode.
Because the DC supply current is drawn from VIN, the
resulting loss increases with input voltage. For
VIN =24V, theDCbiaslossesaregenerallylessthan3%
for load currents over 300mA. However, at very low
loadcurrentstheDCbiascurrentaccountsfornearlyall
of the loss.
4. Transition losses apply only to the P-channel MOSFET,
and only when operating at high input voltages (typi-
cally 24V or greater). Transition losses can be esti-
mated from:
Transition Loss ≈ 5(VIN)2(IMAX)(CRSS)(f)
For example, if VIN = 48V, IMAX = 2A, CRSS = 300pF (a very
largeMOSFET)andf=100kHz, thetransitionlossis0.7W.
A loss of this magnitude would not only kill efficiency but
would probably require additional heat sinking for the
MOSFET! See Design Example for further guidelines on
how to select the P-channel MOSFET.
2. MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from VIN to ground. The
resulting dQ/dt is a current out of VIN which is typically
much larger than the DC supply current. In continuous
Other losses including CIN and COUT ESR dissipative
losses, Schottkyconductionlossesduringdead-time, and
inductor core losses, generally account for less than 2%
total additional loss.
12
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LTC1149-3.3/LTC1149-5
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LTC1149 Package Dissipation
The same calculations were repeated for a smaller device,
the Motorola MTD2955 (RDS(ON) = 0.3Ω)and alarger one,
the Harris RFP30P05 (RDS(ON) = 0.065Ω). The results are
summarized in the table.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1149 series
to beexceeded. The LTC1149supplycurrentis dominated
by the gate charge supply current, which is given as a
function of operating frequency in the Typical Perfor-
mance Characteristics. The LTC1149 series junction tem-
perature can be estimated by using the equations given in
Note 1 of the Electrical Characteristics. For example, the
LT1149CS is limited to less than 11mA from a 48V supply:
CONDITIONS
P-CHANNEL MOSFET
V
= 24V, V
F = 100kHz, I
= 5V
= 2.5A
IN
OUT
OUT
MTD2955
550mW
110mW
60mW
IRF9Z34
270mW
145mW
85mW
RFP30P05
120mW
290mW
240mW
650mW
2
Est. I R Loss (100°C)
Est. Transition Loss
Est. Gate Charge Loss
Est. Total Loss
720mW
500mW
TJ = 70°C + (11mA)(48V)(110°C/W)
= 128°C exceeds absolute maximum
Forthissetofconditions,themidsizedP-channelMOSFET
actually produces the lowest total losses at IMAX. The
resulting efficiency differences will be even more pro-
nounced at lower output currents. Note that only the I2R
and transition losses are dissipated in the MOSFET; the
gate charge supply current loss is dissipated by the
LTC1149 series.
Topreventthemaximumjunctiontemperaturefrombeing
exceeded, the Pin 2 supply current must be checked in
continuous mode when operating at the maximum VIN.
Design Example
As a design example, assume VIN = 24V, VOUT = 5V,
IMAX = 2.5A and f = 100kHz. RSENSE, CT and L can
immediately be calculated:
Selection of the N-channel MOSFET is somewhat easier; it
need only be sized for the anticipated I2R losses at 100%
duty cycle (worst-case assumption for short circuit.) The
Siliconix Si9410, for example, has RDS(ON) = 0.03Ω Max
and QN = 30nC. This will produce an I2R loss of 250mW at
100°C and a gate charge supply current loss of 75mW. As
withtheP-channeldevice,theuseofalargerMOSFETmay
actually result in lower midcurrent efficiency.
100mV
2.5
R
=
= 0.039Ω
SENSE
–5
(7.8)(10 )
100kHz
5V
24V
C =
1 –
= 620pF
T
)
)
5
CIN will require an RMS current rating of at least 1.25A at
temperature, and COUT will require an ESR of 0.04Ω for
optimum efficiency. The output capacitor ESR require-
mentcanbefulfilledbyasingleOS-CONorbytwoormore
surface mount tantalums in parallel.
L
= (5.1)(10 )(0.039Ω)(620pF)(5V) = 62µH
MIN
Selection of the P-channel MOSFET involves doing calcu-
lations for different sized MOSFETs to determine the
relative loss contributions. Taking an International Recti-
fier IRF9Z34 for example, RDS(ON) = 0.14Ω Max,
QP = 35nC and CRSS = 200pF (VDS = VIN/2). These values
can be used to estimate the I2R losses, transition losses
and gate charge supply current losses:
Auxiliary Windings – Suppressing Burst Mode
Operation
The LTC1149 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.
Est. I2R Loss (TJ = 100°C) =
(5V/24V)(2.5)2(1 + 0.5)0.14Ω = 270mW
Est. Transition Loss =
5(24V)2(2.5A)(200pF)(100kHz) = 145mW
Est. Gate Charge Loss =
(100kHz)(35nC)(24V) = 85mW
Burst Mode operation can be suppressed at low output
currents with a simple external network which cancels the
13
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circuitry. Turning on the N-channel MOSFET when this
fault is detected will then force the system fuse to blow.
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (IOUT > 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE– pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 6. Two 100Ω resistors are
inserted in series with the leads from the sense resistor.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the CT Pin 6 high to when the NGATE Pin 13 goes
high is 250ns. Under shutdown conditions, the N-channel
is held off and pulling Pin 6 high will not cause the output
to be crowbarred.
AsmallN-channelFETcanbeusedasaninterfacebetween
theovervoltagedetectcircuitryandtheLTC1149asshown
in Figure 7.
With the addition of R3, a current is generated through R1
causing an offset of:
R1
V
= V
OUT
OFFSET
)
)
R1 + R3
5
V
C
CC
T
IfV
>25mV, theminimumthresholdwillbecancelled
OFFSET
CROWBAR
VN2222LL
6
LTC1149
and Burst Mode operation is prevented from occurring.
Since VOFFSET is constant, the maximum load current is
also decreased by the same offset. Thus, to get back to the
same IMAX, the value of the sense resistor must be lower:
ACTIVE WHEN CROWBAR = V
IN
OFF WHEN CROWBAR = GROUND
1149 F07
75mV
MAX
Figure 7. Output Crowbar Interface
R
≈
SENSE
I
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 8 and 9.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1149 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 8. Check the following
in your layout:
R
L
SENSE
LTC1149
SENSE
+
R2
C
OUT
100Ω
9
8
+
–
1. Are the signal and power grounds segregated? The
LTC1149signalgroundPin11mustconnectseparately
to the (–) plate of COUT. The other ground Pins 12 and
14shouldreturntothesourceoftheN-channelMOSFET,
anode of the Schottky diode and (–) plate of CIN, which
should have as short lead lengths as possible.
R1
100Ω
1000pF
SENSE
1149 F06
R3
Figure 6. Suppressing Burst Mode Operation
2. Does the LTC1149 SENSE– Pin 8 connect to a point
close to RSENSE and the (+) plate of COUT? In adjustable
applications, the resistive divider R1, R2 must be
connected between the (+) plate of COUT and signal
ground.
3. AretheSENSE– andSENSE+ leadsroutedtogetherwith
minimum PC trace spacing? The differential decou-
pling capacitor between Pins 8 and 9 should be as close
as possible to the LTC1149. Up to 100Ω may be placed
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the timing capacitor Pin 6
above 1.5V when the output voltage is greater than the
desiredregulatedvalue,willturnontheN-channelMOSFET.
A fault condition which causes the output voltage to go
above a maximum value can be detected by external
14
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LTC1149-3.3/LTC1149-5
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+
BOLD LINES INDICATE HIGH CURRENT PATHS
C
IN
1N4148
1N4148
+
P-CHANNEL
V
IN
0.068µF
D1
1µF
+
N-CHANNEL
–
1
2
3
4
5
6
7
8
16
PGATE
CAP
15
SHUTDOWN
V
V
SD2
RGND
NGATE
PGND
SGND
IN
14
13
12
11
10
9
0.047µF
CC
L
PDRIVE
V
CC
C
T
–
100pF
V
/
R1
R2
FB
I
TH
SHDN1
C
OUT
+
V
OUT
C
3300pF
T
–
+
SENSE
SENSE
1k
R
SENSE
1000pF
+
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
1149 F08
Figure 8. LTC1149 Series Layout Diagram (see Layout Checklist)
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 6.
in series with each sense lead to help decouple Pins 8
and 9. However, when these resistors are used, the
capacitor should be no larger than 1000pF.
In continuous mode (ILOAD > IBURST) the voltage on Pin 6
should be a sawtooth with a 0.9VP-P swing. This voltage
should never dip below 2V as shown in Figure 9a.
4. Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? An addi-
tional 0.1µF ceramic capacitor between VIN and power
ground may be required in some applications.
When load currents are low (ILOAD < IBURST) Burst Mode
operation should occur with the CT pin waveform periodi-
cally falling to ground as shown in Figure 9b.
5. Is the VCC decoupling capacitor connected closely
between Pin 5 of the LTC1149 and power ground? This
capacitor carries the MOSFET driver peak currents.
If Pin 6 is observed falling to ground at high output
currents,itindicatespoordecouplingorimproperground-
ing. Refer to the Board Layout Checklist.
6. Is the SHDN1 Pin 10 (fixed output versions only)
actively pulled to ground during normal operation? The
SHDN1 pin is high impedance and must not be allowed
to float. In adjustable versions, Pin 10 is the feedback
pinandisverysensitivetopickupfromtheswitchnode.
Care must be taken to isolate VFB from possible capaci-
tive coupling of the inductor switch signal.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
Troubleshooting Hints
Since efficiency is critical to LTC1149 series applications,
it is very important to verify that the circuit is functioning
0V
1149 F09
(b) Burst Mode OPERATION
Figure 9. CT Pin 6 Waveforms
15
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
V
IN
8V TO 20V
+
1N4148
1N4148
100µF
35V
IRFR9024
L*
68µH
R
**
SENSE
1
0.1Ω
16
V
OUT
PGATE
CAP
SHDN2
R-GND
NGATE
3.3V/1A
0.068µF
2
3
4
5
6
7
8
15
14
13
12
11
10
9
V
V
IN
0.047µF
220µF
6.3V
AVX
+
CC
P-DRIVE
LTC1149-3.3
IRFR024
1N5818
V
C
I
PGND
SGND
CC
T
0V = NORMAL
>2V = SHUTDOWN
SHDN1
+
TH
1µF
390pF
3300pF
–
+
SENSE
SENSE
1k
1000pF
1149 F10
*COILTRONICS CTX02-11932
**DALE WSC-1/2-0.1
Figure 10. High Efficiency 8V to 20V Input 3.3V/1A Output Regulator
V
IN
8V TO 20V
+
1N4148
1N4148
220µF
35V
IRF9Z34
L*
33µH
R
**
SENSE
1
2
3
4
5
6
7
8
0.033Ω
16
V
OUT
PGATE
CAP
SHDN2
RGND
3.3V/3A
0.068µF
15
14
13
12
11
10
9
V
V
IN
0.047µF
220µF
+
CC
6.3V × 2
AVX
PDRIVE
NGATE
IRFZ34
1N5818
LTC1149-3.3
V
C
I
PGND
SGND
CC
T
SHDN1
SHUTDOWN
+
TH
3.3µF
470pF
3300pF
100Ω
100Ω
–
+
SENSE
SENSE
1k
1000pF
1149 F11
*COILTRONICS CTX33-4-KM
**KRL SL-1-C1-0R033J
Figure 11. High Efficiency 8V to 20V Input 3.3V/3A Output Regulator
16
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
V
IN
5.5V TO 25V
+
1N4148
1N4148
220µF
35V
Si9435DY
L*
33µH
R
**
SENSE
1
0.05Ω
16
V
OUT
PGATE
CAP
SHDN2
RGND
5V/2A
0.068µF
2
3
4
5
6
7
8
15
14
13
12
11
10
9
V
V
IN
0.047µF
+
220µF
CC
10V × 2
AVX
PDRIVE
NGATE
Si9410DY
1N5818
LTC1149-5
V
C
I
PGND
S-GND
SHDN1
CC
T
SHUTDOWN
+
TH
1µF
220pF
3300pF
–
+
SENSE
SENSE
1k
1000pF
1149 F12
*COILTRONICS CTX33-4 Kool Mµ
**KRL SL-1-C1-0R050J
Figure 12. Ultra Wide Input Range (5.5V to 25V) High Efficiency 5V Regulator
V
IN
8V TO 16V
+
1N4148
1N4148
100µF
25V
Si9430DY
L*
22µH
R
**
SENSE
0.05Ω
1
2
3
4
5
6
7
8
16
V
OUT
5V/2A
PGATE
CAP
SHDN2
RGND
0.068µF
15
14
13
12
11
10
9
V
V
IN
0.047µF
+
220µF
10V
AVX
CC
PDRIVE
NGATE
Si9410DY
1N5818
LTC1149-5
V
C
I
PGND
SGND
CC
T
SHDN1
SHUTDOWN
+
TH
1µF
180pF
3300pF
–
+
SENSE
SENSE
1k
1000pF
1149 F13
*DALE LPE-6562-220MB
**KRL SL-1-C1-0R050J
Figure 13. 250kHz High Efficiency 12V Input 5V/2A Output Regulator
17
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
V
IN
48V
+
1N4148
1N4148
100µF
100V
0.1µF
MTD2955
L*
68µH
R
**
SENSE
1
2
3
4
5
6
7
8
0.04Ω
16
V
OUT
PGATE
CAP
SHDN2
RGND
5V/2.5A
0.068µF
15
14
13
12
11
10
9
V
V
IN
0.047µF
220µF
+
CC
10V
OS-CON
PDRIVE
NGATE
IRFZ34
MBR380
LTC1149-5
V
C
I
PGND
SGND
CC
T
SHDN1
SHUTDOWN
+
TH
3.3µF
620pF
3300pF
100Ω
100Ω
–
+
SENSE
SENSE
1k
1000pF
1149 F14
*HURRICANE LAB HL-KI168M
**IRC LR2512-01-R040-G
Figure 14. High Efficiency 48V Input 5V/2.5A Output Regulator
V
IN
8V TO 20V
+
1N4148
1N4148
100µF
35V
RFD15P05SM
L*
50µH
R
**
SENSE
V
1
2
3
4
5
6
7
8
0.05Ω
OUT
16
PGATE
CAP
SHDN2
RGND
NGATE
PGND
3.3V/2A
OR 5V/2A
0.068µF
15
14
13
12
11
10
9
SHUTDOWN
V
IN
0.047µF
220µF
+
10V × 2
V
CC
AVX
PDRIVE
RFD14N05SM
1N5818
LTC1149
V
CC
0V: V
5V: V
= 3.3V
= 5V
OUT
OUT
VN2222LL
C
T
SGND
R2
56k
1%
R1A
33k
1%
R1B
43k
1%
100pF
I
V
FB
+
TH
1µF
390pF
3300pF
1k
–
+
SENSE
SENSE
1000pF
1149 F15
*COILTRONICS CTX50-2-MP
**IRC LR2010-01-R050-G
Figure 15. Logic Selectable 5V/2A or 3.3V/2A High Efficiency Regulator
18
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
V
IN
12V TO 36V
1N4148
+
1000µF
63V
220Ω
10k
2N3906
0.1µF
470Ω
VN2222LL
2N2222
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGATE
CAP
MTP30N06EL
L*
R
**
SENSE
50µH
0.02Ω
V
IN
SHDM2
RGND
MUR110
V
OUT
5V/5A
0.1µF
V
CC
+
220µF
10V × 2
OS-CON
PDRIVE
NGATE
IRFZ44
MBR380
LTC1149-5
V
C
I
PGND
SGND
CC
T
0V = NORMAL
>2V = SHUTDOWN
SHDN1
+
TH
3.3µF
820pF
3300pF
1k
100Ω
100Ω
–
+
SENSE
SENSE
1000pF
1149 F16
*COILTRONICS CTX50-5-52
**DALE LVR-3-0.02
SEE APPLICATIONS INFORMATION TO SUPPRESS
Burst ModeTM OPERATION AT LOW CURRENTS
Figure 16. 25W High Efficiency Regulator Using N-Channel MOSFET Switches
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
14
12
10
9
15
13
11
16
0.020
(0.508)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
2
1
3
4
6
8
5
7
0.325
–0.015
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
+0.889
8.255
N16 1197
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1149
LTC1149-3.3/LTC1149-5
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
16
15
14
13
12
11
10
9
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S16 0695
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
U
TYPICAL APPLICATION
V
IN
20V TO 30V
+
1N4148
1N4148
220µF
50V
MTP23P06
L*
100µH
1
16
V
OUT
12V/3A
PGATE
CAP
SHDN2
RGND
NGATE
PGND
0.068µF
2
3
4
5
6
7
8
15
14
13
12
11
10
9
V
V
SHUTDOWN
IN
0.047µF
R2
172k
1%
150µF
+
CC
16V × 2
OS-CON
PDRIVE
LTC1149
MTP36N06E
MBR160
V
C
I
CC
SGND
R1
20k
1%
T
R
**
SENSE
0.033Ω
100pF
V
FB
+
TH
3.3µF
300pF
3300pF
100Ω
100Ω
–
+
SENSE
SENSE
OUTPUT
GROUND
CONNECTION
1k
1000pF
1149 F17
*HURRICANE LAB HL-EK210M
**KRL SL-1-C1-0R033J
Figure 17. High Efficiency 24V Input 12V/3A Output Regulator
RELATED PARTS
PART NUMBER
LTC1148HV
LTC1159
DESCRIPTION
COMMENTS
4V < V < 20V
High Efficiency, Synchronous Step-Down Switching Regulator
High Efficiency, Synchronous Step-Down Switching Regulator
High Efficiency, Low Noise, Synchronous Switching Regulator
Dual, Low Noise, Synchronous Switching Regulator
IN
4V < V < 40V, I
= 20µA
IN
SHUTDOWN
LTC1435A
LTC1438
3.5V < V < 36V, N-Channel Driver
IN
3.5V < V < 36V, N-Channel Driver
IN
1149fa LT/TP 0898 REV A 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1993
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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