LTC1150CJ [Linear]
IC OP-AMP, 5 uV OFFSET-MAX, 2.5 MHz BAND WIDTH, CDIP14, CERDIP-14, Operational Amplifier;
| 型号： | LTC1150CJ |
| 厂家： | 
Linear |
| 描述： | IC OP-AMP, 5 uV OFFSET-MAX, 2.5 MHz BAND WIDTH, CDIP14, CERDIP-14, Operational Amplifier 运算放大器 |
| 文件： | 总16页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1150
±15V Zero-Drift
Operational Amplifier with
Internal Capacitors
U
FEATURES
DESCRIPTIO
The LTC®1150 is a high-voltage, high-performance
zero-drift operational amplifier. The two sample-and-hold
capacitors usually required externally by other chopper
amplifiers are integrated on-chip. Further, LTC’s propri-
etary high-voltage CMOS structures allow the LTC1150 to
operate at up to 32V total supply voltage.
■
High Voltage Operation: ±16V
■
No External Components Required
■
Maximum Offset Voltage: 10µV
■
Maximum Offset Voltage Drift: 0.05µV/°C
■
Low Noise 1.8µVP-P (0.1Hz to 10Hz)
■
Minimum Voltage Gain: 135dB
■
Minimum PSRR: 120dB
The LTC1150 has an offset voltage of 0.5µV, drift of
0.01µV/°C, 0.1Hz to 10Hz input noise voltage of 1.8µVP-P
and a typical voltage gain of 180dB. The slew rate of 3V/µs
andagainbandwidthproductof2.5MHzareachievedwith
0.8mA of supply current. Overload recovery times from
positive and negative saturation conditions are 3ms and
20ms, respectively.
■
Minimum CMRR: 110dB
■
Low Supply Current: 0.8mA
■
Single Supply Operation: 4.75V to 32V
■
Input Common Mode Range Includes Ground
■
200µA Supply Current with Pin 1 Grounded
■
Typical Overload Recovery Time 20ms
U
For applications demanding low power consumption,
Pin 1 can be used to program the supply current. Pin 5 is
an optional AC-coupled clock input, useful for
synchronization.
APPLICATIO S
■
Strain Gauge Amplifiers
■
Electronic Scales
■
Medical Instrumentation
The LTC1150 is available in standard 8-lead, plastic dual-
in-line package, as well as an 8-lead SO package. The
LTC1150 can be a plug-in replacement for most standard
bipolar op amps with significant improvement in DC
■
Thermocouple Amplifiers
■
High Resolution Data Acquisition
performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Single Supply Instrumentation Amplifier
Noise Spectrum
160
1k
140
120
100
80
1M
+
V
+
V
1M
2
3
7
–
1k
6
2
3
7
LTC1150
–
60
6
–V
LTC1150
V
+
IN
OUT
GAIN = 1000V/V
4
40
V
+
IN
4
OUTPUT OFFSET ≤ 5mV
TOTAL SUPPLY CURRENT
DECREASES TO 400µA
WHEN BOTH PIN 1s ARE
GROUNDED
20
0
10
100
1k
10k
100k
LTC1150 •TA01
FREQUENCY (Hz)
LTC1150 •TA02
1150fb
1
LTC1150
W W
U W
ABSOLUTE AXI U RATI GS
(Note 1)
Total Supply Voltage (V+ to V–) ............................... 32V
Input Voltage (Note 2) .............. (V+ 0.3V) to (V– –0.3V)
Output Short Circuit Duration .......................... Indefinite
Burn-In Voltage ....................................................... 32V
Operating Temperature Range
LTC1150M (OBSOLETE).....................–55°C to 125°C
LTC1150C .......................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
I
1
2
3
4
CLOCK OUT
8
7
6
5
SUPPLY
–IN
NUMBER
TOP VIEW
+
V
LTC1150CN8
LTC1150CS8
I
1
2
3
4
8
7
6
5
CLOCK OUT
SUPPLY
–IN
+IN
OUT
EXT CLOCK
IN
+
–
V
–
+
V
+IN
OUT
N8 PACKAGE
8-LEAD PDIP
–
EXT CLOCK
IN
V
S8 PART
MARKING
T
= 110°C, θ = 130°C/W
JMAX
JA
S8 PACKAGE
8-LEAD PLASTIC SO
= 110°C, θ = 200°C/W
JA
J8 PACKAGE
8-LEAD CERDIP
LTC1150MJ8
LTC1150CJ8
T
JMAX
1150
OBSOLETE PACKAGE
Consider the N8 or S8 Package as an Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ■ denotes the specifications which apply over the full operating
temperature range otherwise specifications are at TA = 25°C. VS = ±15V, Pin 1 = Open, unless otherwise noted.
LTC1150M
TYP
LTC1150C
TYP MAX UNITS
PARAMETER
CONDITIONS
(Note 3)
MIN
MAX
MIN
Input Offset Voltage
Average Input Offset Drift
Long Term Offset Voltage Drift
Input Offset Current
±0.5
±10
±0.5
±10
µV
µV/°C
(Note 3)
■
±0.01 ±0.05
±0.01 ±0.05
50
50
nV/√mo
±20
±60
±1.5
±20
±200
±0.5
pA
nA
■
■
Input Bias Current
Input Noise Voltage
±10
±50
±2.5
±10
±100
±1.0
pA
nA
RS = 100Ω, 0.1Hz to 10Hz, TC2
RS = 100Ω, 0.1Hz to 1Hz, TC2
f = 10Hz (Note 4)
1.8
0.6
1.8
0.6
µVP-P
Input Noise Current
1.8
1.8
fA/√Hz
dB
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Maximum Output Voltage Swing
VCM = V– to 12V
■
■
■
110
120
135
130
145
180
110
120
135
130
145
180
VS = ±2.375V to ±16V
RL = 10kΩ, VOUT = ±10V
RL = 10kΩ
dB
dB
±13.5 ±14.5
±13.5 ±14.5
V
RL = 10kΩ
■
10.5/
–13.5
10.5/
–13.5
RL = 100kΩ
±14.95
±14.95
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2
LTC1150
ELECTRICAL CHARACTERISTICS
The ■ denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, Pin 1 = Open, unless otherwise noted.
LTC1150M
TYP
LTC1150C
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX UNITS
V/µs
Slew Rate
RL = 10kΩ, CL = 50pF
3
3
Gain Bandwidth Product
Supply Current
2.5
2.5
MHz
No Load
0.8
0.2
1.5
2
0.8
0.2
1.5
2
mA
No Load, Pin 1 = V–
No Load
■
Internal Sampling Frequency
550
550
Hz
The ■ denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VS = 5V, Pin 1 = Open, unless otherwise noted.
LTC1150M
TYP
LTC1150C
TYP MAX UNITS
PARAMETER
CONDITIONS
(Note 3)
MIN
MAX
MIN
Input Offset Voltage
Average Input Offset Drift
Long Term Offset Voltage Drift
Input Offset Current
Input Bias Current
±0.5
±10
±0.05
±10
µV
µV/°C
µV/√mo
pA
(Note 3)
■
±0.01 ±0.05
±0.01 ±0.05
50
50
±10
±5
±60
±30
±10
±5
±60
±30
pA
Input Noise Voltage
RS = 100Ω, 0.1Hz to 10Hz, TC2
RS = 100Ω, 0.1Hz to 1Hz, TC2
2.0
0.7
2.0
0.7
µVP-P
Input Noise Current
f = 10Hz (Note 4)
1.3
130
145
180
1.3
130
145
180
fA/√Hz
dB
Common Mode Rejection Ratio VCM = 0V to 2.7V
■
■
■
106
120
115
106
120
115
Power Supply Rejection Ratio
Large-Signal Voltage Gain
VS = ±2.375V to ±16V
dB
RL = 10kΩ, VOUT = 0.3V to 4.5V
dB
Maximum Output Voltage Swing RL = 10kΩ
RL = 100kΩ
0.15 to 4.85
0.02 to 4.97
0.15 to 4.85
0.02 to 4.97
V
Slew Rate
RL = 10kΩ, CL = 50pF
1.5
1.8
0.4
1.5
1.8
0.4
V/µs
MHz
mA
Gain Bandwidth Product
Supply Current
No Load
1
1
■
1.5
1.5
Internal Sampling Frequency
300
300
Hz
Note 1: Absolute Maximum Ratings are those values beyond which life of
Note 3: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high-speed automatic test
the device may be impaired.
+
systems. V is measured to a limit determined by test equipment
Note 2: Connecting any terminal to voltages greater than V or less than
OS
–
capability.
V may cause destructive latch-up. It is recommended that no sources
operating from external supplies be applied prior to power-up of the
Note 4: Current Noise is calculated from the formula:
LTC1150.
I = √(2q • I )
where q = 1.6 • 10
N
b
–19
Coulomb.
1150fb
3
LTC1150
TEST CIRCUITS
Offset Voltage Test Circuit
DC-10Hz Noise Test Circuit
475k
1M
+
100k
V
1k
0.1µF
2
3
7
–
6
10Ω
LTC1150
OUTPUT
–
158k
316k
475k
+
LTC1150
–
R
4
L
TO X-Y
RECORDER
LT1012
+
–
V
0.1µF
0.1µF
+
LTC1150 •TC01
FOR 1Hz NOISE BW, INCREASE ALL THE CAPACITORS BY A FACTOR OF 10
LTC1150 •TC02
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
Supply Current vs Temperature
Gain/Phase vs Frequency
1400
1200
1000
800
120
100
80
60
1000
900
800
700
600
500
400
300
200
V
= ± 15V
V
C
= ± 15V
T
= 25°C
S
S
L
A
= 100pF
80
PHASE
100
120
140
160
180
200
GAIN
60
40
20
600
0
400
–20
–40
200
220
–55
5
35
65
95
125
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
20 24
–25
4
8
12 16
28 32 36
–
+
AMBIENT TEMPERATURE (°C)
TOTAL SUPPLY VOLTAGE, V TO V (V)
LTC1150 • TPC02
LTC1150 • TPC01
LTC1150 • TPC03
Output Short-Circuit Current vs
Supply Voltage
Supply Current vs RSET
Gain/Phase vs Frequency
1200
1000
800
600
400
200
0
120
100
80
60
6
4
V
T
= ± 15V
= 25°C
T
= 25°C
V
S
= ± 15V
S
A
–
A
V
= V
OUT
C
L
= 100pF
80
I
SOURCE
PIN 1 = –15V
PIN 1 = OPEN
100
120
140
160
180
200
220
2
–
PHASE
PIN 1 = V
60
0
GAIN
–3
–6
–9
–12
–15
40
20
–
PIN 1 = V
+
V
= V
0
OUT
I
SINK
–20
–40
PIN 1 = OPEN
1k
10k
100k
–
1M
20 24
+
4
8
12 16
28 32 36
–
100
1k
10k
100k
1M
10M
R
, PIN 1 TO V (Ω)
FREQUENCY (Hz)
TOTAL SUPPLY VOLTAGE, V TO V (V)
SET
LTC1150 • TPC04
LTC1150 • TPC05
LTC1150 • TPC06
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4
LTC1150
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs Supply
Voltage
Undistorted Output Swing vs
Frequency
Gain/Phase vs Frequency
30
120
100
80
60
12
10
8
V
C
= ±2.5V
= 100pF
T
= 25°C
CM
S
L
A
V
= OV
80
25
20
–
PHASE
PIN 1 = V
L
100
120
140
160
180
200
220
R
= 10k
GAIN
60
6
40
15
10
PIN 1 = FLOATING
= 100k
R
20
L
4
0
2
5
0
–20
–40
0
±10 ±12
0
± 2 ± 4 ± 6 ± 8
±14 ±16
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
FREQUENCY (Hz)
LTC1150 • TPC07
LTC1150 • TPC09
LTC1150 • TPC08
Input Bias Current vs Input
Common Mode Voltage
Common Mode Input Range vs
Supply Voltage
Input Bias Current vs Temperature
–1000
–100
15
10
5
40
30
20
10
V
S
A
= ± 15V
= 25°C
V
V
= 0
CM
= ± 15V
S
T
= 25°C
A
T
–I
B
0
0
–I
B
+I
B
–10
–10
–5
–10
–15
+I
B
–20
–30
–40
–1
–50 –25
0
25
50
75 100 125
0
±5
±7.5 ±10 ±12.5 ±15
±2.5
5
–15 –10
–5
10
15
0
SUPPLY VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
LTC1150 • TPC11
LTC1150 • TPC12
LTC1150 • TPC10
Offset Voltage vs
Sampling Frequency
CMRR vs Frequency
PSRR vs Frequency
160
140
120
100
80
160
140
120
100
80
10
V
T
= ± 15V
= 25°C
POSITIVE SUPPLY, PIN 1 = OPEN
A
A
8
6
–
PIN 1 = V
POSITIVE SUPPLY,
–
PIN 1 = V
4
60
60
NEGATIVE SUPPLY,
PIN 1 = OPEN
PIN 1 = OPEN
40
40
2
0
–
NEGATIVE SUPPLY, PIN 1 = V
20
20
0
0
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
0
2k
SAMPLING FREQUENCY, f (Hz)
3k
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
S
LTC1150 • TPC13
LTC1150 • TPC14
LTC1150 • TPC15
1150fb
5
LTC1150
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage Drift vs Sampling
Frequency
10Hz p-p Noise vs Sampling
Frequency
Sampling Frequency vs
Temperature
900
800
700
600
500
400
300
100
90
80
70
60
50
40
30
20
10
0
4
3
2
1
0
V
= ± 15V
V
= ± 15V
V
= ± 15V
= 25°C
S
S
S
A
T
PIN 1 = OPEN
–55
5
35
65
95
125
100
1k
SAMPLING FREQUENCY, f (Hz)
10k
–25
100
1k
SAMPLING FREQUENCY, f (Hz)
10k
AMBIENT TEMPERATURE (°C)
S
S
LTC1150 • TPC16
LTC1150 • TPC18
LTC1150 • TPC17
Large-Signal Transient Response,
Pin 1 = V–
Large-Signal Transient Response
Small-Signal Transient Response
VS = ±15V, AV = 1, CL = 100pF, RL = 10kΩ
VS = ±15V, AV = 1, CL = 100pF, PIN 1 = V–
VS = ±15V, AV = 1, CL = 100pF, RL = 10kΩ
Small-Signal Transient Response,
Pin 1 = V–
Overload Recovery from Negative
Saturation
Overload Recovery from Positive
Saturation
VS = ±15V, AV = 1, CL = 100pF, RL = 10kΩ,
VS = ±15V, AV = –100, 2ms/DIV
VS = ±15V, AV = –100, 2ms/DIV
PIN 1 = V–
1150fb
6
LTC1150
U W
TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Noise, V = ±15V, TA = 25°C, Internal Clock
2.0µV
P-P
1µV
10s
LTC1150 • TPC25
1s
0.1Hz to 10Hz Noise, V = ±15V, TA = 25°C, fS = 1800Hz
1.0µV
P-P
1µV
10s
LTC1150 • TPC26
1s
0.1Hz to 1Hz Noise, V = ±15V, TA = 25°C, Internal Clock
700nV
P-P
500nV
100s
LTC1150 • TPC27
10s
1150fb
7
LTC1150
U W
TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 1Hz Noise, V = ±15V, TA = 25°C, fS = 1800Hz
300nV
P-P
500nV
100s
LTC1150 • TPC28
10s
U
U
PI DESCRIPTIO S 8-Pin Packages
ISUPPLY (Pin 1): Supply Current Programming. The sup-
ply current can be programmed through Pin 1. When
Pin 1 is left open or tied to V+, the supply current defaults
to 800µA. Tying a resistor between Pin 1 and Pin 4, the
negative supply pin, will reduce the supply current. The
supply current, as a function of the resistor value, is
shown in Typical Performance Characteristics.
simplified interface requirements. The amplitude of the
clock input signal needs to be greater than 2V and the
voltage level has to be within the supply voltage range.
Duty cycle is not critical. The internal chopping frequency
is the external clock frequency divided by four. When
frequency of the external clock falls below 100Hz (internal
chopping at 25Hz), the internal oscillator takes over and
the circuit chops at 550Hz.
–IN (Pin 2): Inverting Input.
+IN (Pin 3): Noninverting Input.
V– (Pin 4): Negative Supply.
OUT (Pin 6): Output.
V+ (Pin 7): Positive Supply.
CLOCK OUT (Pin 8): Clock Output. The signal coming out
of this pin is at the internal oscillator frequency of about
2.2kHz (four times the chopping frequency) and has
voltage levels at VH = VS and VL = VS –4.6. If the circuit is
driven by an external clock, Pin 8 is pulled up to VS.
EXTCLOCKIN(Pin5):OptionalExternalClockInput. The
LTC1150 has an internal oscillator to control the circuit
operation of the amplifier if Pin 5 is left open or biased at
any DC voltage in the supply voltage range. When an
external clock is desirable, it can be applied to Pin 5. The
applied clock is AC-coupled to the internal circuitry to
1150fb
8
LTC1150
W U U
APPLICATIO S I FOR ATIO
U
ACHIEVING PICOAMPERE/MICROVOLT
PERFORMANCE
number of junctions in the amplifier’s input signal path.
Avoid connectors, sockets, switches, and relays where
possible. In instances where this is not possible, attempt
to balance the number and type of junctions so that
differential cancellation occurs. Doing this may involve
deliberately introducing junctions to offset unavoidable
junctions.
Picoamperes
In order to realize the picoampere level of accuracy of the
LTC1150, proper care must be exercised. Leakage cur-
rentsincircuitryexternaltotheamplifiercansignificantly
degrade performance. High quality insulation should be
used (e.g., Teflon, Kel-F); cleaning of all insulating sur-
faces to remove fluxes and other residues will probably
be necessary–particularly for high temperature perfor-
mance. Surface coating may be necessary to provide a
moisture barrier in high humidity environments.
Figure 1 is an example of the introduction of an unneces-
sary resistor to promote differential thermal balance.
Maintaining compensating junctions in close physical
proximity will keep them at the same temperature and
reduce thermal EMF errors.
NOMINALLY UNNECESSARY
Board leakage can be minimized by encircling the input
connections with a guard ring operated at a potential
close to that of the inputs: in inverting configurations the
guard ring should be tied to ground; in noninverting
connections to the inverting input. Guarding both sides
of the printed circuit board is required. Bulk leakage
reduction depends on the guard ring width.
LEAD WIRE/SOLDER
RESISTOR USED TO
THERMALLY BALANCE
OTHER INPUT RESISTOR
COPPER TRACE JUNCTION
+
LTC1150
OUTPUT
–
RESISTOR LEAD, SOLDER,
COPPER TRACE JUNCTION
Microvolts
ThermocoupleeffectsmustbeconsiderediftheLTC1150’s
ultralow drift is to be fully utilized. Any connection of
dissimilarmetalsformsathermoelectricjunctionproduc-
ing an electric potential which varies with temperature
(Seebeckeffect).Astemperaturesensors,thermocouples
exploit this phenomenon to produce useful information.
Inlowdriftamplifiercircuitstheeffectisaprimarysource
of error.
LTC1150 •AI01
Figure 1. Extra Resistors Cancel Thermal EMF
When connectors, switches, relays and/or sockets are
necessary, they should be selected for low thermal EMF
activity. The same techniques of thermally-balancing and
coupling the matching junctions are effective in reducing
the thermal EMF errors of these components.
Connectors, switches, relay contacts, sockets, resistors,
solder, and even copper wire are all candidates for
thermal EMF generation. Junctions of copper wire from
different manufacturers can generate thermal EMFs of
200nV/°C—four times the maximum drift specification
oftheLTC1150.Thecopper/kovarjunction,formedwhen
wire or printed circuit traces contact a package lead, has
athermalEMFofapproximately35µV/°C—700timesthe
maximum drift specification of the LTC1150.
Resistors are another source of thermal EMF errors.
Table 1 shows the thermal EMF generated for different
resistors. The temperature gradient across the resistor is
important, not the ambient temperature. There are two
junctions formed at each end of the resistor and if these
junctions are at the same temperature, their thermal EMFs
will cancel each other. The thermal EMF numbers are
approximate and vary with resistor value. High values give
higher thermal EMF.
Minimizing thermal EMF-induced errors is possible if
judicious attention is given to circuit board layout and
component selection. It is good practice to minimize the
1150fb
9
LTC1150
W U U
U
APPLICATIO S I FOR ATIO
Table 1. Resistor Thermal EMF
LEVEL SHIFTING THE CLOCK
RESISTOR TYPE
Tin Oxide
THERMAL EMF/°C GRADIENT
Level shifting is needed if the clock output of the LTC1150
in ±15V operation must interface to regular 5V logic
circuits. Figures 2 and 3 show some typical level shifting
circuits.
~mV/°C
~450µV/°C
~20µV/°C
Carbon Composition
Metal Film
WireWound
Evenohm
Manganin
When operated from single 5V or ±5V supplies, the
LTC1150 clock output at Pin 8 can interface to TTL or
CMOS inputs directly.
~2µV/°C
~2µV/°C
PACKAGE-INDUCED OFFSET VOLTAGE
LOW SUPPLY OPERATION
Package-induced thermal EMF effects are another impor-
tant source of errors. It arises at the copper/kovar
junctions formed when wire or printed circuit traces
contact a package lead. Like all the previously mentioned
thermal EMF effects, it is outside the LTC1150’s offset
nulling loop and cannot be cancelled. Metal can
H packages exhibit the worst warm-up drift. The input
offset voltage specification of the LTC1150 is actually set
by the package-induced warm-up drift rather than by the
circuit itself. The thermal time constant ranges from 0.5 to
3 minutes, depending on package type.
The minimum supply for proper operation of the LTC1150
is typically below 4.0V (±2.0V). In single supply applica-
tions, PSRR is guaranteed down to 4.7V (±2.35V)
to ensure proper operation down to the minimum TTL
specified voltage of 4.75V.
15V
10k
7
5V
2
3
–
8
6
LTC1150
ALIASING
LOGIC
CIRCUIT
+
4
Like all sampled data systems, the LTC1150 exhibits
aliasing behavior at input frequencies near the sampling
frequency. The LTC1150 includes a high-frequency
correction loop which minimizes this effect; as a result,
aliasing is not a problem for most applications.
10k
–15V
LTC1150 • AI02
Figure 2. Output Level Shift (Option 1)
For a complete discussion of the correction circuitry and
aliasing behavior, please refer to the LTC1051/53 data
sheet.
5V
5V
15V
100pF
6
10k
SYNCHRONIZATION OF MULTIPLE LTC115O’S
7
2
3
–
LOGIC
CIRCUIT
8
When synchronization of several LTC1150’s is required,
one of the LTC1150’s can be used to provide the “master”
clock to control over 100 “slave” LTC1150’s. The master
clock, coming from Pin 8 of the master LTC1150, can
directlydrivePin5oftheslaves.NotethatPin8oftheslave
LTC1150’s will be pulled up to VS.
LTC1150
+
4
10k
–15V
LTC1150 • AI03
GND
Figure 3. Output Level Shift (Option 2)
IfalltheLTC1150’saretobesynchronizedwithanexternal
clock, then the external clock should drive Pin 5 of all the
LTC1150’s.
1150fb
10
LTC1150
U
TYPICAL APPLICATIO S
Low Level Photodetector
15pF
1M
10Ω
+
HP 5082-4204
V
10k
7
2
3
–
6
9
OUTPUT = I • 10 Ω
P
LTC1150
I
P
+
4
LTC1150 • TA03
Ground Force Reference
1k
15V
15V
1000pF
7
2
3
–
6
LTC1150
LT1010
+
4
SINGLE
POINT
FORCED
GROUND
–15V
–15V
SENSE
GROUND
LTC1150 • TA04
APPLICATION: TO FORCE TWO GROUND POINTS IN A SYSTEM WITHIN 5µV
1150fb
11
LTC1150
U
TYPICAL APPLICATIO S
Paralleling to Improve Noise
CLK IN
10k
MEASURED NOISE
V
= 1.1µV
OS
10Ω
10Ω
10Ω
CLK
FREE
RUN
–
10Hz = 700nV
1Hz = 200nV
P-P
P-P
10k
LTC1150
V
= 10µV
OS
CLK
DRIVEN
1800Hz
+
10Hz = 360nV
1Hz = 160nV
P-P
P-P
10k
–
10k
10k
10k
25k
LTC1150
+
10k
–
LTC1150
–
V
= 10k V
IN
OUT
LTC1150
+
+
IN
10k
10Ω
–
LTC1150
+
LTC1150 • TA05
Battery Discharge Monitor
OPEN AT t = 0
C
+
R2
2
–
6
LTC1150
3
+
–IR1
V
=
t
OUT
R2C
5µV 30pA R2
ERROR ≤
+
I
IR1
I
R1
R1
LOAD
LTC1150 • TA06
1150fb
12
LTC1150
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.405
(10.287)
MAX
CORNER LEADS OPTION
(4 PLCS)
.005
(0.127)
MIN
6
5
4
8
7
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
.025
.220 – .310
(5.588 – 7.874)
.045 – .068
(0.635)
RAD TYP
(1.143 – 1.650)
FULL LEAD
OPTION
1
2
3
.200
(5.080)
MAX
.300 BSC
(7.62 BSC)
.015 – .060
(0.381 – 1.524)
.008 – .018
(0.203 – 0.457)
0° – 15°
.045 – .065
(1.143 – 1.651)
.125
3.175
MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.014 – .026
(0.360 – 0.660)
.100
(2.54)
BSC
J8 0801
OBSOLETE PACKAGE
1150fb
13
LTC1150
U
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
4
.255 ± .015*
(6.477 ± 0.381)
1
2
3
.130 ± .005
.300 – .325
.045 – .065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
.325
–.015
.018 ± .003
(0.457 ± 0.076)
.100
(2.54)
BSC
+0.889
8.255
(
)
N8 1002
–0.381
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1150fb
14
LTC1150
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 ±.005
NOTE 3
.050 BSC
N
7
5
8
6
N
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
2
3
N/2
N/2
4
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
1
3
2
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0502
1150fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1150
U
TYPICAL APPLICATIO
DC Stabilized, Low Noise Amplifier
15V
3
2
7
INPUT
+
6
LTC1150
–
4
–15V
0.01µF
15V
130Ω
68Ω
1
15V
3
7
+
8
6
LT1028
OUTPUT
100k
2
–
4
10k
–15V
(A = 1000)
10Ω
LTC1150 • TA07
1150fb
LW/TP 1202 1K REV B • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
■
■
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 1991
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