LTC1198-1BCS8 [Linear]
8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options; 8位， SO - 8 ， 1MSPS ADC，具有自动关机选项
| 型号： | LTC1198-1BCS8 |
| 厂家： | 
Linear |
| 描述： | 8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options |
| 文件： | 总28页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1196/LTC1198
8-Bit, SO-8, 1MSPS ADCs with
Auto-Shutdown Options
U
DESCRIPTIO
EATURE
High Sampling Rates: 1MHz (LTC1196)
750kHz (LTC1198)
Low Cost
SO-8 Plastic Package
Single Supply 3V and 5V Specifications
Low Power: 10mW at 3V Supply
50mW at 5V Supply
Auto-Shutdown: 1nA Typical (LTC1198)
±1/2LSB Total Unadjusted Error over Temperature
3-Wire Serial I/O
1V to 5V Input Span Range (LTC1196)
Converts 1MHz Inputs to 7 Effective Bits
Differential Inputs (LTC1196)
2-Channel MUX (LTC1198)
S
F
■
The LTC1196/LTC1198 are 600ns, 8-bit A/D converters
with sampling rates up to 1MHz. They are offered in 8-pin
SO packages and operate on 3V to 6V supplies. Power
dissipation is only 10mW with a 3V supply or 50mW with
a 5V supply. The LTC1198 automatically powers down to
a typical supply current of 1nA whenever it is not perform-
ing conversions. These 8-bit switched-capacitor succes-
sive approximation ADCs include sample-and-holds. The
LTC1196 has a differential analog input; the LTC1198
offers a software selectable 2-channel MUX.
■
■
■
■
■
■
■
■
■
■
■
The 3-wire serial I/O, SO-8 packages, 3V operation and
extremely high sample rate-to-power ratio make these
ADCs an ideal choice for compact, high speed systems.
TheseADCscanbeusedinratiometricapplicationsorwith
external references. The high impedance analog inputs
and the ability to operate with reduced spans below 1V full
scale (LTC1196) allow direct connection to signal sources
in many applications, eliminating the need for gain stages.
O U
PPLICATI
S
A
■
■
■
■
High Speed Data Acquisition
Disk Drives
Portable or Compact Instrumentation
Low Power or Battery-Operated Systems
The A grade devices are specified with total unadjusted
error of ±1/2LSB maximum over temperature.
U
O
TYPICAL APPLICATI
Single 5V Supply, 1MSPS, 8-Bit Sampling ADC
Effective Bits and S/(N + D) vs Input Frequency
8
7
6
5
4
3
2
1
0
50
44
1µF
5V
V
= V = 2.7V
CC
REF
f
f
= 383kHz (LTC1196)
= 287kHz (LTC1198)
SMPL
SMPL
V
= V = 5V
CC
REF
f
= 1MHz (LTC1196)
1
2
3
4
8
7
6
5
SMPL
CS
V
CC
f
= 750kHz (LTC1198)
SMPL
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP,
OR SHIFT REGISTERS
+IN LTC1196 CLK
(SO-8)
ANALOG INPUT
0V TO 5V RANGE
–IN
D
OUT
GND
V
REF
1196/98 TA01
T
= 25°C
A
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
1196/98 G24
1
LTC1196/LTC1198
W W W
U
ABSOLUTE AXI U RATI GS (Notes 1, 2)
Supply Voltage (VCC) to GND.................................... 7V
Voltage
Analog Reference ...................... –0.3V to VCC + 0.3V
Digital Inputs.......................................... –0.3V to 7V
Digital Outputs .......................... –0.3V to VCC + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1196-1AC, LTC1198-1AC, LTC1196-1BC,
LTC1198-1BC, LTC1196-2AC, LTC1198-2AC,
LTC1196-2BC, LTC1198-2BC................ 0°C to 70°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
NUMBER*
ORDER PART
NUMBER*
TOP VIEW
TOP VIEW
CS/
SHUTDOWN
CH0
LTC1196-1ACS8
LTC1198-1ACS8
1
2
3
4
8
7
6
5
(V
)
V
1
2
3
4
8
7
6
5
V
CS
+IN
CC REF
CC
LTC1196-1BCS8
LTC1196-2ACS8
LTC1196-2BCS8
LTC1198-1BCS8
LTC1198-2ACS8
LTC1198-2BCS8
CLK
D
CLK
D
CH1
GND
–IN
OUT
OUT
D
V
REF
GND
IN
S8 PACKAGE
8-LEAD PLASTIC SOIC
S8 PACKAGE
8-LEAD PLASTIC SOIC
S8 PART MARKING
S8 PART MARKING
1981A
1981B
1982A
1982B
1961A
1961B
1962A
1962B
TJMAX = 150°C, θJA = 175°C/W
TJMAX = 150°C, θJA = 175°C/W
*Parts available in N8 package. Consult factory for N8 samples.
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
V
Supply Voltage
= 5V Operation
2.7
6
2.7
6
V
CC
CC
V
f
Clock Frequency
0.01
0.01
14.4
12.0
0.01
0.01
12.0
9.6
MHz
MHz
CLK
●
t
Total Cycle Time
LTC1196
LTC1198
12
16
12
16
CLK
CLK
CYC
t
t
t
Analog Input Sampling Time
2.5
10
20
2.5
13
26
CLK
ns
SMPL
hCS
Hold Time CS Low After Last CLK↑
Setup Time CS↓ Before First CLK↑
(See Figures 1, 2)
ns
suCS
t
Hold Time D After CLK↑
LTC1198
20
26
ns
hDI
IN
2
LTC1196/LTC1198
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
t
t
t
t
t
Setup Time D Stable Before CLK↑
LTC1198
20
40%
40%
25
26
40%
40%
32
ns
suDI
IN
CLK High Time
f
f
= f
= f
1/f
1/f
WHCLK
WLCLK
WHCS
WLCS
CLK
CLK
CLK(MAX)
CLK(MAX)
CLK
CLK Low Time
CLK
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
ns
LTC1196
LTC1198
11
15
11
15
CLK
CLK
U
U W
CO VERTER A D ULTIPLEXER CHARACTERISTICS
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196-XA
LTC1198-XA
LTC1196-XB
LTC1198-XB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
Bits
No Missing Codes Resolution
Offset Error
●
●
●
●
●
8
8
±1/2
±1/2
±1/2
±1/2
±1
±1
±1
±1
LSB
LSB
LSB
LSB
Linearity Error
(Note 3)
Full-Scale Error
Total Unadjusted Error (Note 4)
LTC1196, V
= 5.000V
REF
CC
LTC1198, V = 5.000V
–0.05V to V + 0.05V
Analog and REF Input Range
Analog Input Leakage Current
LTC1196
(Note 5)
V
CC
●
±1
±1
µA
U
D
A
ELECTRICAL CHARACTERISTICS
DC
DIGITAL
VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.0
IH
IL
CC
CC
IN
0.8
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
V
V
= 4.75V, I = 10µA
= 4.75V, I = 360µA
●
●
4.5
2.4
4.74
4.71
V
V
OH
CC
CC
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
V
= 4.75V, I = 1.6mA
●
●
0.4
V
µA
OL
CC
O
I
I
I
I
CS = High
±3
OZ
Output Source Current
Output Sink Current
V
V
= 0V
–25
45
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
Reference Current, LTC1196
CS = V
●
●
0.001
0.5
3
1
µA
mA
REF
CC
f
= f
SMPL(MAX)
SMPL
I
Supply Current
CS = V , LTC1198 (Shutdown)
●
●
●
0.001
7
11
3
15
20
µA
mA
mA
CC
CC
CS = V , LTC1196
CC
f
= f
LTC1196/LTC1198
SMPL
SMPL(MAX),
3
LTC1196/LTC1198
U W
DY A IC ACCURACY
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196
TYP
LTC1198
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
47/45
49/47
55/48
51
MAX
UNITS
dB
S/(N + D) Signal-to-Noise Plus Distortion
500kHz/1MHz Input Signal
500kHz/1MHz Input Signal
500kHz/1MHz Input Signal
47/45
49/47
55/48
51
THD
IMD
Total Harmonic Distortion
dB
Peak Harmonic or Spurious Noise
Intermodulation Distortion
dB
f
f
= 499.37kHz,
= 502.446kHz
dB
IN1
IN2
Full Power Bandwidth
8
1
8
1
MHz
MHz
Full Linear Bandwidth [S/(N + D) > 44dB]
AC CHARACTERISTICS
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
t
Conversion Time (See Figures 1, 2)
600
710
710
900
ns
ns
CONV
●
f
Maximum Sampling Frequency
LTC1196
LTC1196
LTC1198
LTC1198
1.20
1.00
0.90
0.75
1.00
0.80
0.75
0.60
MHz
MHz
MHz
MHz
SMPL(MAX)
●
●
t
Delay Time, CLK↑ to D
Data Valid
C
= 20pF
55
64
73
68
78
94
ns
ns
dDO
OUT
LOAD
●
●
●
●
t
t
t
Delay Time CS↑ to D
Hi-Z
70
30
45
120
50
88
43
55
150
63
ns
ns
ns
DIS
en
OUT
Delay Time, CLK↓ to D
Enabled
C
C
= 20pF
= 20pF
OUT
LOAD
LOAD
Time Output Data Remains Valid
30
30
hDO
After CLK↑
t
t
D
D
Fall Time
C
C
= 20pF
= 20pF
●
●
5
5
15
15
10
10
20
20
ns
ns
r
f
OUT
OUT
LOAD
LOAD
Rise Time
C
IN
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
30
5
5
30
5
5
pF
pF
pF
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
VCC = 2.7V Operation
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
f
Clock Frequency
0.01
0.01
5.4
4.6
0.01
0.01
4
3
MHz
MHz
CLK
●
t
Total Cycle Time
LTC1196
LTC1198
12
16
12
16
CLK
CLK
CYC
t
t
t
Analog Input Sampling Time
2.5
20
40
2.5
40
78
CLK
ns
SMPL
hCS
Hold Time CS Low After Last CLK↑
Setup Time CS↓ Before First CLK↑
(See Figures 1, 2)
ns
suCS
4
LTC1196/LTC1198
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
VCC = 2.7V Operation
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
t
t
t
t
t
t
Hold Time D After CLK↑
LTC1198
LTC1198
40
40
78
78
ns
ns
hDI
IN
Setup Time D Stable Before CLK↑
suDI
IN
CLK High Time
f
f
= f
= f
40%
40%
50
40%
40%
96
1/f
1/f
WHCLK
WLCLK
WHCS
WLCS
CLK
CLK
CLK(MAX)
CLK(MAX)
CLK
CLK Low Time
CLK
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
ns
LTC1196
LTC1198
11
15
11
15
CLK
CLK
U
U W
CO VERTER A D ULTIPLEXER CHARACTERISTICS
VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196-XA
LTC1198-XA
LTC1196-XB
LTC1198-XB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
Bits
No Missing Codes Resolution
Offset Error
●
●
●
●
●
8
8
±1/2
±1/2
±1/2
±1/2
±1
±1
±1
±1
LSB
LSB
LSB
LSB
Linearity Error
(Note 3)
Full-Scale Error
Total Unadjusted Error (Note 4)
LTC1196, V = 2.500V
REF
LTC1198, V = 2.700V
CC
–0.05V to V + 0.05V
Analog and REF Input Range
Analog Input Leakage Current
LTC1196
(Note 5)
V
CC
●
±1
±1
µA
U
D
A
ELECTRICAL CHARACTERISTICS
DC
DIGITAL
VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.6V
= 2.7V
●
●
●
●
1.9
IH
IL
CC
CC
IN
0.45
2.5
V
I
I
= V
µA
IH
IL
CC
= 0V
–2.5
µA
IN
V
V
V
= 2.7V, I = 10µA
●
●
2.3
2.1
2.60
2.45
V
V
OH
CC
CC
O
= 2.7V, I = 360µA
O
V
Low Level Output Voltage
Hi-Z Output Leakage
V
= 2.7V, I = 400µA
●
●
0.3
V
µA
OL
CC
O
I
I
I
I
CS = High
±3
OZ
Output Source Current
Output Sink Current
V
V
= 0V
–10
15
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
Reference Current, LTC1196
CS = V
●
●
0.001
0.25
3.0
0.5
µA
mA
REF
CC
f
= f
SMPL
SMPL(MAX)
I
Supply Current
CS = V = 3.3V, LTC1198 (Shutdown)
●
●
●
0.001
1.5
2.0
3.0
4.5
6.0
µA
mA
mA
CC
CC
CS = V = 3.3V, LTC1196
CC
f
= f
LTC1196/LTC1198
SMPL
SMPL(MAX),
5
LTC1196/LTC1198
U W
DY A IC ACCURACY
V CC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196
TYP
LTC1198
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
47/45
49/47
53/46
51
MAX
UNITS
dB
S/(N + D) Signal-to-Noise Plus Distortion
190kHz/380kHz Input Signal
190kHz/380kHz Input Signal
190kHz/380kHz Input Signal
47/45
49/47
53/46
51
THD
IMD
Total Harmonic Distortion
dB
Peak Harmonic or Spurious Noise
Intermodulation Distortion
dB
f
f
= 189.37kHz,
= 192.446kHz
dB
IN1
IN2
Full Power Bandwidth
5
5
MHz
MHz
Full Linear Bandwidth [S/(N+ D) > 44dB]
0.5
0.5
AC CHARACTERISTICS
VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
t
Conversion Time (See Figures 1, 2)
1.58
1.85
2.13
2.84
µs
µs
CONV
●
f
Maximum Sampling Frequency
LTC1196
LTC1196
LTC1198
LTC1198
450
383
337
287
333
250
250
187
kHz
kHz
kHz
kHz
SMPL(MAX)
●
●
t
Delay Time, CLK↑ to D
Data Valid
C
= 20pF
100
150
180
130
200
250
ns
ns
dDO
OUT
LOAD
●
●
●
●
t
t
t
Delay Time CS↑ to D
Hi-Z
110
80
220
130
120
100
120
250
200
ns
ns
ns
DIS
en
OUT
Delay Time, CLK↓ to D
Enabled
C
C
= 20pF
= 20pF
OUT
LOAD
LOAD
Time Output Data Remains Valid
45
90
45
hDO
After CLK↑
t
t
D
D
Fall Time
C
C
= 20pF
= 20pF
●
●
10
10
30
30
15
15
40
40
ns
ns
r
f
OUT
OUT
LOAD
LOAD
Rise Time
C
IN
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
30
5
5
30
5
5
pF
pF
pF
The
●
denotes specifications which apply over the full operating
Note 4: Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
temperature range.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 5: Channel leakage current is measured after the channel selection.
Note 2: All voltage values are with respect to GND.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
6
LTC1196/LTC1198
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Clock Rate
Supply Current vs Supply Voltage
Supply Current vs Sample Rate
9
8
7
6
5
4
3
2
1
0
10
1
14
12
10
8
LT1196 V = 5V
CC
T
A
= 25°C
V
= 5V
CC
LT1196 V = 2.7V
CC
“ACTIVE” MODE
CS = 0V
T
A
= 25°C
LT1198 V = 5V
CC
0.1
LTC1196
LTC1198
CS = 0V
V
= V
REF
CC
6
LT1198 V = 2.7V
CC
4
V
= 2.7V
12
0.01
CC
“SHUTDOWN” MODE
CS = V
2
T
= 25°C
CC
LTC1198
A
0.000002
0.001
0
4
6
8
14
4.5
5.5
6.0
0
2
10
16
2.5 3.0
3.5 4.0
5.0
100
1k
10k
100k
1M
SAMPLE RATE (Hz)
FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
1196/98 G03
1196/98 G01
1196/98 G02
Supply Current vs Temperature
Offset vs Reference Voltage
Offset vs Supply Voltage
10
9
8
7
6
5
4
3
2
1
0
0.5
0.4
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CS = 0V
T
= 25°C
T = 25°C
A
A
V
= 5V
V
= V
CC
= 3MHz
CC
REF
CLK
0.3
f
= 12MHz
f
CLK
V
CC
= 5V
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 2.7V
CC
–55 –35 –15
5
25 45 65 85 105 125
2.5
3.5 4.0 4.5
5.0 5.5 6.0
3.0
1.5
2.5 3.0 3.5
4.5
5.0
0.5 1.0
4.0
2.0
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
1196/98 G04
1196/98 G06
1196/98 G05
Linearity Error vs
Reference Voltage
Linearity Error vs Supply Voltage
Gain Error vs Reference Voltage
0.5
0.4
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
T
= 25°C
= V
T
= 25°C
T
= 25°C
= 5V
A
REF
A
A
CC
V
f
V
f
= 5V
V
f
CC
CC
0.3
= 3MHz
= 12MHz
= 12MHz
0.3
CLK
CLK
CLK
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
2.5
3.5 4.0 4.5
5.0 5.5 6.0
1.5
2.5 3.0 3.5
4.5
5.0
3.0
0.5 1.0
4.0
2.0
0
1.0
2.0
3.0 3.5 4.0 4.5 5.0
2.5
0.5
1.5
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1196/98 G08
1196/98 G07
1196/98 G09
7
LTC1196/LTC1198
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Clock Frequency vs
Supply Voltage
Maximum Clock Frequency vs
Source Resistance
Gain vs Supply Voltage
0.5
0.4
18
16
14
12
10
8
19
17
15
13
11
9
T
f
= 25°C
A
T = 25°C
A
= 3MHz
CLK
REF
V
= V
REF
CC
0.3
V
= V
CC
0.2
V
+IN
IN
0.1
–IN
0
–
R
SOURCE
–0.1
–0.2
–0.3
–0.4
–0.5
6
4
T
= 25°C
7
A
CC
2
V
= V
= 5V
REF
0
5
1
10
1k
10k
100k
2.5
3.5 4.0 4.5
5.0 5.5 6.0
100
3.0
4.5
5.0
5.5
6.0
2.5 3.0
3.5 4.0
SOURCE RESISTANCE (Ω)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1196/98 G12
1196/98 G10
1196/98 G11
Minimum Clock Rate for
0.1LSB* Error
ADC Noise vs Reference and
Supply Voltage
Sample-and-Hold Acquisition
Time vs Source Resistance
100
90
80
70
60
50
40
30
20
10
0
10000
1000
100
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
T
= 25°C
= V
V
V
= 5V
= 5V
A
CC
CC
REF
T = 25°C
A
V
= 5V
REF
V
= V
REF
CC
+
R
SOURCE
V
+IN
–IN
IN
–55 –35 –15
5
25 45 65 85 105 125
1
10
100
1k
10k
4.5
5.0
5.5 6.0
2.5 3.0
3.5 4.0
TEMPERATURE (°C)
SOURCE RESISTANCE (Ω)
SUPPLY VOLTAGE (V)
1196/98 G15
1196/98 G13
1196/98 G14
DOUT Delay Time vs
Supply Voltage
Digital Input Logic Threshold vs
Supply Voltage
DOUT Delay Time vs Temperature
160
140
120
100
80
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
140
120
100
80
V
REF
= V
CC
T
= 25°C
T = 25°C
A
REF
A
V
= V
CC
V
CC
= 2.7V
V
CC
= 5V
60
60
40
40
20
20
0
0
0
120
140
4.5
SUPPLY VOLTAGE (V)
5.0
5.5 6.0
–60 –40 –20
20 40 60 80 100
2.5
3.0
3.5 4.0
4.5
SUPPLY VOLTAGE (V)
5.5 6.0
2.5 3.0
3.5 4.0
5.0
TEMPERATURE (°C)
1196/98 G18
1196/98 G16
1196/98 G17
*AS THE FREQUENCY IS DECREASED FROM 12MHz, MINIMUM CLOCK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE
FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 12MHz VALUE IS FIRST DETECTED.
8
LTC1196/LTC1198
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Channel Leakage Current
vs Temperature
Integral Nonlinearity vs
Code at 5V
Differential Nonlinearity vs
Code at 5V
0.5
0.5
1000
100
10
V
V
f
= 5V
= 5V
V
V
f
= 5V
= 5V
V
V
= 5V
= 5V
CC
REF
CC
REF
CC
REF
= 12MHz
= 12MHz
CLK
CLK
0
0
ON CHANNEL
1
OFF CHANNEL
0.1
–0.5
–0.5
0.01
160 256
192 224
0
128
32 64 96
160 256
192 224
0
128
32 64 96
0
120
140
–60 –40 –20
20 40 60 80 100
CODE
CODE
TEMPERATURE (°C)
1196/98 G21
1196/98 G20
1196/98 G19
Differential Nonlinearity vs
Code at 2.7V
Effective Bits and S/(N + D) vs
Input Frequency
Integral Nonlinearity vs
Code at 2.7V
0.5
0.5
8
7
6
5
4
3
2
1
0
50
44
V
V
= 2.7V
V
V
= 2.7V
CC
REF
CLK
CC
REF
CLK
V
= V = 2.7V
CC
REF
= 2.5V
= 2.5V
f
f
= 383kHz (LTC1196)
= 287kHz (LTC1198)
SMPL
SMPL
f
= 3MHz
f
= 3MHz
V
= V = 5V
CC
REF
f
= 1MHz (LTC1196)
SMPL
f
= 750kHz (LTC1198)
SMPL
0
0
T
= 25°C
A
–0.5
–0.5
160 256
192 224
0
128
192 224
0
128
32 64 96
160
256
32 64 96
1k
10k
100k
1M
CODE
CODE
INPUT FREQUENCY (Hz)
1196/98 G24
1196/98 G22
1196/98 G23
FFT Output of 455kHz AM Signal
Digitized at 1MSPS
4096 Point FFT at 2.7V
4096 Point FFT Plot at 5V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
V
f
SMPL
= 5V
V
= 2.7V
CC
IN
V
= 5V
CC
CC
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 455kHz WITH 20kHz AM
= 1MHz
f
f
= 29kHz
f
f
= 29kHz
IN
SMPL
IN
SMPL
f
= 340kHz
= 882kHz
0
100
200
300
400
500
0
50
100
FREQUENCY (kHz)
150
200
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
1196/98 G27
1196/98 G26
1196/98 G25
9
LTC1196/LTC1198
TYPICAL PERFOR A CE CHARACTERISTICS
U W
S/(N + D) vs Reference Voltage
and Input Frequency
Power Supply Feedthrough vs
Ripple Frequency
Power Supply Feedthrough vs
Ripple Frequency
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
50
45
40
35
30
25
T
= 25°C
CC RIPPLE
= 5MHz
T
= 25°C
CC RIPPLE
= 12MHz
A
A
V
f
(V
= 10mV)
V
f
(V
= 20mV)
f
= 500kHz
IN
CLK
CLK
f
= 200kHz
IN
f
= 100kHz
IN
V
= 5V
CC
1k
10k
100k
1M
1k
10k
100k
1M
1.25
2.75 3.25 3.75
1.75 2.25
4.25 4.75
5.25
RIPPLE FREQUENCY (Hz)
RIPPLE FREQUENCY (Hz)
REFERENCE VOLTAGE (V)
1196/98 G29
1196/98 G28
1196/98 G30
Intermodulation Distortion at 2.7V
Intermodulation Distortion at 5V
S/(N + D) vs Input Level
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 2.7V
V
= 5V
CC
V
= V = 5V
CC
CC
REF
f1 = 100kHz
f2 = 110kHz
f1 = 200kHz
f2 = 210kHz
f
f
= 500kHz
IN
SMPL
= 1MHz
f
= 420kHz
f
= 750kHz
SMPL
SMPL
–20
–40 –35 –30 –25
–15 –10 –5
0
0
50
100
150
200
250
0
100
200
FREQUENCY (kHz)
300
400
INPUT LEVEL (dB)
FREQUENCY (kHz)
1196/98 G33
1196/98 G31
1196/98 G32
Output Amplitude vs
Input Frequency
Spurious-Free Dynamic Range vs
Frequency
70
100
80
60
40
20
0
V
CLK
= 5V
CC
60
50
40
30
20
10
0
f
= 12MHz
V
= V = 5V
CC
REF
V
CLK
= 3V
CC
= 5MHz
V
= V = 2.7V
CC
REF
f
T
= 25°C
10k
A
1k
10k
100k
1M
1k
100k
FREQUENCY (Hz)
1M
10M
10M
INPUT FREQUENCY (Hz)
1196/98 G34
1196/98 G35
10
LTC1196/LTC1198
U
U
U
PI FU CTIO S
LTC1198
LTC1196
CS/SHUTDOWN (Pin 1): Chip Select Input. A logic low on
this input enables the LTC1198. A logic high on this input
disablestheLTC1198andDISCONNECTSTHEPOWERTO
THE LTC1198.
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1196. A logic high on this input disables
the LTC1196.
IN+ (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
IN– (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
CHO(Pin2):AnalogInput. Thisinputmustbefreeofnoise
with respect to GND.
CH1 (Pin 3):Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
REF (Pin 5): Reference Input. The reference input defines
DIN (Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.
the span of the A/D converter and must be kept free of
noise with respect to GND.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer.
VCC(VREF)(Pin 8): Power Supply and Reference Voltage.
This pin provides power and defines the span of the A/D
converter. It must be kept free of noise and ripple by
bypassing directly to the analog ground plane.
VCC (Pin 8): Power Supply Voltage. This pin provides
power to the A/D converter. It must be kept free of noise
and ripple by bypassing directly to the analog ground
plane.
W
CS
BLOCK DIAGRA
V
(V /V
CC CC REF
)
(CS/SHUTDOWN) CLK
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
D
OUT
+
IN (CH0)
C
SMPL
–
+
SAR
–
IN (CH1)
HIGH SPEED
COMPARATOR
CAPACITIVE DAC
GND
V
(D )
REF IN
PIN NAMES IN PARENTHESES
REFER TO THE LTC1198
1196/98 BD
11
LTC1196/LTC1198
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
On and Off Channel Leakage Current
5V
1.4V
I
ON
A
3k
ON CHANNEL
D
OUT
TEST POINT
I
OFF
A
100pF
OFF
CHANNEL
1196/98 TC02
•
•
•
•
POLARITY
1196/98 TC01
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
Voltage Waveform for DOUT Delay Time, tdDO and thDO
V
OH
V
IH
D
OUT
CLK
V
OL
t
dDO
t
hDO
t
t
1196/98 TC04
r
f
V
OH
D
OUT
V
OL
1196/98 TC03
Load Circuit for tdis and ten
Voltage Waveforms for tdis
V
CS
IH
TEST POINT
D
OUT
90%
WAVEFORM 1
(SEE NOTE 1)
V
t
WAVEFORM 2, t
CC dis en
3k
D
OUT
t
dis
t
WAVEFORM 1
dis
D
20pF
OUT
WAVEFORM 2
(SEE NOTE 2)
10%
1196/98 TC05
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1196/98 TC06
12
LTC1196/LTC1198
TEST CIRCUITS
Voltage Waveforms for ten
LTC1196
CS
CLK
2
3
1
4
B7
D
OUT
V
OL
1196/98 TC07
t
en
Voltage Waveforms for ten
LTC1198
CS
D
IN
START
CLK
5
1
2
3
4
6
7
B7
D
OUT
V
OL
1196/98 TC08
t
en
13
LTC1196/LTC1198
O U
W
U
PPLICATI
A
S I FOR ATIO
OVERVIEW
LTC1198 has a 2-channel input multiplexer and can con-
verteitherchannelwithrespecttogroundorthedifference
between the two. It also automatically powers down when
not performing conversion, drawing only leakage current.
The LTC1196/LTC1198 are 600ns sampling 8-bit A/D
converters packaged in tiny 8-pin SO packages and oper-
ating on 3V to 6V supplies. The ADCs draw only 10mW
from a 3V supply or 50mW from a 5V supply.
SERIAL INTERFACE
Both the LTC1196 and the LTC1198 contain an 8-bit,
switched-capacitor ADC, a sample-and-hold, and a serial
port (see Block Diagram). The on-chip sample-and-holds
have full-accuracy input bandwidths of 1MHz. Although
they share the same basic design, the LTC1196 and
LTC1198 differ in some respects. The LTC1196 has a
differential input and has an external reference input pin.
It can measure signals floating on a DC common-mode
voltageandcanoperatewithreducedspansbelow1V.The
The LTC1196/LTC1198 will interface via three or four
wires to ASICs, PLDs, microprocessors, DSPs, or shift
registers (see Operating Sequence in Figures 1 and 2). To
run at their fastest conversion rates (600ns), they must be
clocked at 14.4MHz. HC logic families and any high speed
ASIC or PLD will easily interface to the ADCs at that speed
(see Data Transfer and Typical Application sections). Full
speedoperationfroma3Vsupplycanstillbeachievedwith
3V ASICs, PLDs or HC logic circuits.
t
(12 CLKs)
CYC
CS
t
suCS
CLK
t
dDO
NULL
BITS
B5
(8.5 CLKs)
B4
B3
B1
B6
B2
B0*
B7
B0
NULL BITS
D
OUT
Hi-Z
Hi-Z
t
t
t
CONV
SMPL
SMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
1196/98 F01
Figure 1. LTC1196 Operating Sequence
t
(16 CLKs)
CYC
CS
POWER
DOWN
t
suCS
CLK
ODD/
SIGN
START
DUMMY
D
DON’T CARE
B4
IN
SGL/
DIFF
DUMMY
t
dDO
Hi-Z
D
B7
B6
B5
B3
B2
B1
B0*
OUT
NULL BITS
HI-Z
t
(2.5CLKs)
t
(8.5CLKs)
CONV
SMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
1196/98 F02
Figure 2. LTC1198 Operating Sequence Example: Differential Inputs (CH1, CH0)
14
LTC1196/LTC1198
O U
W
U
PPLICATI
A
S I FOR ATIO
Connection to a microprocessor or a DSP serial port is
quite simple (see Data Transfer section). It requires no
additional hardware, but the speed will be limited by the
clock rate of the microprocessor or the DSP which limits
the conversion time of the LTC1196/LTC1198.
conversion result are output on the DOUT line. At the end
of the data exchange CS should be brought high. This
resets the LTC1198 in preparation for the next data ex-
change.
Input Data Word
Data Transfer
The LTC1196 requires no DIN word. It is permanently
configured to have a single differential input. The conver-
sion result is output on the DOUT line in an MSB-first
sequence, followed by zeros indefinitely if clocks are
continuously applied with CS low.
DatatransferdiffersslightlybetweentheLTC1196andthe
LTC1198. The LTC1196 interfaces over 3 lines: CS, CLK
and DOUT. A falling CS initiates data transfer as shown in
the LTC1196 Operating Sequence. After CS falls, the first
CLK pulse enables DOUT. After two null bits, the A/D
conversion result is output on the DOUT line. Bringing CS
high resets the LTC1196 for the next data exchange.
The LTC1198 clocks data into the DIN input on the rising
edge of the clock. The input data word is defined as follows:
SGL/
DIFF
ODD/
SIGN
The LTC1198 can transfer data with 3 or 4 wires. The
additional input, DIN, is used to select the 2-channel MUX
configuration.
DUMMY DUMMY
START
MUX
ADDRESS
DUMMY
BITS
119698 AI02
The data transfer between the LTC1198 and the digital
systemscanbebrokenintotwosections:InputDataWord
and A/D Conversion Result. First, each bit of the input data
word is captured on the rising CLK edge by the LTC1198.
Second, each bit of the A/D conversion result on the DOUT
line is updated on the rising CLK edge by the LTC1198.
This bit should be captured on the next rising CLK edge by
the digital systems (see A/D Conversion Result section).
Start Bit
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1198 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputsontheDINpinarethenignoreduntilthenextCScycle.
Multiplexer (MUX) Address
Data transfer is initiated by a falling chip select (CS) signal
as shown in the LTC1198 Operating Sequence. After CS
falls the LTC1198 looks for a start bit. After the start bit is
received, the 4-bit input word is shifted into the DIN input.
ThefirsttwobitsoftheinputwordconfiguretheLTC1198.
ThelasttwobitsoftheinputwordallowtheADCtoacquire
the input voltage by 2.5 clocks before the conversion
starts. After the conversion starts, two null bits and the
The 2 bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND.
CS
LTC1198 Channel Selection
D
D
IN2
IN1
MUX ADDRESS
CHANNEL #
SGL/DIFF ODD/SIGN
0
1
GND
D
D
OUT2
OUT1
1
1
0
0
0
1
0
1
+
–
–
SINGLE-ENDED
MUX MODE
SHIFT MUX
ADDRESS IN
+
–
+
+
–
DIFFERENTIAL
MUX MODE
2 NULL BITS SHIFT A/D CONVERSION
RESULT OUT
1196/98 AI03
1196/98 AI01
15
LTC1196/LTC1198
O U
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PPLICATI
A
S I FOR ATIO
Unipolar Output Code
Dummy Bits
INPUT VOLTAGE
(V = 5.000V)
The last 2 bits of the input word following the MUX
Address are dummy bits. Either bit can be a “logical
one” or a “logical zero.” These 2 bits allow the ADC 2.5
clocks to acquire the input signal after the channel
selection.
OUTPUT CODE
INPUT VOLTAGE
REF
4.9805V
1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
4.9609V
1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
•
0.0195V
0V
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1LSB
0V
1196/98 AI05
A/D Conversion Result
Both the LTC1196 and the LTC1198 have the A/D
Operation with DIN and DOUT Tied Together
conversion result appear on the D
line after two null
OUT
The LTC1198 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to
communicate to the digitalsystems. Data is transmitted in
both directions on a single wire. The pin of the digital
systemsconnectedtothisdatalineshouldbeconfigurable
as either an input or an output. The LTC1198 will take
control of the data line and drive it low on the 5th falling
CLK edge after the start bit is received (see Figure 4).
Therefore the port line of the digital systems must be
switched to an input before this happens to avoid a
conflict.
bits (see Operating Sequence in Figures 1 and 2). Data
ontheD lineisupdatedontherisingedgeoftheCLK
OUT
line. The D
data should also be captured on the
OUT
risingCLKedgebythedigitalsystems.DataontheD
OUT
line remains valid for a minimum time of t
(30ns at
hDO
5V) to allow the capture to occur (see Figure 3).
V
IH
CLK
t
dDO
t
hDO
V
OH
D
OUT
V
OL
REDUCING POWER CONSUMPTION
1196/98 TC03
The LTC1196/LTC1198 can sample at up to a 1MHz rate,
drawing only 50mW from a 5V supply. Power consump-
tion can be reduced in two ways. Using a 3V supply lowers
thepowerconsumptiononbothdevicesbyafactoroffive,
to 10mW. The LTC1198 can reduce power even further
because it shuts down whenever it is not converting.
Figure 5 shows the supply current versus sample rate for
the LTC1196 and LTC1198 on 3V and 5V. To achieve such
a low power consumption, especially for the LTC1198,
several things must be taken into consideration.
Figure 3. Voltage Waveform for DOUT Delay Time,
tdDO and thDO
Unipolar Transfer Curve
The LTC1196/LTC1198 are permanently configured for
unipolar only. The input span and code assignment for
this conversion type are shown in the following figures.
Unipolar Transfer Curve
Shutdown (LTC1198)
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
Figure 2 shows the operating sequence of the LTC1198.
The converter draws power when the CS pin is low and
powersitselfdownwhenthatpinishigh. Forlowestpower
consumption in shutdown, the CS pin should be driven
with CMOS levels (0V to VCC) so that the CS input buffer
of the converter will not draw current.
•
•
•
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V
IN
1196/98 AI04
16
LTC1196/LTC1198
O U
S
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DUMMY BITS LATCHED
BY LTC1198
CS
1
2
3
4
5
CLK
DATA (D /D
)
START
DUMMY
IN OUT
SGL/DIFF
ODD/SIGN
DUMMY
B7
B6
THE DIGITAL SYSTEM CONTROLS DATA LINE
AND SENDS MUX ADDRESS TO LTC1198
LTC1198 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO THE DIGITAL SYSTEM
THE DIGITAL SYSTEM MUST RELEASE
DATA LINE AFTER 5TH RISING CLK
AND BEFORE THE 5TH FALLING CLK
LTC1198 TAKES CONTROL OF
DATA LINE ON 5TH FALLING CLK
1196/98 F04
Figure 4. LTC1198 Operation with DIN and DOUT Tied Together
10
1
Minimize CS Low Time (LTC1198)
LT1196 V = 5V
CC
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transfering data as quickly as
possible, thenbringingitbackhighwillresultinthelowest
current drain. This minimizes the amount of time the
device draws power.
LT1196 V = 2.7V
CC
LT1198 V = 5V
CC
0.1
LT1198 V = 2.7V
CC
0.01
OPERATING ON OTHER THAN 5V SUPPLIES
0.001
100
1k
10k
100k
1M
The LTC1196/LTC1198 operate from single 2.7V to 6V
supplies. To operate the LTC1196/LTC1198 on other than
5V supplies, a few things must be kept in mind.
SAMPLE RATE (Hz)
1196/98 F05
Figure 5. Supply Current vs Sample Rate for LTC1196/
LTC1198 Operating on 5V and 2.7V Supplies
Input Logic Levels
When the CS pin is high (= supply voltage), the LTC1198
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK input has no effect on the supply
current during this time. There is no need to stop DIN and
CLK with CS = high; they can continue to run without
drawing current.
The input logic levels of CS, CLK and DIN are made to
meet TTL on 5V supply. When the supply voltage varies,
the input logic levels also change (see typical curve of
Digital Input Logic Threshold vs Supply Voltage). For
these two ADCs to sample and convert correctly, the
digital inputs have to be in the logical low and high relative
to the operating supply voltage. If achieving micropower
consumption is desirable on the LTC1198, the digital
inputs must go rail-to-rail between supply voltage and
ground (see Reducing Power Consumption section).
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Clock Frequency
The VCC pin should be bypassed to the ground plane with
a1µFtantalumwithleadsasshortaspossible.Ifthepower
supply is clean, the LTC1196/LTC1198 can also operate
with smaller 0.1µF surface mount or ceramic bypass
capacitors. All analog inputs should be referenced directly
to the single-point ground. Digital inputs and outputs
should be shielded from and/or routed away from the
reference and analog circuitry.
The maximum recommended clock frequency is 14.4MHz
at25°CfortheLTC1196/LTC1198runningoffa5Vsupply.
With the supply voltage changing, the maximum clock
frequency for the devices also changes (see the typical
curve of Maximum Clock Rate vs Supply Voltage). If the
supply is reduced, the clock rate must be reduced also. At
3V the devices are specified with a 5.4MHz clock at 25°C.
SAMPLE-AND-HOLD
Mixed Supplies
Both the LTC1196 and the LTC1198 provide a built-in
sample-and-hold (S&H) function to acquire the input
signal. The S&H acquires the input signal from “+” input
during tSMPL as shown in Figures 1 and 2. The S&H of the
LTC1198 can sample input signals in either single-ended
or differential mode (see Figure 7).
It is possible to have a digital system running off a 5V
supply and communicate with the LTC1196/LTC1198
operating on a 3V supply. Achieving this reduces the
outputs of DOUT from the ADCs to toggle the equivalent
input of the digital system. The CS, CLK and DIN inputs of
the ADCs will take 5V signals from the digital system
without causing any problem (see typical curve of Digital
Input Logic Threshold vs Supply Voltage). With the
LTC1196operatingona3Vsupply,theoutputofDOUT only
goes between 0V and 3V. This signal easily meets TTL
levels (see Figure 6).
Single-Ended Inputs
The sample-and-hold of the LTC1198 allows conversion
of rapidly varying signals. The input voltage is sampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the first DUMMY bit is
shifted in and continues until the falling CLK edge after the
second DUMMY bit is received. On this falling edge, the
S&H goes into hold mode and the conversion begins.
3V
4.7µF
MPU
(e.g., 8051)
5V
V
CS
P1.4
CC
Differential Inputs
CLK
P1.3
P1.2
DIFFERENTIAL INPUTS
+IN
–IN
GND
LTC1196
COMMON-MODE RANGE
0V TO 3V
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
age onthe selected “–”inputmust remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 8.5 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input, this error would be:
D
OUT
V
REF
3V
1196/98 F06
Figure 6. Interfacing a 3V Powered LTC1196 to a 5V System
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1196/LTC1198 are easy to use if some care is
taken. They should be used with an analog ground plane
and single-point grounding techniques. The GND pin
should be tied directly to the ground plane.
VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 8.5/fCLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
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SAMPLE
HOLD
“+” INPUT MUST
SETTLE DURING
THIS TIME
CS
t
t
CONV
SMPL
CLK
START
D
IN
SGL/DIFF
ODD/SIGN
DUMMY
DUMMY
DON’T CARE
B7
D
OUT
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
“+” INPUT
“–” INPUT
1196/98 F07
Figure 7. LTC1198 “+” and “–” Input Settling Windows
“+” Input Settling
CLK. VERROR is proportional to f(“–”) and inversely pro-
portional to fCLK. For a 60Hz signal on the “–” input to
generate a 1/4LSB error (5mV) with the converter running
at CLK = 12MHz, its peak value would have to be 18.7V.
The input capacitor of the LTC1196 is switched onto “+”
input at the end of the conversion and samples the input
signaluntiltheconversionbegins(seeFigure1). Theinput
capacitoroftheLTC1198isswitchedonto“+”inputduring
the sample phase (tSMPL, see Figure 7). The sample phase
is 2.5 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within tSMPL for the
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1196/
LTC1198 have one capacitive switching input current
spike per conversion. These current spikes settle quickly
and do not cause a problem. However, if source resis-
tances larger than 100Ω are used or if slow settling op
ampsdrivetheinputs,caremustbetakentoinsurethatthe
transients caused by the current spikes settle completely
before the conversion begins.
+
LTC1196/LTC1198. Minimizing RSOURCE will improve
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
allowing more time between conversions for the LTC1196
or by using a slower CLK frequency for the LTC1198.
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“–” Input Settling
REFERENCE INPUT
At the end of the tSMPL, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settle completely during the first CLK cycle of the
The voltage on the reference input of the LTC1196 defines
the voltage span of the A/D converter. The reference input
has transient capacitive switching currents which are due
to the switched-capacitor conversion technique (see Fig-
ure 9). During each bit test of the conversion (every CLK
cycle), a capacitive current spike will be generated on the
reference pin by the ADC. These high frequency current
spikes will settle quickly and do not cause a problem if the
referenceinputisbypassedwithatleasta0.1µFcapacitor.
–
conversiontimeandbefreeofnoise.MinimizingRSOURCE
will improve settling time. If a large “–” input source
resistance must be used, the time allowed for settling can
be extended by using a slower CLK frequency.
The reference input can be driven with standard voltage
references.Bypassingthereferencewitha0.1µFcapacitor
is recommended to keep the high frequency impedance
low as described above. Some references require a small
resistor in series with the bypass capacitor for frequency
stability.Seetheindividualreferencedatasheetfordetails.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figures 1 and 7). Again, the “+” and “–” input
sampling times can be extended as described above to
accommodate slower op amps.
+
REF
LTC1196
5
To achieve the full sampling rate, the analog input should
be driven with a low impedance source (<100Ω) or a high
speed op amp (e.g., the LT1223, LT1191, or LT1226).
Higher impedance sources or slower op amps can easily
be accommodated by allowing more time for the analog
input to settle as described above.
EVERY CLK CYCLE
R
OUT
R
ON
5pF TO
30pF
V
REF
GND
4
1196/98 F09
Figure 9. Reference Input Equivalent Circuit
Source Resistance
Reduced Reference Operation
The analog inputs of the LTC1196/LTC1198 look like a
25pF capacitor (CIN) in series with a 120Ω resistor (RON)
as shown in Figure 8. CIN gets switched between the
selected “+” and “–” inputs once during each conversion
cycle. Largeexternalsourceresistorswillslowthe settling
of the inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
The minimum reference voltage of the LTC1198 is limited
to 2.7V because the VCC supply and reference are inter-
nally tied together. However, the LTC1196 can operate
with reference voltages below 1V.
The effective resolution of the LTC1196 can be increased
by reducing the input span of the converter. The LTC1196
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Linearity and Full-
Scale Error vs Reference Voltage). However, care must be
taken when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. The following factors
must be considered when operating at low VREF values.
completely settle within tSMPL
.
“+”
+
INPUT
R
SOURCE
LTC1196
LTC1198
V
+
–
IN
↑t
SMPL
R
ON
120Ω
C
“–”
INPUT
IN
–
25pF
R
SOURCE
t
↓
SMPL
V
IN
1196/98 F08
1. Offset
2. Noise
Figure 8. Analog Input Equivalent Circuit
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DYNAMIC PERFORMANCE
Offset with Reduced VREF
The LTC1196/LTC1198 have exceptionally high speed
sampling capability. Fast Fourier Transform (FFT) test
techniques are used to characterize the ADC’s frequency
response, distortion and noise at the rated throughput. By
applying a low distortion sine wave and analyzing the
digital output using a FFT algorithm, the ADC’s spectral
content can be examined for frequencies outside the
fundamental. Figure 10 shows a typical LTC1196 FFT plot.
The offset of the LTC1196 has a larger effect on the output
code when the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Unadjusted Offset Error vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example,
a VOS of 2mV which is 0.1LSB with a 5V reference
becomes 0.5LSB with a 1V reference and 2.5LSB with a
0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input of the LTC1196.
0
V
= 5V
CC
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
f
f
= 29kHz
IN
SMPL
= 882kHz
Noise with Reduced VREF
The total input referred noise of the LTC1196 can be
reduced to approximately 2mVP-P using a ground plane,
good bypassing, good layout techniques and minimizing
noise on the reference inputs. This noise is insignificant
with a 5V reference but will become a larger fraction of an
LSB as the size of the LSB is reduced.
0
100
200
300
400
500
FREQUENCY (kHz)
1196/98 G25
For operation with a 5V reference, the 2mV noise is only
0.1LSB peak-to-peak. In this case, the LTC1196 noise
will contribute virtually no uncertainty to the output
code. However, for reduced references, the noise may
become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with
a 1V reference, this same 2mV noise is 0.5LSB peak-to-
peak. This will reduce the range of input voltages over
which a stable output code can be achieved by 1LSB. If
the reference is further reduced to 200mV, the 2mV
noise becomes equal to 2.5LSB and a stable code is
difficult to achieve. In this case averaging readings is
necessary.
Figure 10. LTC1196 Non-Averaged, 4096 Point FFT Plot
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 10 shows a typical spec-
tral content with a 882kHz sampling rate.
Effective Number of Bits
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, VREF or VIN) will add
to the internal noise. The lower the reference voltage to be
used, the more critical it becomes to have a clean, noise-
free setup.
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to S/(N + D)
by the equation:
N = [S/(N + D) –1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
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rate of 1.2MHz with a 5V supply the LTC1196 maintains
above7.5ENOBsat400kHzinputfrequency.Above500kHz
the ENOBs gradually decline, as shown in Figure 11, due
to increasing second harmonic distortion. The noise floor
remains low.
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
wavesareequalinmagnitudes, thevalue(indB)ofthe2nd
order IMD products can be expressed by the following
formula:
8
7
6
5
4
3
2
1
0
50
44
V
= V = 2.7V
CC
REF
f
f
= 383kHz (LTC1196)
= 287kHz (LTC1198)
SMPL
SMPL
V
= V = 5V
CC
REF
f
= 1MHz (LTC1196)
SMPL
f
= 750kHz (LTC1198)
SMPL
T
= 25°C
A
amplitude f ± f
(
)
b
a
1k
10k
100k
1M
IMD f ± f = 20log
(
)
a
b
INPUT FREQUENCY (Hz)
amplitude at fa
1196/98 G24
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
For input frequencies of 499kHz and 502kHz, the IMD of
the LTC1196/LTC1198 is 51dB with a 5V supply.
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is defined as:
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
valueisexpressedindBsrelativetotheRMSvalueofafull-
scale input signal.
V2 + V32 + V42 +... + VN2
Full-Power and Full-Linear Bandwidth
2
THD = 20log
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input.
V
1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD speci-
fication in the Dynamic Accuracy table includes the 2nd
through 5th harmonics. With a 100kHz input signal, the
LTC1196/LTC1198 have typical THD of 50dB and 49dB
with VCC = 5V and VCC = 3V, respectively.
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 7 bits. Beyond
this frequency, distortion of the sampled input signal
increases. The LTC1196/LTC1198 have been designed to
optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters’ Nyquist Frequency.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
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3V VERSUS 5V PERFORMANCE COMPARISON
S I FOR ATIO
A
Table 1. 5V/3V Performance Comparison
LTC1196-1
5V
50mW
3V
10mW
Table 1 shows the performance comparison between 3V
and 5V supplies. The power dissipation drops by a factor
of five when the supply is reduced to 3V. The converter
slows down somewhat but still gives excellent perfor-
mance on a 3V rail. With a 3V supply, the LTC1196
converts in 1.6µs, samples at 450kHz, and provides a
500kHz linear-input bandwidth.
P
DISS
Max f
1MHz
383kHz
1.6µs
SMPL
Min t
600ns
CONV
INL (Max)
0.5LSB
7.9 at 300kHz
1MHz
0.5LSB
Typical ENOBs
7.9 at 100kHz
500kHz
Linear Input Bandwidth (ENOBs > 7)
LTC1198-1
Dynamic accuracy is excellent on both 5V and 3V. The
ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic
accuracy at both 3V and 5V. The noise floor is extremely
low, corresponding to a transition noise of less than
0.1LSB. DC accuracy includes ±0.5LSB total unadjusted
error at 5V. At 3V, linearity error is ±0.5LSB while total
unadjusted error increases to ±1LSB.
P
50mW
15µW
10mW
9µW
DISS
P
(Shutdown)
DISS
Max f
750kHz
600ns
287kHz
1.6µs
SMPL
CONV
Min t
INL (Max)
0.5LSB
0.5LSB
Typical ENOBs
7.9 at 300kHz
1MHz
7.9 at 100kHz
500kHz
Linear Input Bandwidth (ENOBs > 7)
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TYPICAL APPLICATI S
PLD Interface Using the Altera EPM5064
goes high for one CLK cycle with every 12 CLK cycles. The
inverted signal, EN, of the CS output makes the 8-bit data
available on the B0-B7] lines. Figures 13 and 14 show the
interconnection between the LTC1196 and EPM5064 and
the timing diagram of the signals between these two
devices. The CLK frequency in this circuit can run up to
fCLK(MAX) of the LTC1196.
The Altera EPM5064 has been chosen to demonstrate the
interface between the LTC1196 and a PLD. The EPM5064
is programmed to be a 12-bit counter and an equivalent
74HC595 8-bit shift register as shown in Figure 12. The
circuit works as follows: bringing ENA high makes the CS
output high and the EN input low to reset the LTC1196 and
disable the shift register. Bringing ENA low, the CS output
CLK
V
CC
1µF
8-BIT
SHIFT REGISTER
3, 14, 25, 36
1
33
23
34
35
DATA
DATA
CLK
ENA
EPM5064
CLK
DATA
B7
37
38
39
40
41
42
44
1
2
3
4
8
7
6
5
CS
V
CLK
EN
B0-B7
B0-B7
CS
CC
+
–
CLK
+IN
–IN
GND
CLK
12-BIT
CONVERTER
ENA
LTC1196
D
OUT
V
REF
CS
ENA
B0
RESERVE PINS OF EPM5064:
2, 4-8,15-20, 22, 24, 26-30
9-13, 21,
31, 32, 43
1196/98 F13
1196/98 F12
Figure 12. An Equivalent Circuit of the EPM5064
Figure 13. Intefacing the LTC1196 to the Altera EPM5064 PLD
23
LTC1196/LTC1198
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DATA
CLK
CS
B7
B6
B5
B4
B3
B2
B1
B0
70 140 210 280 350 420 490
630
560
TIME (ns)
770 840 910 980 1050 1120
700
1196/98 F14
Figure 14. The Timing Diagram
the LTC1198 in Figure 15 can be 2.7V to 6V with fCLK
=
Interfacing the LTC1198 to the TMS320C25 DSP
5MHz. At 2.7V, fCLK = 5MHz will work at 25°C. See
Recommended Operating Conditions for limits over tem-
perature.
Figure 15 illustrates the interface between the LTC1198
8-bit data acquisition system and the TMS320C25 digital
signal processor (DSP). The interface, which is optimized
for speed of transfer and minimum processor supervi-
sion, can complete a conversion and shift the data in 4µs
with fCLK = 5MHz. The cycle time, 4µs, of each conversion
is limited by maximum clock frequency of the serial port
of the TMS320C25 which is 5MHz. The supply voltage for
Hardware Description
The circuit works as follows: the LTC1198 clock line
controls the A/D conversion rate and the data shift rate.
Data is transferred in a synchronous format over DIN and
DOUT.TheserialportoftheTMS320C25iscompatiblewith
that of the LTC1198. The data shift clock lines (CLKR,
CLKX) are inputs only. The data shift clock comes from an
external source. Inverting the shift clock is necessary
because the LTC1198 and the TMS320C25 clock the input
data on opposite edges.
5MHz CLK
CLK
CS
CH0
CH1
CLKX
CLKR
FSR
LTC1198
The schematic of Figure 15 is fed by an external clock
source. The signal is fed into the CLK pin of the LTC1198
directly. The signal is inverted with a 74HC04 and then
applied to the data shift clock lines (CLKR, CLKX). The
framing pulse of the TMS320C25 is fed directly to the CS
of the LTC1198. DX and DR are tied directly to DIN and
DOUT respectively.
TMS320C25
FSX
DX
D
IN
DR
D
OUT
1196/98 F15
Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP
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LTC1196/LTC1198
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The timing diagram of Figure 16 was obtained from the
circuit of Figure 15. The CLK was 5MHz for the timing
diagram and the TMS320C25 clock rate was 40MHz.
Figure 17 shows the timing diagram with the LTC1198
running off a 2.7V supply and 5MHz CLK.
Software Description
The software configures and controls the serial port of the
TMS320C25.
The code first sets up the interrupt and reset vectors. On
reset the TMS320C25 starts executing code at the label
INIT. Upon completion of a 16-bit data transfer, an inter-
rupt is generated and the DSP will begin executing code at
the label RINT.
CS
CLK
In the beginning, the code initializes registers in the
TMS320C25 that will be used in the transfer routine. The
interrupts are temporarily disabled. The data memory
page pointer register is set to zero. The auxiliary register
pointer is loaded with one and auxiliary register one is
loaded with the value 200 hexadecimal. This is the data
memory location where the data from the LTC1198 will be
stored. The interrupt mask register (IMR) is configured to
recognize the RINT interrupt, which is generated after
receivingthelastof16bitsontheserialport.Thisinterrupt
is still disabled at this time. The transmit framing synchro-
nization pin (FSX) is configured to be an output. The F0 bit
of the status register ST1, is initialized to zero which sets
up the serial port to operate in the 16-bit mode.
DIN
DOUT
MSB
(B7)
LSB
(B0)
NULL
BITS
HORIZONTAL: 1500ns/DIV
1196/98 F16
Figure 16. Scope Trace the LTC1198 Running Off
5V Supply in the Circuit of Figure 15
Next, the code in TXRX routine starts to transmit and
receive data. The DIN word is loaded into the ACC and
shifted left eight times so that it appears as in Figure 18.
This DIN word configures the LTC1198 for CH0 with
respect to CH1. The DIN word is then put in the transmit
register and the RINT interrupt is enabled. The NOP is
repeated 3 times to mask out the interrupts and minimize
the cycle time of the conversion to be 20 clock cycles. All
clocking and CS functions areperformed by the hardware.
CS
CLK
DIN
DOUT
B15
0
B8
0
NULL
BITS
MSB
(B7)
LSB
(B0)
1
0
S/D
0
0
1
0
START
O/S DUMMY DUMMY
L1196/98 F18
HORIZONTAL: 500ns/DIV
1196/98 F17
Figure 18. DIN Word in ACC of TMS320C25 for the
Circuit in Figure 15
Figure 17. Scope Trace the LTC1198 Running Off
2.7V Supply in the Circuit of Figure 15
25
LTC1196/LTC1198
U
O
TYPICAL APPLICATI S
MSB
LSB
0
Once RINT is generated the code begins execution at the
label RINT. This code stores the DOUT word from the
LTC1198 in the ACC and then stores it in location 200 hex.
The data appears in location 200 hex right-justified as
shown in Figure 19. The code is set up to continually loop,
so at this point the code jumps to label TXRX and repeats
from here.
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
> 200
L1196/98 F19
D
FROM LTC1198 STORED IN TMS320C25 RAM
OUT
Figure 19. Memory Map for the Circuit in Figure 15
LABEL
MNEMONIC
COMMENTS
AORG
B
0
INIT
ON RESET CODE EXECUTION STARTS AT 0
BRANCH TO INITIALIZATION ROUTINE
AORG
B
>26
RINT
ADDRESS OF RINT INTERRUPT VECTOR
BRANCH TO RINT SERVICE ROUTINE
AORG
DINT
>32
MAIN PROGRAM STARTS HERE
DISABLE INTERRUPTS
INIT
LDPK
LARP
LRLK
LACK
SACL
STXM
FORT
>0
>1
AR1,>200
>10
>4
SET DATA MEMORY PAGE POINTER TO 0
SET AUXILIARY REGISTER POINTER TO 1
SET AUXILIARY REGISTER 1 TO >200
LOAD IMR CONFIG WORD INTO ACC
STORE IMR CONFIG WORD INTO IMR
CONFIGURE FSX AS AN OUTPUT
SET SERIAL PORT TO 16-BIT MODE
0
TXRX
LACK
SFSM
RPTK
SFL
>44
LOAD LTC1198 D WORD INTO ACC
FSX PULSES GENERATED ON XSR LOAD
REPEAT NEXT INSTRUCTION 8 TIMES
IN
7
SHIFTS D WORD TO RIGHT POSITION
IN
SACL
EINT
>1
PUT D WORD IN TRANSMIT REGISTER
ENABLE INTERRUPT (DISABLED ON RINT)
IN
RPTK
NOP
2
MINIMIZE THE CONVERSION CYCLE TIME
TO BE 20 CLOCK CYCLES
RINT
ZALS
SACL
B
>0
*, 0
TXRX
STORE LTC1198 DOUT WORD IN ACC
STORE ACC IN LOCATION >200
BRANCH TO TRANSMIT RECEIVE ROUTINE
END
Figure 20. TMS320C25 Code for the Circuit in Figure 15
26
LTC1196/LTC1198
U
Dimension in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic SOIC
0.189 – 0.197
(4.801 – 5.004)
7
5
8
6
0.228 – 0.244
0.150 – 0.157
(5.791 – 6.197)
(3.810 – 3.988)
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
SO8 0493
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1196/LTC1198
U.S. Area Sales Offices
SOUTHWEST REGION
Linear Technology Corporation
22141 Ventura Blvd.
SOUTHEAST REGION
Linear Technology Corporation
17060 Dallas Parkway
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Phone: (214) 733-3071
FAX: (214) 380-5138
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FAX: (818) 703-0517
Phone: (215) 757-8578
FAX: (215) 757-5631
NORTHWEST REGION
Linear Technology Corporation
782 Sycamore Dr.
CENTRAL REGION
Linear Technology Corporation
Chesapeake Square
Linear Technology Corporation
266 Lowell St., Suite B-8
Wilmington, MA 01887
Milpitas, CA 95035
Phone: (408) 428-2050
FAX: (408) 432-6331
229 Mitchell Court, Suite A-25
Addison, IL 60101
Phone: (708) 620-6910
FAX: (708) 620-6977
Phone: (508) 658-3881
FAX: (508) 658-2701
International Sales Offices
JAPAN
FRANCE
TAIWAN
Linear Technology KK
5F YZ Bldg.
4-4-12 Iidabashi, Chiyoda-Ku
Tokyo, 102 Japan
Phone: 81-3-3237-7891
FAX: 81-3-3237-8010
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Immeuble "Le Quartz"
58 Chemin de la Justice
92290 Chatenay Malabry
France
Linear Technology Corporation
Rm. 801, No. 46, Sec. 2
Chung Shan N. Rd.
Taipei, Taiwan, R.O.C.
Phone: 886-2-521-7575
FAX: 886-2-562-2285
Phone: 33-1-41079555
FAX: 33-1-46314613
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UNITED KINGDOM
GERMANY
Linear Technology Korea Branch
Namsong Building, #505
Itaewon-Dong 260-199
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The Coliseum, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
Phone: 44-276-677676
FAX: 44-276-64851
Linear Techonolgy GMBH
Untere Hauptstr. 9
D-85386 Eching
Germany
Phone: 49-89-3197410
FAX: 49-89-3194821
Phone: 82-2-792-1617
FAX: 82-2-792-1619
SINGAPORE
Linear Technology Pte. Ltd.
101 Boon Keng Road
#02-15 Kallang Ind. Estates
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Phone: 65-293-5322
FAX: 65-292-0398
World Headquarters
Linear Technology Corporation
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Phone: (408) 432-1900
FAX: (408) 434-0507
08/16/93
LT/GP 0893 10K REV 0 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
28
●
●
LINEAR TECHNOLOGY CORPORATION 1993
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
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