LTC1235C [Linear]
Microprocessor Supervisory Circuit; 微处理器监控电路
| 型号： | LTC1235C |
| 厂家： | 
Linear |
| 描述： | Microprocessor Supervisory Circuit |
| 文件： | 总16页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1235
Microprocessor
Supervisory Circuit
U
DESCRIPTIO
EATURE
S
F
■
■
■
The LTC1235 provides complete power supply monitoring
and battery control functions for microprocessor reset,
battery backup, RAM write protection, power failure warn-
ing and watchdog timing. The LTC1235 has all the LTC695
features plus conditional battery backup and external reset
control. When an out-of-tolerance power supply condition
occurs, the reset outputs are forced to active states and the
Chip Enable output write-protects external memory. The
RESET output is guaranteed to remain logic low with VCC as
lowas1V.Externalresetcontrolisprovidedbyadebounced
push-button reset input.
Guaranteed Reset Assertion at VCC = 1V
1.5mA Maximum Supply Current
Fast (35ns Max.) Onboard Gating of RAM Chip
Enable Signals
Conditional Battery Backup Extends Battery Life
4.65V Precision Voltage Monitor
Power OK/Reset Time Delay: 200ms
External Reset Control
Minimum External Component Count
1µA Maximum Standby Current
Voltage Monitor for Power Fail or Low Battery
Warning
■
■
■
■
■
■
■
The LTC1235 powers the active CMOS RAMs with a charge
pumped NMOS power switch to achieve low dropout and
low supply current. When primary power is lost, auxiliary
power, connected to the battery input pin, provides backup
power to the RAMs. The LTC1235 can be programmed by
a µP signal to either back up the RAMs or not. This extends
the battery life in situations where RAM data need not
always be saved when power goes down.
■
■
■
Thermal Limiting
Performance Specified Over Temperature
All the LTC695 Features Plus Conditional Battery
Backup and External Reset Control
O U
PPLICATI
A
S
■
■
■
■
For an early warning of impending power failure, the
LTC1235 provides an internal comparator with a user-
defined threshold. An internal watchdog timer is also avail-
able, which forces the reset pins to active states when the
watchdog input is not toggled prior to the time-out period.
Critical µP Power Monitoring
Intelligent Instruments
Battery-Powered Computers and Controllers
Automotive Systems
U
O
TYPICAL APPLICATI
Battery Life vs
Backup Duty Cycle
10
LT1086-5
V
≥ 7.5V
9
IN
+5V
+
LTC1235
POWER TO
µP
V
V
OUT
V
V
V
IN
CC
OUT
8
7
6
5
4
3
2
+
CMOS RAM POWER
0.1µF
0.1µF
100µF
10µF
51k
ADJ
LTC1235
I/O LINE
BACKUP
RESET
BATT
+3V
LTC695
µP RESET
(WITHOUT
CONDITIONAL
BATTERY
BACKUP)
µP
SYSTEM
µP NMI
PFO
WDI
PFI
PB RST
I/O LINE
10k
1
0
LTC1235 TA1
0
20
40
60
80
100
BACKUP DUTY CYCLE (%)
THE LTC1235 EXTENDS BATTERY LIFE BY PROVIDING BATTERY POWER ONLY WHEN REQUIRED TO BACK UP RAM DATA.
IT SAVES THE BATTERY WHEN NO DATA BACKUP IS NEEDED. THE µP REQUESTS BACKUP WITH THE BACKUP PIN.
LTC1235 TA02
1
LTC1235
W W W
U
(Notes 1 and 2)
ABSOLUTE AXI U RATI GS
Terminal Voltage
VOUT Output Current .................. Short Circuit Protected
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1235C ............................................ 0°C to 70°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
VCC .................................................... –0.3V to 6.0V
BATT................................................. –0.3V to 6.0V
All Other Inputs.................... –0.3V to (VCC + 0.3V)
Input Current
CC .............................................................. 200mA
VBATT............................................................. 50mA
V
V
W
U
/O
PACKAGE RDER I FOR ATIO
(Note 3)
TOP VIEW
LTC1235
ORDER PART
NUMBER
ORDER PART
TOP VIEW
V
NUMBER
1
2
3
4
16 PRESET
BATT
V
1
2
RESET
RESET
WDO
16
15
14
13
BATT
V
15
14
13
12
11
10
9
PRESET
WDO
OUT
V
OUT
V
LTC1235CN
LTC1235CS
CC
V
3
4
5
6
7
8
CC
GND
CE IN
CE OUT
WDI
GND
CE IN
BATT ON
LOW LINE
PB RST
5
6
LTC1235
BATT ON
LOW LINE
PB RST
12
CE OUT
11 WDI
PFO
7
8
PFO
PFI
10
9
PFI
BACKUP
BACKUP
S PACKAGE
N PACKAGE
16-LEAD PLASTIC SOL
16-LEAD PLASTIC DIP
TJMAX = 110°C, θJA = 130°C/W
TJMAX = 110°C, θJA = 130°C/W
CONDITIONS: PCB MOUNT ON FR4 MATERIAL,
STILL AIR AT 25°C, COPPER TRACE
U
PRODUCT SELECTIO GUIDE
CONDITIONAL
BATTERY
BACKUP
WATCHDOG
TIMER
BATTERY
BACKUP
POWER FAIL
WARNING
RAM WRITE
PROTECT
PUSH-BUTTON
PINS
RESET
RESET
LTC1235
LTC690
LTC691
LTC694
LTC695
LTC699
LTC1232
16
8
16
8
16
8
8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
LTC1235
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITONS
MIN
TYP
MAX
UNITS
Battery Backup Switching
Operating Voltage Range
V
V
4.75
2.00
5.50
4.25
V
V
CC
BATT
V
Output Voltage
I
I
= 1mA
V
V
– 0.05
V
V
– 0.005
– 0.005
OUT
OUT
OUT
CC
CC
CC
●
– 0.1
CC
= 50mA
V
– 0.5
V
– 0.25
CC
CC
BACKUP Input Threshold
V
> Reset Voltage Threshold
Logic Low
CC
0.8
V
Logic High
2.0
BACKUP Pullup Current (Note 4)
3
– 0.02
µA
V
V
V
in Battery Backup Mode (Note 5)
in Battery Saving Mode (Note 5)
I
= 250µA, V < V
V
– 0.1
V
BATT
OUT
OUT
OUT
CC
BATT
BATT
V
< V
0
V
CC
BATT
1MΩ Pulldown on V
OUT
V
Supply Current (excluding I
)
I ≤ 50mA
OUT
0.6
0.6
1.5
2.5
mA
µA
CC
OUT
●
●
●
Battery Supply Current in Battery Backup Mode and
Battery Saving Mode (Note 5)
V
= 0V, V
= 2.8V
BATT
0.04
0.04
1
5
CC
Battery Standby Current
5.5 > V > V
+ 0.2V
BATT
–0.1
–1.0
+0.02
+0.10
µA
CC
(+ = Discharge, – = Charge)
Battery Switchover Threshold
Power Up
Power Down
70
50
mV
V
– V
CC
BATT
Battery Switchover Hysteresis
20
mV
V
BATT ON Output Voltage (Note 6)
BATT ON Output Short Circuit Current (Note 6)
I
= 3.2mA
0.4
25
SINK
BATT ON = V
BATT ON = 0V Source Current
Sink Current
35
1
mA
µA
OUT
0.5
Push-Button Reset
PB RST Input Threshold
Logic Low
Logic High
0.8
V
2.0
40
PB RST Input Low Time (Notes 4, 7)
Reset and Watchdog Timer
Reset Voltage Threshold
Reset Threshold Hysteresis
Reset Active Time
●
●
ms
4.5
4.65
40
4.75
V
mV
ms
V
V
= 5V
= 5V
160
140
200
200
240
280
CC
CC
●
●
Watchdog Time-out Period
1.2
1.0
1.6
1.6
2.00
2.25
sec
Reset Active Time PSRR
1
8
ms/V
ms/V
ns
Watchdog Time-out Period PSRR
Minimum WDI Input Pulse Width
V
= 0.4V, V = 3.5V
●
200
3.5
IL
IH
RESET Output Voltage At V = 1V
I
= 10µA, V = 1V
4
200
0.4
mV
V
CC
SINK
CC
RESET and LOW LINE Output Voltage
(Note 6)
I
I
= 1.6mA, V = 4.25V
SINK CC
SOURCE
= 1µA, V = 5V
CC
3
LTC1235
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITONS
= 1.6mA, V = 5V
MIN
TYP
MAX
UNITS
RESET and WDO Output Voltage
(Note 6)
I
0.4
V
SINK
SOURCE
CC
= 1µA, V = 4.25V
3.5
1
CC
RESET, RESET, WDO, LOW LINE
Output Short Circuit Current (Note 6)
Output Source Current
Output Sink Current
3
25
25
0.8
50
µA
mA
WDI Input Threshold
Logic Low
Logic High
V
2.0
WDI Input Current
WDI = V
●
●
4
–8
µA
OUT
WDI = 0V
–50
Power Fail Detector
PFI Input Threshold
V
CC
= 5V
●
1.25
1.3
0.3
1.35
V
mV/V
nA
PFI Input Threshold PSRR
PFI Input Current
±0.01
±25
PFO Output Voltage (Note 6)
I
I
= 3.2mA
SOURCE
0.4
V
SINK
= 1µA
3.5
1
PFO Short Circuit Source Current
(Note 6)
PFI = HIGH, PFO = 0V
PFI = LOW, PFO = V
3
30
25
µA
mA
OUT
PFI Comparator Response Time (falling)
∆V = –20mV, V = 15mV
2
µs
µs
IN
OD
PFI Comparator Response Time (rising)
(Note 6)
∆V = 20mV, V = 15mV
40
8
IN
OD
with 10kΩ Pullup
Chip Enable Gating
CE IN Threshold
V
V
0.8
0.4
V
IL
IH
2.0
CE IN Pullup Current (Note 4)
CE OUT Output Voltage
3
µA
I
I
I
= 3.2mA
V
SINK
SOURCE
SOURCE
= 3.0mA
V
V
– 1.50
OUT
OUT
= 1µA, V = 0V
– 0.05
CC
CE Propagation Delay
V
CC
= 5V, C = 20pF
20
20
35
45
ns
L
●
CE OUT Output Short Circuit Current
Output Source Current
Output Sink Current
30
35
mA
The
range.
●
denotes specifications which apply over the operating temperature
in Battery Backup Mode and will be switched to V
when V falls
CC
BATT
below V
. If the latched logic level of the BACKUP pin is low, V
BATT
will
OUT
be in Battery Saving Mode when V falls below V
.
Note 1: Absolute maximum ratings are those values beyond which the life
CC
BATT
of device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range parts, consult the factory.
Note 6: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pullups of typically 3µA. However, external
pullup resistors may be used when higher speed is required.
Note 7: The push-button reset input requires an active low signal.
Internally, this input signal is debounced and timed for a minimum of
40ms. When this condition is satisfied, the reset outputs go to the active
states. The reset outputs will remain in active states for a minimum of
140ms from the moment the push-button reset input is released from
logic low level.
Note 4: The input pins of PB RST, BACKUP and CE IN, have weak internal
pullups which pull to the supply when the input pins are floating.
Note 5: The LTC1235 can be programmed either to provide or not to
provide battery backup power to the V
pin during power failure. The
OUT
power down condition of V
is selected by the logic level of the BACKUP
OUT
pin which is latched internally when V falls through the reset voltage
CC
threshold. If the latched logic level of the BACKUP pin is high, V
will be
OUT
4
LTC1235
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Power Failure Input Threshold
vs Temperature
VOUT vs IOUT
VOUT vs IOUT
5.00
2.80
2.78
2.76
2.74
2.72
1.308
1.306
V
V
T
= 0V
V
CC
= 5V
V
V
T
= 5V
CC
BATT
A
CC
BATT
= 25
= 2.8V
= 25
= 2.8V
°
C
°
C
4.95
4.90
A
1.304
1.302
1.300
1.298
1.296
1.294
BACKUP MODE
SELECTED
SLOPE = 125Ω
SLOPE = 5Ω
4.85
4.80
4.75
0
10
20
30
40
50
0
100
200
300
400
500
50
TEMPERATURE (
100 125
–50 –25
0
25
75
C)
LOAD CURRENT (mA)
LOAD CURRENT (µA)
˚
LTC1235 G01
LTC1235 G02
LTC1235 G03
RESET Output Voltage vs Supply
Voltage
Reset Voltage Threshold
vs Temperature
Reset Active Time vs
Temperature
4.66
5
232
224
216
208
V
= 5V
T
= 25°C
CC
A
EXTERNAL PULLUP = 10µA
= 0V
4.65
4.64
4.63
4.62
V
4
3
BATT
2
1
0
200
192
184
4.61
4.60
50
TEMPERATURE (
100 125
–50 –25
0
25
75
C)
0
1
2
3
4
5
50
TEMPERATURE (
100 125
–50 –25
0
25
75
C)
°
SUPPLY VOLTAGE (V)
°
LTC1235 G04
LTC1235 G06
LTC1235 G05
Power Fail Comparator
Response Time
Power Fail Comparator
Response Time
Power Fail Comparator Response
Time with Pullup Resistor
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
T
= 5V
V
T
= 5V
V
T
= 5V
CC
A
CC
A
CC
A
= 25°C
= 25
°
C
= 25°C
V
+
–
PFI
PFO
1.3V
V
+
–
30pF
PFI
PFO
+5V
10k
1.3V
30pF
V
+
–
PFI
PFO
12
1.3V
30pF
1.315V
1.295V
1.315V
1.295V
1.305V
1.285V
V
= 20mV STEP
V
= 20mV STEP
V
= 20mV STEP
PFI
PFI
4
PFI
2
14
140
0
6
16 18
0
60
120
160 180
2
8
10
0
1
3
4
5
7
8
20 40
80 100
6
TIME (µs)
TIME (µs)
TIME (µs)
LTC1235 G09
LTC1235 G08
LTC1235 G07
5
LTC1235
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PI FU CTIO S
PFI: Power Failure Input. PFI is the noninverting input to
the Power Fail Comparator, C3. The inverting input is
internallyconnectedtoa1.3Vreference.ThePowerFailure
Output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or VOUT when
C3 is not used.
VCC: +5V supply input. The VCC pin should be bypassed
with a 0.1µF capacitor.
Backup: Logic input to control the PMOS switch, M2,
when VCC is lower than VBATT. While VCC is falling through
the reset voltage threshold, the status of the BACKUP pin
(logic low or logic high) is latched in Memory Logic and
used to turn on or off M2 when VCC is below VBATT. If the
latched status of the BACKUP pin is high, the Memory
Logic turns on M2 when VCC falls to 50mV greater than
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
VBATT. If the latched status of the BACKUP pin is low, the
Memory Logic keeps M2 off even after VCC falls below
VBATT.IftheBACKUPpinisleftfloatingitwillbepulledhigh
by an internal pullup and the LTC1235 will provide battery
backup when VCC falls.
PB RST: Logic input for direct connection to a push-
button. The push-button reset input requires an active low
signal. Internally, thisinputsignalisdebouncedandtimed
for a minimum of 40ms. When this condition is satisfied,
the reset pulse generator forces RESET to active low. The
RESET signal will remain active low for a minimum of
140ms from the moment the push-button reset input is
released from logic low level.
VOUT: Voltage output for backed up memory. Bypass with
a capacitor of 0.1µF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch,M1,whichcandeliverupto50mAandhasatypical
on resistance of 5Ω. When VCC is lower than VBATT, the
statusoftheBACKUPpinstoredinMemoryLogiccontrols
M2. If the status is high, the Memory Logic turns on M2
and VOUT is internally switched to VBATT through M2. If the
status is low, the Memory Logic keeps M2 off and VOUT is
in Battery Saving Mode. If VOUT and VBATT are not used,
connect VOUT to VCC.
RESET: Logic output for µP reset control. The LTC1235
provides three ways to generate µP reset. First, whenever
VCC falls below either the reset voltage threshold (4.65V,
typically) or VBATT, RESET goes active low. After VCC
returns to 5V, the reset pulse generator forces RESET to
remainactivelowforaminimumof140ms. Second, when
the watchdog timer is enabled but not serviced prior to the
time-out period, the reset pulse generator also forces
RESET to active low for a minimum of 140ms for every
time-out period (see Figure 11). Third, when the PB RST
pin stays active low for a minimum of 40ms, RESET is
forced low by reset pulse generator. The RESET signal will
remain active low for a minimum of 140ms from the
momentthepush-buttonresetinputisreleasedfromlogic
low level.
VBATT: Backup battery input. When VCC falls below VBATT
,
the status of the BACKUP pin stored in the Memory Logic
controlsM2.Ifthestatusishigh,auxiliarypower,connected
to VBATT is delivered to VOUT through M2. If the status is
low, theMemoryLogickeepsM2 offandVOUT is inBattery
Saving Mode. If backup battery or auxiliary power is not
used, VBATT should be connected to GND.
GND: Ground pin.
RESET: RESET is an active high logic output. It is the
inverse of RESET.
BATT ON: Battery on logic output from comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC.Theoutputtypicallysinks35mAandcanprovidebase
drive for an external PNP transistor to increase the output
current above the 50mA rating of VOUT. BATT ON goes
high when VCC falls below VBATT, if the status of the
BACKUP pin stored in Memory Logic is high and VOUT is
LOW LINE: Logic output from comparator C1. LOW LINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (4.65V typically),
LOW LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when VCC drops below VBATT (see
Table 1).
switched to VBATT
.
6
LTC1235
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PI FU CTIO S
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog time-
outperiod,forcesbothRESETandWDOlow.FloatingWDI
disables the Watchdog Timer. The timer resets itself with
each transition of the Watchdog Input (see Figure 11).
CE IN: Logic input to the Chip Enable gating circuit. CE IN
canbederivedfrommicroprocessor'saddresslineand/or
decoderoutput. SeeApplicationsInformationSectionand
Figure 6 for additional information.
CE OUT: Logic output from the Chip Enable gating circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 6).
WDO: Watchdog logic output. When the watchdog input
remains either high or low for longer than the watchdog
time-outperiod,WDOgoeslow.WDOissethighwhenever
thereisatransitionontheWDIpin,orLOWLINEgoeslow.
The watchdog timer can be disabled by floating WDI (see
Figure 11).
W
BLOCK DIAGRA
M2
V
V
BATT
OUT
M1
V
CC
BACKUP
MEMORY
LOGIC
CHARGE
PUMP
–
BATT ON
C2
+
LOW LINE
+
C1
–
CE OUT
1.3V
GND
CE IN
PFI
–
+
PFO
OSC
RESET
RESET
LEVEL SENSE
AND
RESET PULSE
PB RST
WDI
GENERATOR
DEBOUNCE
TRANSITION
DETECTOR
WATCHDOG
TIMER
WDO
LTC1235 BD
7
LTC1235
PPLICATI
O U
W
U
A
S I FOR ATIO
Power Monitoring
To help prevent mistriggering due to transient loads, VCC
pin should be bypassed with a 0.1µF capacitor with the
leads trimmed as short as possible.
The LTC1235 uses a bandgap voltage reference and a
precision voltage comparator C1 to monitor the 5V supply
input on VCC (see BLOCK DIAGRAM). When VCC falls
below the reset voltage threshold, the reset outputs are
forced to active states. The reset voltage threshold ac-
counts for a 5% variation on VCC, so the reset outputs
becomeactivewhenVCC fallsbelow4.75V(4.65Vtypical).
On power-up, the reset signals are held active states for a
minimum of 140ms after the reset voltage threshold is
reached to allow the power supply and microprocessor to
stabilize. On power-down, the RESET signal remains ac-
tive low even with VCC as low as 1V. This capability helps
hold the microprocessor in stable shutdown condition.
Figure 1 shows the timing diagram of the RESET signal.
LOW LINE is the output of the precision voltage compara-
tor C1. When VCC falls below the reset voltage threshold,
LOW LINE goes low. LOW LINE returns high as soon as
VCC rises above the reset voltage threshold.
Push-Button Reset
The LTC1235 provides an logic input pin for direct
connectiontoapush-button. Thepush-buttonresetinput,
PBRST, requiresanactivelowsignal. Internally, thisinput
signal is debounced and timed for a minimum of 40ms.
When this condition is satisfied, the reset pulse generator
forces the reset outputs to active states. The reset signals
will remain in active states for a minimum of 140ms from
the moment the push-button reset input is released from
logic low level (Figure 2).
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at VCC pin do not
activatetheresetoutputs.Responsetimeistypically10µs.
V2
V2
V1
V1
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
V
CC
RESET THRESHOLD HYSTERESIS
RESET
t1
t1
t1 = RESET ACTIVE TIME
LOW LINE
LTC1235 F01
Figure 1. Reset Active Time
V
= 5V
CC
t1
LOGIC
HIGH
PB RST
LOGIC LOW
t2
RESET
RESET
LOGIC HIGH
LOGIC LOW
t1 = PUSH-BUTTON RESET LOW TIME
t2 = RESET ACTIVE TIME
Figure 2. Push-Button Reset
8
LTC1235
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PPLICATI
A
S I FOR ATIO
Voltage Output
uses a charge pumped NMOS power switch to eliminate
unwanted charging current while achieving low dropout
and low supply current. Since no current goes to the
substrate, the current collected by VBATT pin is strictly
junction leakage.
During normal operation, the LTC1235 uses a charge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
50mA to VOUT from VCC and has a typical on resistance of
5Ω. The VOUT pin should be bypassed with a capacitor of
0.1µF or greater to ensure stability. Use of a larger bypass
capacitor is advantageous for supplying current to heavy
transient loads.
Conditional Battery Backup
LTC1235 provides an unique feature to either allow VOUT
to be switched to VBATT or to disable the CMOS RAM
battery backup function when primary power is lost.
Disabling the battery backup function is useful in conserv-
ing the backup battery's life when the SRAM doesn't need
battery backup during long term storage of a computer
system, or delivery of the computer system to the end
user.
When operating currents larger than 50mA are required
from VOUT, or a lower dropout (VCC - VOUT voltage differ-
ential) is desired, the LTC1235 provides BATT ON output
to drive the base of external PNP transistor (Figure 3).
Another alternative to provide higher current is to connect
a high current Schottky diode from the VCC pin to the VOUT
pin to supply the extra current.
The BACKUP pin (Pin 8) is used to serve this feature on
power-down.WhenVCC isfallingthroughtheresetvoltage
threshold, the status of the BACKUP pin (logic low or logic
high) is stored in the Memory Logic (see BLOCK DIA-
GRAM). If the stored status is logic high and VCC fall to
50mV greater than VBATT, a 125Ω PMOS switch, M2,
connectstheVBATTinputtoVOUT andthebatteryswitchover
comparator, C2, shuts off the NMOS power switch, M1.
M2 is designed for very low dropout voltage (input-to-
output differential). This feature is advantageous for low
currentapplicationssuchasbatterybackupinCMOSRAM
and other low power CMOS circuitry. If the stored status
is logic low and VCC falls to 50mV greater than VBATT, the
Memory Logic keeps M2 off and C2 shuts off M1. VOUT is
in Battery Saving Mode (see Figure 4). The supply current
in both mode is 1µA maximum.
ANY PNP POWER TRANSISTOR
R1
BATT ON
+5V
0.1µF
V
OUT
V
CC
0.1µF
LTC1235
V
BATT
GND
+3V
LTC1235 F03
Figure 3. Using BATT ON to Drive External PNP Transistor
The LTC1235 is protected for safe area operation with
short circuit limit. Output current is limited to approxi-
mately200mA.Ifthedeviceisoverloadedforalongperiod
of time, thermal shutdown turns the power switch off until
the device cools down. The threshold temperature for
thermal shutdown is approximately 155°C with about
10°C of hysteresis which prevents the device from oscil-
lating in and out of shutdown.
On power-ups, C2 keeps M1 off before VCC reaches 70mV
higher than VBATT. On the first power-up after the battery
is replaced (with power off), the status stored in the
Memory Logic is undetermined. VOUT could be either in
Battery Backup Mode or in Battery Saving Mode. When
VCC is70mVgreaterthanVBATT, M1connectsVOUT toVCC.
C2 has typically 20mV of hysteresis to prevent spurious
switching when VCC remains nearly equal to VBATT and the
status stored in the Memory Logic is high. The response
time of C2 is approximately 20µs.
The PNP switch was not chosen for the internal power
switch because it injects unwanted current into the sub-
strate. This current is collected by the VBATT pin in com-
petitive devices and adds to the charging current of the
battery which can damage lithium batteries. LTC1235
9
LTC1235
PPLICATI
O U
W
U
A
S I FOR ATIO
V
OUT
IN BATTERY SAVING MODE
Replacing the Backup Battery with Power On
When changing the backup battery with system power on,
spurious resets can occur while battery is removed due to
battery standby current. Although battery standby current
isonlyatinyleakagecurrent, itcanstillchargeupthestray
capacitance on the VBATT pin. The oscillation cycle is as
follows: When VBATT reaches within 50mV of VCC, the
LTC1235 switches to battery backup or battery saving
mode. In either case, the battery supply current pulls
BACKUP
LOGIC LOW
RESET VOLTAGE THRESHOLD
V
CC
V
BATT
V
OUT
Hi-Z
VBATT low and the device goes back to normal operation.
The leakage current then charges up the VBATT pin again
and the cycle repeats.
V
IN BATTERY BACKUP MODE
OUT
LOGIC
HIGH
BACKUP
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, two
methods can be used to eliminate this problem. First, a
capacitor from VBATT to GND will allow time for battery
replacement by slowing the charge rate. For example, the
battery standby current is 1µA maximum over tempera-
ture and the external capacitor required to slow the charge
RESET VOLTAGE THRESHOLD
V
CC
V
BATT
V
OUT
V
= V
BATT
OUT
rate is:
LTC1235 F04
1µA
C
≥ T
REQ'D
EXT
V – V
Figure 4. Conditional Battery Backup Operation
CC
BATT
where TREQ'D is the maximum time required to replace the
backup battery. With VCC = 4.5V, VBATT = 3V and TREQ'D
3 sec, the value for external capacitor is 2µF. Second, a
resistor from VBATT to GND will hold the pin low while
changing the battery. For example, the battery standby
current is 1µA maximum over temperature and the exter-
nal resistor required to hold VBATT below VCC is:
The operating voltage at the VBATT pin ranges from 2.0V to
4.25V. Highvaluecapacitors, suchaselectrolyticorfarad-
size double layer capacitors, can be used for short term
memorybackupinsteadofabattery.Forcapacitorbackup,
see Typical Applications. The charging resistor for re-
charging rechargeable batteries should be connected to
VOUT through a diode since this eliminates the discharge
paththatexistswhenVCCcollapsesandRAMisnotbacked
up (Figure 5).
=
V – 50mV
CC
R ≤
1µA
With VCC = 4.5V, a 4.3MΩ resistor will work. With a 3V
battery, thisresistorwilldrawonly0.7µAfromthebattery,
which is negligible in most cases.
V
OUT
– V
R
– V
BATT D
I =
1N4148
R
+5V
0.1µF
V
V
OUT
If the battery connections are made with long wires or PC
traces, inductive spikes can be generated during battery
replacement. Even if a resistor is used to prevent spurious
resets as describedabove, these spikescan take the VBATT
pin below GND violating the LTC1235 absolute maximum
ratings. A 0.1µF capacitor from VBATT to GND is recom-
mended to eliminate these potential spikes when battery
replacement is made through long wires.
CC
RAM
0.1µF
LTC1235
BACKUP
I/O LINE
µP
V
BATT
GND
4
+3V
LTC1235 F05
Figure 5. Charging External Battery Through VOUT
10
LTC1235
O U
W
U
PPLICATI
A
S I FOR ATIO
Table 1 shows the state of each pin during battery backup.
If the backup battery is not used, connect VBATT to GND
and VOUT to VCC.
IN and CE OUT, control the Chip Enable or Write inputs of
CMOS RAM. When VCC is +5V, CE OUT follows CE IN with
a typical propagation delay of 20ns. When VCC falls below
the reset voltage threshold or VBATT, CE OUT is forced
high, independent of CE IN. CE OUT is an alternative signal
to drive the CE, CS, or Write input of battery-backed up
CMOS RAM. CE OUT can also be used to drive the Store
or Write input of an EEPROM, EAROM or NOVRAM to
achieve similar protection. Figure 6 shows the timing
diagram of CE IN and CE OUT.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL
STATUS
V
CC
C2 monitors V for active switchover.
CC
BACKUP
BACKUP is ignored.
V
V
V
is connected to V
through an internal PMOS switch.
OUT
OUT
BATT
The supply current is 1µA maximum.
BATT
BATT ON Logic high. The open circuit output voltage is equal to V
.
.
OUT
CE IN can be derived from the microprocessor’s address
decoder output. Figure 7 shows a typical nonvolatile
CMOS RAM application.
PFI
Power Failure Input is ignored.
PFO
Logic low
PB RST
RESET
RESET
PB RST is ignored.
Logic low
Logic high. The open circuit output voltage is equal to V
OUT
V
V
V
+5V
0.1µF
CC
OUT
CC
+
0.1µF
LOW LINE Logic low
10µF
62512
RAM
LTC1235
WDI
Watchdog Input is ignored.
CE OUT
CS
GND
WDO
CE IN
CE OUT
Logic high. The open circuit output voltage is equal to V
Chip Enable Input is ignored.
.
.
OUT
20ns PROPAGATION DELAY
FROM DECODER
V
BATT
CE IN
BACKUP
+3V
Logic high. The open circuit output voltage is equal to V
OUT
GND
RESET
LTC1235 F06
TO µP
Memory Protection
Figure 7. A Typical Nonvolatile CMOS RAM Application
The LTC1235 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when VCC is at invalid level. Two pins, CE
BACKUP = V
CC
V2
V
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CC
V1
CE IN
V
= V
BATT
OUT
CE OUT
V
= V
BATT
OUT
LTC1235 F06
Figure 6. Timing Diagram for CE IN and CE OUT
11
LTC1235
PPLICATI
O U
W
U
A
S I FOR ATIO
Power Fail Warning
R1
R3
V
= 5V
= 850mV
HYSTERESIS
The LTC1235 generates a Power Failure Output (PFO) for
early warning of failure in the microprocessor's power
supply. This is accomplished by comparing the Power
Failure Input (PFI) with an internal 1.3V reference. PFO
goes low when the voltage at PFI pin is less than 1.3V.
Typically PFI is driven by an external voltage divider (R1
and R2 in Figures 8 and 9) which senses either an
unregulatedDCinputoraregulated5Voutput.Thevoltage
divider ratio can be chosen such that the voltage at PFI pin
falls below 1.3V several milliseconds before the +5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microproces-
sor to execute shut-down procedure between PFO and
RESET or RESET.
R3 ≈ 5.88 R1
Choose R3 = 300kΩ and R1 = 51kΩ. Also select R4 =
10kΩ which is much smaller than R3.
51kΩ (5V – 1.3V)51kΩ
R2
7.5V = 1.3V 1+
–
1.3V(310kΩ)
R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalcu-
late VL,
51kΩ (5V – 1.3V)51kΩ
V = 1.3V 1+
–
= 7.32V
L
10kΩ
1.3V(310kΩ)
51kΩ 51kΩ
+
The power fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
V = 1.3V 1+
= 8.151V
H
10kΩ 300kΩ
(7.32V – 6.25V)
100mV/ms
= 10.7ms
VHYSTERESIS = 8.151V – 7.32V = 831mV
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
LT1086-5
V
≥ 7.5V
IN
+5V
V
V
R1 R1
R2 R3
IN
V
OUT
CC
V = 1.3V 1+
+
+
+
H
0.1µF
R4
10k
10µF
100µF
ADJ
LTC1235
R3
300k
R1
51k
WhenPFOoutputishigh,theseriescombinationofR3and
R4 source current into the PFI summing junction.
BACKUP
PFI GND
PFO
TO µP
R2
10k
R1 (5V – 1.3V)R1
R2 1.3V(R3 +R4)
LTC1235 F07
V = 1.3V 1+
–
L
Figure 8. Monitoring Unregulated DC Supply with the
LTC1235 Power Fail Comparator
R1
R3
Assuming R4«R3,V
= 5V
HYSTERESIS
LT1086-5
V
≥ 6.5V
0.1µF
10µF
IN
+5V
R4
V
V
V
CC
OUT
IN
ADJ
+
+
Example1:Thecircuit in Figure 8demonstratesthe use of
the power fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supplyinputVIN is100mV/msandthetotaltimetoexecute
a shut-down procedure is 8ms. Also the noise of VIN is
200mV. With these assumptions in mind, we can reason-
ably set VL = 7.5V which 1.25V greater than the sum of
maximum reset voltage threshold and the dropout voltage
of LT1086-5 (4.75V + 1.5V) and VHYSTERESIS = 850mV.
R1
10µF
10k
27k
LTC1235
R3
2.7M
BACKUP
PFO
PFI GND
TO µP
R2
8.2k
LTC1235 F08
R5
3.3k
Figure 9. Monitoring Regulated DC Supply with the LTC1235
Power Fail Comparator
12
LTC1235
O U
W
U
PPLICATI
A
S I FOR ATIO
The 10.7ms allows enough time to execute shut-down
procedure for microprocessor and 831mV of hysteresis
would prevent PFO from going low due to the noise of VIN.
watchdog time-out period and reset active time. The
watchdog time-out period is restarted as soon as the reset
outputs are inactive. When either a high-to-low or low-to-
high transition occurs at the WDI pin prior to time-out, the
watchdog time is reset and begins to time out again. To
ensure the watchdog time does not time out, either a high-
to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum time-out period. If the
input to the WDI pin remains either high or low, reset
pulses will be issued every 1.6 seconds typically. The
watchdogtimercanbedeactivatedbyfloatingtheWDIpin.
The timer is also disabled when VCC falls below the reset
Example 2: The circuit in Figure 9 can be used to measure
the regulated 5V supply to provide early warning of power
failure. Because of variations in the PFI threshold, this
circuit requires adjustment to ensure that the PFI com-
parator trips before the reset threshold is reached. Adjust
R5suchthatthePFOoutputgoeslowwhentheVCC supply
reaches the desired level (e.g., 4.85V).
Monitoring the Status of the Battery
voltage threshold or VBATT
.
C3 can also monitor the status of the memory backup
battery (Figure 10). If desired, the CE OUT can be used to
applyatestloadtothebattery.SinceCEOUTisforcedhigh
in battery backup mode, the test load will not be applied to
the battery while it is in use, even if the microprocessor is
not powered.
The Watchdog Output, WDO, goes low if the watchdog
timer is allowed to time out and remains low until set high
by the next transition on the WDI pin. WDO is also set high
when VCC falls below the reset voltage threshold or VBATT
.
+5V
V
BATT
Watchdog Timer
LOW BATTERY SIGNAL
TO µP I/O PIN
PFO
R1
1M
The LTC1235 provides a watchdog timer function to
monitor the activity of the microprocessor. If the micro-
processor does not toggle the Watchdog Input (WDI)
within the time-out period, the reset outputs are forced to
active states for a minimum of 140ms. The watchdog
time-out period is fixed at 1.0 second minimum on the
LTC1235. Thistime-outperiodprovidesadequatetimefor
many systems to service the watchdog timer immediately
after a reset. Figure 11 shows the timing diagram of
LTC1235
PFI
BACKUP
CE IN
R2
1M
+3V
TO µP I/O PIN
}
CE OUT
GND
RL 20K
OPTIONAL TEST LOAD
LTC1235 F09
Figure 10. Backup Battery Monitor with Optional Test Load
V
= 5V
CC
WDI
t1 = RESET ACTIVE TIME
t2 = WATCHDOG TIME-OUT PERIOD
WDO
t2
t2
t1
RESET
t1
t1
LTC1235 F11
Figure 11. Watchdog Time-out Period and Reset Active Time
13
LTC1235
TYPICAL APPLICATI S
U
O
Capacitor Backup with 74HC4016 Switch
Write Protect for Additional RAMs
0.1µF
V
V
+5V
V
+5V
OUT
CC
CC
+
V
62512
V
10µF
CC
0.1µF
OUT
LTC1235
RAM
A
0.1µF
0.1µF
CS
CE OUT
R1
10k
10 11 12 14
20ns PROPAGA-
TION DELAY
LTC1235
V
BATT
2
1
BACKUP
CE IN
V
LOW LINE
74HC4016
BATT
+3V
LOW LINE
R2
30k
7
13
100µF
GND
+
0.1µF
0.1µF
GND
V
CC
62128
RAM
B
CS
CS
B
A
CS
1
LTC1235 TA3
CS
2
CS
C
V
CC
62128
µP
SYSTEM
RAM
C
CS
1
CS
2
OPTIONAL CONNECTION FOR
ADDITIONAL RAMs
LTC1235 TA4
14
LTC1235
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N Package
16-Lead Plastic DIP
0.770
(19.558)
12
14
13
10
9
8
16
15
11
0.260 ± 0.010
(6.604 ± 0.254)
2
1
3
4
5
6
7
0.300 – 0.325
0.130 ± 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 ± 0.127)
(1.143 – 1.651)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.009 - 0.015
(0.229 - 0.381)
+0.025
–0.015
0.325
0.125
(3.175)
MIN
0.045 ± 0.015
(1.143 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
N16 1291
SO Package
16-Lead SOIC
0.398 – 0.413
(10.109 – 10.490)
15 14
12
10
9
16
13
11
0.394 – 0.419
(10.008 – 10.643)
SEE NOTE
2
3
5
7
8
1
4
6
0.291 – 0.299
(7.391 – 7.595)
0.005
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
(0.127)
0.010 – 0.029
(0.254 – 0.737)
× 45°
RAD MIN
0° – 8° TYP
0.050
(1.270)
TYP
0.009 – 0.013
0.004 – 0.012
(0.229 – 0.330)
(0.102 – 0.305)
SEE NOTE
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
(0.356 – 0.483)
TYP
SOL16 12/91
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
15
LTC1235
U.S. Area Sales Offices
NORTHEAST REGION
Linear Technology Corporation
One Oxford Valley
CENTRAL REGION
Linear Technology Corporation
Chesapeake Square
NORTHWEST REGION
Linear Technology Corporation
782 Sycamore Dr.
2300 E. Lincoln Hwy.,Suite 306
Langhorne, PA 19047
Phone: (215) 757-8578
FAX: (215) 757-5631
229 Mitchell Court, Suite A-25
Addison, IL 60101
Phone: (708) 620-6910
FAX: (708) 620-6977
Milpitas, CA 95035
Phone: (408) 244-2050
FAX: (408) 432-6331
SOUTHEAST REGION
Linear Technology Corporation
17060 Dallas Parkway
Suite 208
SOUTHWEST REGION
Linear Technology Corporation
22141 Ventura Blvd.
Suite 206
Dallas, TX 75248
Phone: (214) 733-3071
FAX: (214) 380-5138
Woodland Hills, CA 91364
Phone: (818) 703-0835
FAX: (818) 703-0517
International Sales Offices
FRANCE
KOREA
UNITED KINGDOM
Linear Technology S.A.R.L.
"Le Quartz"
58 Chemin de la Justice
92290 Chatenay Mallabry
France
Linear Technology Korea Branch
Namsong Building, #505
Itaewon-Dong 260-199
Yongsan-Ku, Seoul
Korea
Linear Technology (UK) Ltd.
The Coliseum, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
Phone: 011-44-276-677676
FAX: 011-44-276-64851
Phone: 33-1-46316161 (170)
FAX: 33-1-46314613
Phone: 82-2-792-1617
FAX: 82-2-792-1619
JAPAN
TAIWAN
GERMANY
Linear Technology KK
4F Ichihashi Building
1-8-4 Kudankita Chiyoda-Ku
Tokoyo, 102 Japan
Phone: 81-3-3237-7891
FAX: 81-3-3237-8010
Linear Technology Corporation
Rm. 801, No. 46, Sec. 2
Chung Shan N. Rd.
Taipei, Taiwan, R.O.C.
Phone: 886-2-521-7575
FAX: 886-2-521-7575
Linear Technology GMBH
Untere Hauptstr. 9
D-8057 Eching
Germany
Phone: 49-89-3195023
Telex: 17-897457
FAX: 49-89-3194821
SINGAPORE
Linear Technology PTE. LTD.
101 Boon Keng Road
#02-15 Kallang Ind. Estates
Singapore 1233
Phone: 65-293-5322
FAX: 65-292-0398
World Headquarters
Linear Technology Corporation
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Phone: (408) 432-1900
FAX: (408) 434-0507
01/21/92
LT/GP 0192 10K REV 0
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
16
●
●
LINEAR TECHNOLOGY CORPORATION 1992
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
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