LTC1257IS8 [Linear]
Complete Single Supply 12-Bit Voltage Output DAC in SO-8; 完整的单电源， 12位电压输出DAC，采用SO- 8
| 型号： | LTC1257IS8 |
| 厂家： | 
Linear |
| 描述： | Complete Single Supply 12-Bit Voltage Output DAC in SO-8 |
| 文件： | 总12页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1257
Complete Single Supply
12-Bit Voltage Output
DAC in SO-8
U
DESCRIPTIO
EATURE
S
F
The LTC®1257 is a complete single supply, 12-bit voltage
output D/A converter (DAC) in an SO-8 package. The
LTC1257 includes an output buffer amplifier, 2.048V
voltagereferenceandaneasytousethree-wirecascadable
serial interface. An external reference can be used to
override the internal reference and extend the output
voltage range to 12V. The power supply current is a low
350µA when operating from a 5V supply, making the
LTC1257idealforbattery-poweredapplications.Thespace-
saving 8-pin SO package and operation with no external
components provide the smallest 12-bit D/A system
available.
■
■
■
■
■
■
■
■
■
8-Pin SO Package
Buffered Voltage Output
Built-In 2.048V Reference
500µV/LSB with 2.048V Full Scale
1/2LSB Max DNL Error
Guaranteed 12-Bit Monotonic
3-Wire Cascadable Serial Interface
Wide Single Supply Range: VCC = 4.75V to 15.75V
Low Power: ICC Typ = 350µA with 5V Supply
O U
PPLICATI
A
S
■
■
■
Digital Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Daisy-Chained Control Outputs
Differential Nonlinearity
vs Input Code
5V
0.5
0.0
0.1µF
V
D
IN
CC
CLK
LTC1257
µP
V
V
CONTROL OUTPUT 1
OUT
LOAD
D
V
GND
OUT
REF
0.1µF
V
D
IN
CC
CLK
LTC1257
CONTROL OUTPUT 2
OUT
LOAD
V
D
GND
REF
OUT
–0.5
0
512 1024 1536 2048 2560 3072 3584 4098
CODE
TO NEXT DAC
1257 TA01
1257 TA05
1
LTC1257
W
U
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
TOP VIEW
VCC to GND ............................................ –0.5V to 16.5V
TTL Input Voltage .......................... –0.5V to VCC + 0.5V
VOUT .............................................. –0.5V to VCC + 0.5V
REF ................................................ –0.5V to VCC + 0.5V
Operating Temperature Range
ORDER PART
V
V
CLK
1
2
3
4
NUMBER
8
7
6
5
CC
D
OUT
IN
REF
LTC1257CN8
LTC1257IN8
LOAD
GND
D
OUT
LTC1257C ............................................. 0°C to 70°C
LTC1257I......................................... –40°C to 85°C
Maximum Junction Temperature
Plastic Package ............................. –65°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
N8 PACKAGE
8-LEAD PDIP
TJMAX = 125°C, θJA = 100°C/W
TOP VIEW
LTC1257CS8
LTC1257IS8
CLK
1
2
3
4
8
7
6
5
V
V
CC
D
IN
OUT
LOAD
REF
S8 PART MARKING
D
GND
OUT
S8 PACKAGE
8-LEAD PLASTIC SO
JMAX = 125°C, θJA = 150°C/W
1257
1257I
T
Consult factory for Military grade parts.
VCC = 4.75V to 15.75V, internal or external reference
(2.475V ≤ VREF ≤ VCC – 2.7V), IOUT ≤ 2mA, TA = TMIN to TMAX, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
●
●
12
Bits
LSB
DNL
INL
Differential Nonlinearity
Guaranteed Monotonic
±0.5
Integral Nonlinearity
LTC1257C
LTC1257I
●
●
±3.5
±4.0
LSB
LSB
OFF
Offset Error
When Using Internal Reference, LTC1257C
When Using Internal Reference, LTC1257I
●
●
±8
±10
LSB
LSB
When Using External Reference, LTC1257C
When Using External Reference, LTC1257I
●
●
±4
±5
mV
mV
OFF
Offset Error Tempco
When Using Internal Reference (Note 1)
When Using External Reference (Note 1)
●
●
±0.02
±15
±0.066
±30
LSB/°C
µV/°C
TC
FSE
FSE
Full-Scale Error
●
●
0.5
±2
LSB
Full-Scale Error Tempco
(Note 1)
± 0.01
±0.02
LSB/°C
TC
Reference
Reference Output Voltage
I
I
= 0, LTC1257C
= 0, LTC1257I
●
●
2.028
2.018
2.048
2.068
2.078
V
V
OUT
OUT
Reference Output Tempco
Reference Line Regulation
I
= 0
●
±0.06
LSB/°C
OUT
I
I
= 0, LTC1257C
= 0, LTC1257I
●
●
±0.4
±0.7
LSB/V
LSB/V
OUT
OUT
Reference Load Regulation
Reference Input Range
0 ≤ I
≤ 100µA
●
●
●
±1
12
18
LSB
V
OUT
V
CC
> V
+ 2.7V
2.475
8
REF
Reference Input Resistance
Reference Input Capacitance
Short-Circuit Current
14
15
kΩ
pF
(Note 1)
Shorted to GND
V
OUT
●
90
mA
2
LTC1257
VCC = 4.75V to 15.75V, internal or external reference
(2.475V ≤ VREF ≤ VCC – 2.7V), IOUT ≤ 2mA, TA = TMIN to TMAX, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
Positive Supply Voltage
Supply Current
For Specified Performance
●
4.75
15.75
V
CC
I
4.75V ≤ V ≤ 5.25V
●
●
350
800
600
1500
µA
µA
CC
CC
4.75V ≤ V ≤ 15.75V
CC
Op Amp DC Performance
Short-Circuit Current Low
V
V
Shorted to GND
●
●
●
60
60
mA
mA
Ω
OUT
OUT
Short-Circuit Current High
Output Impedance to GND
Shorted to V
CC
Input Code = 0
150
50
400
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
5kΩ in Parallel with 100pF
To ±1/2LSB, 5kΩ in Parallel with 100pF
(Notes 1,2)
●
●
1.0
2.4
V/µs
µs
6
nV/s
Digital I/O
V
V
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
●
●
●
●
●
●
V
V
IH
IL
0.8
I
I
= –1mA, D
Only
V – 1
CC
V
OH
OL
OUT
OUT
OUT
= 1mA, D
Only
0.4
V
OUT
I
V
= GND to V
CC
±10
µA
pF
LEAK
IN
C
Digital Input Capacitance
(Note 1)
10
IN
Switching (Note 1)
t1
t2
t3
t4
t5
t6
t7
t8
D
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
100
25
ns
ns
IN
IN
CLK High Time
350
350
150
0
ns
CLK Low Time
ns
LOAD Pulse Width
LSB CLK to LOAD
LOAD High to CLK
ns
ns
0
ns
D
Output Delay
C
= 15pF
LOAD
35
150
1.4
ns
OUT
f
Maximum Clock Frequency
MHz
CLK
The
●
denotes specifications which apply over the full operating
Note 1: Guaranteed by design; not subject to test.
Note 2: DAC switched from all 1s to all 0s, and all 0s to all 1s code.
temperature range.
3
LTC1257
TYPICAL PERFORMANCE CHARACTERISTICS
U W
Minimum Supply Voltage
vs Load Current #2
Minimum Supply Voltage
vs Load Current #1
Supply Current vs Temperature
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
0.38
0.37
0.36
0.35
0.34
0.33
0.32
0.31
V
V
T
= INTERNAL
V
V
T
= 10V
REF
OUT
A
REF
OUT
A
= FULL SCALE
= FULL SCALE
= 25°C
= 25°C
V
= 5.25V
CC
V
= 5V
CC
V
CC
= 4.75V
0.01
0.1
1
10
0.01
0.1
1
10
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
OUTPUT LOAD CURRENT (mA)
OUTPUT LOAD CURRENT (mA)
1257 G01
1257 G02
1257 G03
Pull-Down Voltage vs Output Sink
Current Capability
Supply Current vs
Logic Input Voltage
Output Swing vs Load Resistance
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.59
0.54
0.49
0.44
0.39
0.34
1000
100
10
V
= 5V
V
A
= 5V
CC
CC
= 25°C
T
FULL SCALE
TIED TO GND
R
L
ZERO SCALE
R
L
TIED TO V
CC
HOT
COLD
ROOM
1
0.1
10
100
1k
10k
0
1
2
3
4
5
1
10
100
1000
LOAD RESISTANCE (Ω)
OUTPUT SINK CURRENT (µA)
LOGIC VOLTAGE (V)
1257 G05
1257 G04
1257 G06
Full-Scale Voltage vs
Temperature
Zero-Scale Voltage vs
Temperature
Integral Nonlinearity (INL)
2.0495
2.0490
2.0485
2.0480
2.0475
2.0470
2.0465
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.0
1.6
V
CC
= 5V
V
= 5V
CC
INTERNAL REFERENCE
INTERNAL REFERENCE
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
V
= 5V
CC
INTERNAL REFERENCE
= 25°C
T
A
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
3584
4096
–50 –25
0
25
50
125
0
512 1024 1536 2048 2560 3072
CODE
75 100
TEMPERATURE (°C)
1257 G07
1257 G08
1257 G09
4
LTC1257
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Compensation
Resistance vs CL
Broadband Noise
Differential Nonlinearity (DNL)
0.5
70
60
50
40
30
20
10
0
CODE = FFFH
BW = 3Hz TO 1MHz
GAIN = 1100×
0.0
–0.5
0.01
0.1
1
(µF)
10
100
TIME = 5ms/DIV
0
512 1024 1536 2048 2560 3072 3584 4098
CODE
1257 G12
C
L
1257 G11
1257 TA05
U
U
U
PI FU CTIO S
CLK (Pin 1): The TTL level input for the serial interface
GND (Pin 5): Ground.
clock.
REF (Pin 6): The output of the 2.048V reference and the
inputtotheDACresistorladder.Anexternalreferencewith
voltagefrom2.475VtoVCC –2.7Vmaybeusedtooverride
the internal reference.
DIN(Pin2): TheTTLlevelinputfortheserialinterfacedata.
Data on the DIN pin is latched into the shift register on the
rising edge of the serial clock.
LOAD (Pin 3): The TTL level input for the serial interface
load control. Data is loaded from the shift register into the
DAC register, thus updating the DAC output when LOAD is
pulled low. The DAC register is transparent as long as
LOAD is held low.
VOUT (Pin 7): The buffered DAC output is capable of
sourcing 2mA over temperature while pulling within 2.7V
of VCC. The output will pull to ground through an internal
200Ω equivalent resistance.
VCC (Pin 8): The positive supply input. 4.75V ≤ VCC
≤
DOUT(Pin 4): The output of the shift register which
becomes valid on the rising edge of the serial clock. The
DOUT pin is driven from GND to VCC by an internal CMOS
inverter. MultipleLTC1257smaybecascadedbyconnect-
ing the DOUT pin to the DIN pin of the next chip.
15.75V. Requires a bypass capacitor to ground.
5
LTC1257
U U
DEFI ITIO S
LSB: Theleastsignificantbitortheidealvoltagedifference
between two successive codes.
Offset Error: The theoretical voltage at the output when
the DAC is loaded with all zeros. The output amplifier can
have a true negative offset, but because the part is oper-
ated from a single supply, the output cannot go below
ground.Iftheoffsetisnegative,theoutputwillremainnear
0V resulting in the transfer curve shown in Figure 1.
LSB = (VFS – VOS)/2n – 1
n
= The number of digital input bits
VOS = The zero code error or offset of the DAC
VFS = The full-scale output voltage of the DAC
measured when all bits are set to 1
OUTPUT
VOLTAGE
Resolution: The resolution is the number of DAC output
states (2n) that divide the full-scale range. The resolution
does not imply linearity.
0V
NEGATIVE
OFFSET
DAC CODE
{
1257 F01
INL: End-point integral nonlinearity is the maximum de-
viationfromastraightlinepassingthroughtheend-points
of the DAC transfer curve. Because the part operates from
a single supply and the output cannot go below ground,
the linearity is measured between full-scale and the first
code that guarantees a positive output. The INL error at a
given input code is calculated as follows:
Figure 1. Effect of Negative Offset
The offset of the part is measured at the first code that
produces an output voltage 0.5LSB greater than the pre-
vious code:
VOS = VOUT – [(Code)(VFS)/(2n – 1)]
Full-Scale Error: Full-scale error is the difference be-
tweentheidealandmeasuredDACoutputvoltageswithall
bits set to one (Code = 4095). The full-scale error includes
the offset error and is calculated as follows:
INL = (VOUT – VIDEAL)/LSB
VIDEAL = (Code)(LSB) + VOS
VOUT = The output voltage of the DAC measured at
the given input code
FSE = (VOUT – VIDEAL)/LSB
VIDEAL = (VREF)(1 – 2–n) – VOS
VREF = The reference voltage, either internal or
external
DNL: Differential nonlinearity is the difference between
the measured change and the ideal 1LSB change between
any two adjacent codes. The DNL error between any two
codes is calculated as follows:
DigitalFeedthrough: Theglitchthatappearsattheanalog
outputcausedbyACcouplingfromthedigitalinputswhen
they change state. The area of the glitch is specified in
(nV)(sec).
DNL = (∆VOUT – LSB)/LSB
∆VOUT = The measured voltage difference between
two adjacent codes
6
LTC1257
W
BLOCK DIAGRA
LOGIC
5V REGULATOR
V
D
CC
SUPPLY
CLK
12-BIT
SHIFT REGISTER
OUT
D
IN
12
GND
LOAD
REF
12-BIT LATCH
12
+
–
2.048V REFERENCE
DAC
V
OUT
1257 BD
W U
W
TI I G DIAGRA
t
t
t
t
2
1
6
7
CLK
t
t
3
4
B11
MSB
B0
LSB
B10
B1
D
IN
t
5
LOAD
t
8
B11
(PREVIOUS WORD)
B11
D
B1
B10
B0
OUT
CURRENT WORD
1257 TD
7
LTC1257
U
OPERATIO
Serial Interface
Reference
The LTC1257 includes an internal 2.048V reference, mak-
ing 1LSB equal to 500µV. The internal reference output is
turned off when the pin is forced above the reference
voltage, allowing an external reference to be connected to
the reference pin. The external reference must be greater
than 2.475V and less than VCC – 2.7V, and be capable of
driving the 10k minimum DAC resistor ladder.
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first and
theLSBlast. TheDACregisterloadsthedatafromtheshift
register when LOAD is pulled low, and remains transpar-
ent until LOAD is pulled high and the data is latched.
An internal 5V regulator provides the supply for the digital
logic. By limiting the internal digital signal swings to 5V,
digital noise is reduced. The buffered output of the 12-bit
shift register is available on the DOUT pin which will swing
from GND to VCC.
If the reference output is driving a large capacitive load, a
series resistor must be added to insure stability. For any
capacitive load greater than 1µF, a 10Ω series resistor will
suffice.
Multiple LTC1257s may be daisy chained together by
connecting the DOUT pin to the DIN pin of the next chip,
while the clock and load signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips, then the LOAD signal is pulled low to update all
of them simultaneously. The maximum clocking rate is
1.4MHz.
Voltage Output
The LTC1257 voltage output is able to pull within 2.7V of
VCC while sourcing 2mA. A internal NMOS transistor with
a 200Ω equivalent impedance pulls the output to ground.
The output is protected against short circuits and is able
to drive up to a 500pF capacitive load without oscillation.
If digital noise on the output causes a problem, a simple
100Ω, 0.1µF RC circuit can be used to filter the noise.
U
O
TYPICAL APPLICATI S
DAC with External Reference
Filtering VREF and VOUT
15V
V
CC
IN
0.1µF
LT1021-10
GND
0.1µF
OUT
D
V
CC
IN
100Ω
5%
CLK
V
OUT
V
OUT
LTC1257
GND
V
D
IN
V
CC
REF
LOAD
CLK
0.1µF
D
V
OUT
REF
LTC1257
µP
V
CONTROL OUTPUT
OUT
LOAD
1µF
D
GND
OUT
1257 TA06
10Ω
5%
1257 TA03
8
LTC1257
U
O
TYPICAL APPLICATI S
Auto Ranging 8-Channel ADC with Shutdown
22µF
5V
V
CC
CH0
CS
8 ANALOG
INPUT CHANNELS
D
•
•
•
OUT
µP
LTC1296
CLK
D
IN
CH7
COM
REF
+
–
REF
SSO
50k
50k
5V
74HC04
0.1µF
100Ω
V
D
IN
CC
CLK
LTC1257
V
OUT
LOAD
0.1µF
D
V
GND
OUT
REF
V
CC
D
IN
100Ω
0.1µF
CLK
LTC1257
V
OUT
LOAD
D
GND
V
REF
OUT
1257 TA02
12-Bit Single 5V Control System with Shutdown
5V
100k
10k
10µF
2N3906
CB/POWER DOWN
CLK
V
CC
–IN
+IN
CS
D
0.1µF
V
OUT
IN
DATA
µP
J
–
+
CLK
DAC LOAD
LTC1297
ADC
LT1025A
GND COMMON
V
REF
GND
+
–
47k
10µF
LTC1050
74k
1µF
1µF
100k
V
D
IN
V
CC
REF
CLK
CONTORL
OUTPUT
LTC1257
V
OUT
1k
LOAD
D
OUT
GND
1257 TA04
9
LTC1257
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
N8 1197
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
LTC1257
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
PACKAGE DESCRIPTIO
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1257
U
O
TYPICAL APPLICATI
Driving LTC1257 with Optoisolators
12V
V
V
IN
OUT
LT1021-5
0.1µF
2k
5%
2k
5%
2k
5%
V
V
CLK
REF
CC
MOC5008
6
D
IN
V
V
OUT
1
OUT
LTC1257
GND
CLK
LOAD
4
5
D
OUT
2
MOC5008
1
6
4
5
D
IN
2
MOC5008
6
4
5
1
2
LOAD
1257 TA07
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1446: V = 4.5V to 5.5V, V
LTC1446/LTC1446L Dual 12-Bit V
DACs in SO-8 Package
= 0V to 4.095V
OUT
OUT
CC
LTC1446L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
OUT
LTC1448
Dual 12-Bit V
DAC in SO-8 Package, V : 2.7V to 5.5V
Output Swings from GND to REF,
REF Input Can Be Tied to V
OUT
CC
CC
LTC1450/LTC1450L Single 12-Bit V
DACs with Parallel Interface
LTC1450: V = 4.5V to 5.5V, V = 0V to 4.095V
OUT
OUT
CC
LTC1450L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
OUT
LTC1451
LTC1452
LTC1453
Single Rail-to-Rail 12-Bit V
5.5V, Internal 2.048V Reference Brought Out to Pin
DAC, Full Scale: 4.095V, V : 4.5V to
Low Power, Complete V
DAC in SO-8 Package
OUT
CC
OUT
Single Rail-to-Rail 12-Bit V
Multiplying DAC, V : 2.7V to 5.5V
Low Power, Multiplying V
Buffer Amplifier in SO-8 Package
DAC with Rail-to-Rail
OUT
CC
OUT
Single Rail-to-Rail 12-Bit V
DAC, Full Scale: 2.5V, V : 2.7V to 5.5V
3V, Low Power, Complete V DAC in SO-8 Package
OUT
CC
OUT
LTC1454/LTC1454L Dual 12-Bit V
DACs in SO-16 Package with Added Functionality
LTC1454: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
OUT
CC
OUT
LTC1454L: V = 2.7V to 5.5V, V
CC
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Full Scale: 4.095V, V : 4.5V to 5.5V
Low Power, Complete V
Package with Clear Pin
DAC in SO-8
OUT
CC
LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
CC
LTC1659
Single Rail-to-Rail 12-Bit V
DAC in MSOP-8 Package,
Output Swings from GND to REF,
REF Input Can Be Tied to V
OUT
V
CC
= 2.7V to 5.5V
CC
1257fa LT/TP 0198 REV A 4K • PRINTED IN USA
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
12
●
●
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1994
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