LTC1290CCN [Linear]
Single Chip 12-Bit Data Acquisition System; 单芯片12位数据采集系统
| 型号： | LTC1290CCN |
| 厂家： | 
Linear |
| 描述： | Single Chip 12-Bit Data Acquisition System |
| 文件： | 总28页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1290
Sing le Chip 12-Bit Da ta
Ac q uisitio n Syste m
U
DESCRIPTIO
EATURE
S
F
The LTC®1290 is a data acquisition component which
contains a serial I/O successive approximation A/D con-
verter. It uses LTCMOSTM switched capacitor technology
toperformeither12-bitunipolaror11-bitplus signbipolar
A/D conversions. The 8-channel input multiplexer can be
configuredforeithersingle-endedordifferentialinputs (or
combinations thereof). An on-chip sample-and-hold is
included for all single-ended input channels. When the
LTC1290 is idle it can be powered down with a serial word
in applications where low power consumption is desired.
■
Software Programmable Features
– Unipolar/Bipolar Conversion
– Four Differential/Eight Single-Ended Inputs
– MSB- or LSB-First Data Sequence
– Variable Data Word Length
– Power Shutdown
Built-In Sample-and-Hold
Single Supply 5V or ±5V Operation
Direct Four-Wire Interface to Most MPU Serial Ports
and All MPU Parallel Ports
■
■
■
■
50kHz Maximum Throughput Rate
The serial I/O is designed to be compatible with industry
standardfullduplexserialinterfaces. Itallows eitherMSB-
or LSB-first data and automatically provides 2's comple-
ment output coding in the bipolar mode. The output data
word can be programmed for a length of 8, 12 or 16 bits.
This allows easy interface to shift registers and a variety of
processors.
U
KEY SPECIFICATIO S
■
■
■
Resolution: 12 Bits
Fast Conversion Time: 13µs Max Over Temp
Low Supply Current: 6.0mA
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
12-Bit 8-Channel Sampling Data Acquisition System
SINGLE-ENDED INPUT
0V TO 5V OR ±5V
±15V OVERVOLTAGE RANGE*
1k
5V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
V
CC
+
•
•
•
22µF
TANTALUM
1N5817
ACLK
SCLK
TO AND FROM
MICROPROCESSOR
D
IN
1N4148
DIFFERENTIAL INPUT (+)
D
OUT
LTC1290
±5V COMMON MODE RANGE (–)
CS
+
LT®1027
8V TO 40V
1µF
•
•
•
REF
+
–
4.7µF
REF
TANTALUM
–
–5V
1N5817
V
DGND
AGND
0.1µF
1290 • TA01
* FOR OVERVOLTAGE PROTECTION ON ONLY ONE CHANNEL LIMIT THE INPUT CURRENT TO 15mA. FOR OVERVOLTAGE PROTECTION
ON MORE THAN ONE CHANNEL LIMIT THE INPUT CURRENT TO 7mA PER CHANNEL AND 28mA FOR ALL CHANNELS. (SEE SECTION ON
OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION SECTION.) CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED
–
OR ANY OTHER CHANNEL IS OVERVOLTAGED (V < V OR V > V ).
IN
IN
CC
1
LTC1290
W W W
U
ABSOLUTE AXI U RATI GS (Notes 1, 2)
Supply Voltage (V ) to GND or V – ........................ 12V
Operating Temperature Range
CC
Negative Supply Voltage (V–) .................... –6V to GND
LTC1290BC, LTC1290CC, LTC1290DC .... 0°C to 70°C
LTC1290BI, LTC1290CI, LTC1290DI .... –40°C to 85°C
LTC1290BM, LTC1290CM,
Voltage
Analog/Reference Inputs ......... (V–) – 0.3V to V + 0.3V
CC
Digital Inputs ........................................ –0.3V to 12V
LTC1290DM....................................... –55°C to 125°C
Digital Outputs ........................... –0.3V to VCC + 0.3V Storage Temperature Range ................ –65°C to 150°C
Power Dissipation............................................. 500mW
Lead Temperature (Soldering, 10 sec.)................ 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
NUMBER
1
2
V
CC
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
20
V
CC
ACLK
SCLK
LTC1290BMJ
LTC1290CMJ
LTC1290DMJ
LTC1290BIJ
LTC1290CIJ
LTC1290DIJ
LTC1290BIN
LTC1290CIN
LTC1290DIN
LTC1290BCN
LTC1290CCN
LTC1290DCN
19 ACLK
18 SCLK
LTC1290BCSW
LTC1290CCSW
LTC1290DCSW
LTC1290BISW
LTC1290CISW
LTC1290DISW
3
CH2
4
D
IN
CH3
17
16
D
IN
5
D
OUT
CH4
D
OUT
6
CS
CH5
15 CS
+
7
REF
CH6
+
14 REF
–
8
REF
CH7
–
13 REF
–
–
9
V
COM
DGND
12
V
10
AGND
DGND 10
11 AGND
N PACKAGE
J PACKAGE
SW PACKAGE
20-LEAD PLASTIC SO WIDE
20-LEAD PDIP
20-LEAD CERAMIC DIP
T
T
JMAX = 150°C, θJA = 80°C/W (J)
JMAX = 110°C, θJA = 100°C/W (N)
T
JMAX = 110°C, θJA = 130°C/W (SW)
U
U W
(Note 3)
CO VERTER A D ULTIPLEXER CHARACTERISTICS
LTC1290B
TYP
LTC1290C
TYP
LTC1290D
PARAMETER
Offset Error
CONDITIONS
(Note 4)
MIN
MAX
±1.5
±0.5
±0.5
12
MIN
MAX
MIN
TYP
MAX UNITS
●
●
●
●
±1.5
±0.5
±1.0
12
±1.5
±0.75
±4.0
12
LSB
LSB
LSB
Bits
Linearity Error (INL)
Gain Error
(Notes 4,5)
(Note 4)
Minimum Resolution for Which
No Missing Codes are Guaranteed
–
–
–
Analog and REF Input Range
(Note 7)
(V ) – 0.05V to V + 0.05V (V ) – 0.05V to V + 0.05V (V ) – 0.05V to V + 0.05V
V
CC
CC
CC
On Channel Leakage Current
(Note 8)
On Channel = 5V
Off Channel = 0V
●
●
●
●
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
µA
On Channel = 0V
Off Channel = 5V
µA
µA
µA
Off Channel Leakage Current
(Note 8)
On Channel = 5V
Off Channel = 0V
On Channel = 0V
Off Channel = 5V
2
LTC1290
(Note 3)
AC CHARACTERISTICS
LTC1290B/LTC1290C/LTC1290D
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
f
Shift Clock Frequency
A/D Clock Frequency
V = 5V (Note 6)
= 5V (Note 6)
CC
0
2.0
SCLK
CC
f
V
(Note 10)
4.0
MHz
ACLK
t
t
t
t
t
Delay time from CS↓ to D
Data Valid
(Note 9)
2
7
ACLK
Cycles
ACC
OUT
Analog Input Sample Time
Conversion Time
See Operating Sequence
See Operating Sequence
See Operating Sequence (Note 6)
SCLK
Cycles
SMPL
CONV
CYC
52
ACLK
Cycles
Total Cycle Time
12 SCLK +
56 ACLK
Cycles
Delay Time, SCLK↓ to D
Data Valid
See Test Circuits LTC1290BC, LTC1290CC
LTC1290DC, LTC1290BI
●
●
130
180
220
270
ns
dDO
OUT
LTC1290CI, LTC1290DI
LTC1290BM, LTC1290CM
LTC1290DM
ns
t
t
t
t
t
t
t
t
t
Delay Time, CS↑ to D
Hi-Z
See Test Circuits
See Test Circuits
●
●
70
100
200
ns
ns
ns
ns
ns
ns
ns
ns
dis
OUT
Delay Time, 2nd ACLK↓ to D
Enabled
130
en
OUT
Hold Time, CS After Last SCLK↓
Hold Time, D After SCLK↑
V
= 5V (Note 6)
= 5V (Note 6)
CC
0
hCS
hDI
hDO
f
CC
V
50
IN
Time Output Data Remains Valid After SCLK↓
50
65
25
D
OUT
Fall Time
See Test Circuits
See Test Circuits
●
●
130
50
D
OUT
Rise Time
r
Setup Time, D Stable Before SCLK↑
V = 5V (Note 6)
CC
50
suDI
suCS
IN
Setup Time, CS↓ Before Clocking in
(Notes 6, 9)
2 ACLK Cycles
First Address Bit
+ 100ns
t
CS High Time During Conversion
V
CC
= 5V (Note 6)
52
ACLK
Cycles
WHCS
C
IN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
100
5
pF
pF
Digital Inputs
5
pF
U
D
A
ELECTRICAL CHARACTERISTICS
DC
DIGITAL
(Note 3)
LTC1290B/LTC1290C/LTC1290D
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP MAX
UNITS
V
V
IH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
= 5.25V
= 4.75V
CC
●
●
●
●
2.0
CC
V
IL
V
0.8
2.5
V
I
IH
V = V
IN CC
µA
µA
I
IL
V = 0V
IN
–2.5
V
OH
V
CC
= 4.75V I = 10µA
4.7
4.0
V
V
O
I = 360µA
O
●
●
2.4
V
OL
Low Level Output Voltage
High-Z Output Leakage
V
CC
= 4.75V I = 1.6mA
0.4
V
O
I
OZ
V
OUT
= V , CS High
●
●
3
–3
µA
µA
CC
V
= 0V, CS High
= 0V
OUT
OUT
I
Output Source Current
V
–20
mA
SOURCE
3
LTC1290
U
D
A
ELECTRICAL CHARACTERISTICS
DC
DIGITAL
(Note 3)
LTC1290B/LTC1290C/LTC1290D
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
20
6
MAX
UNITS
mA
I
Output Sink Current
V
= V
SINK
OUT CC
I
CC
Positive Supply Current
CS High
CS High
●
●
12
10
mA
LTC1290BC, LTC1290CC
5
µA
Power Shutdown LTC1290DC, LTC1290BI
ACLK Off
LTC1290CI, LTC1290DI
LTC1290BM, LTC1290CM
LTC1290DM
●
5
15
µA
I
Reference Current
V
= 5V
●
●
10
1
50
50
µA
µA
REF
REF
–
I
Negative Supply Current
CS High
–
The
●
denotes specifications which apply over the full operating
below V or one diode drop above V . Be careful during testing at low
CC
temperature range; all other limits and typicals T = 25°C.
V levels (4.5V), as high level reference or analog inputs (5V) can cause
CC
A
this input diode to conduct, especially at elevated temperatures and cause
errors for inputs near full scale. This spec allows 50mV forward bias of
either diode. This means that as long as the reference or analog input does
not exceed the supply voltage by more than 50mV, the output code will be
correct. To achieve an absolute 0V to 5V input voltage range will therefore
require a minimum supply voltage of 4.950V over initial tolerance,
temperature variations and loading.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND
–
and REF wired together (unless otherwise noted).
–
+
–
Note 3: V = 5V, V
= 5V, V
= 0V, V = 0V for unipolar mode and
CC
REF
REF
–5V for bipolar mode, ACLK = 4.0MHz unless otherwise speicfied.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
Note 8: Channel leakage current is measured after the channel selection.
mode, one LSB is equal to the bipolar input span (2V ) divided by 4096.
REF
Note 9: To minimize errors caused by noise at the chip select input, the
internal circuitry waits for two ACLK falling edge after a chip select falling
edge is detected before responding to control input signals. Therefore, no
attempt should be made to clock an address in or data out until the
minimum chip select setup time has elapsed.
For example, when V = 5V, 1LSB (bipolar) = 2(5V)/4096 = 2.44mV.
REF
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Recommended operating conditions.
Note 10: Increased leakage currents at elevated temperatures cause the
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
S/H to droop, therefore it's recommended that f
≥ 500kHz at 125°C,
ACLK
f
≥ 125kHz at 85°C and f
≥ 15kHz at 25°C.
ACLK
ACLK
U W
TYPICALPERFOR A CE CHARACTERISTICS
Unadjusted Offset Voltage vs
Reference Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
26
22
18
14
10
6
0.9
10
9
V
= 5V
ACLK = 4MHz
T = 25°C
A
CC
ACLK = 4MHz
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
= 5V
CC
8
7
V
= 0.25mV
OS
6
5
V
= 0.125mV
3
OS
4
2
3
1
2
4
5
4
6
8
10
–50 –30 –10 10
70 90 110 130
30 50
SUPPLY VOLTAGE, V (V)
REFERENCE VOLTAGE, V (V)
REF
AMBIENT TEMPERATURE, T (°C)
CC
A
1290 • TPC03
1290 • TPC01
LT1290 • TPC02
4
LTC1290
U W
TYPICALPERFOR A CE CHARACTERISTICS
Change in Linearity vs Reference
Voltage
Change in Gain vs Reference
Voltage
Change in Offset vs Temperature
0
1.25
1.00
0.75
0.50
0.25
0
0.5
0.4
0.3
0.2
0.1
0
V
CC
= 5V
ACLK = 4MHz
V
= 5V
= 5V
CC
–0.1
–0.2
V
REF
–0.3
–0.4
–0.5
V
CC
= 5V
3
1
2
4
5
0
1
2
3
4
5
–50 –30 –10 10 30 50 70 90 110 130
REFERENCE VOLTAGE, V (V)
REF
REFERENCE VOLTAGE, V (V)
AMBIENT TEMPERATURE, T (°C)
REF
A
1290 • TPC05
1290 • TPC04
1290 • TPC06
Change in Linearity Error vs
Temperature
Change in Gain Error vs
Temperature
0.6
0.5
0.5
ACLK = 4MHz
ACLK = 4MHz
V
= 5V
= 5V
V
= 5V
= 5V
CC
CC
V
0.4
0.3
0.2
0.1
0
V
REF
REF
0.4
0.3
0.2
0.1
0
–50 –30 –10 10 30 50 70 90 110 130
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE, T (°C)
AMBIENT TEMPERATURE, T (°C)
A
A
1290 • TPC07
1290 • TPC08
Maximum ACLK Frequency vs
Source Resistance
Maximum Filter Resistor vs
Cycle Time
5
4
10k
V
= 5V
= 5V
CC
V
REF
T = 25°C
A
1k
100
10
3
2
1
V
R
+
–
INPUT
INPUT
IN
–
SOURCE
R
FILTER
V
+
–
IN
C
≥ 1µF
FILTER
0
100
1.0
1k
10 k
(Ω)
100k
10
100
CYCLE TIME, t
1000
(µs)
10000
R
SOURCE
CYC
1290 • TPC09
1290 • TPC10
* MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK
FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT
ANY CODE TRANSITION FROM ITS 4MHz VALUE IS FIRST DETECTED.
** MAXIMUM R
AT WHICH A 0.1LSB CHANGE IN FULL-SCALE ERROR FROM
ITS VALUE AT R = 0 IS FIRST DETECTED.
REPRESENTS THE FILTER RESISTOR VALUE
FILTER
FILTER
5
LTC1290
U W
TYPICALPERFOR A CE CHARACTERISTICS
Sample-and-Hold Acquisition
Time vs Source Resistance
Supply Current (Power Shutdown)
vs Temperature
Supply Current (Power Shutdown)
vs ACLK
10
9
8
7
6
5
4
3
2
1
0
100
200
180
160
140
120
100
80
V = 5V
CC
CMOS LEVELS
ACLK OFF DURING
POWER SHUTDOWN
V
= 5V
= 5V
REF
V
CC
T = 25°C
A
0V TO 5V INPUT STEP
R
+
SOURCE
V
+
–
IN
10
60
40
20
1
3.00
1.00
ACLK FREQUENCY (MHz)
0
2.00
4.00
–50 –30 –10 10 30 50 70 90 110 130
1k
10k
100
AMBIENT TEMPERATURE, T (°C)
R
+ (Ω)
A
SOURCE
1290 • TPC13
1290 • TPC12
LTC1290 • TPC11
Input Channel Leakage Current
vs Temperature
Noise Error vs Reference Voltage
1000
900
800
700
600
500
400
300
200
100
0
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
LTC1290 NOISE 200µV
P-P
GUARANTEED
ON CHANNEL
OFF CHANNEL
0
–50 –30 –10 10 30 50 70 90 110 130
0
4
5
1
2
3
AMBIENT TEMPERATURE, T (°C)
REFERENCE VOLTAGE, V (V)
REF
A
1290 • TPC14
1290 • TPC15
U
U
U
PI FU CTIO S
V– (Pin 12): Negative Supply. Tie V– to most negative
potential in the circuit. (Ground in single supply applica-
tions.)
CH0 to CH7 (Pin 1 to Pin 8): Analog Inputs. The analog
inputs must be free of noise with respect to AGND.
COM (Pin 9): Common. The common pin defines the zero
reference point for all single-ended inputs. It must be free
of noise and is usually tied to the analog ground plane.
REF–, REF+ (Pins 13, 14): Reference Inputs. The refer-
ence inputs must be kept free of noise with respect to
AGND.
DGND (Pin 10):Digital Ground. This is the ground for the
internal logic. Tie to the ground plane.
CS (Pin 15): Chip Select Input. A logic low on this input
enables data transfer.
AGND (Pin 11): Analog Ground. AGND should be tied
directly to the analog ground plane.
DOUT (Pin 16): Digital Data Output. The A/D conversion
result is shifted out of this output.
6
LTC1290
U
U
U
PI FU CTIO S
D (Pin 17): Digital Data Input. The A/D configuration
IN
ACLK (Pin 19): A/D Conversion Clock. This clock controls
word is shifted into this input after CS is recognized.
the A/D conversion process.
SCLK (Pin 18): Shift Clock. This clock synchronizes the
V (Pin 20): Positive Supply. This supply must be kept
CC
serial data transfer.
free of noise and ripple by bypassing directly to the analog
ground plane.
BLOCK DIAGRAM
18
SCLK
20
V
CC
INPUT
SHIFT
REGISTER
OUTPUT
16
17
D
OUT
D
IN
SHIFT
REGISTER
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SAMPLE-
AND-
HOLD
COMP
ANALOG
INPUT MUX
12-BIT
SAR
12-BIT
CAPACITIVE
DAC
COM
19
15
ACLK
CS
CONTROL
AND
TIMING
10
11
AGND
12
14
+
13
–
–
V
REF
REF
DGND
LTC1290 • BD
TEST CIRCUITS
On and Off Channel Leakage Current
Load Circuit for tdis and ten
5V
I
ON
TEST POINT
ON CHANNEL
A
5V WAVEFORM 2
WAVEFORM 1
I
OFF
3k
D
OUT
A
100pF
•
•
•
•
OFF
CHANNELS
LTC1290 • TC02
POLARITY
LTC1290 • TC01
7
LTC1290
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO
SCLK
0.8V
t
dDO
2.4V
D
OUT
0.4V
LTC1290 • TC03
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
2.4V
0.4V
D
OUT
t
t
LTC1290 • TC04
r
f
Load Circuit for tdDO, tr and tf
1.4V
3k
D
OUT
TEST POINT
100pF
1290 • TC05
Voltage Waveforms for ten and tdis
1
2
ACLK
CS
2.0V
D
OUT
2.4V
0.8V
90%
10%
WAVEFORM 1
(SEE NOTE 1)
t
t
dis
en
D
OUT
WAVEFORM 2
(SEE NOTE 2)
LTC1290 • TC06
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
8
LTC1290
O U
W
U
PPLICATI
A
S I FOR ATIO
The LTC1290 is a data acquisition component which
contains the following functional blocks:
of the data exchange the requested conversion begins and
CS should be brought high. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one CS cycle from the input word requesting
it.
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
D
D
WORD 1
D
WORD 2
D WORD 3
IN
IN
IN
IN
D
OUT
D
OUT
WORD 0
D
OUT
WORD 1
D WORD 2
OUT
DIGITAL CONSIDERATIONS
t
t
CONV
A/D
CONV
A/D
DATA
DATA
TRANSFER
TRANSFER
CONVERSION
CONVERSION
Serial Interface
LTC1290 • AI01
The LTC1290 communicates with microprocessors and
other external circuitry via a synchronous, full duplex,
four-wire serial interface (see Operating Sequence). The
shift clock (SCLK) synchronizes the data transfer with
each bit being transmitted on the falling SCLK edge and
captured on the rising SCLK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
Input Data Word
The LTC1290 8-bit data word is clocked into the D input
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the D pin are then ignored
until the next CS cycle. The eight bits of the input word are
defined as follows:
IN
IN
UNIPOLAR/
BIPOLAR
WORD
LENGTH
Datatransferis initiatedbyafallingchipselect(CS)signal.
After the falling CS is recognized, an 8-bit input word is
SGL/
DIFF
ODD/
SIGN
SELECT SELECT
UNI
MSBF
WL1
WL0
1
0
shifted into the D input which configures the LTC1290
IN
for the next conversion. Simultaneously, the result of the
previous conversion is output on the DOUT line. At the end
MSB-FIRST/
LSB-FIRST
MUX ADDRESS
LTC1290 • AI02
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
t
CYC
1
2
3
4
5
6
7
8
9
10 11 12
SCLK
CS
DON’T CARE
t
t
CONV
SMPL
D
IN
DON’T CARE
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
D
OUT
(SB)
SHIFT CONFIGURATION
WORD IN
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
LTC1290 • AI03
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MUX Address
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs
in the selected row of Table 1. Note that in differential
mode (SGL/DIFF = 0) measurements are limited to four
adjacent input pairs with either polarity. In single-ended
mode, all input channels are measured with respect to
COM.
Table 1. Multiplexer Channel Selection
DIFFERENTIAL CHANNEL SELECTION
SINGLE-ENDED CHANNEL SELECTION
MUX ADDRESS
MUX ADDRESS
SGL/ ODD SELECT
SGL/ ODD SELECT
1
0
1
2
3
4
5
6
7
COM
0
2
3
4
5
6
7
SIGN
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
DIFF
DIFF SIGN
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
+
–
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
+
–
–
–
–
–
–
–
–
+
–
+
+
–
+
+
–
–
+
–
+
+
–
+
+
–
+
+
+
+
4 Differential
8 Single-Ended
Combinations of Differential and Single-Ended
CHANNEL
CHANNEL
CHANNEL
+
–
(
(
)
)
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
+
–
0,1
0,1
{
{
+
–
+
–
(
(
)
)
+
–
–
2,3
2,3
{
{
+
4
5
6
7
+
+
–
(
(
)
)
+
–
4,5
{
+
+
+
–
(
(
)
)
+
+
–
6,7
{
COM (
)
COM (
)
–
–
Changing the MUX Assignment “On the Fly”
+
–
4,5
6,7
5,4
{
{
{
{
+
–
6
7
+
+
+
–
COM (UNUSED)
COM ( )
–
1ST CONVERSION
2ND CONVERSION
LTC1290 • F01
Figure 1. Examples of Multiplexer Options on the LTC1290
10
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Unipolar/Bipolar (UNI)
The fifth input bit (UNI) determines whether the conver-
sion will be unipolar or bipolar. When UNI is a logical one,
a unipolar conversion will be performed on the selected
input voltage. When UNI is a logical zero, a bipolar conver-
sion will result. The input span and code assignment for
each conversion type are shown in the figures below.
Unipolar Transfer Curve (UNI = 1)
Unipolar Output Code (UNI = 1)
INPUT VOLTAGE
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
(V = 5V)
OUTPUT CODE
INPUT VOLTAGE
REF
4.9988V
1 1 1 1 1 1 1 1 1 1 1 1
V
REF
– 1LSB
REF
4.9976V
1 1 1 1 1 1 1 1 1 1 1 0
V
– 2LSB
•
•
•
•
•
•
•
•
•
•
•
•
0.0012V
0V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
LTC1290 • AI04a
LTC1290 AI04b
Bipolar Output Code (UNI = 0)
INPUT VOLTAGE
(V = 5V)
INPUT VOLTAGE
(V = 5V)
OUTPUT CODE
INPUT VOLTAGE
OUTPUT CODE
INPUT VOLTAGE
REF
REF
4.9976V
4.9851V
–0.0024V
–0.0048V
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
V
V
REF
– 1LSB
– 2LSB
•
•
•
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
–1LSB
–2LSB
•
•
•
REF
•
•
•
•
•
•
•
•
•
•
•
•
0.0024V
0V
–4.9976V
–5.0000V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
1 0 0 0 0 0 0 0 0 0 0 1 –(V ) + 1LSB
REF
1 0 0 0 0 0 0 0 0 0 0 0
– (V
)
REF
LTC1290 AI05a
Bipolar Transfer Curve (UNI = 0)
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0
LTC1290 AI05b
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MSB-First/LSB-First Format (MSBF)
resumed once CS goes low or an SCLK is applied, if CS is
already low.
The output data of the LTC1290 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. For MSB
first output data the input word clocked to the LTC1290
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data the input
wordclockedtotheLTC1290shouldalways containazero
in the MSBF bit location. The MSBF bit affects only the
order of the output data word. The order of the input word
is unaffected by this bit.
WL1
WL0
OUTPUT WORD LENGTH
0
0
1
1
0
1
0
1
8-Bits
Power Shutdown
12-Bits
16-Bits
Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1290 to minimize the effects of errors
causedbynoiseonthatinput.This circuitignores changes
in state on the CS input that are shorter in duration than
oneACLKcycle.AfterachangeofstateontheCSinput,the
LTC1290 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
MSBF
OUTPUT FORMAT
LSB First
0
1
MSB First
Word Length (WL1, WL0) and Power Shutdown
The last two bits of the input word (WL1 and WL0)
program the output data word length and the power
shutdown feature of the LTC1290. Word lengths of 8, 12
or 16 bits can be selected according to the following table.
The WL1 and WL0 bits in a given D word control the
length of the present, not the next, DOUT word. WL1 and
WL0 are never “don’t cares” and must be set for the
IN
CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1290 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
DOUT line will become active with the first output bit. Then
the data transfer can begin as normal.
correct DOUT word length even when a “dummy” D word
IN
is sent. On any transfer cycle, the word length should be
made equal to the number of SCLK cycles sent by the
MPU. Power down will occur when WL1 = 0 and WL0 = 1
is selected. The previous conversion result will be clocked
out as a 10 bit word so a “dummy”conversion is required
before powering down the LTC1290. Conversions are
Low CS Recognized Internally
High CS Recognized Internally
ACLK
ACLK
CS
CS
HI-Z
HI-Z
D
OUT
D
OUT
VALID OUTPUT
VALID OUTPUT
LTC1290 • AI06
LTC1290 • AI07
12
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8-Bit Word Length
t
t
CONV
SMPL
CS
SCLK
1
8
(SB)
D
THE LAST FOUR BITS
ARE TRUNCATED
OUT
B11 B10
B9
B2
B8
B3
B7
B4
B6
B5
B5
B6
B4
MSB-FIRST
D
OUT
B0
B1
B7
LSB-FIRST
12-Bit Word Length
t
t
SMPL
CONV
CS
1
10
12
SCLK
(SB)
B11 B10 B9
D
OUT
B8
B3
B7
B4
B6
B5
B5
B6
B4
B7
B3
B8
B2
B1
B0
MSB-FIRST
(SB)
B9 B10 B11
D
OUT
B0
B1
B2
LSB-FIRST
16-Bit Word Length
t
t
CONV
SMPL
CS
SCLK
1
12
16
(SB)
B11 B10 B9
FILL
ZEROS
D
OUT
B8
B3
B7
B4
B6
B5
B5
B6
B4
B7
B3
B8
B2
B1
B0
MSB-FIRST
(SB)
B9 B10 B11
D
OUT
B0
B1
B2
*
*
*
LSB-FIRST
* IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROS.
IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS.
LTC1290 F02
Figure 2. Data Output (DOUT) Timing with Different Word Lengths
13
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SHIFT
MUX ADDRESS
IN
t
SMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK
DON’T CARE
D
IN
D
OUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
LTC1290 F03
Figure 3. CS High During Conversion
SHIFT
MUX ADDRESS
IN
t
SMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK MUST
REMAIN LOW
SCLK
D
IN
DON’T CARE
D
OUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
LTC1290 F04
Figure 4. CS Low During Conversion (CS Must go High to Low Once to Insure Proper Operation in this Mode)
Microprocessor Interfaces
Serial Port Microprocessors
TheLTC1290caninterfacedirectly(withoutexternalhard-
ware) to most popular microprocessor (MPU) synchro-
nous serial formats (see Table 2). If an MPU without a
serialinterfaceis used, thenfouroftheMPU’s parallelport
lines can be programmed to form the serial link to the
LTC1290. Included here are two serial interface examples
and one example showing a parallel port programmed to
form the serial interface
Most synchronous serial formats contain a shift clock
(SCLK)andtwodatalines,onefortransmittingandonefor
receiving. In most cases data bits are transmitted on the
falling edge of the clock (SCLK) and captured on the rising
edge. However, serial port formats vary among MPU
manufactures as tothesmallestnumberofbits thatcanbe
sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers).
They also vary as to the order in which the bits are
transmitted (LSB or MSB first). The following examples
showhowtheLTC1290accommodates thesedifferences.
14
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Table 2. Microprocessors with Hardware Serial Interfaces
Compatible with the LTC1290**
National MICROWIRE (COP402)
The COP402 transfers data MSB first and in 4-bit incre-
ments (nibbles). This is easily accommodated by setting
the LTC1290 to MSB-first format and 12-bit word length.
The data output word is then received by the COP402 in
three 4-bit blocks.
PART NUMBER
Motorola
TYPE OF INTERFACE
MC6805S2, S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
COP402 Code
CDP68HC05
SPI
MNEMONIC
COMMENTS
Hitachi
CLRA
LBI 1,0
STII
STII
STII
LEI
SC
LDD 1,0
OGI
XAS
LDD 1,1
NOP
XAS
XIS
LDD 1,2
XAS
XIS
Must be First Instruction
BR = 1BD = 0 Initialize B Reg.
HD6305
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
8
E
0
First D Nibble in $10
IN
Second D Nibble in $11
IN
Null Data in $12, B = $13
Set EN to (1100) BIN
Carry Set
C
National Semiconductor
LOOP
TM
COP400 Family
COP800 Family
NS8050U
MICROWIRE
MICROWIRE/PLUSTM
MICROWIRE/PLUS
MICROWIRE/PLUS
Load First D Nibble In ACC
IN
0
Go (CS) Cleared
ACC to Shift Reg. Begin Shift
HPC16000 Family
Load Next D Nibble in ACC
IN
Texas Instruments
Timing
TMS7002
TMS7042
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
SPI
Next Nibble, Shift Continues
0
First Nibble D
to $13
OUT
TMS70C02
TMS70C42
TMS32011*
TMS32020
TMS370C050
Put Null Data in ACC
Shift Continues, D
to ACC
OUT
0
Next Nibble D
to $14
OUT
RC
Clear Carry
Clear ACC
CLRA
XAS
OGI
XIS
*Requires external hardware
** Contact factory for interface information for processors not on this list
Third Nibble D
to ACC
to $15
OUT
1
0
Go (CS) Set
Third Nibble D
OUT
Hardware and Software Interface to COP402 Processor
LBI 1,3
Set B Reg. For Next Loop
LTC1290
COP402
GO
SK
CS
Motorola SPI (MC68HC05C4)
SCLK
•
•
•
•
The MC68HC05C4 transfers data MSB first and in 8-bit
increments. Programming the LTC1290 for MSB-first
format and 16-bit word length allows the 12-bit data
output to be received by the MPU as two 8-bit bytes with
the final four unused bits filled with zeros by the LTC1290.
ANALOG
INPUTS
D
IN
SO
SI
D
OUT
LTC1290 • AI08
D
OUT
from LTC1290 Stored in COP402 RAM
†
MSB
LOCATION $13
LOCATION $14
FIRST 4 BITS
SECOND 4 BITS
THIRD 4 BITS
B11
B7
B10
B6
B9
B5
B8
B4
LSB
B0
LOCATION $15
†
B3
B2
B1
MICROWIRE and MICROWIRE PLUS are trademarks of National Semiconductor Corp
B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
15
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Hardware and Software Interface to Motorola
MC68HC05C4 Processor
Parallel Port Microprocessors
When interfacing the LTC1290 to an MPU which has a
parallel port, the serial signals are created on the port with
software. Three MPU port lines are programmed to create
LTC1290
MC68HC05C4
CO
CS
SCK
SCLK
the CS, SCLK and D signals for the LTC1290. A fourth
•
•
•
•
ANALOG
INPUTS
IN
D
IN
MOSI
MISO
port line reads the DOUT line. An example is made of the
Intel 8051/8052/80C252 family.
D
OUT
LTC1290 • AI09
Intel 8051
D
OUT
from LTC1290 Stored in MC68HC05C4 RAM
To interface to the 8051, the LTC1290 is programmed for
MSB-first format and 12-bit word length. The 8051 gener-
MSB*
ates CS, SCLK and D on three port lines and reads DOUT
on the fourth.
IN
B11
B10
B9
B8
B7
B6
0
B5
0
B4
0
LOCATION $61
BYTE 1
BYTE 2
LSB
B0
Hardware and Software Interface to Intel 8051 Processor
B3
B2
B1
0
LOCATION $62
LTC1290
8051
*B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
P1.1
P1.2
D
OUT
•
•
•
•
•
•
•
•
MC68HC05C4 Code
D
IN
MNEMONIC
COMMENTS
ANALOG
INPUTS
SCLK
CS
P1.3
P1.4
LDA #$50
STA $0A
LDA #$FF
STA $06
LDA #$0F
STA $50
BCLR 0,$20
LDA $50
STA $0C
Configuration Data for SPCR
Load Data Into SPCR ($0A)
Config. Data for Port C DDR
Load Data Into Port C DDR
ALE
ACLK
LTC1290 • AI10
Load LTC1290 D Data Into ACC
IN
Load LTC1290 D Data Into $50
IN
START
CO Goes Low (CS Goes Low)
Load D Into ACC from $50
Load D Into SPI, Start SCK
D
OUT
from LTC1290 Stored in 8051 RAM
IN
MSB*
IN
B11
B10
B9
B8
B7
B6
B5
54
0
R2
R3
NOP
8 NOPs for Timing
LSB
B0
LDA $0B
LDA $0C
STA $61
STA $0C
Check SPI Status Reg
Load LTC1290 MSBs Into ACC
Store MSBs in $61
B3
B2
B1
0
0
0
Start Next SPI Cycle
*B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
NOP
6 NOPs for Timing
BSET 0,$02
LDA $0B
LDA $0C
STA $62
CO Goes High (CS Goes High)
Check SPI Status Register
Load LTC1290 LSBs Into ACC
Store LSBs in $62
16
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A
8051 Code
Sharing the Serial Interface
MNEMONIC
COMMENTS
The LTC1290 can share the same 3-wire serial interface
with other perpheral components or other LTC1290s (see
Figure 5). In this case, the CS signals decide which
LTC1290 is being addressed by the MPU.
MOV P1,#02H
CLR P1.3
SETB P1.4
MOV A,#0EH
CLR P1.4
MOV R4,#08H
NOP
Bit 1 Port 1 Set as Input
SCLK Goes Low
CS Goes High
D Word for LTC1290
IN
CS Goes Low
CONT
LOOP
Load Counter
ANALOG CONSIDERATIONS
1. Grounding
Delay for Deglitcher
Read Data Bit Into Carry
Rotate Data Bit Into ACC
MOV C,P1.1
RLC
A
MOV P1.2,C
SETB P1.3
CLR P1.3
DJNZ R4,LOOP
MOV R2,A
MOV C,P1.1
Output D Bit to LTC1290
IN
SCLK Goes High
SCLK Goes Low
Next Bit
Store MSBs in R2
Read Data Bit Into Carry
Clear ACC
Rotate Data Bit Into ACC
SCLK Goes High
The LTC1290 should be used with an analog ground plane
and single point grounding techniques.
AGND(Pin11)shouldbetieddirectlytothis groundplane.
CLR
RLC
A
A
DGND (Pin 10) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
SETB P1.3
CLR P1.3
MOV C,P1.1
SCLK Goes Low
Read Data Bit Into Carry
Rotate Data Bit Into ACC
SCLK Goes High
V (Pin 20) should be bypassed to the ground plane with
RLC
A
CC
a 22µF tantalum with leads as short as possible. V– (Pin
12) should be bypassed with a 0.1µF ceramic disk. For
single supply applications, V– can be tied to the ground
plane.
SETB P1.3
CLR P1.3
MOV C,P1.1
SCLK Goes Low
Read Data Bit Into Carry
Rotate Data Bit Into ACC
SCLK Goes High
RLC
A
SETB P1.3
CLR P1.3
MOV C, P1.1
RRC A
RRC A
RRC A
SCLK Goes Low
It is also recommended that REF– (Pin 13) and COM (Pin
9) be tied directly to the ground plane. All analog inputs
should be referenced directly to the single point ground.
Digital inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Read Data Bit Into Carry
Rotate Right Into ACC
Rotate Right Into ACC
Rotate Right Into ACC
Rotate Right Into ACC
Store LSBs in R3
SCLK Goes High
SCLK Goes Low
CS Goes High
RRC A
MOV R3,A
SETB P1.3
CLR P1.3
SETB P1.4
MOV R5,#0BH
Load Counter
DELAY
DJNZ R5,DELAY Go to Delay if Not Done
2
1
0
OUTPUT PORT
SERIAL DATA
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1290s
3
3
3
3
CS
LTC1290
CS
LTC1290
CS
LTC1290
MPU
8 CHANNELS
8 CHANNELS
8 CHANNELS
LTC1290 F05
Figure 5. Several LTC1290s Sharing One 3-Wire Serial Interface
17
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V
CC
22µF
TANTALUM
20
HORIZONTAL: 10µs/DIV
Figure 7. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors
–
V
0.1µF
10
CERAMIC
DISK
ANALOG
GROUND
PLANE
LTC1290 F06
CS
Figure 6. Example Ground Plane for the LTC1290
Figure6shows anexampleofanidealgroundplanedesign
for a two-sided board. Of course, this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
V
CC
HORIZONTAL: 10µs/DIV
2. Bypassing
Figure 8. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce
spikes settle quickly and do not cause a problem. How-
ever, iflargesourceresistances areusedorifslowsettling
opamps drivetheinputs, caremustbetakentoinsurethat
the transients caused by the current spikes settle com-
pletely before the conversion begins.
errors ornoiseintheoutputcode. V noiseandripplecan
CC
be kept below 0.5mV by bypassing the V pin directly to
CC
the analog ground plane with a 22µF tantalum capacitor
and leads as short as possible. The lead from the device to
the V supply should also be kept to a minimum and the
CC
V supply should have a low output impedance such as
CC
Source Resistance
that obtained from a voltage regulator (e.g., LT323A).
The analog inputs of the LTC1290 look like a 100pF
Figures 7 and 8 show the effects of good and poor V
CC
capacitor (C ) in series with a 500Ω resistor (RON) as
IN
bypassing.
shown in Figure 9. C gets switched between the selected
IN
“+”and“–”inputs onceduringeachconversioncycle. Large
external source resistors and capacitances will slow the
settlingoftheinputs.Itis importantthattheoverallRCtime
constants be short enough to allow the analog inputs to
completely settle within the allowed time.
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1290 have
capacitive switching input current spikes. These current
18
LTC1290
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“+”
“–” Input Settling
INPUT
R
+
SOURCE
LTC1290
V
+
IN
Attheendofthesamplephasetheinputcapacitorswitches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
RSOURCE– and C2 will improve settling time. If large “–”
inputsourceresistancemustbeused, thetimeallowedfor
4TH SCLK
= 500Ω
C1
R
ON
“–”
INPUT
C =
IN
100pF
LAST SCLK
R
–
SOURCE
V
IN
–
LTC1290 F09
C2
Figure 9. Analog Input Equivalent Circuit
“+” Input Settling
settling can be extended by using a slower ACLK fre-
This input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 10). The sample
phasestarts atthe4thSCLKcycleandlasts untilthefalling
edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
depending on the selected word length). The voltage on
the “+” input must settle completely within this sample
time. Minimizing RSOURCE+ and C1 will improve the input
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 2µs, RSOURCE+ < 1k
and C1 < 20pF will provide adequate settling.
–
quency. At the maximum ACLK rate of 4MHz, RSOURCE
<
250Ω and C2 < 20pF will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommo-
date slower op amps. Most op amps including the LT1006
and LT1013 single supply op amps can be made to settle
well even with the minimum settling windows of 2µs (“+”
input) and 1µs (“–” input) which occur at the maximum
“+” INPUT
SAMPLE
MUST SETTLE
HOLD
DURING THIS TIME
MUX ADDRESS
SHIFTED IN
t
SMPL
CS
• • •
• • •
• • •
LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORD LENGTH)
SCLK
1
2
3
4
1
2
3
4
• • •
ACLK
1ST BIT TEST
“–” INPUT MUST SETTLE
DURING THIS TIME
“+” INPUT
“–” INPUT
1290 • F10
Figure 10. “+” and “–” Input Settling Windows
19
LTC1290
PPLICATI
clock rates (ACLK = 4MHz and SCLK = 2MHz). Figures 11
and 12 show examples of adequate and poor op amp
settling.
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I
DC
R
FILTER
V
IN
"+"
LTC1290
"–"
C
FILTER
LTC1290 F13
Figure 13. RC Input Filtering
Input Leakage Current
Input leakage currents can also create errors if the source
resistancegets toolarge.Forinstance,themaximuminput
leakage specification of 1µA (at 125°C) flowing through a
source resistance of 1kΩ will cause a voltage drop of 1mV
or 0.8LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see the
typical curve of Input Channel Leakage Current vs Tem-
perature).
HORIZONTAL: 500ns/DIV
Figure 11. Adequate Settling of Op Amps Driving Analog Input
Noise Coupling Into Inputs
High source resistance input signals (>500Ω) are more
sensitive to coupling from external sources. It is prefer-
able to use channels near the center of the package (i.e.,
CH2 to CH7) for signals which have the highest output
resistance because they are essentially shielded by the
pins on the package ends (DGND and CH0). Grounding
any unused inputs (especially the end pin, CH0) will also
reduce outside coupling into high source resistances.
HORIZONTAL: 20µs/DIV
Figure 12. Poor Op Amp Settling Can Cause A/D Errors
4. Sample-and-Hold
Single-Ended Inputs
RC Input Filtering
Itis possibletofiltertheinputs withanRCnetworkas shown
inFigure13. Forlargevalues ofCF (e.g., 1µF), thecapacitive
input switching currents are averaged into a net DC current.
Therefore,afiltershouldbechosenwithasmallresistorand
large capacitor to prevent DC drops across the resistor. The
magnitude of the DC current is approximately IDC
(100pF)(VIN/tCYC) and is roughly proportional to V . When
running at the minimum cycle time of 20µs, the input
current equals 25µA at V = 5V. In this case, a filter resistor
of 5Ω will cause 0.1LSB of full-scale error. If a larger filter
resistor must be used, errors can be eliminated by increas-
ingthecycletimeas showninthetypicalcurveofMaximum
Filter Resistor vs Cycle Time.
The LTC1290 provides a built-in sample-and-hold (S&H)
function for all signals acquired in the single-ended mode
(COM pin grounded). This sample-and-hold allows the
LTC1290 to convert rapidly varying signals (see the typical
curve of S&H Acquisition Time vs Source Resistance). The
input voltage is sampled during the tSMPL time as shown in
Figure 10. The sampling interval begins after the fourth MUX
address bit is shifted in and continues during the remainder
of the data transfer. On the falling edge of the final SCLK, the
S&H goes into hold mode and the conversion begins. The
voltagewillbeheldoneitherthe8th, 12thor16thfallingedge
of the SCLK depending on the word length selected.
=
IN
IN
20
LTC1290
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Differential Inputs
When driving the reference inputs, two things should be
kept in mind:
With differential inputs or when the COM pin is not tied to
ground, the A/D no longer converts just a single voltage but
rather the difference between two voltages. In these cases,
thevoltageontheselected“+”inputis stillsampledandheld
and therefore may be rapidly time varying just as in single-
endedmode. However, thevoltageontheselected“–”input
must remain constant and be free of noise and ripple
throughouttheconversiontime.Otherwise,thedifferencing
operationmaynotbeperformedaccurately.Theconversion
time is 52 ACLK cycles. Therefore, a change in the “–” input
voltage during this interval can cause conversion errors.
Forasinusoidalvoltageonthe“–”inputthis errorwouldbe:
1. Transients on the reference inputs caused by the
capacitive switching currents must settle completely
during each bit test (each 4 ACLK cycles). Figures 15
and 16 show examples of both adequate and poor
settling. Using a slower ACLK will allow more time for
the reference to settle. However, even at the maximum
ACLK rate of 4MHz most references and op amps can
be made to settle within the 1µs bit time. For example
theLT1027willsettleadequatelyorwitha10µFbypass
capacitor at REF+ the LT1021 can also be used.
2. It is recommended that REF– input be tied directly to
the analog ground plane. If REF– is biased at a voltage
otherthanground, thevoltagemustnotchangeduring
a conversion cycle. This voltage must also be free of
noise and ripple with respect to analog ground.
V
ERROR (MAX) = (VPEAK)(2π)[ f(“–”)](52/fACLK
Where f(“–”) is the frequency of the “–” input voltage,
PEAK is its peak amplitude and fACLK is the frequency of
)
V
theACLK. Inmostcases VERROR willnotbesignificant. For
a 60Hz signal on the “–” input to generate a 0.25LSB error
(300µV) with the converter running at ACLK = 4MHz, its
peak value would have to be 61mV.
5. Reference Inputs
The voltage between the reference inputs of the LTC1290
defines the voltage span of the A/D converter. The refer-
ence inputs will have transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 14). During each bit test of the conversion
(every 4 ACLK cycles), a capacitive current spike will be
generated on the reference pins by the A/D. These current
spikes settle quickly and do not cause a problem. How-
ever, if slow settling circuitry is used to drive the reference
inputs, caremustbetakentoinsurethattransients caused
by these current spikes settle completely during each bit
test of the conversion.
HORIZONTAL: 1µs/DIV
Figure 15. Adequate Reference Settling
REF+
LTC1290
14
EVERY 4 ACLK CYCLES
R
OUT
R
ON
V
REF
8pF TO 40pF
REF–
13
LTC 1290 F14
HORIZONTAL: 1µs/DIV
Figure 14. Reference Input Equivalent Circuit
Figure 16. Poor Reference Settling Can Cause A/D Errors
21
LTC1290
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6. Reduced Reference Operation
reduce the range of input voltages over which a stable
output code can be achieved by 0.64LSB. In this case
averaging readings may be necessary.
The effective resolution of the LTC1290 can be increased
by reducing the input span of the converter. The LTC1290
exhibits good linearity and gain over a wide range of This noise data was taken in a very clean setup. Any setup
reference voltages (see the typical curves of Linearity and
Gain Error vs Reference Voltage). However, care must be
taken when operating at low values of VREF because of the
induced noise (noise or ripple on V , VREF, V or V–) will
add to the internal noise. The lower the reference voltage
to be used, the more critical it becomes to have a clean,
CC IN
reduced LSB step size and the resulting higher accuracy noise-free setup.
requirementplacedontheconverter. Thefollowingfactors
7. LTC1290 AC Characteristics
must be considered when operating at low VREF values:
Two commonly used figures of merit for specifying the
dynamic performance of the A/D’s in digital signal pro-
cessing applications are the Signal-to-Noise Ratio (SNR)
and the “effective number of bits (ENOB).” SNR is defined
as the ratio of the RMS magnitude of the fundamental to
the RMS magnitude of all the nonfundamental signals up
to the Nyquist frequency (half the sampling frequency).
The theoretical maximum SNR for a sine wave input is
given by:
1. Offset
2. Noise
Offset with Reduced V
REF
The offset of the LTC1290 has a larger effect on the output
code when the A/D is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Unadjusted Offset Error vs
Reference Voltage shows how offset in LSBs is related to
SNR = (6.02N + 1.76dB)
reference voltage for a typical value of V . For example,
OS
where N is the number of bits. Thus the SNR is a function
oftheresolutionoftheA/D.Foranideal12-bitA/DtheSNR
is equal to 74dB. A Fast Fourier Transform(FFT) plot of the
output spectrum of the LTC1290 is shown in Figures 17a
and 17b. The input (fIN) frequencies are 1kHz and 25kHz
with the sampling frequency (fS) at 50.6kHz. The SNR
obtained from the plot are 73.25dB and 72.54dB.
a VOS of 0.1mV which is 0.1LSB with a 5V reference
becomes 0.4LSB with a 1.25V reference. If this offset is
unacceptable, it can be corrected digitally by the receiving
system or by offsetting the “–” input to the LTC1290.
Noise with Reduced V
REF
The total input referred noise of the LTC1290 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificantwitha5Vreferencebutwillbecomealarger
fraction of an LSB as the size of the LSB is reduced. The
typical curve of Noise Error vs Reference Voltage shows
the LSB contribution of this 200µV of noise.
Rewriting the SNR expression it is possible to obtain the
equivalent resolution based on the SNR measurement.
N = (SNR – 1.76dB)/6.02
This is the so-called effective number of bits (ENOB). For
the example shown in Figures 17a and 17b, N = 11.9 bits
and11.8bits,respectively.Figure18shows aplotofENOB
as a function of input frequency. The curve shows the
A/D’s ENOB remain in the range of 11.9 to 11.8 for input
frequencies up to fS/2.
For operation with a 5V reference, the 200µV noise is only
0.16LSB peak-to-peak. In this case, the LTC1290 noise
will contribute virtually no uncertainty to the output code.
However, for reduced references, the noise may become
asignificantfractionofanLSBandcauseundesirablejitter
in the output code. For example, with a 1.25V reference,
this same 200µV noise is 0.64LSB peak-to-peak. This will
Figure19shows anFFTplotoftheoutputspectrumfortwo
tones applied to the input of the A/D. Nonlinearities in the
A/D will cause distortion products at the sum and differ-
ence frequencies of the fundamentals and products of the
22
LTC1290
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f
f
= 1kHz
0
f
f
= 25kHz
IN
0
–20
IN
= 50.6kHz
= 50.6kHz
SAMPLE
SAMPLE
SNR = 73.25dB
SNR = 72.54dB
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
4
8
12
16
20
24
0
4
8
12
16
20
24
FREQUENCY (kHz)
FREQUENCY (kHz)
1290 • F17a
1290 • F17b
Figure 17a. LTC1290 FFT Plot
Figure 17b. LTC1290 FFT Plot
f
= 50.6kHz
12
11.6
11.2
10.8
10.4
10
SAMPLE
f
= 5.1kHz
= 5.6kHz
0
–20
IN1
f
IN2
f
= 50.6kHz
SAMPLE
–40
–60
–80
9.6
–100
–120
9.2
8.8
0
20
40
60
80
100
0
4
8
12
16
20
24
FREQUENCY (kHz)
FREQUENCY (kHz)
1290 F18
1290 • F19
Figure 18. LTC1290 ENOB vs Input Frequency
Figure 19. LTC1290 FFT Plot
fundamentals. This is classically referred to as
intermodulation distortion (IMD).
then the following guidelines can be used. Limit the
current to 7mA per channel and 28mA for all channels.
This means fourchannels canhandle7mAofinputcurrent
each. Reducing the ACLK and SCLK frequencies from the
maximum of 4MHz and 2MHz, respectively, (see Typical
Peformance Characteristics curves Maximum ACLK Fre-
quency vs Source Resistance and Sample-and-Hold
Acquisition Time vs Source Resistance) allows the use of
8. Overvoltage Protection
Applying signals to the analog MUX that exceed the
positive or negative supply of the device will degrade the
accuracy of the A/D and possibly damage the device. For
example this condition would occur if a signal is applied to
the analog MUX before power is applied to the LTC1290.
Another example is the input source is operating from
different supplies of larger value than the LTC1290. These
conditions should be prevented either with proper supply
sequencing or by use of external circuitry to clamp or
current limit the input source. As shown in Figure 20, a 1k
resistor is enough to stand off ±15V (15mA for one only
channel). If more than one channel exceeds the supplies
1k
V
IN
V
CC
5V
CH0
22µF
LTC1290
–
V
–5V
0.1µF
DGND
AGND
1290 F20
Figure 20. Overvoltage Protection for MUX
23
LTC1290
PPLICATI
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largercurrentlimitingresistors.Use1N4148diodeclamps
powersupplyreversalfromoccuringwhenaninputsource
is appliedtotheanalogMUXbeforepoweris appliedtothe
device. Power supply reversal occurs, for example, if the
fromtheMUXinputs toV andV– ifthevalueoftheseries
CC
resistor will not allow the maximum clock speeds to be
usedorifanunknownsourceis usedtodrivetheLTC1290
MUX inputs.
input is pulled below V– then V will pull a diode drop
CC
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above V then
CC
How the various power supplies to the LTC1290 are
applied can also lead to overvoltage conditions. For single
V– will be pulled a diode drop above ground. If no inputs
are present on the MUX, the Schottky diodes are not
supply operation (i.e., unipolar mode), if V and REF+ are
required if V– is applied first, then V .
CC
CC
not tied together, then V should be turned on first, then
CC
REF+. If this sequence cannot be met, connecting a diode
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
from REF+ to V is recommended (see Figure 21).
CC
exceed the device V without damaging the device.
CC
For dual supplies (bipolar mode) placing two Schottky
diodes from V and V– to ground (Figure 23) will prevent
CC
20
V
CC
5V
V
CC
5V
1N5817
22µF
22µF
LTC1290
LTC1290
1N4148
–
V
–5V
14
1N5817
0.1µF
DGND
AGND
+
REF
V
REF
1290 F21
1290 F22
Figure 21
Figure 22. Power Supply Reversal
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TYPICAL APPLICATI S
A “Quick Look” Circuit for the LTC1290
A “Quick Look” Circuit for the LTC1290
5V
Users can get a quick look at the function and timing of the
LTC1290 by using the following simple circuit. REF+ and
22µF
LTC1290
f/128
V
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
CC
D are tied to VCC selecting a 5V input span, CH7 as a
IN
0.1µF
CLK
EN
V
ACLK
SCLK
DD
single-ended input, unipolar mode, MSB-first format and
16-bit word length. ACLK and SCLK are tied together and
driven by an external clock. CS is driven at 1/128 the clock
rate by the CD4520 and DOUT outputs the data. All other
pins are tied to a ground plane. The output data from the
DOUT pin can be viewed on an oscilloscope which is set up
to trigger on the falling edge of CS.
f
RESET
Q4
Q1
D
IN
Q2
Q3
D
OUT
CD4520
Q3
Q2
Q1
CS
+
Q4
REF
–
V
IN
RESET
EN
REF
–
V
CLK
V
SS
AGND
CLOCK IN
2MHz MAX
1290 TA02
TO
OSCILLOSCOPE
24
LTC1290
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TYPICAL APPLICATI S
Scope Trace of LTC1290 “Quick Look” Circuit
Showing A/D Output of 010101010101 (555HEX
)
CS
ACLK/
SCLK
DOUT
FILLS
ZEROS
LSB
(B0)
DEGLITCHER
TIME
MSB
(B11)
VERTICAL: 5V/DIV
HORIZONTAL: 1µs/DIV
TM
SNEAK-A-BIT
The LTC1290’s unique ability to software select the polar-
ity of the differential inputs and the output word length is
used to achieve one more bit of resolution. Using the
circuit below with two conversions and some software, a
2’s complement 12-bit + sign word is returned to memory
inside the MPU. The MC68HC05C4 was chosen as an
example, however, any processor could be used.
Two 12-bit unipolar conversions are performed: the first
over a 0V to 5V span and the second over a 0V to –5V span
(by reversing the polarity of the inputs). The sign of the
input is determined by which of the two spans contained
it. Then the resulting number (ranging from –4095 to
+4095 decimal) is converted to 2’s complement notation
and stored in RAM.
SNEAK-A-BIT Circuit
SNEAK-A-BIT
V
IN
22µF
5V
0V
5V
0V
LT1021-5
9V
(+) CH6
(–) CH7
V
IN
1ST CONVERSION
4096 STEPS
2MHz
CLOCK
SOFTWARE
8191
STEPS
1ST CONVERSION
0V
V
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CC
ACLK
SCLK
(–) CH6
V
IN
2ND CONVERSION
4096 STEPS
MC68HC05C4
SCLK
OTHER CHANNELS
OR SNEAK-A-BIT
INPUTS
(+) CH7
MOSI
MISO
CO
D
–5V
–5V
IN
2ND CONVERSION
D
OUT
LTC1290
1290 TA05
CS
V
IN
+
REF
–5V TO 5V
–
1290 TA04
REF
–
V
AGND
DGND
0.1µF
–5V
SNEAK-A-BIT is a trademark of Linear Technology Corp.
25
LTC1290
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TYPICAL APPLICATI S
SNEAK-A-BIT Code
SNEAK-A-BIT Code for the LTC1290 Using the MC68HC05C4
D
OUT
from LTC1290 in MC68HC05C4 RAM
MNEMONIC
DESCRIPTION
Sign
READ –/+: LDA #$3F
Load D Word for LTC1290 into ACC
IN
LOCATION $77 B12 B11 B10 B9
B8
B7
B6
B5
JSR TRANSFER Read LTC1290 Routine
LDA $60
STA $71
LDA $61
Load MSBs from LTC1290 into ACC
Store MSBs in $71
Load LSBs from LTC1290 into ACC
Store LSBs in $72
LSB
B0
LOCATION $87 B4
B3
B2
B1
Filled with 0s
STA $72
RTS
Return
D Words for LTC1290
IN
READ +/–: LDA #$7F
Load D Word for LTC1290 into ACC
IN
JSR TRANSFER Read LTC1290 Routine
MSBF
LDA $60
STA $73
Load MSBs from LTC1290 into ACC
Store MSBs in $73
MUX Addr.
UNI
Word
Length
(ODD/SIGN)
LDA $61
STA $74
RTS
Load LSBs from LTC1290 into ACC
Store LSBs in $74
Return
D
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IN
D
IN
2
1
1
TRANSFER: BCLR 0,$02
STA $0C
CS Goes Low
Load D into SPI, Start Transfer
IN
D
IN
3
LOOP 1:
TST $0B
BPL LOOP 1
LDA $0C
STA $0C
STA $60
TST $0B
BPL LOOP 2
BSET 0,$02
LDA $0C
STA $61
RTS
Test Status of SPIF
1290 TA06
Loop to Previous Instruction if Not Done
Load Contents of SPI Data Reg. into ACC
Start Next Cycle
Store MSBs in $60
Test Status of SPIF
Loop to Previous Instruction if Not Done
CS Goes High
Load Contents of SPI Data Reg. into ACC
Store LSBs in $61
SNEAK-A-BIT Code for the LTC1290 Using the MC68HC05C4
LOOP 2:
MNEMONIC
DESCRIPTION
LDA #$50
STA $0A
LDA #$FF
STA $06
BSET 0,$02
Configuration Data for SPCR
Load Configuration Data into $0A
Configuration Data for Port C DDR
Load Configuration Data into Port C DDR
Make Sure CS is High
Return
CHK SIGN: LDA $73
ORA $74
BEQ MINUS
CLC
Load MSBs of ± Read into ACC
Or ACC (MSBs) with LSBs of ± Read
If Result is 0 Go to Minus
Clear Carry
Rotate Right $73 Through Carry
Rotate Right $74 Through Carry
Load MSBs of ± Read into ACC
Store MSBs in RAM Location $77
Load LSBs of ± Read into ACC
Store LSBs in RAM Location $87
Go to End of Routine
JSR READ –/+ Dummy Read Configures LTC1290
for next read
JSR READ –/+ Read CH6 with Respect to CH7
JSR READ –/+ Read CH7 with Respect to CH6
JSR CHK Sign Determines which Reading has Valid Data,
Converts to 2’s Complement and
ROR $73
ROR $74
LDA $73
STA $77
LDA $74
STA $87
BRA END
Stores in RAM
MINUS:
CLC
Clear Carry
ROR $71
ROR $72
COM $71
COM $72
LDA $72
ADD #$01
STA $72
CLRA
Shift MSBs of ± Read Right
Shift LSBs of ± Read Right
1’s Complement of MSBs
1’s Complement of LSBs
Load LSBs into ACC
Add 1 to LSBs
Store ACC in $72
Clear ACC
ADC $71
STA $71
STA $77
LDA $72
STA $87
RTS
Add with Carry to MSBs. Result in ACC
Store ACC in $71
Store MSBs in RAM Location $77
Load LSBs in ACC
Store LSBs in RAM Location $87
Return
END:
26
LTC1290
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TYPICAL APPLICATI S
Power Shutdown
To place the device in power shutdown the word length
bits are set to WL1 = 0 and WL0 = 1. The LTC1290 is
powered up on the next request for a conversion and it’s
ready to digitize an input signal immediately.
For battery-powered applications it is desirable to keep
power dissipation at a minimum. The LTC1290 can be
powered down when not in use reducing the supply
current from a nominal value of 5mA to typically 5µA (with
ACLKturnedoff). SeethecurveforSupplyCurrent(Power
Shutdown)vs ACLKifACLKcannotbeturnedoffwhenthe
LTC1290 is powered down. In this case the supply current
is proportional to the ACLK frequency and is independent
oftemperatureuntilitreaches themagnitudeofthesupply
current attained with ACLK turned off.
Power Shutdown Timing Considerations
After power shutdown has been requested, the LTC1290
is powered up on the next request for a conversion. This
request can be initiated either by bringing CS low or by
starting the next cycle of SCLKs if CS is kept low (see
Figures 3 and 4). When the SCLK frequency is much
slower than the ACLK frequency a situation can arise
where the LTC1290 could power down and then prema-
turely power back up. Power shutdown begins at the
negative going edge of the 10th SCLK once it has been
requested. A dummy conversion is executed and the
LTC1290 waits for the next request for conversion. If the
SCLKs havenotfinishedoncetheLTC1290has finishedits
dummy conversion, it will recognize the next remaining
SCLKs as a request to start a conversion and power up the
LTC1290 (see Figure 23). To prevent this, bring either CS
high at the 10th SCLK (Figure 24) or clock out only 10
SCLKs (Figure 25) when power shutdown is requested.
As an example of how to use this feature let’s add this to
the previous application, SNEAK-A-BIT. After the CHK
SIGN subroutine call insert the following:
•
•
JSR CHK SIGN
Determines which reading has valid
data, converts to 2’s complement
and stores in RAM
JSR SHUTDOWN
LTC1290 power shutdown routine
The actual subroutine is:
SHUTDOWN: LDA #$3D
Load D word for
IN
LTC1290 into ACC
JSR TRANSFER Read LTC1290 routine
RTS
Return
CS
SCLK
1
10
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
POWER UP 1290 TAF23
Figure 23. Power Shutdown Timing Problem
CS
SCLK
POWER UP
1
10
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
1290 TAF24
Figure 24. Power Shutdown Timing
CS
1
10
POWER UP
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
1290 TAF25
Figure 25. Power Shutdown Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
27
LTC1290
U
Dimensions in inches (millimeters) unless otherwise noted.
J Package
PACKAGE DESCRIPTIO
20-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
1.060
(26.924)
MAX
0.200
0.015 – 0.060
(0.381 – 1.524)
0.300 BSC
(5.080)
MAX
CORNER LEADS OPTION
(4 PLCS)
20
11
(0.762 BSC)
19 18 17 16 15 14 13 12
0.023 – 0.045
0.220 – 0.310 0.025
(0.584 – 1.143)
HALF LEAD
OPTION
(5.588 – 7.874) (0.635)
RAD TYP
0.008 – 0.018
0° – 15°
(0.203 – 0.457)
0.045 – 0.068
2
3
4
5
6
7
8
9
(1.143 – 1.727)
FULL LEAD
OPTION
1
10
J20 1197
0.005
0.125
(3.175)
MIN
0.100 ± 0.010
(0.127)
MIN
0.045 – 0.068
(1.143 – 1.727)
0.014 – 0.026
(2.540 ± 0.254)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
(0.356 – 0.660)
N Package
20-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.040*
(26.416)
MAX
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
0.045 – 0.065
(1.143 – 1.651)
(3.302 ± 0.127)
20 19 18 17 16 15 14 13 12 11
0.020
(0.508)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.009 – 0.015
0.065
(1.651)
TYP
(0.229 – 0.381)
+0.035
–0.015
1
2
3
4
5
6
7
8
9
10
0.325
0.125
0.005
(0.127)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
N20 1197
+0.889
–0.381
(3.175)
MIN
8.255
(
)
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.291 – 0.299**
(7.391 – 7.595)
0.496 – 0.512*
(12.598 – 13.005)
0.037 – 0.045
0.093 – 0.104
0.010 – 0.029
(0.254 – 0.737)
× 45°
20 19 18 17 16 15 14 13 12 11
(0.940 – 1.143)
(2.362 – 2.642)
0° – 8° TYP
0.394 – 0.419
(10.007 – 10.643)
0.050
(1.270)
TYP
NOTE 1
NOTE 1
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
(0.229 – 0.330)
0.016 – 0.050
0.014 – 0.019
(0.406 – 1.270)
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S20 (WIDE) 0396
1
2
3
4
5
6
7
8
9 10
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
*
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
**
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1286/LTC1298
12-Bit, Micropower Serial ADC in SO-8
1- or 2-Channel, Autoshutdown
LTC1293/LTC1294/LTC1296 12-Bit, Multiplexed Serial ADC
LTC1594/LTC1598 12-Bit, Micropower Serial ADC
6-, 8- or 8-Channel with Shutdown Output
4- or 8-Channel, 3V Versions Available
1290fcs, sn1290 LT/GP 1098 2K REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1991
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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