LTC1291DCJ8 [Linear]
Single Chip 12-Bit Data Acquisition System; 单芯片12位数据采集系统
| 型号： | LTC1291DCJ8 |
| 厂家： | 
Linear |
| 描述： | Single Chip 12-Bit Data Acquisition System |
| 文件： | 总20页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1291
Single Chip 12-Bit
Data Acquisition System
U
FEATURES
DESCRIPTIO
■
Built-In Sample-and-Hold
The LTC®1291 is a data acquisition system that contains
a serial I/O successive approximation A/D converter. It
uses LTCMOSTM switched capacitor technology to per-
form a 12-bit unipolar A/D conversion. The input multi-
plexer can be configured for either single-ended or differ-
ential inputs. An on-chip sample-and-hold is included on
the “+” input. When the LTC1291 is idle, it can be powered
down in applications where low power consumption is
desired. An external reference is not required because the
LTC1291 takes its reference from the power supply (VCC).
All these features are packaged in an 8-pin DIP.
■
Single Supply 5V Operation
■
Power Shutdown
■
Direct 3- or 4-Wire Interface to Most MPU Serial
Ports and All MPU Parallel Ports
Two-Channel Analog Multiplexer
Analog Inputs Common Mode to Supply Rails
8-Pin DIP Package
■
■
■
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KEY SPECIFICATIO S
■
TheserialI/Oisdesignedtocommunicatewithoutexternal
hardware to most MPU serial ports and all MPU parallel
I/O ports allowing data to be transmitted over three or four
wires. Given the accuracy, ease of use and small package
size, this device is well suited for digitizing analog signals
in remote applications where minimum number of inter-
connects, small physical size, and low power consump-
tion are important.
Resolution: 12 Bits
■
Fast Conversion Time: 12µs Max Over Temp.
■
Low Supply Current:
6.0mA (Typ) Active Mode
10µA (Max) Shutdown Mode
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOSTM is a trademark of Linear Technology Corporation
U
TYPICAL APPLICATIO
2-Channel 12-Bit Data Acquisition System
22µF
TANTALUM
Channel-to-Channel
5V
INL Matching
0.5
0.4
0.3
V
(V
CC REF
)
DO
CS
0.2
0.1µF
0.1
CH0
CLK
SCK
0
2-CHANNEL
MUX*
LTC1291
MC68HC11
–0.1
CH1
GND
D
OUT
MISO
–0.2
–0.3
MOSI
D
IN
–0.4
1291 TA01
–0.5
0
512 1024 1536
2048
CODE
2560 4096
3072 3584
*FOR OVERVOLTAGE PROTECTION, LIMIT THE INPUT CURRENT TO 15mA
PER PIN OR CLAMP THE INPUTS TO V AND GND WITH 1N4148 DIODES.
CC
1291 TA02
CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED CHANNEL OR
THE OTHER CHANNEL IS OVERVOLTAGED (V < GND OR V > V ). SEE
IN
IN
CC
SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION.
1291fa
1
LTC1291
W W W
U
W
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ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
(Notes 1 and 2)
Supply Voltage (VCC) to GND.................................. 12V
Voltage
TOP VIEW
ORDER PART
NUMBER
1
2
3
4
V
(V
)
8
7
6
5
CS
CH0
CH1
CC REF
Analog Inputs............................ –0.3V to VCC + 0.3V
Digital Inputs........................................ –0.3V to 12V
Digital Outputs .......................... –0.3V to VCC + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
CLK
D
LTC1291BCN8
LTC1291CCN8
LTC1291DCN8
OUT
D
GND
IN
N8 PACKAGE
8-LEAD PLASTIC DIP
JMAX = 100°C, θJA = 130°C/ W (N8)
T
LTC1291BC, LTC1291CC,
LTC1291DC............................................ 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
J8 PACKAGE
LTC1291BCJ8
LTC1291CCJ8
LTC1291DCJ8
8-LEAD CERAMIC DIP
TJMAX = 150°C, θJA = 100°C/ W (J8)
OBSOLETE PACKAGE
Consider N8 Package for Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
U
U W
The ● denotes the specifications
CO VERTER A D ULTIPLEXER CHARACTERISTICS
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
LTC1291B
LTC1291C
LTC1291D
PARAMETER
Offset Error
CONDITIONS
(Note 4)
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
UNITS
LSB
●
●
●
●
±3.0
±0.5
±1.0
12
±3.0
±0.5
±2.0
12
±3.0
±0.75
±4.0
12
Linearity Error (INL)
Gain Error
(Note 4 & 5)
(Note 4)
LSB
LSB
Minimum Resolution for which No
Missing Codes are Guaranteed
Bits
Analog Input Range
(Note 7)
V
–0.05V to V + 0.05V
CC
On Channel Leakage Current
(Note 8)
On Channel = 5V
Off Channel = 0V
●
●
●
●
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
µA
On Channel = 0V
Off Channel = 5V
µA
µA
µA
Off Channel Lekage Current
(Note 8)
On Channel = 5V
Off Channel = 0V
On Channel = 0V
Off Channel = 5V
AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
LTC1291B/LTC1291C/LTC1291D
SYMBOL
PARAMETER
CONDITIONS
= 5V (Note 6)
MIN
TYP
MAX
UNITS
MHz
f
t
t
t
Clock Frequency
Analog Input Sample Time
Conversion Time
Total Cycle Time
V
(Note 9)
1.0
CLK
CC
See Operating Sequence
2.5
12
CLK Cycles
CLK Cycles
Cycles
SMPL
CONV
CYC
See Operating Sequence
See Operating Sequence (Note 6)
18 CLK
+ 500ns
t
Delay Time, CLK↓ to D
Data Valid
OUT
See Test Circuits
●
160
300
ns
dDO
1291fa
2
LTC1291
The ● denotes the specifications which apply over the full operating temperature range,
AC CHARACTERISTICS
otherwise specifications are at TA = 25°C. (Note 3)
LTC1291B/LTC1291C/LTC1291D
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
150
200
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
Delay Time, CS↑ to D
Hi-Z
OUT
See Test Circuits
See Test Circuits
●
●
80
ns
dis
Delay Time, CLK↓ to D
Enabled
OUT
80
ns
en
Hold Time, D after CLK↑
V
= 5V (Note 6)
50
ns
hDI
IN
CC
Time Output Data Remains Valid after CLK↓
CLK High Time
130
ns
hDO
WHCLK
WLCLK
f
V
V
= 5V (Note 6)
= 5V (Note 6)
300
400
ns
CC
CC
CLK Low Time
ns
D
D
Fall Time
See Test Circuits
See Test Circuits
●
●
65
25
130
50
ns
OUT
Rise Time
ns
r
OUT
Setup Time, D Stable before CLK↑
V
V
V
V
= 5V (Note 6)
= 5V (Note 6)
= 5V (Note 6)
= 5V (Note 6)
50
50
ns
ns
suDI
suCS
WHCS
WLCS
IN
CC
CC
CC
CC
Setup Time, CS↓ before CLK↑
CS High Time During Conversion
CS Low Time During Data Transfer
Input Capacitance
500
18
ns
CLK Cycles
C
Analog Inputs On Channel
Analog Inputs Off Channel
Digital Inputs
100
5
5
pF
pF
pF
IN
U
The ● denotes the specifications which
D
A
ELECTRICAL CHARACTERISTICS
DC
DIGITAL
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
LTC1291B/LTC1291C/LTC1291D
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.0
IH
CC
CC
IN
0.8
2.5
V
IL
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
OH
V
V
= 4.75V, I
= 4.75V, I
= –10µA
= – 360µA
4.7
4.0
V
V
CC
OUT
OUT
●
●
2.4
CC
V
Low Level Output Voltage
High Z Output Leakage
V
CC
= 4.75V, I
= 1.6mA
0.4
V
OL
OUT
I
V
V
= V , CS High
= 0V, CS High
●
●
3
–3
µA
µA
OZ
OUT
CC
OUT
I
I
I
Output Source Current
Output Sink Current
V
V
= 0V
–20
20
6
mA
mA
mA
µA
SOURCE
SINK
CC
OUT
= V
OUT
CC
Positive Supply Current
CS High
CS High Power Shutdown CLK Off
●
●
12
10
5
Note 7: Two on-chip diodes are tied to each analog input which will
conduct for analog voltages one diode drop below GND or one diode drop
above V . Be careful during testing at low V levels (4.5V), as high level
analog inputs (5V) can cause this input diode to conduct, especially at
elevated temperature, and cause errors for inputs near full scale. This spec
allows 50mV forward bias of either diode. This means that as long as the
analog input does not exceed the supply voltage by more than 50mV, the
output code will be correct.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground (unless otherwise
noted).
CC
CC
Note 3: V = 5V, CLK = 1.0MHz unless otherwise specified.
CC
Note 4: One LSB is equal to V divided by 4096. For example, when V
=
CC
CC
5V, 1LSB = 5V/4096 = 1.22mV.
Note 5: Linearity error is specified between the actual end points of the
A/D transfer curve. The deviation is measured from the center of the
quantization band.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: Increased leakage currents at elevated temperatures cause the
S/H to droop, therefore it is recommended that f
CLK
≥ 125kHz at 125°C,
CLK
Note 6: Recommended operating conditions.
f
≥ 30kHz at 85°C and f
≥ 3kHz at 25°C.
CLK
1291fa
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LTC1291
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Change in Offset vs Supply
Voltage
Supply Current vs Temperature
Supply Current vs Supply Voltage
10
8
10
0.5
0.4
0.3
0.2
CLK = 1MHz
CLK = 1MHz
T
= 25°C
V
CC
= 5V
A
9
8
7
6
5
4
3
6
0.1
0
4
–0.1
–0.2
2
–0.3
–0.4
–0.5
0
5
50
90
130
4
–50
–30 –10 10 30
6
70
110
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1291 G01
1291 G02
1291 G03
Change in Linearity vs Supply
Voltage
Change in Gain Error vs Supply
Voltage
Change in Offset vs Temperature
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
V
CC
= 5V
CLK = 1MHz
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
6.0
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
6.0
–50
0
25
50
75 100 125
–25
AMBIENT TEMPERATURE (°C)
1291 G04
1291 G05
1291 G06
Change in Linearity vs
Temperature
Minimum Clock Rate for
0.1 LSB Error
Change in Gain vs Temperature
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
V
CC
= 5V
V
CC
= 5V
V
CC
= 5V
CLK = 1MHz
CLK = 1MHz
0.25
0.20
0.15
0.10
0.05
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
–25
–50
0
25
50
75
–25
100 125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
1291 G07
1291 G08
1291 G09
* AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE
FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED
1291fa
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LTC1291
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Filter Resistor vs
Cycle Time
Maximum Clock Rate vs Source
DOUT Delay Time vs Temperature
Resistance
250
200
150
100
50
1.0
0.8
10k
1k
V
= 5V
CC
V
= 5V
CC
CLK = 1MHz
R
FILTER
+V
IN
FILTER
+
–
C
≥1µF
+V
IN
+
+IN
MSB-FIRST DATA
0.6
0.4
0.2
0
R
–
SOURCE
–IN
–
100
10
1
LSB-FIRST DATA
0
–50
0
25
50
75
100
1k
R
10k
– (Ω)
100k
–25
100 125
10
100
CYCLE TIME (µs)
10k
1k
SOURCE
AMBIENT TEMPERATURE (°C)
1291 G11
1291 G10
1291 G12
Sample-and-Hold Acquisition
Time vs Source Resistance
Input Channel Leakage Current
vs Temperature
1000
900
800
700
600
500
400
300
200
100
0
100
V
A
= 5V
CC
GUARANTEED
T
= 25°C
0V TO 5V INPUT STEP
R
+
SOURCE
* MAXIMUM CLK FREQUENCY REPRESENTS THE CLK
FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE
ERROR AT ANY CODE TRANSITION FROM ITS 1MHz
VALUE IS FIRST DETECTED
V
IN
+
–
10
**MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR
VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE
ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST
DETECTED
ON CHANNEL
OFF CHANNEL
1
–50 –30 –10 10 30 50 70 90 110 130
1k
10k
100
AMBIENT TEMPERATURE (°C)
R
+ (Ω)
SOURCE
1291 G14
1291 G13
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PI FU CTIO S
DOUT (Pin 6): Digital Data Output. The A/D conversion
CS (Pin 1): Chip Select Input. A logic low on this input
result is shifted out of this output.
enables the LTC1291.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
VCC(VREF)(Pin8):PositiveSupplyandReferenceVoltage.
This pin provides power and defines the span of the A/D
converter. This supply must be kept free of noise and
ripple by bypassing directly to the analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
DIN (Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.
1291fa
5
LTC1291
W
BLOCK DIAGRA
7
6
CLK
D
8
V
(V
)
CC REF
INPUT
SHIFT
REGISTER
OUTPUT
SHIFT
REGISTER
5
OUT
D
IN
2
CH0
CH1
SAMPLE
AND
HOLD
ANALOG
INPUT MUX
3
COMP
12-BIT
SAR
12-BIT
CAPACITIVE
DAC
CONTROL
AND
TIMING
1
4
CS
GND
1291 BD
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Load Circuit for tdis and ten
1.4V
TEST POINT
3k
5V t WAVEFORM 2, t
dis
en
3k
D
TEST POINT
D
OUT
OUT
t
WAVEFORM 1
dis
100pF
100pF
1291 TC02
1291 TC05
On and Off Channel Leakage Current
Voltage Waveforms for tdis
2.0V
CS
5V
I
ON
A
D
OUT
90%
ON CHANNEL
OFF CHANNEL
WAVEFORM 1
(SEE NOTE 1)
I
OFF
t
dis
A
D
OUT
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1291 TC06
POLARITY
1291 TC01
1291fa
6
LTC1291
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
CLK
2.4V
0.4V
0.8V
t
D
OUT
dDO
2.4V
0.4V
t
r
t
1291 TC04
D
OUT
f
1291 TC03
Voltage Waveforms for ten
CS
D
START
IN
CLK
2
1
3
4
5
D
OUT
B11
0.8V
1291 TC07
t
en
O U
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PPLICATI
S
I FOR ATIO
A
The LTC1291 is a data acquisition component which
contains the following functional blocks:
being transmitted on the falling CLK edge and captured on
the rising CLK edge in both transmitting and receiving
systems.
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
CS
D
1
D
2
IN
IN
D
1
D
2
OUT
4. Synchronous, half duplex serial interface
5. Control and timing logic
OUT
SHIFT MUX 1 NULL SHIFT A/D CONVERSION
ADDRESS IN BIT RESULT OUT
1291 F01
DIGITAL CONSIDERATIONS
Serial Interface
Figure 1
TheinputdataisfirstreceivedandthentheA/Dconversion
result is transmitted (half duplex). Because of the half
duplex operation DIN and DOUT may be tied together
allowing transmission over just 3 wires: CS, CLK and
The LTC1291 communicates with microprocessors and
other external circuitry via a synchronous, half duplex,
4-wire serial interface (see Operating Sequence). The
clock (CLK) synchronizes the data transfer with each bit
1291fa
7
LTC1291
PPLICATI
DATA(DIN/DOUT). Datatransferisinitiatedbyafallingchip
select (CS) signal. After CS falls, the LTC1291 looks for a
start bit. After the start bit is received, a 4-bit input word
is shifted into the DIN input which configures the LTC1291
and starts the conversion. After one null bit, the result of
O U
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A
S I FOR ATIO
the conversion appears MSB-first on the DOUT line. The
conversion result is output, bit by bit, as the conversion is
performed. At the end of the data exchange, CS should be
brought high. This resets the LTC1291 in preparation for
the next data exchange.
Operating Sequence
+
–
(Example: Differential Inputs (CH0 , CH1 ))
MSB-FIRST DATA (MSBF = 1)
t
CYC
CS
DON'T
CARE
CLK
ODD/
SIGN
START
PS
D
DON'T CARE
B1 B0
IN
MSBF
SGL/
DIFF
HI-Z
B11
D
OUT
FILLED WITH ZEROES
t
t
SMPL
CONV
LSB-FIRST DATA (MSBF = 0)
t
CYC
CS
DON’T
CARE
CLK
START
ODD/
SIGN
PS
DON'T CARE
D
IN
MSBF
SGL/
DIFF
HI-Z
B11
B11
B0
B1
B1
D
OUT
t
t
SMPL
CONV
FILLED WITH
ZEROES
1291 AI03
Power Shutdown Operating Sequence
+
–
(Example: Differential Inputs (CH0 , CH1 ) and MSB-First Data)
SHUTDOWN*
NEW CONVERSION BEGINS
CS
REQUEST POWER SHUTDOWN
CLK
ODD/
SIGN
START
START
PS
ODD/
SIGN
PS
D
DON'T CARE
IN
MSBF
MSBF
SGL/
DIFF
SGL/
DIFF
HI-Z
HI-Z
B0
FILLED WITH
ZEROES
B11
DATA NOT VALID
D
OUT
1291 AI04
* STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION
CS CAN BE BROUGHT HIGH ONCE D HAS BEEN CLOCKED IN
IN
1291fa
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LTC1291
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W
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PPLICATI
S I FOR ATIO
A
Multiplexer Channel Selection
MUX ADDRESS CHANNEL #
SGL/DIFF ODD/SIGN
Input Data Word
The4-bitdatawordisclockedintotheDIN pinontherising
edge of the clock after chip select goes low and the start
bit has been recognized. Further inputs on the DIN pin are
then ignored until the next CS cycle. The input word is
defined as follows:
0
1
GND
–
–
1
1
0
0
0
1
0
1
+
+
–
+
+
–
MSB-FIRST/
LSB-FIRST
MSB-First/LSB-First (MSBF)
SGL/
DIFF
ODD/
SIGN
MSBF
START
PS
The output data of the LTC1291 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. When the
MSBF bit is a logical one, data will appear on the DOUT line
in MSB-first format. Logical zeroes will be filled in indefi-
nitely following the last data bit to accommodate longer
word lengths required by some microprocessors. When
the MSBF bit is a logical zero, LSB-first data will follow the
normal MSB-first data on the DOUT line (see Operating
Sequence).
POWER
SHUTDOWN
1291 F02
MUX ADDRESS
Figure 2. Input Data Word
Start Bit
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer and all leading zeroes which precede this logical
one will be ignored. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the DIN pin are then ignored until the next CS
cycle.
Power Shutdown
The power shutdown feature of the LTC1291 is activated
by making the PS bit a logical zero. If CS remains low after
the PS bit has been received, a 12-bit DOUT word with all
logical ones will be shifted out followed by logical zeroes
until CS goes high. Then the DOUT line will go into its high
impedance state. The LTC1291 will remain in the shut-
down mode until the next CS cycle. There is no warm-up
or wait period required after coming out of the power
shutdown cycle so a conversion can commence after CS
goes low (see Power Shutdown Operating Sequence).
MUX Address
The bits of the input word following the START BIT assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND. Only the “+” inputs have sample-and-
holds. Signals applied at the “–” inputs must not change
more than the required accuracy during the conversion.
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Output Code
The LTC1291 performs a unipolar conversion. The follow-
ing shows the output code and transfer curve:
Unipolar Transfer Curve
Unipolar Output Code
1 1 1 1 1 1 1 1 1 1 1 1
INPUT VOLTAGE
(V = 5V)
1 1 1 1 1 1 1 1 1 1 1 0
OUTPUT CODE
INPUT VOLTAGE
REF
•
•
•
4.9988V
1 1 1 1 1 1 1 1 1 1 1 1
V
REF
V
REF
– 1LSB
4.9976V
1 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
•
V
IN
0.0012V
0V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
1291 AI05a
1291 AI05b
Microprocessor Interfaces
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1291**
TheLTC1291caninterfacedirectly(withoutexternalhard-
ware)tomostpopularmicroprocessors’s(MPU)synchro-
nous serial formats (see Table 1). If an MPU without a
dedicated serial port is used, then three of the MPU’s
parallel port lines can be programmed to form the serial
link to the LTC1291. Included here are one serial interface
example and one example showing a parallel port pro-
grammed to form the serial interface.
PART NUMBER
TYPE OF INTERFACE
Motorola
MC6805S2, S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
SPI
Hitachi
HD6305
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
Motorola SPI (MC68HC11)
TheMC68HC11hasbeenchosenasanexampleofanMPU
with a dedicated serial port. This MPU transfers data MSB
-firstandin8-bitincrements. TheDIN wordsenttothedata
register starts the SPI process. With three 8-bit transfers,
the A/D result is read into the MPU. The second 8-bit
transfer clocks B11 through B8 of the A/D conversion
resultintotheprocessor.Thethird8-bittransferclocksthe
remaining bits, B7 through B0, into the MPU. The data is
right justified in the two memory locations. ANDing the
second byte with 0DHEX clears the four most significant
bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
National Semiconductor
COP400 Family
COP800 Family
NS8050U
†
MICROWIRE
†
MCROWIRE/PLUS
MICROWIRE/PLUS
MICROWIRE/PLUS
HPC16000 Family
Texas Instruments
TMS7002
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
SPI
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020*
TMS370C050
* Requires external hardware
** Contact LTC marketing for interface information for processors not on
this list
†
MICROWIRE and MICROWIRE/PLUS are trademarks of National
Semiconductor Corporation.
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Timing Diagram for Interface to the MC68HC11
CS
CLK
SGL/
DIFF
ODD/
EVEN
DON'T CARE
MSBF PS
D
IN
START
D
OUT
B11 B10
B9
X
B8
X
B7
B6
X
B5
B4
X
B3
X
B2
X
B1
X
B0
X
MPU
TRANSMIT
WORD
ODD/
SGL/
DIFF
0
?
0
?
0
?
0
0
0
?
1
?
MSBF
?
PS
?
X
X
X
X
X
EVEN
BYTE 2
BYTE 1
BYTE 3 (DUMMY)
MPU
RECEIVED
WORD
?
?
?
?
0
B11 B10
B9
B8
B7
B6
B5
B3
BYTE 3
B2
B1
B4
B0
BYTE 2
BYTE 1
LTC1291 AI06
Hardware and Software Interface to Motorola MC68HC11
D
FROM LTC1291 STORED IN MC68HC11 RAM
OUT
MSB
CH0
D0
SCK
CS
0
0
B11
B3
B9
B1
B8
B0
BYTE 1
BYTE 2
#62
#63
0
0
B10
B2
CLK
ANALOG
INPUTS
LTC1291
MC68HC11
LSB
B4
D
OUT
MISO
B7
B6
B5
D
MOSI
CH1
IN
LTC1291 AI07
MC68HC11 CODE
In this example the DIN word configures the input MUX for
a single-ended input to be applied to CH0. The conversion
result is output MSB-first.
LABEL MNEMONIC OPERAND
COMMENTS
LABEL MNEMONIC OPERAND
COMMENTS
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
#$50
$1028
#$1B
$1009
#$03
$50
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $50
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $51
LDAA
#$00
LOAD DUMMY DIN WORD INTO
ACC A
LOAD DUMMY DIN DATA INTO $52
LOAD INDEX REGISTER X WITH
$1000
STAA
LDX
$52
#$1000
LOOP BCLR
LDAA
$08,X,#$01 D0 GOES LOW (CS GOES LOW)
$50
$102A
LOAD DIN INTO ACC A FROM $50
LOAD DIN INTO SPI, START SCK
#$60
$51
STAA
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LABEL MNEMONIC OPERAND
COMMENTS
LABEL MNEMONIC OPERAND
COMMENTS
LDAA
WAIT1 BPL
$1029
WAIT1
$51
$102A
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
LOAD DIN INTO SPI, START SCK
STAA
$102A
LOAD DUMMY DIN INTO SPI,
START SCK
CHECK SPI STATUS REG
WAIT3 LDAA
BPL
$1029
WAIT3
LDAA
STAA
CHECK IF TRANSFER IS DONE
WAIT2 LDAA
BPL
$1029
WAIT2
$102A
$62
CHECK SPI STATUS REG
BSET
LDAA
STAA
$08,X#$01 D0 GOES HIGH (CS GOES HIGH)
CHECK IF TRANSFER IS DONE
LOAD LTC1291 MSBs INTO ACC A
STORE MSBs IN $62
$102A
$63
LOAD LTC1291 LSBs IN ACC
STORE LSBs IN $63
LDAA
STAA
LDAA
$52
LOAD DUMMY DIN INTO ACC A
FROM $52
JMP
LOOP
START NEXT CONVERSION
Interfacing to the Parallel Port of the Intel 8051 Family
This works very well. One can save a line by tying the DIN
and DOUT lines together. The 8051 first sends the start bit
and MUX Address to the LTC1291 over the line connected
toP1.2. ThenP1.2isreconfiguredasaninputandthe8051
reads back the 12-bit A/D result over the same data line.
The Intel 8051 has been chosen to show the interface
between the LTC1291 and parallel port microprocessors.
UsuallythesignalsCS, DIN andCLKaregeneratedonthree
port lines and the DOUT signal is read on a fourth port line.
Timing Diagram for Interface to Intel 8051
PS BIT LATCHED
INTO LTC1291
CS
1
3
2
4
5
CLK
SGL/
DIFF MSBF
ODD/
SIGN
B11 B10 B9 B8 B7 B6
B3 B2 B1 B0
B5 B4
DATA
IN OUT
START
PS
(D /D
)
LTC1291 AI08
8051 P1.2 OUTPUT DATA
TO LTC1291
LTC1291 SENDS A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 RECONFIGURED
AS INPUT AFTER THE 5TH RISING
CLK BEFORE THE 5TH FALLING CLK
LTC1291 TAKES CONTROL OF DATA
LINE ON 5TH FALLING CLK
Hardware and Software Interface to Intel 8051
D
FROM LTC1291 STORED IN 8051 RAM
OUT
MSB
CH0
P1.4
P1.3
CS
B11
B8
B7
0
B5
0
B4
0
B10
B9
B1
B6
0
R2
R1
CLK
ANALOG
INPUTS
LTC1291
8051
LSB
B0
D
OUT
P1.2
B3
B2
D
CH1
IN
LTC1291 AI09
MUX ADDRESS
A/D RESULT
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8051 Code
In this example the input MUX is configured to accept a
differential input between CH0 and CH1. The result from
the conversion is clocked out MSB-first.
LABEL MNEMONIC OPERAND
COMMENTS
CS GOES HIGH
DIN WORD FOR LTC1291
CS GOES LOW
LOAD COUNTER
ROTATE DIN BIT INTO CARRY
CLK GOES LOW
OUTPUT DIN BIT TO LTC1291
CLK GOES HIGH
LABEL MNEMONIC OPERAND
COMMENTS
CLK GOES LOW
CLEAR ACC
ROTATE DATA BIT (B3) INTO ACC
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B2) INTO ACC
CLK GOES HIGH
CLR
CLR
P1.3
A
SETB
CONT MOV
CLR
MOV
LOOP1 RLC
CLR
P1.4
A,#98H
P1.4
R4,#05H
A
P1.3
RLC
MOV
RLC
A
C,P1.2
A
SETB
CLR
MOV
P1.3
P1.3
C,P1.2
A
CLK GOES LOW
MOV
SETB
P1.2,C
P1.3
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B1) INTO ACC
CLK GOES HIGH
CLK GOES LOW
READ DATA BIT INTO CARRY
CS GOES HIGH
ROTATE DATA BIT (B0) INTO ACC
ROTAGE RIGHT INTO ACC
ROTAGE RIGHT INTO ACC
ROTAGE RIGHT INTO ACC
STORE LSBs IN R3
RLC
DJNZ
MOV
CLR
R4,LOOP1 NEXT DIN BIT
P1,#04H
P1.3
SETB
CLR
P1.3
P1.3
C,P1.2
P1.4
A
A
A
P1.2 BECOMES AN INPUT
CLK GOES LOW
LOAD COUNTER
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B3) INTO ACC
CLK GOES HIGH
CLK GOES LOW
NEXT DOUT BIT
MOV
SETB
RRC
RRC
RRC
RRC
MOV
AJMP
MOV
LOOP MOV
RLC
R4,#09H
C,P1.2
A
SETB
CLR
P1.3
P1.3
A
DJNZ
MOV
R4,LOOP
R2,A
R3,A
CONT
STORE MSBS IN R2
READ DATA BIT INTO CARRY
CLK GOES HIGH
START NEXT CONVERSION
MOV
SETB
C,P1.2
P1.3
Sharing the Serial Interface
(Figure 3). The CS signals decide which LTC1291 is being
addressed by MPU.
The LTC1291 can share the same 3-wire serial interface
with other peripheral components or other LTC1291s
2
1
0
OUTPUT PORT
SERIAL DATA
3-WIRE SERIAL
3
INTERFACE TO OTHER
3
3
3
PERIPHERALS OR LTC1291s
MPU
CS
LTC1291
CS
LTC1291
CS
LTC1291
2 CHANNELS
2 CHANNELS
2 CHANNELS
LTC1291 F03
Figure 3. Several LTC1291s Sharing One 3-Wire Serial Interface
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ANALOG CONSIDERATIONS
Grounding
The LTC1291 should be used with an analog ground plane
and single point grounding techniques. Do not use wire
wrappingtechniquestobreadboardandevaluatethedevice.
Toachievetheoptimumperformance,useaPCboard.The
ground pin (Pin 4) should be tied directly to the ground
plane with minimum lead length. Figure 4 shows an
exampleofanidealLTC1291groundplaneforatwo-sided
board. Of course this much ground plane will not always
be possible, but users should strive to get as close to this
ideal as possible.
HORIZONTAL: 10µs/DIV
Figure 5. Poor VCC Bypassing. Noise and
Ripple Can Cause A/D Errors
22µF
TANTALUM
V
CC
CS
0.1µF
1
8
7
6
5
VCC
2
3
4
LTC1291
ANALOG GROUND
PLANE
HORIZONTAL: 10µs/DIV
LTC1291 F04
Figure 6. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
Figure 4. Example Ground Plane for the LTC1291
Analog Inputs
Bypassing
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1291 have
capacitive switching input current spikes. These current
spikes settle quickly and do not cause a problem. If large
source resistances are used or if slow settling op amps
drive the inputs, take care to insure the transients caused
by the current spikes settle completely before the
conversion begins.
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
ground during the conversion cycle can induce error or
noise in the output code. VCC noise and ripple can be kept
below 0.5mV by bypassing the VCC pin directly to the
analog ground plane with a minimum of 22µF tantalum
capacitor and with leads as short as possible. A 0.1µF
ceramic disk capacitor should also be placed directly
across VCC (Pin 8) and GND (Pin 4) as close to the pins as
possible. The VCC supply should have a low output
impedance such as that obtained from a voltage regulator
(e.g., LT323A). Figures 5 and 6 show the effects of good
and poor VCC bypassing.
Minimizing Gain and Offset Error
Because the LTC1291’s reference is taken from the power
supply pin (VCC), proper PC board layout and supply
bypassing is important for attaining the best performance
from the A/D converter. Any parasitic resistance in the VCC
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orGNDleadwillcausegainerrorsandoffseterrors(Figure
7). For the best performance the LTC1291 should be
soldered directly to the PC board. If the source can not be
placed next to the pin and the gain parameter is important,
the pin should be Kelvin-sensed to eliminate parasitic
resistances due to long PC traces. For example, 0.1Ω of
resistance in the VCC lead can typically cause 0.5LSB
(ICC • 0.1Ω/VCC) of gain error for VCC = 5V.
and capacitances will slow the settling of the inputs. It is
important that the overall RC time constant is short
enough to allow the analog inputs to settle completely
within the allowed time.
“+” Input Settling
The input capacitor is switched onto the “+” input during
thesamplephase(tSMPL, seeFigure9). Thesampleperiod
is 2.5 CLK cycles before a conversion starts. The voltage
on the “+” input must settle completely within the sample
period. Minimizing RSOURCE+ and C1 will improve the
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
CLK frequency. With the minimum possible sample time
of 2.5µs, RSOURCE+ < 1.0k and C1 < 20pF will provide
adequate settle time.
When the input MUX is selected for single-ended input the
minus terminal is connected to GND internally on the die.
Any parasitic resistance from the GND pin to the ground
plane will lead to an offset voltage (ICC • RP2).
R
P1
LTC1291
V
CC
5V
“–” Input Settling
+
–
–
+
REF
REF
D/A
Attheendofthesamplephasetheinputcapacitorswitches
to the “–” input and the conversion starts (see Figure 9).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. It is critical that the “–” input voltage be
free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing RSOURCE– and C2 will
improve settling time. If large “–” input source resistance
must be used, the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 1MHz,
R
P2
GND
LTC1291 F07
Figure 7. Parasitic Resistance in the VCC and GND Leads
Source Resistance
RSOURCE– < 250
settling.
Ωand C2 < 20pF will provide adequate
The analog inputs of the LTC1291 look like a 100pF
capacitor (CIN) in series with a 500Ω resistor (RON). CIN
gets switched between “+” and “–” inputs once during
each conversion cycle. Large external source resistors
Input Op Amps
When driving the analog inputs with an op amp, it is
important that the op amp settles within the allowed time
(see Figure 9). Again the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps including the LT1006 and
LT1013 single supply op amps can be made to settle well
even with the minimum settling windows of 2.5µs (“+”
input) and 1µs (“–” input) that occurs at the maximum
clock rate of 1MHz. Figures 10 and 11 show examples
adequate and poor op amp settling.
“+”
INPUT
R
+
SOURCE
LTC1291
= 500Ω
V
+
–
IN
3RD CLK↑
C1
R
ON
“–”
INPUT
C
=
IN
100pF
5TH CLK↓
R
–
SOURCE
V
IN
C2
LTC1291 F08
Figure 8. Analog Input Equivalent Circuit
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HOLD
SAMPLE
CS
CLK
SGL/
ODD/
SIGN
D
IN
MSBF
PS
START
DIFF
t
SMPL
“+” INPUT MUST SETTLE DURING THIS TIME
D
OUT
B11
HI-Z
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
LTC1291 F09
Figure 9. “+” and “–” Input Settling Windows
HORIZONTAL: 500ns/DIV
HORIZONTAL: 20µs/DIV
Figure 10. Adequate Settling of Op Amp Driving Analog Input
Figure 11. Poor Op Amp Settling Can Cause A/D Errors
(Note Horizontal Scale)
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RC Input Filtering
allowstheLTC1291toconvertrapidlyvaryingsignals(see
typicalperformancecharacteristicscurveofS/HAcquisition
Time vs Source Resistance). The input voltage is sampled
during the tSMPL time as shown in Figure 9. The sampling
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling edge of the PS bit is
received. On this falling edge, the S/H goes into the hold
mode and the conversion begins.
It is possible to filter the inputs with an RC network as
shown in Figure 12. For large values of CF (e.g., 1µF) the
capacitive input switching currents are averaged into a net
DC current. A filter should be chosen with a small resistor
and a large capacitor to prevent DC drops across the
resistor.ThemagnitudeoftheDCcurrentisapproximately
I
DC = 100pF • VIN/tCYC and is roughly proportional to VIN.
When running at the minimum cycle time of 18.5µs, the
input current equals 27µA at VIN = 5V. Here a filter resistor
of4.5Ωwillcause0.1LSBoffull-scaleerror. Ifalargefilter
resistormustbeused,errorscanbereducedbyincreasing
the cycle time as shown in the Typical Performance
Characteristics curve Maximum Filter Resistor vs Cycle
Time.
Differential Input
WithadifferentialinputtheA/Dnolongerconvertsasingle
voltage but converts the difference between two voltages.
The voltage on the +IN pin is sampled and held and can be
rapidly time varying. The voltage on the –IN pin must
remainconstantandbefreeofnoiseandripplethroughout
the conversion time. Otherwise the differencing operation
will not be done accurately. The conversion time is 12 CLK
cycles. Therefore a change in the –IN input voltage during
this interval can cause conversion errors. For a sinusoidal
voltage on the –IN input this error would be:
I
DC
R
FILTER
V
–
“+”
LTC1291
“–”
IN
C
FILTER
12
fCLK
VERROR(MAX) = 2π f(−IN)VPEAK
(
)
LTC1291 F12
Figure 12. RC Input Filtering
Where f(–IN) is the frequency of the –IN input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
CLK. Usually VERROR will not be significant. For a 60Hz
signal on the –IN input to generate a 0.25LSB error
(300µV) with the converter running at CLK = 1MHz, its
peakvaluewouldhavetobe66mV. Rearrangingtheabove
equation, the maximum sinusoidal signal that can be
digitized to a given accuracy is given as:
Input Leakage Current
Input leakage currents also can create errors if the source
resistancegetstoolarge.Forexample,themaximuminput
leakage specification of 1µA (at 125°C) flowing through a
source resistance of 1k will cause a voltage drop of 1mV
or 0.8LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
performance characteristics curve Input Channel Leakage
Current vs Temperature).
VERROR(MAX)
fCLK
12
f(−IN)
=
2 V
π
PEAK
For 0.25LSB error (300µV), the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
SAMPLE-AND-HOLD
Single-Ended Input
The LTC1291 provides a built-in sample-and-hold (S/H)
functiononthe+INinputforsignalsacquiredinthesingle-
ended mode (–IN pin grounded). The sample-and-hold
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1N4148 DIODES
Overvoltage Protection
Applying signals to the LTC1291’s analog inputs that
exceed the positive supply or that go below ground will
degrade the accuracy of the A/D and possibly damage the
device. For example, this condition will occur if a signal is
applied to the analog inputs before power is applied to the
LTC1291. It can also happen if the input source is operat-
ingfromsuppliesoflargervaluethantheLTC1291supply.
These conditions should be prevented either with proper
supply sequencing or by use of external circuitry to clamp,
or current limit the input source.
5V
CS
V
(V )
CC REF
CH0
CH1
GND
CLK
LTC1291
D
OUT
D
IN
LTC1291 F13
Figure 13. Overvoltage Protection for Inputs
There are two ways to protect the inputs. In Figure 13
diode clamps from the inputs to VCC and GND are used.
The second method is to put resistors in series with the
analog inputs for current limiting. Limit the current to
15mA per channel. The +IN input can accept a resistor
value of 1k but the –IN input cannot accept more than
250Ω when clocked at its maximum clock frequency of
1MHz. If the LTC1291 is clocked at the maximum clock
frequency and 250Ω is not enough to current limit the
input source, then the clamp diodes are recommended
(Figures14and15). Thereasonforthelimitontheresistor
value is that the MSB bit test is affected by the value of the
resistor placed at the –IN input (see discussion on Analog
Inputs and the typical performance characteristics Maxi-
mum CLK Rate vs Source Resistance).
5V
CS
V
(V )
CC REF
1k
CH0
CH1
GND
CLK
LTC1291
250Ω
D
OUT
D
IN
LTC1291 F14
Figure 14. Overvoltage Protection for Inputs
1N4148 DIODES
CS
5V
V
(V
CC REF
)
1k
CH0
CH1
CLK
LTC1291
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
D
OUT
GND
D
IN
LTC1291 F15
Figure 15. Overvoltage Protection for Inputs
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A “Quick Look” Circuit for the LTC1291
data is output MSB-first. CS is driven at 1/64, the clock
frequency by the 74HC393 and D
outputs the data.
OUT
Users can get a quick look at the function and timing of
the LTC1291 by using the following simple circuit
The output data from the D
pin can be viewed on a
OUT
oscilloscope that is set up to trigger on the falling edge
of CS (Figure 17).
(Figure 16). D is tied to V . This requires V be
IN
CC
IN
applied to CH1 with respect to the ground plane. The
22µF TANTALUM
5V
f/64
0.1µF
A1
V
CC
CS
V (V
CC REF
)
0.1µF
CLR1
1QA
A2
CLR2
f
CH0
CH1
GND
CLK
LTC1291
1QB 74HC393 2QA
V
D
OUT
IN
1QC
1QD
GND
2QB
2QC
2QD
D
IN
CLOCK IN 1MHz
TO OSCILLOSCOPE
LTC1291 F16
Figure 16. “Quick Look” Circuit for the LTC1291
CLK
CS
DOUT
MSB
(B11)
LSB
(B0)
FILLS WITH
ZEROES
NULL
BIT
VERTICAL: 5V/DIV
HORIZONTAL: 5µs/DIV
Figure 17. Scope Trace of the LTC1291 "Quick Look"
Circuit Showing Output 101010101010 (AAAHEX
)
1291fa
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1291
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.405
(10.287)
MAX
.005
(0.127)
MIN
.200
(5.080)
MAX
.300 BSC
(7.62 BSC)
CORNER LEADS OPTION
(4 PLCS)
6
5
4
8
7
.015 – .060
(0.381 – 1.524)
.023 – .045
.025
(0.635)
RAD TYP
.220 – .310
(5.588 – 7.874)
(0.584 – 1.143)
HALF LEAD
OPTION
.008 – .018
(0.203 – 0.457)
0° – 15°
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
1
2
3
.045 – .065
.125
3.175
MIN
NOTE: LEAD DIMENSIONS APPLY TO
SOLDER DIP/PLATE OR TIN PLATE LEADS
(1.143 – 1.651)
.014 – .026
.100
(2.54)
BSC
(0.360 – 0.660)
J8 0801
OBSOLETE PACKAGE
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
.130 ± .005
.300 – .325
.045 – .065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
8
7
6
5
4
.065
(1.651)
TYP
.255 ± .015*
(6.477 ± 0.381)
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
–.015
1
2
3
.325
.018 ± .003
(0.457 ± 0.076)
.100
(2.54)
BSC
+0.889
8.255
(
)
N8 1002
–0.381
NOTE:
INCHES
MILLIMETERS
1. DIMENSIONS ARE
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1298
12-bit, 2-Channel, Micropower ADC in SO-8
12-bit, 2-Channel, 250ksps ADC in MSOP
16-bit, 2-Channel, 250ksps ADC in MSOP
11.1ksps, Autoshutdown
LTC1861
850µA Supply Current, 2µA at 1ksps
850µA Supply Current, 2µA at 1ksps
LTC1865
1291fa
LT/TP 0703 1K REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
LINEAR TECHNOLOGY CORPORATION 1992
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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