LTC1294BCSW#TRPBF [Linear]
LTC1294 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C;
| 型号： | LTC1294BCSW#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1294 - Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1293/LTC1294/LTC1296
Single Chip 12-Bit
Data Acquisition System
U
DESCRIPTIO
EATURE
Software Programmable Features
Unipolar/Bipolar Conversion
S
F
■
The LTC1293/4/6 is a family of data acquisition systems
which contain a serial I/O successive approximation A/D
converter. It uses LTCMOSTM switched capacitor technol-
ogy to perform either 12-bit unipolar, or 11-bit plus sign
bipolar A/D conversions. The input multiplexer can be
configured for either single ended or differential inputs (or
combinations thereof). An on-chip sample and hold is
included for all single ended input channels. When the
LTC1293/4/6 is idle it can be powered down in applica-
tions where low power consumption is desired. The
LTC1296 includes a System Shutdown Output pin which
can be used to power down external circuitry, such as
signal conditioning circuitry prior to the input mux.
Differential/Single Ended Inputs
MSB-First or MSB/LSB Data Sequence
Power Shutdown
■
■
■
Built-In Sample and Hold
Single Supply 5V or ±5V Operation
Direct 4-Wire Interface to Most MPU Serial
Ports and All MPU Parallel Ports
46.5kHz Maximum Throughput Rate
System Shutdown Output (LTC1296)
■
■
U
KEY SPECIFICATIO S
TheserialI/Oisdesignedtocommunicatewithoutexternal
hardware to most MPU serial ports and all MPU parallel
I/O ports allowing up to eight channels of data to be
transmitted over as few as three wires.
■
Resolution: 12 Bits
■
Fast Conversion Time: 12µs Max Over Temp
■
Low Supply Current: 6.0mA
LTCMOSTM is a trademark of Linear Technology Corporation
U
O
TYPICAL APPLICATI
12-Bit Data Acquisition System with Power Shutdown
R
B
5.1k
2N3906
R2
1.2M
74HC04
V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
+5V
+
CC
R1
10k
SSO
CLK
CS
47µF
1/4 LT1014
–
350Ω STRAIN
GAUGE BRIDGE
MPU
D
OUT
R2
1N4148
LTC1296
1.2M
D
IN
+
REF
C2
1µF
–
REF
AGND
THREE ADDITIONAL STRAIN GAUGE INPUTS
CAN BE ACCOMMODATED USING THE OTHER
AMPLIFIERS IN THE LT1014
–
V
LTC1293 TA01
129346fs
1
LTC1293/LTC1294/LTC1296
W W W
U
(Notes 1 and 2)
ABSOLUTE AXI U RATI GS
Supply Voltage (VCC) to GND or V– ......................... 12V
Negative Supply Voltage (V–) ..................... –6V to GND
Voltage
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1293/4/6BC, LTC1293/4/6CC,
LTC1293/4/6DC ....................................... 0°C to 70°C
LTC1296BI, LTC1296CI, LTC1296DI ...–40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
Analog and Reference
Inputs............................ (V–) –0.3V to VCC + 0.3V
Digital Inputs .........................................–0.3V to 12V
Digital Outputs .......................... –0.3V to VCC + 0.3V
W U
/O
(Top Views) Consult factory for Industrial and Military grades.
PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
1
2
3
4
5
6
7
8
16
V
CC
CH0
CH1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CH0
CH1
V
CC
NUMBER
NUMBER
15 CLK
14 CS
CLK
CS
D
CH2
CH2
LTC1293BCSW
LTC1293CCSW
LTC1293DCSW
LTC1293BCN
LTC1293CCN
LTC1293DCN
13
12
11
D
D
V
CH3
CH3
OUT
IN
OUT
CH4
CH4
D
V
IN
CH5
CH5
REF
REF
10 AGND
V–
COM
DGND
COM
DGND
AGND
V–
9
SW PACKAGE, 16-LEAD PLASTIC SO WIDE
JMAX = 110°C, θJA = 150°C/ W
N PACKAGE, 16-LEAD PDIP
TJMAX = 110°C, θJA = 100°C/ W (N)
T
1
2
20 DV
19 AV
CH0
CH1
CC
LTC1294BCN
LTC1294CCN
LTC1294DCN
CC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
20
19
18
DV
AV
CC
3
18 CLK
17 CS
CH2
CC
LTC1294BCSW
LTC1294CCSW
LTC1294DCSW
4
CH3
CLK
5
16
D
OUT
CH4
17 CS
6
15
D
CH5
IN
16
D
OUT
7
14 REF+
13 REF–
12 AGND
11 V–
CH6
15
D
IN
8
CH7
14 REF+
13 REF–
12 AGND
11 V–
9
COM
DGND
10
N PACKAGE, 20-LEAD PDIP
TJMAX = 110°C, θJA = 100°C/ W (N)
DGND 10
SW PACKAGE, 20-LEAD PLASTIC SO WIDE
JMAX = 110°C, θJA = 150°C/ W
J PACKAGE, 20-LEAD CERDIP
LTC1294BCJ
LTC1294CCJ
LTC1294DCJ
T
TJMAX = 150°C, θJA = 80°C/ W (J)
OBSOLETE PACKAGE
Consider the N Package for Alternate Source
1
2
20
V
CC
CH0
CH1
LTC1296BIN
LTC1296CIN
LTC1296DIN
LTC1296BCN
LTC1296CCN
LTC1296DCN
19 SSO
18 CLK
17 CS
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
3
CH2
LTC1296BCSW
LTC1296CCSW
LTC1296DCSW
LTC1296BISW
LTC1296CISW
LTC1296DISW
SSO
CLK
CS
4
CH3
5
16
15
D
CH4
OUT
6
D
IN
CH5
D
14 REF+
13 REF–
12 AGND
11 V–
OUT
7
CH6
D
IN
8
CH7
REF+
REF–
AGND
V–
9
COM
DGND
10
N PACKAGE, 20-LEAD PDIP
TJMAX = 110°C, θJA = 100°C/ W (N)
DGND 10
SW PACKAGE, 20-LEAD PLASTIC SO WIDE
J PACKAGE, 20-LEAD CERDIP
LTC1296BCJ
LTC1296CCJ
LTC1296DCJ
TJMAX = 110°C, θJA = 150°C/ W
TJMAX = 150°C, θJA = 80°C/ W (J)
OBSOLETE PACKAGE
Consider the N Package for Alternate Source
129346fs
2
LTC1293/LTC1294/LTC1296
U
U W
(Note 3)
CO VERTER A D ULTIPLEXER CHARACTERISTICS
LTC1293/4/6D
LTC1293/4/6B
LTC1293/4/6C
MIN TYP MAX
PARAMETER
Offset Error
CONDITIONS
(Note 4)
MIN TYP MAX
MIN TYP MAX
UNITS
LSB
●
●
●
●
±3.0
±0.5
±0.5
12
±3.0
±0.5
±1.0
12
±3.0
±0.75
±4.0
12
Linearity Error (INL)
Gain Error
(Notes 4, 5)
(Note 4)
LSB
LSB
Minimum Resolution for which No
Missing Codes are Guaranteed
Bits
–
Analog and REF Input Range
(Note 7)
(V )–0.05V to V + 0.05V
V
CC
On Channel Leakage Current (Note 8)
On Channel = 5V
Off Channel = 0V
●
●
●
●
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
µA
On Channel = 0V
Off Channel = 5V
µA
µA
µA
Off Channel Lekage Current (Note 8)
On Channel = 5V
Off Channel = 0V
On Channel = 0V
Off Channel = 5V
AC CHARACTERISTICS (Note 3)
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
SYMBOL
PARAMETER
CONDITIONS
= 5V (Note 6)
MIN
TYP
MAX
UNITS
MHz
f
t
t
t
Clock Frequency
Analog Input Sample Time
Conversion Time
Total Cycle Time
V
CC
0.1
1.0
CLK
See Operating Sequence
2.5
12
CLK Cycles
CLK Cycles
Cycles
SMPL
CONV
CYC
See Operating Sequence
See Operating Sequence (Note 6)
21 CLK
+500ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay Time, CLK↓ to D
Data Valid
See Test Circuits
See Test Circuits
See Test Circuits
●
●
●
160
80
300
150
200
ns
dDO
dis
OUT
Delay Time, CS↑ to D
Hi-Z
ns
OUT
Delay Time, CLK↓ to D
Enabled
80
ns
en
OUT
Hold Time, D after CLK↑
V = 5V (Note 6)
CC
50
ns
hDI
IN
Time Output Data Remains Valid After CLK↓
130
65
ns
hDO
f
D
D
Fall Time
See Test Circuits
See Test Circuits
●
●
130
50
ns
OUT
Rise Time
25
ns
r
OUT
CLK High Time
CLK Low Time
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5V (Note 6)
= 5V (Note 6)
= 5V (Note 6)
= 5V (Note 6)
= 5V (Note 6)
= 5V (Note 6)
300
400
50
ns
WHCLK
WLCLK
suDI
suCS
wHCS
wLCS
enSSO
disSSO
ns
Set-up Time, D Stable Before CLK↑
ns
IN
Set-up Time, CS↓ before CLK↑
CS High Time During Conversion
CS Low Time During Data Transfer
Delay Time, CLK↓ to SSO↓
Delay Time, CS↓ to SSO↑
Input Capacitance
50
ns
500
21
ns
CLK Cycles
See Test Circuits
See Test Circuits
●
●
750
250
1500
500
ns
ns
pF
C
Analog Inputs On Channel
Analog Inputs Off Channel
Digital Inputs
100
5
5
IN
129346fs
3
LTC1293/LTC1294/LTC1296
U
(Note 3)
D
A
ELECTRICAL CHARACTERISTICS
DC
DIGITAL
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.0
V
IH
CC
CC
IN
0.8
2.5
V
µA
µA
V
IL
I
I
= V
CC
IH
IL
= 0V
–2.5
IN
V
= 4.75V, I = –10mA
4.7
4.0
OH
CC
O
I
= 360µA
●
●
2.4
O
V
Low Level Output Voltage
High Z Output Leakage
V
= 4.75V, I = 1.6mA
0.4
V
OL
CC
O
I
V
V
V , CS High
OUT = CC
●
●
3
–3
µA
OZ
= 0V, CS High
OUT
OUT
OUT
I
I
I
I
Output Source Current
Output Sink Current
V
V
= 0V
–20
20
6
mA
mA
mA
µA
SOURCE
SINK
CC
= V
CC
Positive Supply Current
Positive Supply Current
CS High
●
●
12
10
CS High,
Power
Shutdown
LTC1294BC, LTC1294CC,
LTC1294DC, LTC1294BI,
LTC1294CI, LTC1294DI,
5
CC
CLK Off
LTC1294BM, LTC1294CM,
LTC1294DM
●
5
15
µA
I
I
I
I
Reference Current
CS High
CS High
●
●
●
●
10
1
50
50
µA
µA
REF
–
Negative Supply Current
SSO Source Current
SSO Sink Current
V
V
= 0V
0.8
0.5
1.5
1.0
mA
mA
SOURCEs
SINKs
SSO
SSO
= V
CC
Note 6: Recommended operating conditions.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to DGND, AGND and REF wired
together (unless otherwise noted).
Note 7: Two on-chip diodes are tied to each reference and analog input
–
which will conduct for reference or analog input voltages one diode drop
–
below V or one diode drop above V . Be careful during testing at low
CC
–
V
levels (4.5V), as high level reference or analog inputs (5V) can cause
CC
Note 3: V = 5V, V
+ = 5V, V
–
= 0V, V = 0V for unipolar mode and
CC
REF
REF
this input diode to conduct, especially at elevated temperatures, and cause
errors for inputs near full scale. This spec allows 50mV forward bias of
either diode. This means that as long as the reference or analog input
does not exceed the supply voltage by more than 50mV, the output code
will be correct. To achieve an absolute 0V to 5V input voltage range will
therefore require a minimum supply voltage of 4.950V over initial
tolerance, temperature variations and loading.
–5V for bipolar mode, CLK = 1.0MHz unless otherwise specified. The
denotes specifications which apply over the full operating temperature
●
range; all other limits and typicals T = 25°C.
A
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
mode, one LSB is equal to the bipolar input span (2V ) divided by 4096.
REF
For example, when V = 5V, 1LSB (bipolar) = 2 (5V)/4096 = 2.44mV.
REF
Note 5: Linearity error is specified between the actual end points of the A/
D transfer curve. The deviation is measured from the center of the
quantization band.
Note 8: Channel leakage current is measured after the channel selection.
129346fs
4
LTC1293/LTC1294/LTC1296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Unadjusted Offset Voltage vs
Reference Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
10
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
10
8
V
= 5V
CC
CLK = 1MHz
CLK = 1MHz
T
= 25°C
V
CC
= 5V
A
9
8
7
6
5
4
3
6
4
V
OS
= 0.250mV
2
V
= 0.125mV
2
OS
0
3
1
4
5
50
90
130
110
–50 –30 –10 10
5
30
70
4
6
REFERENCE VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
LTC1293 G03
LTC1293 G02
LTC1293 G01
Change in Gain vs Reference
Voltage
Change in Linearity vs Reference
Voltage
Change in Offset vs Temperature
1.25
1.00
0.75
0.50
0.25
0
0
0.5
0.4
V
= 5V
V
V
= 5V
REF
CLK = 1MHz
CC
CC
= 5V
–0.2
–0.4
–0.6
LTC1294/6
0.3
0.2
0.1
0
–0.8
–1.0
–1.2
LTC1293
1
0
1
2
3
4
5
0
2
3
4
–50
25
50
75
5
0
–25
100 125
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
LTC1293 G04
LTC1293 G05
LTC1293 G06
Minimum Clock Rate for 0.1LSB
Error
Change in Linearity vs
Temperature
Change in Gain vs Temperature
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
V
V
= 5V
= 5V
V
V
= 5V
= 5V
V
CC
= 5V
CC
REF
CLK = 1MHz
CC
REF
CLK = 1MHz
0.25
0.20
0.3
0.2
0.1
0
0.15
0.10
0.05
–50
0
25
50
75
–50
0
25
50
75
–25
100 125
–25
100 125
–50
0
25
50
75
–25
100 125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
LTC1293 G07
LTC1293 G08
LTC1293 G09
* AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS
THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED.
129346fs
5
LTC1293/LTC1294/LTC1296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Clock Rate vs Source
Resistance
Maximum Filter Resistor vs Cycle
Time
DOUT Delay Time vs Temperature
10k
1k
1.0
0.8
250
200
150
100
50
V
V
= 5V
REF
CLK = 1MHz
CC
V
= 5V
CC
= 5V
R
FILTER
+V
IN
+
–
C
≥1µF
FILTER
+V
+
+IN
IN
MSB FIRST DATA
0.6
0.4
0.2
0
R
–
SOURCE
–IN
–
100
10
1
LSB FIRST DATA
0
100
1k
R
10k
– (Ω)
100k
–50
0
25
50
75
10
100
CYCLE TIME (µs)
10k
–25
100 125
1k
SOURCE
AMBIENT TEMPERATURE (°C)
LTC1293 G12
LTC1293 G11
LTC1293 G10
Input Channel leakage Current vs
Temperature
Sample and Hold Acquisition
Time vs Source Resistance
Noise Error vs Reference Voltage
100
1000
900
800
700
600
500
400
300
200
100
0
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
V
V
A
= 5V
CC
= 25°C
LTC1293/4/6 NOISE = 200µV
p-p
REF
= 5V
GUARANTEED
T
0V TO 5V INPUT STEP
R
+
SOURCE
V
IN
+
–
10
ON CHANNEL
OFF CHANNEL
1
0
1000
+ (Ω)
10000
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE (°C)
100
0
4
5
1
2
3
R
REFERENCE VOLTAGE (V)
SOURCE
LTC1292 G13
LTC1293 G14
LTC1293 G15
LTC1296 SSO Source Current vs
VCC – VSSO
LTC1296 SSO Sink Current vs
VSSO
*
MAXIMUM CLK FREQUENCY REPRESENTS THE CLK
FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR
AT ANY CODE TRANSITION FROM ITS 1MHz VALUE IS
FIRST DETECTED.
500
400
300
200
100
0
500
V
= 5V
V
= 5V
CC
CC
400
300
** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR
VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR
FROM ITS VALUE AT RFILTER = 0Ω IS FIRST DETECTED.
200
100
0
0
0.2 0.3 0.4
0.5
0
0.2
0.6
0.8
0.1
0.6 0.7
0.4
1.0
V
– V VOLTAGE (V)
SSO
V
VOLTAGE (V)
CC
SSO
LTC1293 G17
LTC1293 G16
129346fs
6
LTC1293/LTC1294/LTC1296
U
U
U
PI FU CTIO S
LTC1293
#
PIN
FUNCTION
DESCRIPTION
1 – 6 CH0 – CH5
Analog Inputs
Common
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
7
COM
8
9
DGND
V
AGND
Digital Ground
Negative Supply
Analog Ground
Ref. Input
This is the ground for the internal logic. Tie to the ground plane.
Tie V to most negative potential in the circuit (Ground in single supply applications).
AGND should be tied directly to the analog ground plane.
The reference inputs must be kept free of noise with respect to AGND.
The A/D configuration word is shifted into this input.
–
–
10
11
12
13
14
15
16
V
REF
D
D
Data Input
IN
Digital Data Output The A/D conversion result is shifted out of this output.
Chip Select Input
Clock
OUT
CS
CLK
A logic low on this input enables data transfer.
This clock synchronizes the serial data transfer and controls A/D conversion rate.
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
V
CC
Positive supply
LTC1294
#
PIN
FUNCTION
DESCRIPTION
1 –8
9
CH0 – CH7
COM
Analog Inputs
Common
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
10
11
12
DGND
V
Digital Ground
Negative Supply
Analog Ground
Ref. Inputs
This is the ground for the internal logic. Tie to the ground plane.
Tie V to most negative potential in the circuit (Ground in single supply applications).
AGND should be tied directly to the analog ground plane.
–
–
AGND
–
+
13, 14 REF , REF
The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
+
–
to the difference between REF and REF .
15
16
17
18
D
D
CS
Data Input
The A/D configuration word is shifted into this input.
IN
Digital Data Output The A/D conversion result is shifted out of this output.
Chip Select Input
Clock
OUT
A logic low on this input enables data transfer.
CLK
This clock synchronizes the serial data transfer and controls A/D converion rate.
These supplies must be kept free of noise and ripple by bypassing directly to the analog ground plane. AV
CC
19, 20 AV DV
Positive Supplies
CC,
CC
and DV must be tied together.
CC
LTC1296
#
PIN
FUNCTION
DESCRIPTION
1 –8
9
CH0 – CH7
COM
Analog Inputs
Common
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
10
11
12
DGND
V
Digital Ground
Negative Supply
Analog Ground
Ref. Inputs
This is the ground for the internal logic. Tie to the ground plane.
Tie V to most negative potential in the circuit (Ground in single supply applications).
AGND should be tied directly to the analog ground plane.
–
–
AGND
–
+
13, 14 REF , REF
The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
+
–
to the difference between REF and REF .
15
16
17
18
19
D
D
CS
CLK
SSO
Data Input
The A/D configuration word is shifted into this input.
IN
Digital Data Output The A/D conversion result is shifted out of this output.
Chip Select Input
Clock
System Shutdown System Shutdown Output pin will go low when power shutdown is requested.
Output
OUT
A logic low on this input enables data transfer.
This clock synchronizes the serial data transfer and controls A/D conversion rate.
20
V
CC
Positive Supply
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
129346fs
7
LTC1293/LTC1294/LTC1296
W
(Pin numbers refer to LTC1294)
BLOCK DIAGRA
18
16
CLK
D
20
DV
AV
CC
CC
19
INPUT
SHIFT
REGISTER
OUTPUT
SHIFT
REGISTER
15
D
OUT
IN
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SAMPLE
AND
HOLD
COMP
ANALOG
INPUT MUX
12-BIT
SAR
12-BIT
CAPACITIVE
DAC
COM
CONTROL
AND
TIMING
17
CS
10
11
V–
12
14
REF+
13
REF–
AGND
DGND
LTC1293 BD
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Load Circuit for tenSSO and tdisSSO
1.4V
1.4V
3kΩ
3kΩ
D
TEST POINT
TEST POINT
OUT
SSO
LT1296
100pF
100pF
LTC1293 TC08
LTC1293 TC02
On and Off Channel Leakage Current
Load Circuit for tdis and ten
5V
TEST POINT
I
ON
A
ON CHANNEL
5V t WAVEFORM 2, t
dis en
3k
I
OFF
D
OUT
t
dis
WAVEFORM 1
A
100pF
OFF
CHANNELS
LTC1293 TC05
POLARITY
LTC1293 TC1
129346fs
8
LTC1293/LTC1294/LTC1296
TEST CIRCUITS
Voltage Waveforms for ten
CS
D
IN
START
6
8
4
5
7
3
1
2
CLK
0.8V
D
B11
OUT
t
en
LTC1293 TC07
Voltage Waveform for tdisSSO
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
2.4V
CS
D
OUT
0.8V
t
SSO
dis
0.4V
t
t
r
f
2.4V
SSO
LTC1293 TC04
LTC1293 TC10
Voltage Waveform for for tenSSO
Voltage Waveform for tdis
CLK
2.0V
CS
0.8V
t
SSO
en
D
OUT
90%
WAVEFORM 1
(SEE NOTE 1)
SSO
t
dis
0.8V
D
OUT
LTC1293 TC09
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
Voltage Waveform for DOUT Delay Time, tdDO
LTC1293 TC06
CLK
0.8V
t
dDO
2.4V
D
OUT
0.4V
LTC1293 TC03
129346fs
9
LTC1293/LTC1294/LTC1296
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PPLICATI
S I FOR ATIO
A
The LTC 1293/4/6 is a data acquisition component which
contains the following functional blocks:
INPUT DATA WORD
The LTC1293/4/6 seven-bit data word is clocked into the
DIN input on the rising edge of the clock after chip select
goes low and the start bit has been recognized. Further
inputs on the DIN pin are then ignored until the next CS
cycle. The input word is defined as follows:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample and hold (S/H)
4. Synchronous, half duplex serial interface
5. Control and timing logic
UNIPOLAR/
BIPOLAR
POWER
SHUTDOWN
SGL/
DIFF
SELECT
1
SELECT
0
ODD/
SIGN
UNI
MSBF
START
PS
DIGITAL CONSIDERATIONS
Serial Interface
MSB FIRST/
LSB FIRST
MUX ADDRESS
LTC1293 AI02
Start Bit
The LTC1293/4/6 communicates with microprocessors
andotherexternalcircuitryviaasynchronous,halfduplex,
four-wire serial interface (see Operating Sequence). The
clock (CLK) synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured on
the rising CLK edge in both transmitting and receiving
systems. The input data is first received and then the A/D
conversion result is transmitted (half duplex). Because of
The first "logical one" clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer and all leading zeroes which precede this logical
one will be ignored. After the start bit is received the
remaining bits of the input word will be clocked in. Further
inputs on the DIN pin are then ignored until the next CS
cycle.
CS
D
1
D
IN
2
IN
D
2
D
1
OUT
OUT
SHIFT MUX
ADDRESS IN
SHIFT A/D CONVERSION
RESULT OUT
1 NULL
BIT
LTC1293 AI01
MUX Address
the half duplex operation DIN and DOUT may be tied
together allowing transmission over just 3 wired: CS, CLK
and DATA (DIN/DOUT). Data transfer is initiated by a falling
chip select (CS) signal. After CS falls the LTC1293/4/6
looks for a start bit. After the start bit is received a 7-bit
input word is shifted into the DIN input which configures
the LTC1293/4/6 and starts the conversion. After one null
bit, the result of the conversion is output on the DOUT line.
With the half duplex serial interface the DOUT data is from
the current conversion. After the end of the data exchange
CS should be brought high. This resets the LTC1293/4/6
in preparation for the next data exchange.
The four bits of the input word following the START BIT
assign the MUX configuration for the requested conver-
sion. For a given channel selection, the converter will
measure the voltage between the two channels indicated
by the + and – signs in the selected row of the following
table. Note that in differential mode (SGL/DIFF = 0) mea-
surements are limited to four adjacent input pairs with
either polarity. In single ended mode, all input channels
are measured with respect to COM. Only the +inputs have
sample and holds. Signals applied at the –inputs must not
change more than the required accuracy during the con-
version.
129346fs
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LTC1293/LTC1294/LTC1296
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Table 1a. LTC1294/6 Multiplexer Channel Selection
DIFFERENTIAL CHANNEL SELECTION
SINGLE-ENDED CHANNEL SELECTION
MUX ADDRESS
MUX ADDRESS
ODD SELECT
SGL/
SGL/ ODD SELECT
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
COM
SIGN
1
0
DIFF
DIFF SIGN
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
+
–
–
–
–
–
–
–
–
+
–
+
+
–
+
+
–
–
+
+
–
+
+
–
+
+
–
+
+
+
Table 1b. LTC1293 Channel Selection
MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION
MUX ADDRESS
SINGLE-ENDED CHANNEL SELECTION
SGL/
ODD SELECT
SGL/ ODD SELECT
0
1
2
3
4
5
0
1
2
3
4
5
COM
DIFF
SIGN
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
DIFF SIGN
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
+
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
+
–
+
+
–
+
+
–
Not Used
+
Not Used
+
–
–
–
–
+
–
+
+
–
+
Not Used
Not Used
Unipolar/Bipolar (UNI)
age. When UNI is a logical zero, a bipolar conversion will
result. The input span and code assignment for each
conversion type are shown in the figures below:
The UNI bit determines whether the conversion will be
unipolar or bipolar. When UNI is a logical one, a unipolar
conversion will be performed on the selected input volt-
Unipolar Output Code (UNI = 1)
Unipolar Transfer Curve (UNI = 1)
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
INPUT VOLTAGE
(VREF = 5V)
OUTPUT CODE
INPUT VOLTAGE
•
•
•
4.9988V
1 1 1 1 1 1 1 1 1 1 1 1
V
REF
V
REF
– 1LSB
4.9976V
1 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
0.0012V
0V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
LTC1293 AI03a
LTC1293 AI03b
129346fs
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LTC1293/LTC1294/LTC1296
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Bipolar Transfer Curve (UNI = 0)
INPUT VOLTAGE
(V = 5V)
INPUT VOLTAGE
(V = 5V)
OUTPUT CODE
INPUT VOLTAGE
OUTPUT CODE
INPUT VOLTAGE
REF
REF
4.9976V
–0.0024V
0 1 1 1 1 1 1 1 1 1 1 1
V
REF
V
REF
– 1LSB
1 1 1 1 1 1 1 1 1 1 1 1
–1LSB
4.9851V
–0.0048V
0 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
1 1 1 1 1 1 1 1 1 1 1 0
–2LSB
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0.0024V
0V
–4.9976V
–5.00000V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
1 0 0 0 0 0 0 0 0 0 0 1 –(V ) + 1LSB
1 0 0 0 0 0 0 0 0 0 0 0
REF
– (V
)
REF
LTC1293 AI04a
Bipolar Output Code (UNI = 0)
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0
LTC1293 AI04b
The following discussion will demonstrate how the two
reference pins are to be used in conjunction with the
analog input multiplexer. In unipolar mode the input span
oftheA/DissetbythedifferenceinvoltageontheREF+ pin
and the REF– pin. In the bipolar mode the input span is
twice the difference in voltage on the REF+ pin and the
REF– pin. In the unipolar mode the lower value of the input
span is set by the voltage on the COM pin for single-ended
inputs and by the voltage on the minus input pin for
differential inputs. For the bipolar mode of operation the
voltage on the COM pin or the minus input pin set the
center of the input span.
INPUT
CONFIGURATION
UNIPOLAR MODE
BIPOLAR MODE
+
–
Single-Ended Lower Value COM
–(REF – REF ) + COM
+
–
+
–
Upper Value (REF – REF ) + COM (REF – REF ) + COM
–
+
–
–
Differential
Lower Value IN
Upper Value (REF – REF ) + IN
–(REF – REF ) + IN
+
–
–
+
–
–
(REF – REF ) + IN
The reference voltages REF+ and REF– can fall between
VCC and V–, but the difference (REF+ –REF–) must be less
than or equal to VCC. The input voltages must be less than
or equal to VCC and greater than or equal to V–. For the
LTC1293 REF– = 0V.
The following examples are for a single-ended input con-
figuration.
Example 1: Let VCC = 5V, V– = 0V, REF+ = 4V, REF– = 1V
and COM = 0V. Unipolar mode of operation. The resulting
input span is 0V ≤ IN+ ≤ 3V.
The upper and lower value of the input span can now be
summarized in the following table:
129346fs
12
LTC1293/LTC1294/LTC1296
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Example 2: The same conditions as Example 1 except
COM = 1V. The resulting input span is 1V ≤ IN+ ≤ 4V. Note
if IN+ ≥ 4V the resulting DOUT word is all 1’s. If IN+ ≤ 1V
then the resulting DOUT word is all 0’s.
Example 3: Let VCC = 5V, V– = –5V, REF+ = 4V, REF– = 1V
and COM = 1V. Bipolar mode of operation. The resulting
input span is –2V ≤ IN+ ≤ 4V.
MSB-First/LSB-First (MSBF)
The output data of the LTC1293/4/6 is programmed for
MSB-first or LSB-first sequence using the MSB bit. When
the MSBF bit is a logical one, data will appear on the DOUT
line in MSB-first format. Logical zeroes will be filled in
indefinitely following the last data bit to accommodate
longer word lengths required by some microprocessors.
When the MSBF bit is a logical zero, LSB first data will
follow the normal MSB first data on the DOUT line. In the
bipolar mode the sign bit will fill in after the MSB bit for
For differential input configurations with the same condi-
tions as in the above three examples the resulting input
spans are as follows:
Example 1 (Diff.): IN– ≤ IN+ ≤ IN– + 3V.
Example 2 (Diff.): IN– ≤ IN+ ≤ IN– + 3V.
Example 3 (Diff.): IN– – 3V ≤ IN+ ≤ IN– + 3V.
MSBF = 0 (see Operating Sequence).
Power Shutdowns (PS)
The power shutdown feature of the LTC1293/4/6 is acti-
vatedbymakingthePSbitalogicalzero. IfCSremainslow
after the PS bit has been received, a 12-bit DOUT word with
Operating Sequence
Example: Differential Inputs (CH4+, CH5–), Unipolar Mode
MSB-FIRST DATA (MSBF = 1)
t
CYC
CS
DON'T
CARE
CLK
START
SEL1
UNI
PS
MSBF
D
IN
DON'T CARE
B1 B0
SGL/
DIFF
SEL0
ODD/
SIGN
B11
HI-Z
FILLED WITH ZEROES
D
OUT
t
t
SMPL
CONV
MSB-FIRST DATA (MSBF = 0)
t
CYC
CS
DON'T
CARE
CLK
START
SEL1
UNI
PS
D
DON'T CARE
B1 B0 B1
IN
SGL/
DIFF
SEL0 MSBF
ODD/
SIGN
B11
B11
FILLED WITH
ZEROES
HI-Z
D
OUT
LTC1293 AI05
t
SMPL
t
CONV
129346fs
13
LTC1293/LTC1294/LTC1296
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I FOR ATIO
Power Shutdown Operating Sequence
Example: Differential Inputs (CH4+, CH5–), Unipolar Mode and MSB-First Data
NEW CONVERSION BEGINS
CS
REQUEST POWER SHUTDOWN
SHUTDOWN*
CLK
START
UNI
PS
START
UNI
PS
SEL1
SEL1
MSBF
D
IN
DON'T CARE
ODD/
SIGN
MSBF
SEL0
SEL1/
DIFF
SEL0
SEL1/ ODD/
DIFF SIGN
B11
•
•
•
•
•
•
•
•
•
•
B0
FILLED
WITH
ZEROES
HI-Z
HI-Z
D
OUT
LTC1293 AI06
*STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION.
CS CAN BE BROUGHT HIGH ONCE THE DIN WORD HAS BEEN CLOCKED IN.
Table 1. Microprocessor with Hardware Serial Interfaces Compat-
ible with the LTC1293/4/6**
all logical ones will be shifted out followed by logical
zeroes till CS goes high. Then the DOUT line will go into its
highimpedancestate. TheLTC1293/4/6willremaininthe
shutdown mode till the next CS cycle. There is no warm-
up or wait period required after coming out of the power
shutdown cycle so a conversion can commence after CS
goeslow(seePowerShutdownOperatingSequence).The
LTC1296hasaSystemShutdownOutputpin(SSO)which
willgolowwhenpowershutdownisactivated. Thepinwill
stay low till next CS cycle.
PART NUMBER
TYPE OF INTERFACE
Motorola
MC6805S2, S3
MC68HC11
SPI
SPI
SPI
MC68HC05
RCA
CDP68HC05
SPI
Hitachi
HD6305
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
Microprocessor Interfaces
National Semiconductor
COP400 Family
COP800 Family
NS8050U
MICROWIRE†
The LTC1293/4/6 can interface directly (without external
hardware) to most popular microprocessors (MPU) syn-
chronous serial formats (see Table 1). If an MPU without
a dedicated serial port is used, then three of the MPU’s
parallel port lines can be programmed to form the serial
link to the LTC1293/4/6. Included here are one serial
interface example and one example showing a parallel
port programmed to form the serial interface.
MCROWIRE/PLUS†
MICROWIRE/PLUS
MICROWIRE/PLUS
HPC16000 Family
Texas Instruments
TMS7002
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
SPI
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020*
TMS370C050
Microprocessor Interfaces
*
Requires external hardware
The LTC1293/4/6 can interface directly (without external
hardware) to most popular microprocessors (MPU) syn-
chronous serial formats (see Table 1). If an MPU without
a dedicated serial port is used, then three of the MPU’s
parallel port lines can be programmed to form the serial
link to the LTC1293/4/6.
** Contact factory for interface information for processors not on this list
†
MICROWIRE and MICROWIRE/PLUS are trademarks of National
Semiconductor Corp.
129346fs
14
LTC1293/LTC1294/LTC1296
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Motorola SPI (MC68HC11)
Interfacing to the Parallel Port of the Intel 8051 Family
TheMC68HC11hasbeenchosenasanexampleofanMPU
withadedicatedserialport. ThisMPUtransfersdataMSB-
first and in 8-bit increments. The DIN word sent to the data
register starts the SPI process. With three 8-bit transfers,
the A/D result is read into the MPU. The second 8-bit
transfer clocks B11 through B8 of the A/D conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits B7 through B0 into the MPU. The data
is right justified in the two memory locations. ANDing the
second byte with 0DHEX clears the four most significant
bits. This operation was not included in the code. It can
be inserted in the data gathering loop or outside the loop
when the data is processed.
The Intel 8051 has been chosen to show the interface
between the LTC1293/4/6 and parallel port microproces-
sors. Usually the signals CS, DIN and CLK are generated
on three port lines and the DOUT signal is read on a fourth
portline. Thisworksverywell. Onecansavealinebytying
the DIN and DOUT lines together. The 8051 first sends the
start bit and DIN to the LTC1294 over the line connected to
P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
Data Exchange Between LTC1294 and MC68HC11
CS
CLK
SGL/
DIFF
ODD/
EVEN
SEL SEL
UNI
DON'T CARE
MSBF PS
D
IN
START
1
0
D
OUT
B11 B10
B9
B8
B4
B2
B0
X
B7
B6
B5
B3
B1
START
MPU
SEL
1
SEL
0
TRANSMIT
WORD
0
?
0
?
SGL ODD
MSBF PS
X
X
X
0
?
1
UNI
?
X
X
X
X
X
X
X
X
X
BYTE 2
BYTE 1
BYTE 3 (DUMMY)
MPU
RECEIVED
WORD
?
?
?
?
?
?
B10
B6
B2
?
0
B11
B9
B8
B7
B5
B4
B3
B1
B0
BYTE 2
BYTE 1
BYTE 3
LTC1293 TD01
Hardware and Software Interface to Motorola MC68HC11
D
FROM LTC1294 STORED ON MC68HC11 RAM
OUT
MSB
DO
CS
#62
#63
BYTE 1
BYTE 2
O
O
O
O
B11
B10
B2
B9
B1
B8
SCK
CLK
MC68HC11
ANALOG
INPUTS
LTC1294
LSB
B0
D
MOSI
IN
B7
B6
B5
B3
B4
D
MISO
OUT
LTC1293 TD01a
129346fs
15
LTC1293/LTC1294/LTC1296
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MC68HC11 CODE
LABEL MNEMONIC OPERAND COMMENTS
LABEL MNEMONIC OPERAND COMMENTS
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
#$50
$1028
#$1B
$1009
#$10
$50
#$E0
$51
#$00
$52
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $50
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $51
LOAD DUMMY DIN WORD INTO ACC A
LOAD DUMMY DIN DATA INTO $52
LOAD INDEX REGISTER X WITH $1000
STAA
WAIT2 LDAA
BPL
$102A
$1029
WAIT2
$102A
$62
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1294 MSBs INTO ACC A
STORE MSBs IN $62
LOAD DUMMY DIN INTO ACC A FROM
$52
LOAD DUMMY DIN INTO SPI, START
SCK
LDAA
STAA
LDAA
$52
STAA
$102A
WAIT3 LDAA
BPL
$1029
WAIT3
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
STAA
LDX
#$1000
BSET
LDAA
STAA
$08,X,$01 D0 GOES HIGH (CS GOES HIGH)
$102A
$63
LOOP BCLR
LDAA
STAA
LDAA
WAIT1 BPL
LDAA
$08,X,$01 D0 GOES LOW (CS GOES LOW)
$50
$102A
$1029
WAIT1
$51
LOAD LTC1294 LSBs IN ACC
STORE LSBs IN $63
LOAD DIN INTO ACC A FROM $50
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
JMP
LOOP
START NEXT CONVERSION
Hardware and Software Interface to Intel 8051
PS BIT LATCHED
INTO LTC1294
CS
1
4
6
2
3
5
7
8
CLK
B10
B8
B6
B4
B2
B0
SGL/ ODD/
DIFF SIGN
SEL
1
SEL
0
DATA
IN OUT
PS
UNI
MSB
B11
B9
B7
B5
B3
B1
(D /D
)
START
LTC1293 TD02
8051 P1.2 OUTPUT DATA
TO LTC1294
LTC1294 SEND A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 RECONFIGURED
AS INPUT AFTER THE 8TH RISING
CLK BEFORE THE 8TH FALLING CLK
LTC1294 TAKES CONTROL OF DATA
LINE ON 8TH FALLING CLK
Hardware and Software Interface to Intel 8051
D
FROM LTC1294 STORED IN 8051 RAM
OUT
MSB
P1.4
P1.3
CS
B11
B8
B7
0
B5
0
B4
0
B10
B9
B1
B6
0
R2
R3
CLK
ANALOG
INPUTS
LTC1294
8051
LSB
B0
D
OUT
P1.2
B3
B2
D
IN
LTC1293 TD02a
MUX ADDRESS
A/D RESULT
129346fs
16
LTC1293/LTC1294/LTC1296
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8051 CODE
LABEL MNEMONIC OPERAND
COMMENTS
CLK GOES LOW
CLEAR ACC
ROTATE DATA BIT (B3) INTO ACC
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B2) INTO ACC
CLK GOES HIGH
LABEL MNEMONIC OPERAND
COMMENTS
CS GOES HIGH
DIN WORD FOR LTC1294
CS GOES LOW
LOAD COUNTER
ROTATE DIN BIT INTO CARRY
CLK GOES LOW
OUTPUT DIN BIT TO LTC1294
CLK GOES HIGH
CLR
CLR
P1.3
A
SETB
CONT MOV
CLR
P1.4
A,#87H
P1.4
RLC
A
MOV
RLC
C,P1.2
A
MOV
LOOP1 RLC
CLR
R4,#08H
A
P1.3
SETB
CLR
MOV
RLC
P1.3
P1.3
C,P1.2
A
CLK GOES LOW
MOV
SETB
P1.2,C
P1.3
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B1) INTO ACC
CLK GOES HIGH
CLK GOES LOW
READ DATA BIT INTO CARRY
CS GOES HIGH
ROTATE DATA BIT (B0) INTO ACC
ROTATE RIGHT INTO ACC
ROTATE RIGHT INTO ACC
ROTATE RIGHT INTO ACC
STORE LSBs IN R3
DJNZ
R4,LOOP1 NEXT DIN BIT
SETB
CLR
P1.3
P1.3
C,P1.2
P1.4
A
A
A
A
MOV
CLR
P1,#04H
P1.3
P1.2 BECOMES AN INPUT
CLK GOES LOW
LOAD COUNTER
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B3) INTO ACC
CLK GOES HIGH
CLK GOES LOW
MOV
SETB
RRC
RRC
RRC
RRC
MOV
AJMP
MOV
LOOP MOV
R4,#09H
C,P1.2
RLC
SETB
A
P1.3
CLR
P1.3
DJNZ
MOV
MOV
SETB
R4,LOOP
R2,A
C,P1.2
P1.3
NEXT DOUT BIT
STORE MSBs IN R2
READ DATA BIT INTO CARRY
CLK GOES HIGH
R3,A
CONT
START NEXT CONVERSION
2
1
0
OUTPUT PORT
SERIAL DATA
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1293/4/6s
3
3
3
3
CS
LTC1294
CS
LTC1294
CS
LTC1294
MPU
8 CHANNELS
8 CHANNELS
8 CHANNELS
LTC1293 F03
Figure 3. Several LTC1294 Sharing One 3-Wire Serial Interface
Sharing the Serial Interface
device. To achieve the optimum performance use a PC
board. The analog ground pin (AGND) should be tied
directly to the ground plane with minimum lead length (a
low profile socket is fine). The digital ground pin (DGND)
also can be tied directly to this ground pin because
minimal digital noise is generated within the chip itself.
The LTC1293/4/6 can share the same 3-wire serial inter-
face with other peripheral components or other LTC1293/
4/6’s(Figure3).Now,theCSsignalsdecidewhichLTC1293/
4/6 is being addressed by the MPU.
ANALOG CONSIDERATIONS
Grounding
The LTC1293/4/6 should be used with an analog ground
plane and single point grounding techniques. Do not use
wire wrapping techniques to breadboard and evaluate the
V
CC should be bypassed to the ground plane with a 22µF
(minimum value) tantalum with leads as short as possible
and as close as possible to the pin. A 0.1µF ceramic disk
also should be placed in parallel with the 22µF and again
with leads as short as possible and as close to VCC as
possible. AVCC and DVCC should be tied together on the
129346fs
17
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A
LTC1294.Figure4showsanexampleofanidealLTC1293/
4/6 ground plane design for a two sided board. Of course
this much ground plane will not always be possible, but
users should strive to get as close to this ideal as possible.
HORIZONTAL: 10µs/DIV
V
CC
22µF
TANTALUM
Figure 5. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors.
0.1µF
CERAMIC
1
2
20
19
18
17
16
15
14
13
12
11
3
CS
VCC
4
5
6
7
8
HORIZONTAL: 10µs/DIV
9
–
Figure 6. Good VCC Bypassing Keeps Noise
and Ripple on VCC Below 1mV
10
V
ANALOG
GROUND
PLANE
0.1µF
CERAMIC
DISK
LTC1293 F04
Analog Inputs
Figure 4. Ground Plane for the LTC1293/4/6
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1293/4/6
have capacitive switching input current spikes. These
current spikes settle quickly and do not cause a problem.
If large source resistances are used or if slow settling op
amps drive the inputs, take care to insure the transients
caused by the current spikes settle completely before the
conversion begins.
Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
ground during a conversion cycle can induce errors or
noise in the output code. VCC noise and ripple can be kept
below 0.5mV by bypassing the VCC pin directly to the
analog ground plane with a minimum of 22µF tantalum
capacitor and with leads as short as possible. The lead
from the device to the VCC supply also should be kept to a
minimum and the VCC supply should have a low output
impedance such as obtained from a voltage regulator
(e.g., LT323A). For high frequency bypassing a 0.1µF
ceramic disk placed in parallel with the 22µF is recom-
mended. Again the leads should be kept to a minimum.
Figure 5 and 6 show the effects of good and poor VCC
bypassing.
“+”
INPUT
R
+
SOURCE
LTC1293/4/6
V
+
–
IN
6TH CLK↑
= 500Ω
C1
R
ON
“–”
INPUT
C
=
IN
100pF
8TH CLK↓
R
–
SOURCE
V
IN
C2
LTC1293 F07
Figure 7. Analog Input Equivalent Circuit
129346fs
18
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Source Resistance
“–” Input Settling
The analog inputs of the LTC1293/4/6 look like a 100pF
capacitor (CIN) in series with a 500Ω resistor (RON). CIN
getsswitchedbetween(+)and(–)inputsonceduringeach
conversion cycle. Large external source resistors and
capacitances will slow the settling of the inputs. It is
important that the overall RC time constant is short
enough to allow the analog inputs to settle completely
within the allowed time.
Attheendofthesamplephasetheinputcapacitorswitches
to the “-” input and the conversion starts (see Figure 8).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. It is critical that the “–” input voltage be
free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing RSOURCE– and C2 will
improve settling time. If large “–” input source resistance
must be used the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 1MHz,
“+” Input Settling
The input capacitor is switched onto the “+” input during
thesamplephase(tSMPL, seeFigure8). Thesampleperiod
21/2CLKcyclesbeforeaconversionstarts.Thevoltageon
the “+” input must settle completely within the sample
period. Minimizing RSOURCE+ and C1 will improve the
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
CLK frequency. With the minimum possible sample time
of 2.5µs RSOURCE+ < 1.5kΩ and C1 < 20pF will provide
adequate settling time.
RSOURCE– < 250Ω and C2 < 20pF will provide adequate
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figure 8). Again the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps including the LT1006 and
LT1013 single supply op amps can be made to settle
HOLD
SAMPLE
CS
CLK
SGL/
DIFF
D
IN
MSBF
PS
START
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
D
OUT
B11
HI-Z
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
LTC1293 F08
Figure 8. “+” and “–” Input Settling Windows
129346fs
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LTC1293/LTC1294/LTC1296
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the cycle time as shown in the typical performance char-
acteristic curve Maximum Filter Resistor vs Cycle Time.
within the minimum settling windows of 2.5µs (“+” input)
and 1µs(“–” input) that occurs at the maximum clock rate
of 1MHz. Figures 9 and 10 show examples of adequate
and poor op amp settling.
Input Leakage Current
Input leakage currents also can create errors if the source
resistancegetstoolarge.Forexample,themaximuminput
leakage specification of 1µA (at 125°C) flowing through a
source resistance of 1kΩ will cause a voltage drop of 1mV
or 0.8LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
performance characteristic curve Input Channel Leakage
Current vs Temperature).
HORIZONTAL: 500ns/DIV
Figure 9. Adequate Settling of Op Amp Driving Analog Input
SAMPLE AND HOLD
Single-Ended Input
The LTC1293/4/6 provides a built-in sample and hold
(S&H) function for all signals acquired in the single-ended
mode (COM pin grounded). The sample and hold allows
the LTC1293/4/6 to convert rapidly varying signals (see
typical performance characteristic curve of S&H Acquisi-
tion Time vs Source Resistance). The input voltage is
sampled during the tSMPL time as shown in Figure 8. The
sampling interval begins as the bit preceding the MSBF bit
is shifted in and continues until the falling edge of the PS
bit is received. On this falling edge the S&H goes into the
hold mode and the conversion begins.
HORIZONTAL: 20µs/DIV
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 11. For large values of CF (e.g., 1µF) the
capacitive input switching currents are averaged into a net
DC current. A filter should be chosen with a small resistor
and large capacitor to prevent DC drops across the resis-
tor. The magnitude of the DC current is approximately IDC
= 100pF × VIN/tCYC and is roughly proportional to VIN.
When running at the minimum cycle time of 21.5µs, the
inputcurrentequals23µAatVIN =5V. Hereafilterresistor
of 5Ω will cause 0.1LSB of full-scale error. If a larger filter
resistormustbeused,errorscanbereducedbyincreasing
Differential Input
With a differential input the A/D no longer converts a
single voltage but converts the difference between two
voltages. The voltage on the selected “+” input is sampled
and held and can be rapidly time varying. The voltage on
the “–” pin must remain constant and be free of noise and
ripple throughout the conversion time. Otherwise the
differencing operation will not be done accurately. The
conversion time is 12 CLK cycles. Therefore a change in
the –IN input voltage during this interval can cause con-
version errors. For a sinusoidal voltage on the –IN input
this error would be:
I
IDC
R
FILTER
V
–
"+"
IN
LTC1293/4/6
"–"
C
FILTER
⎛
⎞
12
V
= 2πf V
(
)
⎜
⎝
⎟
⎠
ERROR(MAX)
(–) PEAK
f
CLK
LTC1293 F11
Where f(–) is the frequency of the “–” input voltage, VPEAK
Figure 11. RC Input Filtering
is its peak amplitude and fCLK is the frequency of the CLK.
129346fs
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Usually VERROR will not be significant. For a 60Hz signal
on the “–” input to generate a 0.25LSB error (300µV) with
the converter running at CLK = 1MHz, its peak value would
have to be 66mV. Rearranging the above equation the
maximumsinusoidalsignal thatcanbedigitizedtoagiven
accuracy is given as:
HORIZONTAL: 1µs/DIV
Figure 13. Adequate Reference Settling (LT1027)
⎛
⎞
V
⎛
⎞
f
12
ERROR(MAX)
CLK
f
=
⎜
⎝
⎟
⎠
(–)MAX
⎜
⎟
2πV
⎝
⎠
PEAK
For 0.25LSB error (300µV) the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
Unused inputs should be tied to the ground plane.
Reference Input
HORIZONTAL: 1µs/DIV
The voltage on the reference input of the LTC1293/4/6
determines the voltage span of the A/D converter. The
reference input has transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 12). During each bit test of the conversion
(every CLK cycle) a capacitive current spike will be gener-
ated on the reference pin by the A/D. These current spikes
settle quickly and do not cause a problem. If slow settling
circuitry is used to drive the reference input, take care to
insurethattransientscausedbythesecurrentspikessettle
completely during each bit test of the conversion.
Figure 14. Poor Reference Settling Can Cause A/D Errors
Reduced Reference Operation
The effective resolution of the LTC1293/4/6 can be in-
creased by reducing the input span of the converter. The
LTC1293/4/6 exhibits good linearity over a range of refer-
ence voltages (see typical performance characteristics
curves of Change in Linearity vs Reference Voltage and
Change in Gain Error vs Reference Voltage). Care must be
taken when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. Offset and Noise are
factors that must be considered when operating at low
VREF values. For the LTC1293 REF– has been tied to the
AGND pin. Any voltage drop from the AGND pin to the
ground plane will cause a gain error.
REF+
14
LTC1293/4/6
EVERY CLK CYCLE
R
R
OUT
ON
V
8pF – 40pF
REF
REF–
13
LTC 1293 F12
Figure 12. Reference Input Equivalent Circuit
Offset with Reduced VREF
The offset of the LTC1293/4/6 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical performance characteris-
tic curve of Unadjusted Offset Error vs Reference Voltage
shows how offset in LSB’s is related to reference voltage
for a typical value of VOS. For example a VOS of 0.1mV,
whichis0.1LSBwitha5Vreferencebecomes0.4LSBwith
Figure 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time for
the reference to settle. Even at the maximum CLK rate of
1MHz most references and op amps can be made to settle
within the 1µs bit time. For example the LT1027 will settle
adequately or with a 10µF bypass capacitor at VREF the
LT1021 also can be used.
129346fs
21
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a 1.25 reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input to the LTC1293/4/6.
example, with VREF = 1.25V this will result in a gain error
change of –1.0LSB from the gain error measured with
VREF = 5V.
LTC1293
Noise with Reduced VREF
The total input referred noise of the LTC1293/4/6 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 5V reference input but will become
alargerfractionofanLSBasthesizeoftheLSBisreduced.
The typical performance characteristic curve of Noise
Error vs Reference Voltage shows the LSB contribution of
this 200µV of noise.
DAC
–
+
REF REF
V
AGND
R
REF
I
CC
REFERENCE
VOLTAGE
PIN
±
LTC1293 F15
Figure 15. Parasitic Pin Resistance (RPIN
)
For operation with a 5V reference, the 200µV noise is only
0.16LSB peak-to-peak. Here the LTC1293/4/6 noise will
contribute virtually no uncertainty to the output code. For
reduced references, the noise may become a significant
fraction of an LSB and cause undesirable jitter in the
output code. For example, with a 1.25V reference, this
200µV noise is 0.64LSB peak-to-peak. This will reduce
therangeofinputvoltagesoverwhichastableoutputcode
canbeachievedby0.64LSB. Nowaveragingreadingsmay
be necessary.
LTC1293/4/6 AC Characteristics
Two commonly used figures of merit for specifying the
dynamicperformanceoftheA/Dsindigitalsignalprocess-
ing applications are the Signal-to-Noise Ratio (SNR) and
the “effective number of bits”(ENOB). SNR is the ratio of
the RMS magnitude of the fundamental to the RMS
magnitude of all the non-fundamental signals up to the
Nyquist frequency (half the sampling frequency). The
theoretical maximum SNR for a sine wave input is given
by:
SNR = (6.02N + 1.76dB)
This noise data was taken in a very clean test fixture. Any
setup induced noise (noise or ripple on VCC, VREF or VIN)
will add to the internal noise. The lower the reference
voltage used, the more critical it becomes to have a noise-
free setup.
where N is the number of bits. Thus the SNR depends on
the resolution of the A/D. For an ideal 12-bit A/D the SNR
isequalto74dB. AFastFourierTransform(FFT)plotofthe
output spectrum of the LTC1294 is shown in Figures 16a
and 16b. The input (fIN) frequencies are 1kHz and 22kHz
with the sampling frequency (fS) at 45.4kHz. The SNR
obtained from the plot are 72.7dB and 72.5dB.
Gain Error due to Reduced VREF
The gain error of the LTC1294/6 is very good over a wide
range of reference voltages. The error component that is
seen in the typical performance characteristics curve
ChangeinGainErrorvsReferenceVoltagefortheLTC1293
is due the voltage drop on the AGND pin from the device
to the ground plane. To minimize this error the LTC1293
shouldbesoldereddirectlyontothePCboard.Theinternal
reference point for VREF is tied to AGND. Any voltage drop
in the AGND pin will make the reference voltage, internal
to the device, less than what is applied externally (Figure
15). This drop is typically 400µV due to the product of the
pin resistance (RPIN) and the LTC1293 supply current. For
Rewriting the SNR expression it is possible to obtain the
equivalent resolution based on the SNR measurement.
⎛
⎞
SNR – 1.76dB
6.02
N =
⎜
⎝
⎟
⎠
This is the so-called effective number of bits (ENOB). For
the example shown in Figures 16a and 16b, N = 11.8 bits.
Figure 17 shows a plot of ENOB as a function of input
frequency. The top curve shows the A/D’s ENOB remains
at 11.8 for input frequencies up to fS/2 with ±5V supplies.
129346fs
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PPLICATI
A
0
0
–20
–20
–40
–60
–40
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
10
FREQUENCY (kHz)
20
25
0
5
15
10
FREQUENCY (kHz)
20
25
5
15
1293 F8
1293 F16a
Figure 18. LTC1294 FFT Plot
Figure 16a. LTC1294 FFT Plot
fIN = 1kHz, fS = 45.4kHz,
SNR = 72.7dB with ±5V Supplies
fIN1 = 5.1kHz, fIN2 = 5.6kHz, fS = 45.4kHz
with ±5V Supplies
For +5V supplies the ENOB decreases more rapidly. This
isduepredominantlytothe2ndharmonicdistortionterm.
0
–20
Figure 18 shows a FFT plot of the output spectrum for two
tones applied to the input of the A/D. Nonlinearities in the
A/D will cause distortion products at the sum and differ-
ence frequencies of the fundamentals and products of the
fundamentals. This is classically referred to as
intermodulation distortion (IMD).
–40
–60
–80
–100
–120
–140
Overvoltage Protection
10
FREQUENCY (kHz)
20
25
0
5
15
Applying signals to the LTC1293/4/6’s analog inputs that
exceed the positive supply or that go below V– will
degrade the accuracy of the A/D and possibly damage the
device. For example this condition would occur if a signal
is applied to the analog inputs before power is applied to
the LTC1293/4/6. Another example is the input source is
operating from different supplies of larger value than the
LTC1293/4/6. These conditions should be prevented ei-
ther with proper supply sequencing or by use of external
circuitry to clamp or current limit the input source. There
are two ways to protect the inputs. In Figure 19 diode
clamps from the inputs to VCC and V– are used. The
secondmethodistoputresistorsinserieswiththeanalog
inputs for current limiting. As shown in Figure 20a, a 1kΩ
resistor is enough to stand off ±15V (15mA for only one
channel). If more than one channel exceeds the supplies
than the following guidelines can be used. Limit the
current to 7mA per channel and 28mA for all channels.
129346fs
Figure 16b. LTC1294 FFT Plo1t293 F16b
fIN = 22kHz, fS = 45.4kHz,
SNR = 72.5dB with ±5V Supplies
12.0
11.5
11.0
10.5
5V SUPPLIES
10.0
9.5
+5V SUPPLY
9.0
8.5
8.0
f
S
= 45.4kHz
20
40
FREQUENCY (kHz)
80
0
100
60
LT1293 F17
Figure 17. LTC1294 ENOB vs Input Frequency
23
LTC1293/LTC1294/LTC1296
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1N4148 DIODES
Thismeansfourchannelscanhandle7mAofinputcurrent
each. Reducing CLK frequency from a maximum of 1MHz
(See typical performance characteristics curves Maxi-
mum CLK Frequency vs Source Resistance and Sample
and Hold Acquisition Time vs Source Resistance) allows
the use of larger current limiting resistors. The “+” input
can accept a resistor value of 1kΩ but the “–” input cannot
accept more than 250Ω when the maximum clock fre-
quency of 1MHz is used. If the LTC1293/4/6 is clocked at
the maximum clock frequency and 250Ω is not enough to
current limit the “–” input source then the clamp diodes
are recommended (Figures 20a and 20b). The reason for
the limit on the resistor value is the MSB bit test is affected
by the value of the resistor placed at the “–” input (see
discussion on Analog Inputs and the typical performance
characteristics curve Maximum CLK Frequency vs Source
Resistance).
+5V
V
CC
1k
+
LTC1293/4/6
–
AGND
–
DGND
–5V
V
LTC1293 F20b
Figure 20b. Overvoltage Protection for Inputs
powersupplyreversalfromoccuringwhenaninputsource
isappliedtotheanalogMUXbeforepowerisappliedtothe
device. Power supply reversal occurs, for example, if the
input is pulled below V–. VCC will then pull a diode drop
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above VCC, V–
will be pulled a diode drop above ground. If no inputs are
present on the MUX, the Schottky diodes are not required
if V– is applied first then VCC.
If VCC and VREF are not tied together, then VCC should be
turned on first, then VREF. If this sequence cannot be met
connectingadiodefromVREF toVCC isrecommended(see
Figure 21).
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
For dual supplies (bipolar mode) placing two Schottky
diodes from VCC and V– to ground (Figure 22) will prevent
1N4148 DIODES
+5V
V
CC
+5V
–5V
V
CC
1N4148
LTC1293/4/6
REF
LTC1293/4/6
+
+5V
AGND
AGND
DGND
–
DGND
V
LTC1293 F21
Figure 21
LTC1293 F19
Figure 19. Overvoltage Protection for Inputs
+5V
V
CC
1N5817
+5V
V
CC
1k
LTC1293/4/6
AGND
+
LTC1293/4/6
250Ω
–
–
V
–5V
1N5817
LTC1293 F22
DGND
AGND
–
DGND
–5V
V
LTC1293 F20a
Figure 22. Power Supply Reversal
Figure 20a. Overvoltage Protection for Inputs
129346fs
24
LTC1293/LTC1294/LTC1296
O U
W U
PPLICATI
A
S I FOR ATIO
Unipolar conversion is requested and the data is output
MSBfirst.CSisdrivenat1/64theclockratebytheCD4520
and DOUT outputs the data. The output data from the DOUT
pin can be viewed on an oscilloscope that is set up to
trigger on the falling edge of CS (Figure 24).
A “Quick Look” Circuit for the LTC1294/6
Userscangetaquicklookatthefunctionandtimingofthe
LTC1294/6 by using the following simple circuit (Figure
23). VREF is tied to VCC. DIN is tied high which means VIN
should be applied to the CH7 with respect to COM. A
+5V
f/64
22µF
CLK
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DV
AV
CLK
CS
CC
CC
CLK
V
DD
f
CS
EN
Q1
Q2
Q3
Q4
RESET
RESET
Q4
DOUT
D
Q3
Q2
Q1
EN
CLK
OUT
LTC1294
CD4520
D
REF
REF
AGND
V
IN
+
–
V
IN
NULL
BIT
MSB
(B11)
FILLS
ZEROES
LSB
(B0)
V
SS
–
DGND
VERTICAL: 5V/DIV
HORIZONTAL: 2µs/DIV
CLOCK IN
TO
Figure 24. Scope Trace of the
LTC1294/6 “Quick Look” Circuit
Showing A/D Output
LTC1293 F23
1MHz MAX
OSCILLOSCOPE
Figure 23. “Quick Look” Circuit for the LTC1294/6
101010101010 (AAAHEX
)
U
O
TYPICAL APPLICATI S
Digitally Linearized Platinum RTD Signal Conditioner
5V
OUT
+15V
LT1027
+
10µF
500k
400°C TRIM
12.5k*
12k*
+15V
+15V
+
A1
LT1101
A=10
–
+
–
1k
A2
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DV
AV
CLK
CS
CC
CC
LT1006
22µF
TANTALUM
1k*
Rplat.
TO/FROM
30.1k**
1µF
D
OUT
68HC11
LTC1294
D
REF
REF
AGND
PROCESSOR
IN
+
–
* TRW-IRC MAR-6 RESISTOR – 0.1%
** 1% FILM RESISTOR
–
Rplat. = 1kΩ AT 0°C – ROSEMOUNT #118MF
DGND
V
3.92M**
500k
ZERO°C TRIM
LTC1293 TA03
129346fs
25
LTC1293/LTC1294/LTC1296
U
O
TYPICAL APPLICATI S
Micropower, 5000V Opto-Isolated, Multichannel,12-Bit Data
Acquisition System is Accessed Once Every Two Seconds
4N28s
10k
9V
5V
2N3906
10k
10k
10k
10k
10k
2N3906
C1
51k
LT1027
150Ω
5V
5V
10µF*
SCK
C0
51k
150Ω
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DV
5.1k
(3)
CC
AV
CC
150Ω
150Ω
51k
51k
TO
68HC11
CLK
CS
8
ANALOG
5V
INPUTS
D
OUT
0–5V RANGE
LTC1294
D
IN
+
MOSI
REF
REF
–
TO ADDITIONAL
LTC1294s
AGND
5.1k
51k
5V
–
300Ω
V
4N28
*SOLID TANTALUM
10k
MISO
2N3904
4N28
ISOLATION
BARRIER
LT1292 TA02
NC
129346fs
26
LTC1293/LTC1294/LTC1296
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
J Package
20-Lead Ceramic DIP
1.060
(26.924)
MAX
0.160
(4.064)
0.290 - 0.320
GLASS
(7.366 - 8.128)
MAX
SEALANT
20 19 18 17 16
15 14 13 12
11
10
0.015 – 0.060
(0.381 – 1.524)
0.200
(5.080)
MAX
0.220 - 0.310
(5.588 - 7.874) (0.635)
RAD TYP
0.025
0° – 15°
1
2
3
4
5
6
7
8
9
0.005
(0.127)
0.008 – 0.018
(0.203 – 0.457)
0.038 – 0.068
(0.965 – 1.727)
0.125
(3.175)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
J20 12/91
0.080
0.385 ± 0.025
0.014 – 0.026
(2.032)
MAX
(9.779 ± 0.635)
(0.356 – 0.660)
TJMAX
θJA
150°C
80°C/W
OBSOLETE PACKAGE
N Package
16-Lead Plastic DIP
0.770
(19.558)
0.300 – 0.325
0.130 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 0.127)
(1.143 – 1.651)
12
14
13
10
9
16
15
11
0.015
(0.381)
MIN
0.260 0.010
(6.604 0.254)
0.065
(1.651)
TYP
0.009 - 0.015
(0.229 - 0.381)
+0.025
2
1
3
4
5
6
7
8
0.325
–0.015
0.125
(3.175)
MIN
0.045 0.015
(1.143 0.381)
0.018 0.003
(0.457 0.076)
+0.635
8.255
(
)
–0.381
0.100 0.010
N16 1291
(2.540 0.254)
TJMAX
θJA
100°C/W
110°C
N Package
20-Lead Plastic DIP
1.040
(26.416)
MAX
0.300 – 0.325
(7.620 – 8.255)
0.130 0.005
(3.302 0.127)
0.045 – 0.065
(1.143 – 1.651)
20
13
18
17
19
16
15
14
12
11
0.015
0.260 0.010
(6.604 0.254)
(0.381)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
3
1
6
2
4
5
8
9
10
7
0.325
–0.015
0.125
(3.175)
MIN
0.065 0.015
(1.651 0.381)
0.018 0.003
(0.457 0.076)
+0.635
8.255
(
)
–0.381
0.100 0.010
N20 0192
(2.540 0.254)
TJMAX
θJA
100°C/W
110°C
129346fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1293/LTC1294/LTC1296
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic SOL
0.398 – 0.413
(10.109 – 10.490)
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
15 14
12
10
9
16
13
11
0.010 – 0.029
× 45°
(0.254 – 0.737)
0° – 8° TYP
0.050
(1.270)
TYP
0.394 – 0.419
(10.008 – 10.643)
SEE NOTE
0.009 – 0.013
0.004 – 0.012
(0.102 – 0.305)
(0.229 – 0.330)
SEE NOTE
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
(0.356 – 0.483)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2
3
5
7
8
1
4
6
SOL16 12/91
TJMAX
110°C
θJA
150°C/W
S Package
20-Lead Plastic SOL
0.496 – 0.512
(12.598 – 13.995)
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
19 18
16
14 13 12 11
20
17
15
0.010 – 0.029
× 45°
(0.254 – 0.737)
0° – 8° TYP
0.050
(1.270)
TYP
0.394 – 0.419
(10.008 – 10.643)
SEE NOTE
0.009 – 0.013
0.004 – 0.012
(0.102 – 0.305)
(0.229 – 0.330)
SEE NOTE
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
(0.356 – 0.483)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2
3
5
7
8
9
10
1
4
6
SOL20 12/91
TJMAX
110°C
θJA
150°C/W
129346fs
LT/GP 0392 10K REV 0
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
28
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
© LINEAR TECHNOLOGY CORPORATION 1992
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