LTC1326-2.5 [Linear]
Micropower Precision Triple Supply Monitors; 精密微三路电源监视器
| 型号： | LTC1326-2.5 |
| 厂家： | 
Linear |
| 描述： | Micropower Precision Triple Supply Monitors |
| 文件： | 总16页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1326/LTC1326-2.5
Micropower Precision
Triple Supply Monitors
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FEATURES
DESCRIPTIO
The LTC®1326/LTC1326-2.5 are triple supply monitors
intended for systems with multiple supply voltages. They
provide micropower operation, small size and high accu-
racy supply monitoring.
■
Simultaneously Monitors Three Supplies
LTC1326: 5V, 3.3V and ADJ
LTC1326-2.5: 2.5V, 3.3V and ADJ
■
Guaranteed Threshold Accuracy: ±0.75%
■
Low Supply Current: 20µA
Tight 0.75% threshold accuracy and glitch immunity
ensure reliable reset operation without false triggering.
The 20µA typical supply current makes the LTC1326/
LTC1326-2.5 ideal for power-conscious systems.
■
Internal Reset Time Delay: 200ms
■
Manual Push-Button Reset Input
■
Active Low and Active High Reset Outputs
■
Active Low “Soft” Reset Output
■
■
The RST output is guaranteed to be in the correct state for
CC3,VCC5orVCC25downto1V.TheLTC1326/LTC1326-2.5
can be configured to monitor one, two or three inputs,
depending on system requirements.
Power Supply Glitch Immunity
Guaranteed RESET for VCC3 ≥ 1V or VCC5 ≥ 1V
or VCC25 ≥ 1V
V
■
8-Pin SO and MSOP Packages
A manual push-button reset input provides the ability to
generate a very narrow “soft” reset pulse (100µs typ) or a
200ms reset pulse equivalent to a power-on reset. Both
SRST and RST outputs are open-drain and can be OR-tied
with other reset sources.
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APPLICATIO S
■
Desktop Computers
■
Notebook Computers
■
Intelligent Instruments
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Portable Battery-Powered Equipment
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TYPICAL APPLICATIO
RST Output Voltage vs Supply Voltage (LTC1326-2.5)
2.5V
3.5
3.3V
V
V
= V
= V
CCA CC3
DC/DC
CONVERTER
SYSTEM
LOGIC
CC25
3.0
4.7k PULL-UP FROM RST TO V
CORE
CC3
T
= 25°C
A
2.5
2.0
1.5
1.0
0.5
0.1µF
V
V
V
CC25 CC3 CCA
LTC1326-2.5
RST
0
PBR
SRST
GND
2.0
(V)
3.0
3.5
0
0.5
1.0 1.5
2.5
PUSH-BUTTON
RESET
V
CC3
1326/2.5 TA02
1326/2.5 TA01
1
LTC1326/LTC1326-2.5
W W W
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ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Operating Temperature Range
Terminal Voltage
LTC1326C/LTC1326C-2.5....................... 0°C to 70°C
LTC1326I/LTC1326I-2.5 ..................... – 40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
V
CC3, VCC5, VCC25, VCCA......................... –0.5V to 7V
RST, SRST ............................................ –0.5V to 7V
RST ...................................... –0.5V to (VCC3 + 0.3V)
PBR .......................................................... –7V to 7V
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER
ORDER
TOP VIEW
PART NUMBER
PART NUMBER
TOP VIEW
1
2
3
4
8
7
6
5
V
V
V
PBR
SRST
RST
RST
CC3
CC5
V
V
V
1
2
3
4
8 PBR
7 SRST
6 RST
5 RST
CC3
CC5
CCA
LTC1326CMS8
LTC1326CS8
LTC1326IS8
CCA
GND
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
S8 PART NUMBER
S8 PACKAGE
8-LEAD PLASTIC SO
MS8 PART NUMBER
LTBA
TJMAX = 125°C, θJA = 250°C/W
TJMAX = 125°C, θJA = 150°C/W
1326
1326I
ORDER
ORDER
TOP VIEW
PART NUMBER
PART NUMBER
TOP VIEW
1
2
3
4
8
7
6
5
V
PBR
SRST
RST
RST
CC3
V
1
2
3
4
8 PBR
7 SRST
6 RST
5 RST
CC3
V
CC25
LTC1326CMS8-2.5
LTC1326CS8-2.5
LTC1326IS8-2.5
V
V
CC25
CCA
V
CCA
GND
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTEK
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 250°C/W
132625
326I25
TJMAX = 125°C, θJA = 150°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC3 = 3.3V, VCC5 = 5V (for LTC1326),VCC25 = 2.5V (for LTC1326-2.5), VCCA = VCC3, TA = 25°C unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
0°C ≤ T ≤ 70°C
MIN
TYP
MAX
UNITS
V
V
V
V
V
Reset Threshold V
●
●
3.094
3.052
3.118
3.118
3.143
3.143
V
V
RT3
RT5
RT25
RTA
CC3
CC5
CC25
CCA
A
–40°C ≤ T ≤ 85°C
A
Reset Threshold V
Reset Threshold V
Reset Threshold V
(LTC1326)
0°C ≤ T ≤ 70°C
●
●
4.687
4.625
4.725
4.725
4.762
4.762
V
V
A
–40°C ≤ T ≤ 85°C
A
(LTC1326-2.5) 0°C ≤ T ≤ 70°C
●
●
2.344
2.312
2.363
2.363
2.381
2.381
V
V
A
–40°C ≤ T ≤ 85°C
A
0°C ≤ T ≤ 70°C
●
●
0.992
0.980
1.000
1.000
1.007
1.007
V
V
A
–40°C ≤ T ≤ 85°C
A
V
V
Operating Voltage
Supply Current
RST in Correct Logic State
●
●
1
7
V
CC
CC3
CC3
I
PBR = V
20
40
µA
VCC3
CC3
2
LTC1326/LTC1326-2.5
ELECTRICAL CHARACTERISTICS
VCC3 = 3.3V, VCC5 = 5V (for LTC1326),VCC25 = 2.5V (for LTC1326-2.5), VCCA = VCC3, TA = 25°C unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
4
MAX
UNITS
µA
I
I
I
V
V
V
Input Current (LTC1326)
V
V
V
= 5V
●
●
7
7
VCC5
VCC25
VCCA
CC5
CC5
Input Current (LTC1326-2.5)
= 2.5V
2.8
µA
CC25
CC25
Input Current
= 1V
CCA
CCA
0°C ≤ T ≤ 70°C
●
●
–5
–15
0
0
5
15
nA
nA
A
–40°C ≤ T ≤ 85°C
A
t
Reset Pulse Width
RST Low with 10kΩ Pull-Up to V
RST
CC3
0°C ≤ T ≤ 70°C
●
●
140
140
200
200
280
300
ms
ms
A
–40°C ≤ T ≤ 85°C
A
t
t
Soft Reset Pulse Width
SRST Low with 10kΩ Pull-Up to V
●
50
100
13
200
µs
µs
SRST
UV
CC3
V
Undervoltage Detect to RST
V
, V
or V
Less Than Reset
CCA
CC
CC25 CC3
Threshold V by More Than 1%
RT
I
PBR Pull-Up Current
PBR = 0V
PBR
0°C ≤ T ≤ 70°C
●
●
3
3
7
7
10
15
µA
µA
A
–40°C ≤ T ≤ 85°C
A
V
V
PBR, RST Input Low Voltage
PBR, RST Input High Voltage
PBR Min Pulse Width
PBR Debounce
●
●
●
●
0.8
V
V
IL
IH
2
t
t
40
ns
ms
PW
DB
Deassertion of PBR Input to SRST
20
35
Output (PBR Pulse Width = 1µs)
t
PBR Assertion Time for Transition
from Soft to Hard Reset Mode
PBR Held Less Than V
IL
PB
0°C ≤ T ≤ 70°C
●
●
1.4
1.4
2.0
2.0
2.8
3.0
s
s
A
–40°C ≤ T ≤ 85°C
A
V
RST Output Voltage Low
I
I
= 5mA
●
0.15
0.4
V
OL
SINK
= 100µA,
A
V
V
V
= 1V, V
= 0V, V
= 1V, V
= 0V
= 1V
= 1V
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
SINK
CC3
CC3
CC3
CC5
CC5
CC5
0°C ≤ T ≤ 70°C
I
= 100µA,
V
V
V
= 1.1V, V = 0V
CC5
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
SINK
CC3
CC3
CC3
–40°C ≤ T ≤ 85°C
= 0V, V
= 1.1V
= 1.1V
A
CC5
= 1.1V, V
CC5
I
= 100µA,
A
V
V
V
= 1V, V
= 0V, V
= 1V, V
= 0V
= 1V
= 1V
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
SINK
CC3
CC3
CC3
CC25
CC25
CC25
0°C ≤ T ≤ 70°C
I
= 100µA,
V
V
V
= 1.1V, V = 0V
CC25
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
SINK
CC3
CC3
CC3
–40°C ≤ T ≤ 85°C
= 0V, V
= 1.1V
= 1.1V
A
CC25
= 1.1V, V
CC25
SRST Output Voltage Low
I
I
I
I
I
= 2.5mA
= 2.5mA
●
●
●
●
●
0.15
0.15
0.4
0.4
V
V
SINK
RST Output Voltage Low
SINK
V
RST Output Voltage High (Note 3)
SRST Output Voltage High (Note 3)
RST Output Voltage High
= 1µA
V
CC3
V
CC3
V
CC3
– 1
V
OH
SOURCE
SOURCE
SOURCE
= 1µA
– 1
– 1
V
= 600µA
V
t
t
Prop Delay RST to RST
High Input to Low Output
C
= 20pF
25
45
ns
PHL
PLH
RST
Prop Delay RST to RST
Low Input to High Output
C
= 20pF
ns
RST
3
LTC1326/LTC1326-2.5
ELECTRICAL CHARACTERISTICS
LTC1326 Only VCC3 = 3.3V, VCC5 = 5V, VCCA = VCC3, TA = 25°C unless otherwise noted.
SYMBOL
PARAMETER
Reset Override Voltage
CONDITIONS
Override V
MIN
TYP
V ±0.025
CC3
MAX
UNITS
V
V
Ability to Assert RST (Note 4)
V
OVR
CC5
CC5
The
●
denotes specifications which apply over the full operating
Note 3: The output pins SRST and RST have weak internal pull-ups to
of 6µA typ. However, external pull-up resistors may be used when
temperature range.
V
CC3
faster rise times are required.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 4: The V reset override voltage is valid for an operating range less
CC5
than approximately 4.15V. Above this point the override is turned off and
the V pin functions normally.
CC5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
IVCC5 vs Temperature
(LTC1326)
IVCC25 vs Temperature
(LTC1326-2.5)
IVCC3 vs Temperature
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
25
24
23
22
21
20
19
18
17
16
15
3.00
2.95
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.55
2.50
–60
20
TEMPERATURE (°C)
60 80
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
–60
80
–40 –20
0
40
100
–40 –20
0
20 40 60
TEMPERATURE (°C)
100
1326/2.5 G02
1326/2.5 G01
1326/2.5 G03
VCC5 Transient Immunity
(LTC1326)
VCC25 Transient Immunity
(LTC1326-2.5)
VCCA Input Current vs Input Voltage
50
45
40
35
30
25
20
15
10
5
3
2
T
A
= 25°C
RESET OCCURS
ABOVE CURVE
RESET OCCURS
ABOVE CURVE
45
40
35
30
25
20
15
10
5
T
= 25°C
T
= 25°C
A
A
1
0
–1
–2
–3
0
0
0.001
0.01
0.1
1
1.05 1.1
0.8 0.85 0.9 0.95 1.0
1.15 1.2
0.001
0.01
0.1
1
INPUT VOLTAGE (V)
V
RESET COMPARATOR OVERDRIVE (V)
V
RESET COMPARATOR OVERDRIVE (V)
CC5
CC25
1326/2.5 G05
1326/2.5 G06
1326/2.5 G04
4
LTC1326/LTC1326-2.5
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TYPICAL PERFOR A CE CHARACTERISTICS
VCC5 Threshold Voltage
vs Temperature (LTC1326)
4.750
VCC3 Transient Immunity
VCCA Transient Immunity
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
RESET OCCURS
ABOVE CURVE
= 25°C
RESET OCCURS
ABOVE CURVE
T = 25°C
A
4.745
4.740
4.735
4.730
4.725
4.720
4.715
4.710
4.705
4.700
T
A
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
100
100
V
RESET COMPARATOR OVERDRIVE (V)
V
CC3
RESET COMPARATOR OVERDRIVE (V)
CCA
1326/2.5 G07
1326/2.5 G08
1326/2.5 G09
VCC25 Threshold Voltage
VCC3 Threshold Voltage
vs Temperature
VCCA Threshold Voltage
vs Temperature
vs Temperature (LTC1326-2.5)
2.375
2.370
2.365
2.360
2.355
2.350
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
3.135
3.130
3.125
3.120
3.115
3.110
3.105
3.100
–60
20
TEMPERATURE (°C)
60 80
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
–20
0
20 40
100
–40 –20
0
40
–60 –40
60 80
TEMPERATURE (°C)
1326/2.5 G10
1326/2.5 G12
1326/2.5 G11
Reset Pulse Width
vs Temperature
PBR Assertion Time to Reset
vs Temperature
“Soft” Reset Pulse Width
vs Temperature
112.5
110.0
107.5
105.0
102.5
100.0
97.5
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
225
220
215
210
205
200
195
190
95.0
–60
20
TEMPERATURE (°C)
60 80
–60
80
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
–40 –20
0
20 40 60
–40 –20
0
40
100
TEMPERATURE (°C)
1326/2.5 G14
1326/2.5 G15
1326/2.5 G13
5
LTC1326/LTC1326-2.5
U
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PIN FUNCTIONS
VCC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for RST (Pin 6): Reset Logic Output. Active low, open-drain
the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor. logic output with weak pull-up to VCC3. Can be pulled up
greater than VCC3 when interfacing to 5V logic. Asserted
V
CC5 (Pin 2) (LTC1326): 5V Sense Input. Used as gate
when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than
2 seconds and for an additional 200ms after PBR is
released.
drive for the RST output FET when the voltage on VCC3 is
less than the voltage on VCC5. If unused, it can be tied to
V
CC3 (see Dual and Single Supply Monitor Operation in
the Applications Information section).
VCC25 (Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as
gate drive for RST output FET when the voltage on VCC3
is less than the voltage on VCC25. If unused it can be tied
SRST (Pin 7): Soft Reset. Active low, open-drain logic
output with weak pull-up to VCC3. Can be pulled up
greater than VCC3 when interfacing to 5V logic. Asserted
for 100µs after PBR is held low for less than 2 seconds
and released.
to VCC3
.
VCCA (Pin 3): 1V Sense, High Impedance Input. Can be
used as a logic input with a 1V threshold. If unused it can
PBR (Pin 8): Push-Button Reset. Active low logic input
with weak pull-up to VCC3. Can be pulled up greater than
VCC3 wheninterfacingto5Vlogic. Whenassertedforless
than 2 seconds, outputs a soft reset 100µs pulse on the
SRST pin. When PBR is asserted for greater than 2
seconds, the RST output is forced low and remains low
until 200ms after PBR is released.
be tied to either VCC3 or VCC25
.
GND (Pin 4): Ground.
RST (Pin 5):Reset Logic Output. Active high CMOS logic
output,driveshightoVCC3,bufferedcomplementofRST.
An external pull-down on the RST pin will drive this pin
high.
6
LTC1326/LTC1326-2.5
W
BLOCK DIAGRA S
LTC1326
V
CC3
V
CC3
6µA
7µA
7
SRST
SOFT RESET
RESET
PBR
PBR
8
2
TIMER
–
+
TO POWER
DETECT
4.15V
–
+
V
CC5
25mV
25mV
–
+
V
CC3
–
V
CC3
INTERNAL
+
V
1
CC3
V
CC3
V
CC3
6µA
–
+
6
RST
200ms
RESET
GENERATOR
POWER
DETECT/
GATE DRIVE
–
+
V
3
4
CCA
V
CC5
V
CC3
GND
5
RST
REF
1326 BD
LTC1326-2.5
V
CC3
V
CC3
6µA
7µA
7
SRST
SOFT RESET
RESET
PBR
TIMER
PBR
8
TO POWER
DETECT
V
CC25
2
V
CC3
V
CC3
6µA
–
+
6
RST
V
CC3
INTERNAL
200ms
RESET
GENERATOR
POWER
DETECT/
GATE DRIVE
V
1
CC3
V
CC25
V
CC3
–
+
5
RST
–
+
V
3
4
CCA
GND
REF
1326-2.5 BD
7
LTC1326/LTC1326-2.5
W U
W
TI I G DIAGRA S
VCC Monitor Timing
Push-Button Reset Function Timing
PBR
V
RTX
V
CCX
t < t
PB
t
PB
t
RST
t
RST
t
DB
RST
RST
t
SRST
1326/2.5 TD01
1326/2.5 TD02
SRST
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APPLICATIO S I FOR ATIO
Operation
The three internal precision voltage comparators have
response times that are typically 13µs. This slow re-
sponse time helps prevent mistriggering due to tran-
sients on each of the VCC inputs. The part’s ability to
suppress transients can be improved by bypassing each
of the VCC inputs with a 0.1µF capacitor to ground.
The LTC1326/LTC1326-2.5 are micropower, high accu-
racy triple supply monitoring circuits. The parts have two
basic functions: generation of a reset when power sup-
plies are out of range, and generation of reset or a “soft”
reset when the PBR pin is pulled low.
Push-Button Reset
Supply Monitoring
The parts provide a push-button reset input pin. The PBR
inputhasaninternalpull-upcurrentsourcetoVCC3. Ifthe
PBR pin is not used it can be left floating.
All three VCC inputs must be above predetermined
thresholds for 200ms before the reset output is released.
Thepartswillassertresetduringpower-up, power-down
and brownout conditions on any one or more of the VCC
inputs.
When the PBR is pulled low for less than tPB (≈ 2 sec), a
narrow (100µs typ) soft reset pulse is generated on the
SRST output pin after the button is released. The push-
button circuitry contains an internal debounce counter
whichdelaystheoutputofthesoftresetpulsebytypically
20ms. This pin can be OR-tied to the RST pin and issue
what is called a “soft” reset. The SRST thereby resets the
microprocessor without interrupting the DRAM refresh
cycle. In this manner DRAM information remains undis-
turbed. Alternatively, SRST may be monitored by the
processor to initiate a software-controlled reset.
Onpower-up,eithertheVCC5 orVCC3 pinontheLTC1326,
or the VCC25 or VCC3 pin on the LTC1326-2.5, can power
the drive circuits for the RST pin. This ensures that RST
will be low when VCC5, VCC25 or VCC3 reaches 1V. As long
as any one of the VCC inputs is below its predetermined
threshold, RST will stay a logic low. Once all of the VCC
inputs rise above their thresholds, an internal timer is
started and RST is released after 200ms. The RST pin
outputs the inverted state of what is seen on RST pin.
WhenthePBRpinisheldlowforlongerthantPB (≈ 2sec),
a standard reset is generated on the RST and RST pins.
Once the 2 second period has elapsed, a reset signal is
produced by the push-button logic, thereby clearing the
reset counter. Once the button is released, the reset
counter begins counting the reset period (200ms nomi-
nal). Consequently, theresetoutputsremainassertedfor
approximately 200ms after the button is released.
RST is reasserted whenever any one of the VCC inputs
drops below its predetermined threshold and remains
asserted until 200ms after all of the VCC inputs are above
their thresholds.
On power-down, once any of the VCC inputs drop below
itsthreshold,RSTisheldatalogiclow.Alogiclowof0.4V
isguaranteeduntilVCC3 andVCC5 ontheLTC1326orVCC3
and VCC25 on the LTC1326-2.5 drop below 1V.
8
LTC1326/LTC1326-2.5
U
W U U
APPLICATIO S I FOR ATIO
During a supply induced reset condition, the ability of the
PBR pin to force a soft reset condition on the SRST pin
is disabled. In other words SRST will remain high. If the
PBR pin is held low, both during and after a supply
inducedreset(lowRST),theRSTpinwillremainlowuntil
200ms after the PBR goes high.
When monitoring either 3.3V or 5V with VCC3 strapped to
V
CC5, (see Figure 1) the LTC1326 determines which is the
appropriate range. The LTC1326 handles this situation as
shown in Figure 2. Above 1V and below VRT3, RST is held
low. From VRT3 to approximately 4.15V the LTC1326
assumes 3.3V supply monitoring and RST is deasserted.
Above approximately 4.15V the LTC1326 operates as a 5V
monitor. In most systems the 5V supply will pass through
the 3.1V to 4.15V region in <200ms during power-up, and
theRSToutputwillbehaveasdesired.Table1summarizes
the state of RST and RST at various operating voltages
Power Detect/Gate Drive
The LTC1326/LTC1326-2.5 for the most part are powered
internally from the VCC3 pin. The exception is at the gate
drive of the output FET on the RST pin. On the input to this
FET is power detection circuitry used to detect and drive
the gate from either the 3.3V input pin (VCC3) or the 5V
input pin (VCC5) on the LTC1326 or the 2.5V input pin
(VCC25) on the LTC1326-2.5. The gate drive is derived
from the pin with the highest potential. This ensures the
part pulls the RST pin low as soon as either input pin is
≥ 1V.
with VCC3 = VCC5
.
Table 1. Override Truth Table (VCC3 = VCC5
)
INPUTS (V = V = V RST
)
CC
RST
—
1
CC3
CC5
0V ≤ V ≤ 1V
—
0
CC
1V ≤ V ≤ V
CC
RT3
V
≤ V ≤ 4.15V
1
0
RT3
CC
4.15V ≤ V ≤ V
0
1
CC
RT5
Early versions of the LTC1326 did not have the power
detect/gate drive circuitry. These early versions were
powered off of VCC3 alone. Consult factory for date codes
concerning this circuitry change. All date codes of the
LTC1326-2.5 have the power detect/gate drive circuits.
V
≤ V
1
0
RT5
CC
3.3V OR
5V
LTC1326
1
2
3
4
8
7
6
5
V
V
V
PBR
CC3
CC5
CCA
4.7k
SRST
RST
R1
Dual and Single Supply Monitor Operation
ADJUSTABLE
SUPPLY
SYSTEM RESET
The VCC3, VCC5 and VCCA inputs may be individually
disabled by the following override techniques which allow
theLTC1326orLTC1326-2.5tobeusedasadualorsingle
supply monitor.
R2
GND
RST
1326/2.5 F01
Figure 1
LTC1326 Override Functions
5
4
3
V
= V
= V
= 0V TO 5V
CCA
CC3
CC5
The VCCA pin, if unused, can be tied to either VCC3 or VCC5
This is an obvious solution since the trip points for VCC3
andVCC5 willalwaysbegreaterthanthetrippointforVCCA
.
4.7k PULL-UP FROM RST TO V
CC3
.
The VCC5 input trip point is disabled if its voltage is equal
to the voltage on VCC3 ±25mV and the voltage on VCC5 is
less than 4.15V. In this manner the part will behave as a
3.3V monitor and the VCC5 reset will be disabled.
2
1
0
The VCC5 trip point is reenabled when the voltage on VCC5
is equal to the voltage on VCC3 ±25mV and the two inputs
are greater than approximately 4.15V. In this manner the
LTC1326 can function as a 5V monitor with the 3.3V
monitor disabled.
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
1326/2.5 F02
Figure 2. RST Voltage vs Supply Voltage
9
LTC1326/LTC1326-2.5
U
W
U U
APPLICATIO S I FOR ATIO
Figure 3 contains a simple circuit for 5V systems that can’t
risk the RST output going high in the 3.1V to 4.15V range
(possibly due to very slow rise time on the 5V supply).
DiodeD1powerstheLTC1326whiledropping ≈0.6V from
the VCC5 pin to the VCC3 pin. This prevents the part’s
internal override circuit from being activated. Without the
override circuit active, the RST pin stays low until VCC5
reaches VRT5 4.725V. (See Figure 4.)
LTC1326-2.5 Override Functions
TheVCCA pin, ifunused, canbetiedtoeitherVCC3 orVCC25
.
This is an obvious solution since the trip points for VCC3
and VCC25 will always be greater than the trip point for
V
CCA. Likewise, the VCC25, if unused, can be tied to VCC3.
VCC3 must always be used. Tying VCC3 to VCC25 and
operating off of a 2.5V supply will result in the continuous
assertion of RST.
Extending ESD Tolerance on the PBR Input Pin
LTC1326
D1*
1
2
3
4
8
7
6
5
V
V
V
PBR
SRST
RST
CC3
CC5
CCA
4.7k
The PBR pin is susceptible to ESD since it may be brought
out to a front panel in normal applications. The ESD
tolerance of this pin can be increased by adding a resistor
in series with the PBR pin. A 10k resistor can increase the
ESD tolerance of the PBR pin to approximately 10kV. The
PBR’s internal pull-up current of 7µA typical means there
is only 70mV (150mV max) dropped across the resistor.
See Figure 5.
5V
SYSTEM RESET
0.1µF
GND
RST
1326/2.5 F03
*MMBD914 OR EQUIVALENT
Figure 3. LTC1326 Monitoring a Single 5V Supply.
D1 Used to Avoid RST High Near 3.3V to 4V (See
Figure 2).
PUSH-BUTTON
LTC1326-2.5
RESET
10k*
1
2
3
4
8
7
6
5
3.3V
2.5V
V
V
V
PBR
SRST
RST
CC3
5
CC25
CCA
V
CC5
= V = 0V TO 5V
CCA
ADJUSTABLE SUPPLY
OR DC/DC FEEDBACK
DIVIDER
R1
4.7k PULL-UP FROM RST TO V
CC5
SYSTEM RESET
4
3
2
1
0
T
= 25°C
A
R2
GND
RST
*OPTIONAL RESISTOR EXTENDS ESD TOLERANCE OF PBR INPUT TO APPROXIMATELY 10kV
1326/2.5 F05
Figure 5. Triple Supply Monitor (3.3V, 2.5V
and Adjustable) with Extended ESD Tolerance
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
V
CC5
1326/2.5 F04
Figure 4. RST Output Voltage
Characteristics of the Circuit in Figure 3
10
LTC1326/LTC1326-2.5
U
TYPICAL APPLICATIONS N
Triple Supply Monitor (3.3V, 5V and Adjustable)
LTC1326
1
2
3
4
8
7
6
5
3.3V
5V
V
V
V
PBR
CC3
CC5
CCA
SRST
RST
ADJUSTABLE SUPPLY
OR DC/DC FEEDBACK
DIVIDER
R1
SYSTEM RESET
R2
GND
RST
1326/2.5 TA03
Dual Supply Monitor (3.3V and 5V, Defeat VCCA Input)
LTC1326
1
2
3
4
8
7
6
5
3.3V
5V
V
V
V
PBR
SRST
RST
CC3
CC5
CCA
SYSTEM RESET
GND
RST
1326/2.5 TA05
Dual Supply Monitor (3.3V or 5V Plus Adj)
3.3V OR
5V
LTC1326
1
2
3
4
8
7
6
5
V
V
V
PBR
SRST
RST
CC3
CC5
CCA
4.7k
R1
ADJUSTABLE
SUPPLY
SYSTEM RESET
R2
GND
RST
1326/2.5 F01
REFER TO LTC1326 OVERRIDE FUNCTIONS IN
THE APPLICATIONS INFORMATION SECTION.
Dual Supply Monitor (3.3V Plus Adj)
3.3V
LTC1326-2.5
1
2
3
4
8
7
6
5
V
V
V
PBR
SRST
RST
CC3
4.7k
CC25
CCA
R1
ADJUSTABLE
SUPPLY
SYSTEM RESET
R2
GND
RST
1326/2.5 TA07
11
LTC1326/LTC1326-2.5
U
TYPICAL APPLICATIONS N
SRST Tied to RST and OR-Tying Other Sources to RST to
Generate Reset and Reset
PUSHBUTTON
8
LTC1326/
LTC1326-2.5
PBR
3.3V
4.7k
6µA
RESET
SRST
7
6
5
6µA
RST
RST
OTHER OPEN DRAIN
RESET SOURCES
OR-TIED TO RESET
V
CC3
RESET
1326/2.5 TA08
Using VCCA Tied to DC/DC Feedback Divider
2.9V
35.7k
1%
LTC1326
LTC1435
V
1
2
3
4
8
7
6
5
6
3.3V
V
V
V
PBR
CC3
CC5
CCA
OSENSE
2.8k
1%
5V
SRST
RST
SYSTEM
RESET
22.1k
1%
GND
RST
ADJUSTABLE
RESET TRIP
THRESHOLD 2.74V
1326/2.5 TA09
Using the Short Pulse Width, Push-Button Soft Reset Feature
to Initiate Hard Reset
LTC1326-2.5
1
2
3
4
8
7
6
5
40ns ≤ t ≤ 10µs
P
3.3V
2.5V
V
V
V
PBR
SRST
RST
CC3
CC25
CCA
RESET
GND
RST
PBR
RST
20ms
200ms
1326/2.5 TA11
12
LTC1326/LTC1326-2.5
U
TYPICAL APPLICATIONS N
Monitoring a Negative Supply
3.3V
LTC1326
C1
0.1µF
1
2
3
4
8
7
V
V
V
PBR
SRST
RST
CC3
CC5
CCA
5V
R2
150k
1%
R1
150k
1%
6
C2
0.1µF
SYSTEM RESET
5
GND
RST
Q1
2N3906
Q2
2N3906
V
CCA
R3
100k
1%
R4 ≈ (100k)(0.98)(V
TRIP
+ 0.55)(–1)
Q3
2N3904
SUPPLY
–5V
VTRIP
–4.6V
–3V
R4
R4
392k
1%
392k
237k
1M
–3.3V
–12V
–10.8V
1326/2.5 TA12
–5V
Reset Valid for VCC3 Down to 0V
3.3V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
LTC1326-2.5
V
= V
= V
CC25 CCA
CC3
1
2
3
4
8
7
6
5
T
= 25°C
V
V
V
PBR
SRST
RST
A
CC3
100k
2.5V
CC25
CCA
R1
RST OUTPUT WITH
100k PULL-UP TO V
ADJUSTABLE
SUPPLY
CC3
SYSTEM RESET
R2
GND
RST
1326/2.5 TA13
RST OUTPUT
WITHOUT
100k PULL-UP.
10M LOAD TO GND
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
(V)
CC3
1326/2.5 TA13a
13
LTC1326/LTC1326-2.5
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.192 ± 0.004
(4.88 ± 0.10)
1
2
3
4
0.040 ± 0.006
(1.02 ± 0.15)
0.034 ± 0.004
(0.86 ± 0.102)
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.012
(0.30)
REF
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1197
0.0256
(0.65)
TYP
*
DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
14
LTC1326/LTC1326-2.5
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1326/LTC1326-2.5
U
TYPICAL APPLICATIO
Triple Supply Monitor with 3.3V and 5V System Resets
3.3V
5V
LTC1326
1
2
3
4
8
7
6
5
V
V
V
PBR
CC3
CC5
CCA
SRST
RST
10k
10k
Q1
ADJUSTABLE SUPPLY
OR DC/DC FEEDBACK
DIVIDER
R1
TO 3.3V
SYSTEM RESET
R2
GND
RST
TO 5V
SYSTEM RESET
2N7002
1326/2.5 TA14
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC690
5V Supply Monitor, Watchdog Timer and Battery Backup
3.3V Supply Monitor, Watchdog Timer and Battery Backup
5V Supply Monitor and Watchdog Timer
4.65V Threshold
2.9V Threshold
4.65V Threshold
4.37V/4.62V Threshold
LTC694-3.3
LTC699
LTC1232
5V Supply Monitor, Watchdog Timer and Push-Button Reset
Precision Triple Supply Monitor for PCI Applications
LTC1536
Meets PCI t
Timing Specifications
FAIL
132625f LT/TP 1198 4K • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 1998
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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