LTC1390CS [Linear]
8-Channel Analog Multiplexer with Serial Interface; 8通道模拟多路复用器,串行接口型号: | LTC1390CS |
厂家: | Linear |
描述: | 8-Channel Analog Multiplexer with Serial Interface |
文件: | 总8页 (文件大小:227K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1390
8-Channel
Analog Multiplexer
with Serial Interface
U
DESCRIPTIO
EATURE
3-Wire Serial Digital Interface
Data Retransmission Allows Series Connection
with Serial A/D Converters
Single 3V to ±5V Supply Operation
Analog Inputs May Extend to Supply Rails
Low Charge Injection
Low RON: 75Ω Max
Low Leakage: ±5nA Max
Guaranteed Break-Before-Make
TTL/CMOS Compatible for All Digital Inputs
Cascadable to Allow Additional Channels
Can Be Used as a Demultiplexer
S
F
The LTC®1390 is a high performance CMOS 8-to-1 analog
multiplexer. It features a 3-wire digital interface with a
bidirectional data retransmission feature, allowing it to be
wired in series with a serial A/D converter while using only
oneserialport.TheinterfacealsoallowsseveralLTC1390s
to be wired in series or parallel, increasing the number of
MUX channels available using only a single digital port. All
the above features are also valid when LTC1390 operates
as a demultiplexer such as with a D/A converter.
■
■
■
■
■
■
■
■
■
■
■
The LTC1390 features a typical RON of 45Ω, typical switch
leakage of 50pA, and guaranteed break-before-make op-
eration. Charge injection is ±10pC maximum. All digital
inputs are TTL and CMOS compatible when operated from
single or dual supplies. The inputs can withstand 100mA
fault currents.
O U
PPLICATI
A
S
■
■
■
Data Acquisition Systems
Communication Systems
Signal Multiplexing/Demultiplexing
The LTC1390 is available in 16-pin PDIP and narrow SO
packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
V
V
CC EE
ON-Resistance vs
Analog Input Voltage
V
CC
OPTIONAL A/D
INPUT FILTER
250
200
150
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
16
T
= 25°C
+
A
CS
V
CC
S0
S1
S2
S3
S4
S5
S6
S7
V
15
14
13
12
11
10
9
+IN
–IN
CLK
D
–
LTC1390
LTC1096
+
–
V
V
= 3V
= 0V
V
D
OUT
DATA 2
DATA 1
CS
ANALOG
INPUTS
GND
V
REF
100
50
0
CLK
V
CC
+
V
= 5V
GND
–
V
= –5V
47k
3-WIRE
SERIAL
INTERFACE
DATA
CLK
CS
LTC1390 • TA01
–5 –4 –3 –2 –1
0
1
2
3
4
5
TO MUX AND ADC
ANALOG INPUT VOLTAGE, V (V)
S
LTC1390 • TA02
1
LTC1390
W W W
U
W
U
ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
(Note 1)
Total Supply Voltage (V+ to V–).............................. 15V
Input Voltage
TOP VIEW
ORDER PART
NUMBER
+
1
2
3
4
5
6
7
8
V
D
V
16
15
14
13
12
11
10
9
S0
S1
S2
S3
S4
S5
S6
S7
Analog Inputs ........................ V– – 0.3V to V+ + 0.3V
Digital Inputs ........................................ –0.3V to 15V
Digital Outputs............................ –0.3V to V+ + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range ..................... 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
–
LTC1390CN
LTC1390CS
DATA 2
DATA 1
CS
CLK
GND
N PACKAGE
16-LEAD PDIP
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 70°C/ W (N)
JMAX = 150°C, θJA = 100°C/ W (S)
T
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
V+ = 5V, V– = –5V, GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL PARAMETER
Switch
CONDITIONS
MIN
TYP
MAX
UNITS
V
Analog Signal Range
On Resistance
(Note 2)
●
–5
5
V
ANALOG
R
V = ±3.5V, I = 1mA
S D
ON
T
25°C
75
75
120
Ω
Ω
Ω
MIN
45
T
MAX
∆R vs V
20
0.5
%
ON
S
∆R vs Temperature
%/°C
ON
I
I
I
Off Input Leakage
Off Output Leakage
On Channel Leakage
V = 4V, V = –4V; V = –4V, V = 4V
Channel Off
0.05
±5
±50
nA
nA
S(OFF)
D(OFF)
D(ON)
S
D
S
D
●
●
●
V = 4V, V = –4V; V = –4V, V = 4V
0.05
0.05
±5
±50
nA
nA
S
D
S
D
Channel Off
V = V = ±4V
±5
±50
nA
nA
S
D
Channel On
Input
+
V
V
High Level Input Voltage
Low Level Input Voltage
Low or High Level Current
High Level Output Voltage
V = 5.25V
●
●
●
2.4
2.4
V
V
INH
INL
+
V = 4.75V
0.8
I
, I
V
= 5V, V = 0V
±1
µA
INL INH
IN
+
IN
V
OH
V = 4.75V, I = 10µA
4.74
4.50
V
V
O
+
V = 4.75V, I = 360µA
●
●
O
+
V
OL
Low Level Output Voltage
V = 4.75V, I = 0.5mA
0.16
0.8
V
O
2
LTC1390
ELECTRICAL CHARACTERISTICS
V+ = 5V, V– = –5V, GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL PARAMETER
Dynamic
CONDITIONS
MIN
TYP
MAX
UNITS
f
t
t
t
Clock Frequency
5
MHz
ns
CLK
ON
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Off Isolation
V = 2.5V, R = 1k, C = 35pF
260
100
155
70
400
200
S
L
L
V = 2.5V, R = 1k, C = 35pF
ns
OFF
S
L
L
35
ns
OPEN
OIRR
V = 2V , R = 1k, f = 100kHz
dB
pC
pF
S
P-P
L
O
Charge Injection
R = 0, C = 1000pF, V = 1V (Note 2)
±2
5
±10
INJ
S
L
S
C
C
Source Off Capacitance
Drain Off Capacitance
S(OFF)
D(OFF)
10
pF
Supply
+
I
Positive Supply Current
Negative Supply Current
All Logic Inputs Tied Together, V = 0V or V = 5V
●
●
15
15
40
40
µA
µA
IN
IN
–
I
All Logic Inputs Tied Together, V = 0V or V = 5V
IN IN
V+ = 3V, V– = GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL PARAMETER
Switch
CONDITIONS
MIN
TYP
MAX
UNITS
V
Analog Signal Range
On Resistance
(Note 2)
●
0
3
V
ANALOG
R
V = 1.2V, I = 1mA
S D
ON
T
25°C
255
255
300
Ω
Ω
Ω
MIN
200
T
MAX
∆R vs V
20
0.5
%
ON
S
∆R vs Temperature
%/°C
ON
I
I
I
Off Input Leakage
Off Output Leakage
On Channel Leakage
V = 2.5V, V = 0.5V; V = 0.5V, V = 2.5V (Note 3)
Channel Off
±0.05
±5
±50
nA
nA
S(OFF)
D(OFF)
D(ON)
S
D
S
D
●
●
●
V = 2.5V, V = 0.5V; V = 0.5V, V = 2.5V (Note 3)
±0.05
±0.05
±5
±50
nA
nA
S
D
S
D
Channel Off
V = V = 0.5V, V = V = 2.5V (Note 3)
±5
±50
nA
nA
S
D
S
D
Channel On
Input
+
V
V
High Level Input Voltage
Low Level Input Voltage
Low or High Level Current
High Level Output Voltage
V = 3.3V
●
●
●
2.4
2
V
V
INH
INL
+
V = 2.7V
0.8
I
, I
V
= 3V, V = 0V
±1
µA
INL INH
IN
+
IN
V
OH
V = 2.7V, I = 20µA
2.68
2.27
V
V
O
+
V = 2.7V, I = 400µA
●
●
O
+
V
OL
Low Level Output Voltage
V = 2.7V, I = 20µA
0.01
0.15
V
V
O
+
V = 2.7V, I = 300µA
0.8
O
3
LTC1390
ELECTRICAL CHARACTERISTICS
V+ = 3V, V– = GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL PARAMETER
Dynamic
CONDITIONS
MIN
TYP
MAX
UNITS
f
t
t
t
Clock Frequency
5
MHz
ns
CLK
ON
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Off Isolation
V = 1.5V, R = 1k, C = 35pF (Note 4)
490
190
290
70
700
300
S
L
L
V = 1.5V, R = 1k, C = 35pF (Note 4)
ns
OFF
S
L
L
(Note 4)
125
ns
OPEN
OIRR
V = 2V , R = 1k, f = 100kHz
dB
pC
pF
S
P-P
L
O
Charge Injection
R = 0, C = 1000pF, V = 1V (Note 2)
±1
5
±5
INJ
S
L
S
C
C
Source Off Capacitance
Drain Off Capacitance
S(OFF)
D(OFF)
10
pF
Supply
+
I
Positive Supply Current
All Logic Inputs Tied Together, V = 0V or V = 3V
●
0.2
2
µA
IN
IN
The
●
denotes specifications which apply over the full operating
Note 3: Leakage current with a single 3V supply is guaranteed by
correlation with the leakage current of the ±5V supply.
temperature range.
Note 1: Absolute maximum ratings are those beyond which the safety of
the device may be impaired.
Note 4: Timing specifications with a single 3V supply is guaranteed by
correlation with the timing specifications of the ±5V supply.
Note 2: Guaranteed by design.
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
Driver Output Low Voltage
vs Output Current
Driver Output High Voltage
vs Output Current
ON-Resistance vs Temperature
300
250
200
150
6
5
4
3
2
1
0
0
–1
–2
–3
–4
–5
–6
–7
T
V
V
= 25°C
= 5V
T
V
V
= 25°C
= 5V
A
A
+
+
–
–
= –5V
= –5V
DATA 2
+
–
V
V
= 3V
= 0V
V
= 1.2V
S
DATA 1
DATA 1
+
100
50
0
V
–
= 5V
V
V
= –5V
DATA 2
= 0V
S
40
TEMPERATURE (˚C)
60
70
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT VOLTAGE (V)
4.0
OUTPUT VOLTAGE (V)
5.0
0
10
20
30
50
2.0
2.5
3.0
3.5
4.5
LTC1390 • G01
LTC1390 • G02
LTC1390 • G03
4
LTC1390
U
U
U
PIN FUNCTIONS
analog signal transmission and allows data transfer from
Data 2 to Data 1.
S0 to S7 (Pins 1 to 8): Analog Multiplexer Inputs/Analog
Demultiplexer Outputs.
Data 1 (Pin 12): Bidirectional Digital Input/Output (TTL/
CMOS Compatible). Input for the channel selection bits.
GND (Pin 9): Digital Ground. Connect to system ground.
CLK(Pin10):SystemClock(TTL/CMOSCompatible). The
clock synchronizes the channel selection bits and the
serial data transfer from Data 1 to Data 2.
Data 2 (Pin 13): Bidirectional Digital Input/Output (TTL/
CMOS Compatible).
V– (Pin 14): Negative Supply.
CS (Pin 11):Chip Select Input (TTL/CMOS Compatible). A
logic high on this input enables LTC1390 to read in the
channel selection bits and allow data transfer from Data 1
to Data 2. A logic low enables the desired channel for
D (Pin 15): Analog Multiplexer Output/Analog
Demultiplexer Input.
V+ (Pin 16): Positive Supply.
U U
W
U
APPLICATIO S I FOR ATIO
Multiplexer Operation
When CS is high, the input data on the Data 1 pin is latched
into the 4-bit shift register on each rising clock edge. The
input data consists of an “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. To ensure correct operation, the CS must be
pulled low before the next rising clock edge.
Figure 1 shows the block diagram of the components
within the LTC1390 required for MUX operation. The
LTC1390 uses Data 1 to select its 8 channels and a chip
selectinputCStoswitchontheselectedchannelasshown
in Figure 2.
CLK
DATA 1
CS
Once the CS is pulled low, all channels are simultaneously
switched off to ensure a break-before-make interval. After
adelayoftON, theselectedchannelisswitchedonallowing
signal transmission. The selected channel remains on
CONTROL
LOGIC
4-BIT SHIFT
REGISTER
ANALOG
INPUT
MUX
BLOCK
ANALOG
OUTPUT
until the next falling edge of CS, and after a delay of tOFF
,
it terminates the analog signal transmission and subse-
quently allows the selection of the next channel. If “EN” bit
is logic low, as illustrated in the second data sequence, it
disables all channels and there will be no analog signal
LTC1390 • F01
Figure 1: Simplified Block Diagram of the MUX Operation
CLK
CS
EN = LOW
EN = HIGH
DATA 1
B2
B1
B0
B2
B1
B0
ANY
ANALOG
INPUTS
D
LTC1390 • F02
t
t
OFF
ON
Figure 2: Multiplexer Operation
5
LTC1390
APPLICATIO S I FOR ATIO
U U
W
U
transmission. Table 1 shows the various bit combinations
selection or to Data 2 via Buffer 1 for data transfer. Data
appears at Data 2 after the fourth rising edge of the clock.
When CS is low, Buffer 2 is enabled and Buffer 1 is
disabled,thusdigitalinputdataisdirectlytransferredfrom
Data 2 to Data 1 without any clock delay.
for channel selection.
Table 1. Logic Table for Channel Selection
CHANNEL STATUS
All Off
S0
EN
0
1
B2
X
0
B1
X
0
B0
X
0
Multiplexer Expansion
S1
1
0
0
1
S2
S3
S4
S5
S6
S7
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Several LTC1390s can be daisy-chained to expand the
number of multiplexer inputs. No additional interface
ports are required for the expansion. Figure 5 shows two
LTC1390s connected at their analog outputs to form a 16-
to-1 multiplexer at the input to an LTC1286 A/D converter.
V
V
EE
CC
V
CC
Digital Data Transfer Operation
The block diagram of Figure 3 shows the components
contained within the LTC1390 required for digital data
transfer. Digital data transfer operation can be performed
from Data 1 to Data 2 and vice versa as shown in Figure 4.
When CS is high, Buffer 1 is enabled and Buffer 2 is
disabled. The digital input data is fed into the 4-bit shift
register and then shifted to the MUX switches for channel
1
2
3
4
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
V
V
CC
REF
S0
S1
S2
S3
S4
S5
S6
S7
V
7
6
5
+IN
CLK
LTC1286
D
–
LTC1390
A
V
–IN
D
OUT
DATA 2
DATA 1
CS
ANALOG
INPUTS
GND
CS
CLK
GND
CLK
V
CC
4-BIT SHIFT
REGISTER
MUX
SWITCHES
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
47k
D
–
LTC1390
B
DATA 2
BUFFER 1
V
DATA 2
DATA 1
CS
ANALOG
INPUTS
DATA
CS
CS
CLK
CLK
DATA 1
BUFFER 2
GND
LTC1390 • F05
LTC1390 • F03
Figure 5. Daisy-Chaining Two LTC1390s for Expansion
Figure 3. Simplified Block Diagram of the Digital Data
Transfer Operation
To ensure that only one channel is switched on at any one
time,twosetsofchannelselectionbitsareneededforData
as shown in Figure 6. The first data sequence is used to
switch off one MUX and the second data sequence is used
to select one channel from the other MUX, or vice versa.
In other words, if bit “ENA” is high and bit “ENB” is low,
one channel of MUX A is switched on and all channels of
MUX B are switched off. If bit “ENA” is low and bit “ENB”
is high, all channels of MUX A are switched off and one
channel of MUX B is switched on.
CLK
CS
1
2
3
4
Hi-Z
DATA 1
DATA 2
DATA OUT
DATA IN
DATA IN
DATA OUT
LTC1390 • F04
Figure 4. Digital Data Transfer Operation
6
LTC1390
U U
W
U
APPLICATIO S I FOR ATIO
CLK
CS
1
2
3
4
5
6
7
8
NULL
BIT
Hi-Z
ENA A2
A1
A0
ENB B2
B1
B0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
t
t
t
DATA
SMPL
CONV
DIGITAL INPUT FROM LTC1390
DIGITAL OUTPUT FROM LTC1286
LTC1390 • F06
Figure 6. Timing Diagram for Figure 5
Daisy-Chaining Five LTC1390s
U
TYPICAL APPLICATIONS N
+
BYPASS CAPACITOR FROM V TO GND AND
V
CC
–
V
TO GND REQUIRED FOR EACH LTC1390
V
V
CC EE
1
2
3
4
8
V
CC
V
V
CC
REF
7
6
5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
+IN
CLK
LTC1286
47k
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
–IN
D
OUT
LTC1390
A
V
GND
CS
DATA 2
DATA 1
CS
ANALOG
INPUTS
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
V
V
CC EE
D
–
LTC1390
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
V
V
S1
S2
S3
S4
S5
S6
S7
D
–
DATA 2
DATA 1
CS
LTC1390
D
ANALOG
INPUTS
V
DATA 2
DATA 1
CS
ANALOG
INPUTS
CLK
GND
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
GND
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
LTC1390
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
V
D
–
DATA 2
DATA 1
CS
LTC1390
ANALOG
INPUTS
E
V
DATA 2
DATA 1
CS
ANALOG
INPUTS
DATA*
CLK
CS
GND
CLK
CLK
GND
*
REQUIRES FIVE 4-BIT CHANNEL
SELECTION DATA BYTES
LTC1390 • TA03
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
7
LTC1390
TYPICAL APPLICATIONS N
U
Interfacing LTC1390 with LTC1257 for Demultiplex Operation
V
CC
V
EE
OPTIONAL D/A
OUTPUT FILTER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
V
CC
V
LTC1390
CC
1
2
3
4
8
7
6
5
V
CLK
LTC1257
IN
V
CC
47k
DATA 2
DATA 1
CS
ANALOG
OUTPUTS
D
V
OUT
LOAD
V
REF
D
OUT
GND
CLK
GND
DATA
CLK
CS
LTC1390 • F03
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead Plastic DIP
0.770*
(19.558)
MAX
0.300 – 0.325
0.130 ± 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 ± 0.127)
(1.143 – 1.651)
14
12
10
9
8
15
13
11
16
0.015
(0.381)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
+0.025
–0.015
2
1
3
4
6
5
7
0.325
(3.175)
MIN
0.045 ± 0.015
(1.143 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
S Package
16-Lead Plastic SOIC
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
16
15
14
13
12
11
10
9
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.150 – 0.157*
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
1
2
3
4
5
6
7
8
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC201A/LTC202/LTC203
LTC221/LTC222
Micropower, Low Charge Injection, Quad CMOS Analog Switches
Each Channel is Independently Controlled
Parallel Controlled with Data Latches
Micropower, Low Charge Injection, Quad CMOS Analog Switches
with Data Latches
LTC128x/LTC129x
Serial A/Ds with Integral MUXs
LT/GP 0695 10K • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
8
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1995
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