LTC1404CS8#TR [Linear]
LTC1404 - Complete SO-8, 12-Bit, 600ksps ADC with Shutdown; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC1404CS8#TR |
| 厂家： | 
Linear |
| 描述： | LTC1404 - Complete SO-8, 12-Bit, 600ksps ADC with Shutdown; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1404
Complete SO-8, 12-Bit,
600ksps ADC with Shutdown
U
FEATURES
DESCRIPTIO
The LTC®1404 is a complete 600ksps, 12-bit A/D con-
verter which draws only 75mW from 5V or ± 5V supplies.
This easy-to-use device comes complete with a 160ns
sample-and-hold and a precision reference. Unipolar and
bipolar conversion modes add to the flexibility of the ADC.
The LTC1404 has two power saving modes: Nap and
Sleep. In Nap mode, it consumes only 7.5mW of power
and can wake up and convert immediately. In the Sleep
mode, itconsumes60µWofpowertypically. Uponpower-
up from Sleep mode, a reference ready (REFRDY) signal
is available in the serial data word to indicate that the
reference has settled and the chip is ready to convert.
■
Complete 12-Bit ADC in SO-8
■
Single Supply 5V or ±5V Operation
■
■
■
■
■
■
■
■
■
■
Sample Rate: 600ksps
Power Dissipation: 75mW (Typ)
72dB S/(N + D) and –80dB THD at Nyquist
No Missing Codes over Temperature
Nap Mode with Instant Wake-Up: 7.5mW
Sleep Mode: 60µW
High Impedance Analog Input
Input Range (1mV/LSB): 0V to 4.096V or ± 2.048V
Internal Reference Can Be Overdriven Externally
3-Wire Interface to DSPs and Processors (SPI and
MICROWIRETM Compatible)
The LTC1404 converts 0V to 4.096V unipolar inputs from
a single 5V supply and ±2.048V bipolar inputs from ±5V
supplies. Maximum DC specs include ±1LSB INL, ± 1LSB
DNL and 45ppm/°C full-scale drift over temperature.
Guaranteed AC performance includes 69dB S/(N + D)
and –76dB THD at an input frequency of 100kHz over
temperature.
U
APPLICATIO S
■
High Speed Data Acquisition
■
Digital Signal Processing
■
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Digital Radio
Spectrum Analysis
Low Power and Battery-Operated Systems
Handheld or Portable Instruments
■
■
The 3-wire serial port allows compact and efficient data
transfertoawiderangeofmicroprocessors,microcontrollers
and DSPs.
■
■
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
Power Consumption vs Sample Rate
Single 5V Supply, 600kHz, 12-Bit Sampling A/D Converter
100
5V
NORMAL CONVERSION
V
V
SS
CC
10
+
NAP MODE
BETWEEN CONVERSION
10µF*
0.1µF
MPU
P1.4
LTC1404
1
ANALOG INPUT
(0V TO 4.096V)
A
V
CONV
CLK
IN
SLEEP MODE
BETWEEN CONVERSION
REF
2.43V
10µF
OUT
0.1
P1.3
P1.2
REF
+
GND
D
OUT
0.1µF
SERIAL
DATA LINK
0.01
9.6MHz CLOCK
*AVX TPSD106M035R0300
LTC1404 • TA01
0.001
0.01 0.1
100
SAMPLE RATE (Hz)
1
10
1k 10k 100k 1M
LTC1404 • TA02
1404fa
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LTC1404
W W U W
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
TOP VIEW
Supply Voltage (VCC) ................................................. 7V
Negative Supply Voltage (VSS) ................... –6V to GND
Total Supply Voltage (VCC to VSS)
Bipolar Operation Only ........................................ 12V
Analog Input Voltage (Note 3)
V
V
SS
1
2
3
4
8
7
6
5
CC
A
CONV
CLK
IN
V
REF
GND
D
OUT
Unipolar Operation .................. –0.3V to (VCC + 0.3V)
Bipolar Operation........... (VSS – 0.3V) to (VCC + 0.3V)
Digital Input Voltage (Note 4)
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 130°C/W
Unipolar Operation ................................–0.3V to 12V
Bipolar Operation.........................(VSS – 0.3V) to 12V
Digital Output Voltage
Unipolar Operation .................. –0.3V to (VCC + 0.3V)
Bipolar Operation........... (VSS – 0.3V) to (VCC + 0.3V)
Power Dissipation.............................................. 300mW
Operating Ambient Temperature Range
S8 PART MARKING
ORDER PART NUMBER
LTC1404CS8
LTC1404IS8
1404
1404I
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC1404C ............................................... 0°C to 70°C
LTC1404I............................................ –40°C to 85°C
Junction Temperature.......................................... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
U
W
POWER REQUIRE E TS The
●
denotes specifications which apply over the full operating temperature range,
unless otherwise noted specifications are at T = 25°C. V = 5V, f
= 600kHz, t = t = 5ns, unless otherwise specified.
r f
A
CC
SAMPLE
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Positive Supply Voltage
Unipolar
Bipolar
4.75
4.75
5.25
5.25
V
V
V
Negative Supply Voltage
Positive Supply Current
Bipolar Only
–2.45
–5.25
V
SS
I
I
f
= 600ksps
●
●
●
15
30
3.0
20.0
0.6
0.5
10
160
20
150
mA
mA
µA
mA
mA
µA
mW
mW
µW
CC
SAMPLE
Nap Mode
1.3
8.0
Sleep Mode
Negative Supply Current
Power Dissipation
f
= 600ksps, V = –5V
●
●
●
0.2
0.2
4
75
7.5
60
SS
SAMPLE
SS
Nap Mode
Sleep Mode
P
D
f
= 600ksps
●
●
●
SAMPLE
Nap Mode
Sleep Mode
U
U
The
●
denotes specifications which apply over the full operating temperature range, unless otherwise
A ALOG I PUT
noted specifications are at T = 25°C. V = 5V, f
= 600kHz, t = t = 5ns, unless otherwise specified.
r f
A
CC
SAMPLE
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Analog Input Range
4.75V ≤ V ≤ 5.25V (Unipolar)
0 to 4.096
0 to ±2.048
V
V
IN
CC
4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –2.45V (Bipolar)
CC
SS
I
Analog Input Leakage Current
Analog Input Capacitance
During Conversions (Hold Mode)
●
±1
µA
pF
pF
IN
C
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
45
5
IN
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LTC1404
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The
●
denotes specifications which apply over the full operating temperature
CO VERTER
CHARACTERISTICS
range, unless otherwise noted specifications are at T = 25°C. With internal reference V = 5V, f
otherwise specified (Note 6).
= 600kHz, t = t = 5ns, unless
A
CC
SAMPLE
r
f
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
12
(Note 7)
(Note 8)
±1
±1
±6
±8
LSB
LSB
LSB
LSB
●
●
Full-Scale Error
± 15
± 45
LSB
Full-Scale Tempco
I
= 0
± 10
ppm/°C
OUT(REF)
W
U
The
●
denotes specifications which apply over the full operating temperature range, unless
= 600kHz.
DY
A IC
ACCURACY
A
otherwise noted specifications are at T = 25°C. V = 5V, V = –5V, f
SAMPLE
CC
SS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise
100kHz Input Signal
300kHz Input Signal
●
●
●
69
72
72
dB
dB
THD
IMD
Total Harmonic Distortion
100kHz Input Signal
300kHz Input Signal
–82
–80
–76
–76
dB
dB
Up to 5th Harmonic
Peak Harmonic or
Spurious Noise
100kHz Input Signal
300kHz Input Signal
–84
–82
dB
dB
Intermodulation Distortion
f
f
= 99.17kHz, f = 102.69kHz
–82
–70
dB
dB
IN1
IN1
IN2
= 298.68kHz, f = 304.83kHz
IN2
Full Power Bandwidth
5
1
MHz
MHz
Full Linear Bandwidth (S/(N + D) ≥ 68dB)
U U
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I TER AL REFERE CE CHARACTERISTICS The
●
denotes specifications which apply over the full
operating temperature range, unless otherwise noted specifications are at T = 25°C. V = 5V, f
= 600kHz, t = t = 5ns, unless
r f
A
CC
SAMPLE
otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
2.430
±10
MAX
2.450
±45
UNITS
V
V
REF
V
REF
V
REF
Output Voltage
Output Tempco
Line Regulation
I
I
= 0
= 0
2.410
OUT
OUT
●
ppm/°C
4.75V ≤ V ≤ 5.25V
0.5
0.01
LSB/V
LSB/V
CC
–5.25V ≤ V ≤ 0V
SS
V
V
Load Regulation
0 ≤
⏐
I
⏐ ≤ 1mA
1
LSB/mA
ms
REF
OUT
Wake-Up Time from Sleep Mode
C
= 10µF
2.5
REF
VREF
U
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DIGITAL I PUTS AND OUTPUTS The
●
denotes specifications which apply over the full operating temperature
= 600kHz, t = t = 5ns, unless otherwise specified.
range, unless otherwise noted specifications are at T = 25°C. V = 5V, f
A
CC
SAMPLE
r
f
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.0
V
V
IH
IL
CC
CC
IN
0.8
I
± 10
µA
pF
IN
CC
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
= 4.75V, I = –10µA
= 4.75V, I = –200µA
= 4.75V, I = 160µA
= 4.75V, I = 1.6mA
4.7
V
V
OH
CC
CC
O
O
●
●
4.0
V
Low Level Output Voltage
V
V
0.05
0.10
V
V
OL
CC
CC
O
O
0.4
1404fa
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LTC1404
U
U
The
CC
●
denotes specifications which apply over the full operating temperature
= 600kHz, t = t = 5ns, unless otherwise specified.
DIGITAL I PUTS AND OUTPUTS
range, unless otherwise noted specifications are at T = 25°C. V = 5V, f
A
SAMPLE
r
f
SYMBOL PARAMETER
Hi-Z Output Leakage D
CONDITIONS
MIN
TYP
MAX
UNITS
µA
I
V
= 0V to V
●
± 10
OZ
OUT
OUT
CC
C
Hi-Z Output Capacitance D
Output Source Current
Output Sink Current
15
–10
10
pF
OZ
OUT
I
I
V
V
= 0V
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
W U
TI I G CHARACTERISTICS
The
CC
●
denotes specifications which apply over the full operating temperature range,
unless otherwise noted specifications are at T = 25°C. V = 5V, f
= 600kHz, t = t = 5ns, unless otherwise specified. See Figures
A
SAMPLE
r
f
12, 13, 14.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
f
t
t
Maximum Sampling Frequency
Conversion Time
●
600
SAMPLE(MAX)
CONV
f
= 9.6MHz
1.36
µs
CLK
Acquisition Time (Unipolar Mode)
(Bipolar Mode V = –5V)
200
160
ns
ns
ACQ
SS
f
t
t
t
t
t
t
t
t
t
CLK Frequency
●
●
0.1
40
9.6
MHz
ns
ns
ns
ns
ns
CLK
CLK Pulse Width
(Notes 5 and 10)
CLK
Time to Wake Up from Nap Mode
350
WK(NAP)
CLK Pulse Width to Return to Active Mode
CONV↑ to CLK↑Setup Time
●
●
●
●
40
70
0
1
2
3
4
5
6
7
CONV↑After Leading CLK↑
CONV Pulse Width
(Note 9)
40
ns
ns
ns
Time from CLK↑to Sample Mode
Aperture Delay of Sample-and-Hold
60
40
Jitter < 50ps
(Note 5)
Minimum Delay Between Conversion (Unipolar Mode)
(Bipolar Mode V = –5V)
●
●
220
180
310
300
ns
ns
SS
t
t
t
t
Delay Time, CLK↑ to D
Valid
Hi-Z
C
C
C
= 20pF
= 20pF
= 20pF
●
●
●
●
40
40
30
70
70
ns
ns
ns
ns
8
OUT
OUT
LOAD
LOAD
LOAD
Delay Time, CLK↑to D
9
Time from Previous Data Remains Valid After CLK↑
10
50
10
11
Minimum Time Between Nap/Sleep Request to Wake Up Request (Notes 5 and 10)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below V (ground for unipolar
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
SS
mode) or above V , they will be clamped by internal diodes. This product
CC
can handle input currents greater than 60mA without latch-up if the pin is
Note 9: The rising edge of CONV starts a conversion. If CONV returns low
at a bit decision point during the conversion, it can create small errors. For
best performance, ensure that CONV returns low either within 100ns after
the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
Note 10: If this timing specification is not met, the device may not respond
to a request for a conversion. To recover from this condition a NAP
request is required.
driven below V (ground for unipolar mode) or above V
.
CC
SS
Note 4: When these pin voltages are taken below V (ground for unipolar
SS
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA without latch-up if the pin is driven
below V (ground for unipolar mode). These pins are not clamped to V
.
CC
SS
Note 5: Guaranteed by design, not subject to test.
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LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Unipolar Mode Differential
Nonlinearity vs Output Code
Unipolar Mode Integral
Bipolar Mode Differential
Nonlinearity vs Output Code
Nonlinearity vs Output Code
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
f
= 600kHz
SAMPLE
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
0
–2048
–1024
1024
2048
2048 2560
2048 2560
0
512 1024 1536
3072 3584 4096
0
512 1024 1536
3072 3584 4096
1536
–1536
–512
512
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
1404 G02
1404 G01
1404 G03
Unipolar Mode 4096 Nonaverage
FFT with 100kHz Signal
Unipolar Mode 4096 Nonaverage
FFT with 300kHz Signal
Bipolar Mode Integral
Nonlinearity vs Output Code
0
–10
0
–10
1.00
0.75
0.50
0.25
0
–20
–20
–30
–30
–40
–40
–50
–50
–60
–70
–60
–70
–0.25
–0.50
–0.75
–1.00
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
–2048
–1024
1024
2048
0
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
0
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
1536
–1536
–512
512
OUTPUT CODE
1404 G04
1404 G05
1404 G06
Unipolar Mode
Unipolar Mode
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
Bipolar Mode
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
ENOB and Signal/(Noise +
Distortion) vs Input Frequency
74
68
62
56
50
12
11
10
9
80
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
NYQUIST
FREQUENCY
8
7
6
5
4
3
2
1
f
= 600kHz
SAMPLE
f
= 600kHz
f
= 600kHz
SAMPLE
SAMPLE
0
10
100
INPUT FREQUENCY (kHz)
1000
10
100
INPUT FREQUENCY (kHz)
1000
10
100
INPUT FREQUENCY (kHz)
1000
1404 G07
1404 G08
1404 G09
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LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Unipolar Mode
Unipolar Mode Intermodulation
Distortion Plot at 100kHz
Distortion vs Input Frequency
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
f
= 600kHz
SAMPLE
–10
–20
–30
–40
–50
–60
–70
2fa
–80
2ND HARMONIC
2fa – fb
–90
THD
–100
–110
–120
3RD HARMONIC
100
0
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
10
1000
INPUT FREQUENCY (kHz)
1404 G10
1404 G11
Unipolar Mode Intermodulation Distortion Plot at 300kHz
0
–10
fa
fb
–20
–30
–40
2fa + fb
3fa
–50
–60
–70
2fb – fa
2fa
fa + fb
2fb
3fb
–80
–90
–100
–110
–120
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
FREQUENCY (kHz)
1404 G12
Bipolar Mode Intermodulation Distortion Plot at 300kHz
0
–10
fa
–20
–30
–40
–50
–60
–70
fb – fa
–80
–90
–100
–110
–120
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
FREQUENCY (kHz)
1404 G12
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LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Unipolar Mode Peak Harmonic or
Spurious Noise vs Input Frequency
Bipolar Mode S/(N + D) vs Input
Frequency and Amplitude
Unipolar Mode S/(N + D) vs Input
Frequency and Amplitude
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
V
= 0dB
V
V
= 0dB
f
= 600kHz
IN
IN
IN
IN
SAMPLE
= –20dB
= –20dB
V
= –60dB
V
f
= –60dB
IN
IN
f
= 600kHz
= 600kHz
SAMPLE
SAMPLE
10
100
INPUT FREQUENCY (kHz)
1000
10
100
INPUT FREQUENCY (kHz)
1000
10
100
INPUT FREQUENCY (kHz)
1000
1404 G16
1404 G14
1404 G15
Bipolar Mode Power Supply
Feedthrough vs Ripple Frequency
Unipolar Mode Power Supply
Feedthrough vs Ripple Frequency
Bipolar Mode Peak Harmonic or
Spurious Noise vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0
A
A
f
= 0dB
A
A
f
= 0dB
f
= 600kHz
IN
IN
IN
IN
SAMPLE
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
FREQUENCY = 100kHz
= 600kHz
FREQUENCY = 100kHz
= 600kHz
SAMPLE
SAMPLE
V
(V = 1mV)
RIPPLE
CC
V
(V = 10mV)
RIPPLE
SS
V
(V
= 1mV)
RIPPLE
CC
10
100
INPUT FREQUENCY (kHz)
1000
1
10
100
1000
1
10
100
1000
RIPPLE FREQUENCY (kHz)
RIPPLE FREQUENCY (kHz)
1404 G19
1404 G18
1404 G17
Reference Voltage vs
Load Current
Acquisition Time vs
Source Impedance
Reference Voltage vs Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.440
2.438
2.436
2.434
2.432
2.430
2.428
2.426
2.424
2.422
2.420
2.45
2.44
2.43
2.42
2.41
2.40
2.39
T
= 25°C
A
10
100
1k
10k
–50 –25
0
25
50
75 100 125
–8 –7 –6 –5 –4 –3 –2 –1
LOAD CURRENT (mA)
0
1
TEMPERATURE (°C)
SOURCE RESISTANCE (Ω)
1404 G22
1404 G20
1404 G21
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LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Unipolar Mode V Supply Current
Bipolar Mode Supply Current
vs Temperature
CC
vs Temperature
15.0
12.5
10.0
7.5
5.0
2.5
0
300
250
200
150
100
50
20
15
10
5
V
CURRENT
CURRENT
CC
V
SS
f
= 600kHz
SAMPLE
f
= 600kHz
SAMPLE
0
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
1404 G23
1404 G24
U
U
U
PIN FUNCTIONS
CLK (Pin 6): Clock. This clock synchronizes the serial data
transfer. A minimum CLK pulse of 40ns signals the ADC to
wake up from Nap or Sleep mode.
VCC (Pin 1): Positive Supply, 5V. Bypass to GND (10µF
tantalum in parallel with 0.1µF ceramic).
AIN (Pin2):AnalogInput.0Vto4.096V(Unipolar),±2.048V
(Bipolar).
CONV (Pin 7): Conversion Start Signal. This active high
signal starts a conversion on its rising edge. Keeping CLK
lowandpulsingCONVtwo/fourtimeswillputtheADCinto
Nap/Sleep mode.
VREF (Pin 3): 2.43V Reference Output. Bypass to GND
(10µF tantalum in parallel with 0.1µF ceramic).
GND (Pin 4): Ground. GND should be tied directly to an
analog ground plane.
VSS (Pin 8): Negative Supply. –5V for bipolar operation.
Bypass to GND with 10µF tantalum in parallel with 0.1µF
ceramic. VSS shouldbetiedtoGNDforunipolaroperation.
DOUT (Pin5):TheA/Dconversionresultisshiftedoutfrom
this pin.
1404fa
8
LTC1404
U
U
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FUNCTIONAL BLOCK DIAGRA
C
ZEROING SWITCH
SAMPLE
V
CC
A
IN
GND
V
SS
V
REF
2.43V REF
12-BIT CAPACITIVE DAC
COMP
CLK
12
CONTROL
LOGIC
CONV
SUCCESSIVE APPROXIMATION
REGISTER/PARALLEL TO
SERIAL CONVERTER
D
OUT
1404 BD
TEST CIRCUITS
5V
3k
D
OUT
D
OUT
3k
C
LOAD
C
LOAD
Hi-Z TO V
OH
Hi-Z TO V
OL
V
OL
OH
TO V
OH
V
OH
OL
TO V
OL
V
TO Hi-Z
V
TO Hi-Z
1404 TC01
1404fa
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LTC1404
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APPLICATIONS INFORMATION
Conversion Details
Dynamic Performance
The LTC1404 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output based on a precision
internal reference. The control logic provides easy inter-
face to microprocessors and DSPs through 3-wire con-
nections.
The LTC1404 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
totesttheADC’sfrequencyresponse, distortionandnoise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2a shows a
typical LTC1404 FFT plot.
ArisingedgeontheCONVinputstartsaconversion. Atthe
start of a conversion the successive approximation regis-
ter (SAR) is reset. Once a conversion cycle has begun, it
cannot be restarted.
0
–10
–20
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquired phase and the comparator
offset is nulled by the feedback switch. In this acquire
phase, it typically takes 160ns for the sample-and-hold
capacitor to acquire the analog signal. During the convert
phase, the comparator feedback switch opens, putting the
comparator into the compare mode. The input switches
connect CSAMPLE to ground, injecting the analog input
charge onto the summing junction. This input charge is
successively compared with the binary-weighted charges
supplied by the capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
DAC output balances the AIN input charge. The SAR
contents (a 12-bit data word) which represent the input
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
1404 F02a
Figure 2a. LTC1404 Nonaveraged, 4096 Point FFT
Plot with 100kHz Input Frequency in Bipolar Mode
0
–10
–20
voltage, are presented through the serial pin DOUT
.
–30
–40
–50
SAMPLE
S1
–60
–70
–80
C
SAMPLE
DAC
SAMPLE
HOLD
–
+
–90
A
IN
–100
–110
–120
COMP
0
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
C
V
DAC
S
A
R
1404 F02b
DAC
Figure 2b. LTC1404 Nonaveraged, 4096 Point FFT
Plot with 300kHz Input Frequency in Bipolar Mode
D
OUT
1404 F01
Figure 1. A Input
IN
1404fa
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APPLICATIONS INFORMATION
Total Harmonic Distortion
Signal-to-Noise Ratio
Total harmonic distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is expressed as:
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from DC to half the sampling frequency.
Figure 2a shows a typical spectral content with a 600kHz
sampling rate and a 100kHz input. The dynamic perfor-
mance is excellent for input frequencies up to the Nyquist
limit of 300kHz as shown in Figure 2b.
2
2
2
2
V2 + V3 + V4 + …Vn
THD = 20log
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs input frequency is
shown in Figure 4. The LTC1404 has good distortion
performance up to the Nyquist frequency and beyond.
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the effective resolution of an ADC and is directly related to
the S/(N + D) by the equation:
S/ N + D – 1.76
(
)
0
N =
f
= 600kHz
SAMPLE
6.02
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 600kHz, the LTC1404 maintains very good ENOBs
up to the Nyquist input frequency of 300kHz (refer to
Figure 3).
THD
3RD HARMONIC
2ND HARMONIC
12
11
10
9
74
68
62
56
50
NYQUIST
FREQUENCY
10k
100k
INPUT FREQUENCY (Hz)
1M
1404 F04
8
7
Figure 4. Distortion vs Input Frequency in
Bipolar Mode
6
5
4
3
2
Intermodulation Distortion
1
f
= 600kHz
SAMPLE
0
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
10k
100k
1M
INPUT FREQUENCY (Hz)
1404 F03
Figure 3. Effective Bits and Signal-to-Noise +
Distortion vs Input Frequency in Bipolar Mode
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APPLICATIONS INFORMATION
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
Forexample, the2ndorderIMDtermsinclude(fa+fb)and
(fa – fb) while the 3rd order IMD terms includes (2fa + fb),
(2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine
wavesareequalinmagnitude,thevalue(indecibels)ofthe
2ndorderIMDproductscanbeexpressedbythefollowing
formula.
LTC1404 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far be-
yond Nyquist.
Driving the Analog Input
The analog input of the LTC1404 is easy to drive. It draws
only one small current spike while charging the sample-
and-hold capacitor at the end of a conversion. During
conversion, the analog input draws only a small leakage
current. The only requirement is that the amplifier driving
the analog input must settle after the small current spike
before the next conversion starts. Any op amp that settles
in 160ns to small load current transient will allow maxi-
mum speed operation. If a slower op amp is used, more
settling time can be provided by increasing the time
between conversions. Suitable devices capable of driving
the ADC’s AIN input include the LT®1360 and the LT1363
op amps.
Amplitude at (fa ± fb)
IMD fa ± fb = 20log
(
)
Amplitude at fa
Figure 5 shows the IMD performance at a 100kHz input.
0
–10
–20
–30
–40
–50
–60
–70
2fb + fa
–80
TheLTC1404comeswithabuilt-inunipolar/bipolardetec-
tion circuit. If the VSS potential is forced below GND, the
internalcircuitrywillautomaticallyswitchtobipolarmode.
–90
–100
–110
–120
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
The following list is a summary of the op amps that are
suitable for driving the LTC1404, more detailed informa-
tion is available in the Linear Technology databooks or the
Linear Technology Web site.
FREQUENCY (kHz)
1404 F05
Figure 5. Intermodulation Distortion Plot in Bipolar Mode
LT 1215/LT1216: Dual and quad 23MHz, 50V/µs single
supply op amps. Single 5V to ±15V supplies, 6.6mA
specifications, 90ns settling to 0.5LSB.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
LT1223: 100MHz video current feedback amplifier. ±5V
to±15V supplies, 6mA supply current. Low distortion up
to and above 600kHz. Low noise. Good for AC applica-
tions.
Full Power and Full Linear Bandwidth
LT1227: 140MHz video current feedback amplifier. ±5V
to ±15V supplies, 10mA supply current. Lowest distor-
tion at frequencies above 600kHz. Low noise. Best for AC
applications.
The full power bandwidth is the input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
1404fa
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LTC1404
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APPLICATIONS INFORMATION
5V
LT1229/LT1230:Dualandquad100MHzcurrentfeedback
amplifiers. ±2V to ±15V supplies, 6mA supply current
each amplifier. Low noise. Good AC specs.
INPUT RANGE ±4.215V
(= ±0.843 • V
V
CC
A
V
IN
)
REF
10V
LTC1404
V
IN
LT1360: 37MHz voltage feedback amplifier. ±5V to ±15V
supplies. 3.8mA supply current. Good AC and DC specs.
70ns settling to 0.5LSB.
V
REF
OUT
3Ω
10µF
LT1019A-5
GND
GND
LT1363:50MHz,450V/µsopamps.±5Vto±15Vsupplies.
6.3mA supply current. Good AC and DC specs. 60ns
settling to 0.5LSB.
V
SS
1404 F07
–5V
LT1364/LT1365:Dualandquad50MHz,450V/µsopamps.
±5Vto±15Vsupplies,6.3mAsupplycurrentperamplifier.
60ns settling to 0.5LSB.
Figure 7. Supplying a 5V Reference Voltage to the
LTC1404 with the LT1019A-5
Internal Reference
drift (equal to the maximum 5ppm/°C of the LT1019A-5)
and a ±4.215V full scale. If VREF is forced lower than
2.43V, the REFRDY bit in the serial data output will be
forced to low.
The LTC1404 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmedto2.43V. ItisinternallyconnectedtotheDACand
is available at Pin 3 to provide up to 1mA of current to an
external load. For minimum code transition noise, the
reference output should be decoupled with a capacitor to
filter wideband noise from the reference (10µF tantalum in
parallel with a 0.1µF ceramic). The VREF pin can be driven
with a DAC or other means to provide input span adjust-
ment in bipolar mode. The VREF pin must be driven to at
least 2.46V to prevent conflict with the internal reference.
The reference should not be driven to more than 5V.
Figure 6 shows an LT1360 op amp driving the reference
pin. Figure 7 shows a typical reference, the LT1019A-5
connected to the LTC1404. This will provide an improved
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT
Figure 8 shows the ideal input/output characteristics for
theLTC1404. Thecodetransitionsoccurmidwaybetween
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, … FS – 1.5LSB). The output code is straight
binary with 1LSB = 4.096V/4096 = 1mV. Figure 9 shows
the input/output transfer characteristics for the bipolar
mode in two’s complement format.
Unipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Figure
10a shows the extra components required for full-scale
error adjustment. Figure 10b shows offset and full-scale
adjustment. Offset error must be adjusted before full-
scaleerror.Zerooffsetisachievedbyapplying0.5mV(i.e.,
0.5LSB) at the input and adjusting the offset trim until the
LTC1404 output code flickers between 0000 0000 0000
and 0000 0000 0001. For zero full-scale error, apply an
analog input of 4.0945V (FS – 1.5LSB or last code transi-
tion) at the input and adjust R5 until the LTC1404 output
code flickers between 1111 1111 1110 and 1111 1111
1111.
5V
INPUT RANGE
V
CC
A
V
IN
±0.843 • V
REF(OUT)
+
LTC1404
REF
V
≥ 2.46V
3Ω
REF(OUT)
LT1360
–
10µF
GND
V
SS
1404 F06
–5V
Figure 6. Driving the V
with the LT1360 Op Amp
REF
1404fa
13
LTC1404
APPLICATIONS INFORMATION
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R1
FS
4.096
4096
ANALOG
INPUT
1LSB =
=
10k
111...111
111...110
111...101
111...100
4096
+
–
0V TO 4.096V
A
A1
IN
R2
10k
10k
R4
100k
5V
R9
20Ω
LTC1404
R5
4.3k
UNIPOLAR
ZERO
FULL-SCALE
ADJUST
000...011
000...010
000...001
000...000
5V
R3
R7
R8
10k
100k
100k
0V
1
LSB
OFFSET
ADJUST
FS – 1LSB
R6
400Ω
INPUT VOLTAGE (V)
1404 F08
1404 F10b
Figure 8. LTC1404 Unipolar Transfer Characteristics
Figure 10b. LTC1404 Offset and Full-Scale Adjust Circuit
R1
10k
ANALOG
INPUT
±2.048V
+
–
011...111
R2
10k
BIPOLAR
ZERO
011...110
A1
A
IN
R4
100k
000...001
000...000
111...111
111...110
LTC1404
R5
4.3k
FULL-SCALE
ADJUST
100...001
100...000
5V
R8
R3
R7
100k
100k
20k
OFFSET
ADJUST
–1 0V
1
R6
200Ω
–FS/2
FS/2 – 1LSB
LSB
LSB
–5V
INPUT VOLTAGE (V)
1404 F10c
1404 F09
Figure 9. LTC1404 Bipolar Transfer Characteristics
Figure 10c. LTC1404 Bipolar Offset and Full-Scale Adjust Circuit
R1
50Ω
+
V
IN
Bipolar Offset and Full-Scale Error Adjustments
A1
A
IN
Bipolaroffsetandfull-scaleerrorsareadjustedinasimilar
fashion to the unipolar case. Bipolar offset error adjust-
ment is achieved by applying an input voltage of –0.5mV
(–0.5LSB) to the input in Figure 10c and adjusting the op
ampuntiltheADCoutputcodeflickersbetween00000000
0000 and 1111 1111 1111. For full-scale adjustment, an
input voltage of 2.0465V (FS – 1.5LSBs) is applied to the
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111.
–
R4
R2
100Ω
10k
LTC1404
R3
10k
FULL-SCALE
ADJUST
GND
ADDITIONAL PINS OMITTED FOR CLARITY
1404 F10a
±20LSB TRIM RANGE
Figure 10a. LTC1404 Full-Scale Adjust Circuit
1404fa
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BOARD LAYOUT AND BYPASSING
Figure 11 shows the recommended system ground con-
nections. All analog circuitry grounds should be termi-
natedattheLTC1404GNDpin.Thegroundreturnfromthe
LTC1404 Pin 4 to the power supply should be low imped-
ance for noise free operation. Digital circuitry grounds
must be connected to the digital supply common. As an
alternative,insteadofadirectshortbetweenthedigitaland
analog circuitry, a 10Ω or a ferrite bead jumper helps
reduce the digital noise.
To obtain the best performance from the LTC1404, a
printed circuit board is required. Layout for the printed
circuit board should ensure that digital and analog signal
linesareseparatedasmuchaspossible. Inparticular, care
should be taken not to run any digital traces alongside an
analog signal trace or underneath the ADC. The analog
input should be screened by GND.
High quality 10µF surface mount AVX capacitor with a
0.1µF ceramic should be used at the VCC, VSS and VREF
pins.Forbetterresults,another10µFAVXcapacitorcanbe
added to the VCC pin. At 600ksps, the CLK frequency can
be as high as 9.6MHz. A poor quality capacitor can lose
more than 80% of its capacitance at this frequency range.
Therefore, it is important to consult the manufacturer’s
data sheet before the capacitor is used. For the LTC1404,
at 600ksps, every bit decision must be determined within
104ns (9.6MHz). During this short time interval, the
supply disturbance due to a CLK transition needs to settle.
The ADC must update its DAC, make a comparator deci-
sion based on sub-mV overdrive, latch the new DAC
information and output the serial data. This ADC provides
one power supply, VCC, which is connected to both the
internal analog and digital circuitry. Any ringing due to
poor supply or reference bypassing, inductive trace runs,
CLK and CONV over- or undershoot, or unnecessary DOUT
loading can cause ADC errors. Therefore, the bypass
capacitorsmustbelocatedasclosetothepinsaspossible.
The traces connecting the pins and the bypass capacitors
must be kept short and should be made as wide as
possible. In unipolar mode operation, VSS must be con-
nected to the GND pin directly.
ANALOG SUPPLY
GND
DIGITAL SUPPLY
–5V
5V
GND
5V
+
+
+
V
GND
V
GND
V
CC
SS
CC
LTC1404
DIGITAL CIRCUITRY
1404 F11
Figure 11. Power Supply Connection
In applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
Input signal leads to AIN and signal return leads from GND
(Pin 4) should be kept as short as possible to minimize
noise coupling. In applications where this is not possible,
a shielded cable between the analog input signal and the
ADC is recommended. Also, any potential difference in
grounds between the analog signal and the ADC appears
as an error voltage in series with the analog input signal.
Attention should be paid to reducing the ground circuit
impedance as much as possible.
Power-Down Mode
Upon power-up, the LTC1404 is initialized to the active
stateandisreadyforconversion.However,thechipcanbe
easily placed into Nap or Sleep mode by exercising the
right combination of CLK and CONV signals. In Nap mode,
all power is off except for the internal reference, which is
still active and provides 2.43V output voltage to the other
circuitry. In this mode, the ADC draws only 7.5mW of
power instead of 75mW (for minimum power, the logic
1404fa
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LTC1404
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APPLICATIONS INFORMATION
version will result in an all-zero output code, including the
REFRDY bit. If no conversion is attempted, the DOUT pin
remains in a high impedance state. If the ADC wakes from
Sleep mode, this can be determined by monitoring the
state of the REFRDY bit at the DOUT pin.
inputs must be within 500mV of the supply rails). In Sleep
mode, power consumption is reduced to 60µW by cutting
off power to all internal circuitry including the reference.
Figure 12 illustrates power-down modes for the LTC1404.
The chip enters Nap mode by keeping the CLK signal low
and pulsing the CONV signal twice. For Sleep mode
operation, the CONV signal should be pulsed four times
while CLK is kept low. Nap and Sleep modes are activated
on the falling edge of the CONV pulse.
DIGITAL INTERFACE
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the DOUT output provides
the conversion result in serial form.
The LTC1404 returns to active mode easily. The rising
edge of CLK wakes up the LTC1404. From Nap mode,
wake-up occurs within 350ns. During the transition from
Sleepmodetoactivemode,theVREF voltageramp-uptime
is a function of its loading conditions. With a 10µF bypass
capacitor, the wake-up time from Sleep mode is typically
2.5ms. A REFRDY signal is activated once the reference
has settled and is ready for an A/D conversion. This
REFRDY bit is sent to the DOUT pin as the first bit followed
by the 12-bit data word (refer to Figure 13). To save power
during wake-up from Sleep mode, the chip is designed to
enter Nap mode automatically until the reference is ready.
Once REFRDY goes high, the comparator powers up
immediately and is ready for a conversion. During the Nap
interval, any attempt to perform an analog-to-digital con-
Figure13showsthedigitaltimingdiagramoftheLTC1404
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t2, the digital output will be
delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. The digital output data consists of a REFRDY bit
followed by a valid 12-bit data word. DOUT data should be
captured by the receiving system on the rising CLK edge.
Data remains valid for a minimum time of t10 after the
rising CLK edge to allow capture to occur.
t
t
1
1
CLK
t
t
11
11
CONV
NAP
SLEEP
V
REF
REFRDY
REFRDY = 1
REFRDY = 0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ALL ZERO
1
0
1
11 10
D
OUT
REFRDY BIT+12-BIT
DATA WORD
REFRDY BIT
+12-BIT
DATA WORD
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS.
REFRDY APPEARS AS THE FIRST BIT IN THE D
WORD
OUT
1404 F12
Figure 12. Nap Mode and Sleep Mode Waveforms
1404fa
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APPLICATIONS INFORMATION
t
2
t
7
t
3
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
1
2
14
CLK
t
4
t
5
CONV
t
6
t
ACQ
INTERNAL
S/H STATUS
SAMPLE
HOLD
SAMPLE
HOLD
t
8
Hi-Z
Hi-Z
D
OUT
REFRDY D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
REFRDY
REFRDY BIT + 12-BIT DATA WORD
t
CONV
1404 F13
t
SAMPLE
Figure 13. ADC Digital Timing Diagram
CLK
CLK
V
V
IH
IH
t
8
t
9
t
10
V
V
90%
10%
OH
OL
D
D
OUT
OUT
1404 F14
Figure 14. CLK to D
Delay
OUT
1404fa
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LTC1404
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TYPICAL APPLICATIONS
Hardware Interface to the TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX)
7.8MHz
TMS320C50-40MHZ
EXTERNAL CLOCK
5V
TCLKX
TCLKR
TFSX
1
2
6
V
A
CLK
CC
7
UNIPOLAR
INPUT
+
CONV
TFSR
IN
0.1µF
10µF
LTC1404
5
3
TDR
V
V
D
REF
OUT
+
GND
4
SS
8
0.1µF
10µF
1404 TA04a
Logic Analyzer Waveforms Show 2.05µs Throughput Rate (Input Voltage = 1.606V, Output Code = 0110 0100 0110 = 1606 )
10
1404T A04B
NOTE: THE TMS320C50-40MHz HAS A LIMITED SERIAL PORT CLOCK SPEED OF 7.8MHz. TO ALLOW THE LTC1404 TO RUN AT
ITS MAXIMUM SPEED OF 9.6MHz, THE TMS320C50-57 OR TMS320C50-80MHz IS NEEDED
Data from the LTC1404 Loaded into the TMS320C50’s TRCV Register
X
D10 D9
D7 D6 D5 D4 D3
D2
D1 D0
X
X
RDY D11
D8
1404 TA04c
Data Stored in the TMS320C50’s Memory (in Right Justified Format)
0
RDY D11 D9 D8 D7 D6 D5
D10
D4
D3 D2 D1 D0
0
0
1404 TA04d
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18
LTC1404
U
TYPICAL APPLICATIONS
TMS320C50 Code for Circuit
THIS PROGRAM DEMONSTRATES THE LTC1404 INTERFACE TO THE
TMS320C50. FRAME SYNC PULSE IS GENERATED FROM TFSX.
DATA SHIFT CLOCK IS EXTERNALLY GENERATED.
*Start Serial Communication*
SACL TDXR
SPLK #040h, IMR
CLRC INTM
; Generate frame sync pulse
; Turn on TRNT receiver interrupt
; Enable interrupt
*Initialization*
CLRC SXM
; For Unipolar input, set for right shift
.mmregs
; Defines global symbolic names
; with no sign extension
;- - Initialized data memory to zero
MAR *, AR7
LAR AR7, #0F00h
; Load the auxiliary register pointer with seven
.ds
0F00h
; Initialize data to zero
; Load the auxiliary register seven with #0F00h
DATA0 .word
DATA1 .word
DATA2 .word
DATA3 .word
DATA4 .word
DATA5 .word
0
0
0
0
0
0
; Begin sample data location
; as the begin address for data storage
; .
WAIT:
NOP
NOP
; Wait for a receive interrupt
; Location of data
;
;
; .
; .
NOP
SACL TDXR
B
; !! Regenerate the frame sync pulse
;
; End sample data location
WAIT
;- - Set up the ISR vector
; - - - - - - - end of main program - - - - - - - - - - ;
.ps
B
080Ah
; Serial ports interrupts
rint :
xint :
trnt :
txnt :
RECEIVE
TRANSMIT
TREC
; 0A;
; 0C;
; 0E;
; 10;
*Receiver Interrupt Service Routine*
TREC:
B
B
B
LAMM TRCV
SFR
; Load the data received from LTC1404
TTRANX
; Shift right two times
;- - Setup the reset vector
.ps 0A00h
.entry
START:
SFR
;
AND #1FFFh, 0
; ANDed with #1FFFh
; For converting the data to right
; justified format
;
*TMS320C50 Initialization*
SETC INTM
SACL *+, 0
; Write to data memory pointed by AR7 and
; increase the memory address by one
;
; Temporarily disable all interrupts
; Set data page pointer to zero
LDP #0
LACC AR7
SUB #0F05h,0
OPL #0834h, PMST ; Set up the PMST status and control register
LACC #0
; Compare to end sample address #0F05h
BCND END_TRCV, GEQ ; If the end sample address has exceeded jump
SAMMCWSR
SAMMPDWSR
; Set software wait state to 0
;
to END_TRCV
;
; Else Re-enable the TRNT receive interrupt
; Return to main program and enable interrupt
*Configure Serial Port*
SPLK #040h, IMR
RETE
SPLK #0028h, TSPC ; Set TDM Serial Port
; TDM = 0 Stand Alone mode
*After Obtained the Data from LTC1404, Program Jump to END_TRCV*
END_TRCV:
; DLB=0 Not loop back
; FO=0 16 Bits
SPLK #002h, IMR
CLRC INTM
; Enable INT2 for program to halt
; FSM=1 Burst Mode
; MCM=0 CLKR is generated externally
; TXM=1 FSX as output pin
; Put serial port into reset
SUCCESS:
B
SUCCESS
; (XRST=RRST=0)
*Fill the Unused Interrupt with RETE, to avoid program get “lost”*
SPLK #00E8h, TSPC ; Take Serial Port out of reset
; (XRST=RRST=1)
TTRANX:
RETE
RECEIVE:
RETE
TRANSMIT:
RETE
SPLK #0FFFFh, IFR
; Clear all the pending interrupts
INT2:
B halt
; Halts the running CPU
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19
LTC1404
TYPICAL APPLICATIONS
U
LTC1404 Interface to the ADSP2181’s SPORT0 (Frame Sync is Generated from RFS0)
9.6MHz
EXTERNAL CLOCK
ADSP2181
SCLKO
5V
1
2
6
7
CLK
V
A
CC
IN
UNIPOLAR
INPUT
+
CONV
RFSO
DR0
10µF
0.1µF
LTC1404
3
5
V
V
D
REF
OUT
+
GND
SS
8
0.1µF
10µF
4
1404 TA05a
Logic Analyzer Waveforms Show 1.67µs Throughput Rate (Input Voltage = 1.604V, Output Code = 0110 0100 0100 = 1604 )
10
1404 TA05b
NOTE: WITHOUT THE EXTERNAL CLOCKING SIGNAL, THE ADSP2181 SCLK0 CAN BE PROGRAMMED TO RUN AT 8.3MHz
Data from the LTC1404 (Normal Mode)
X
D10 D9
D7 D6 D5 D4 D3
D2
D1 D0
X
X
RDY D11
D8
1404 TA05c
Data Stored in the ADSP2181’s Memory (Normal Mode, SLEN = D)
0
RDY D11
D10
D9 D8 D7 D6 D5
D4
D3 D2 D1
D0
0
0
1404 TA05d
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20
LTC1404
U
TYPICAL APPLICATIONS
ADSP2181 Code for Circuit
THIS PROGRAM DEMONSTRATES THE LTC1404 INTERFACE TO
THE ADSP-2181. FRAME SYNC PULSE IS GENERATED FROM RFS.
DATA SHIFT CLOCK IS EXTERNALLY GENERATED.
/*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/
/*Using an external clock source=9.6MHz*/
/*Does not need to configure CLKDIV*/
/*to Configure RFSDIV*/
/*Section 1: Initialization*/
ax0 = 15;
/*set the RFSDIV reg = 15*/
/*=> the frame sync pulse for every 16 SCLK*/
/*if frame sync pulse in every 15 SCLK, ax0=14*/
.module/ram/abs = 0 adspltc; /*define the program module*/
jump start;
/*jump over interrupt vectors*/
nop; nop; nop;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
ax0 = rx0;
dm(0x3FF4) =ax0;
/*to setup interrupt*/
ifc= 0x0066;
/*code vectors here upon IRQ2 int*/
/*code vectors here upon IRQL1 int*/
/*code vectors here upon IRQL0 int*/
/*code vectors here upon SPORT0 TX int*/
/*Section 5*/
/*clear any extraneous SPORT interrupts*/
/*IRQXB = level sensitivity*/
icntl= 0;
/*disable nesting interrupt*/
imask= 0x0020;
/*bit 0 = timer int = 0*/
dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/
/*bit 1 = SPORT1 or IRQ0B int = 0*/
/*bit 2 = SPORT1 or IRQ1B int = 0*/
/*bit 3 = BDMA int = 0*/
rti;
/* */
/* */
/*end of SPORT0 receive interrupt*/
/*code vectors here upon /IRQE int*/
/*code vectors here upon BDMA interrupt*/
/*code vectors here upon SPORT1 TX (IRQ1) int*/
/*code vectors here upon SPORT1 RX (IRQ0) int*/
/*code vectors here upon TIMER int*/
/*code vectors here upon POWER DOWN int*/
/*bit 4 = IRQEB int = 0*/
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
/*bit 5 = SPORT0 receive int = 1*/
/*bit 6 = SPORT0 transmit int = 0*/
/*bit 7 = IRQ2B int = 0*/
/*enable SPORT0 receive interrupt*/
/*Section 4: Configure System Control Register and Start Communication*/
/*to configure system control reg*/
/*Section 2: Configure SPORT0*/
start:
/*to configure SPORT0 control reg*/
ax0 = dm(0x3FFF);
ay0 = 0xFFF0;
/*read the system control reg*/
ar = ax0 AND ay0;
ay0 = 0x1000;
/*set wait state to zero*/
/*SPORT0 address = 0X3FF6*/
/*RFS is used for frame sync generation*/
/*RFS is internal, TFS is not used*/
/*bit 0-3 = Slen*/
ar = ar OR ay0;
dm(0x3FFF) = ar;
/*bit 12 = 1, enable SPORT0*/
/*frame sync pulse regenerated automatically*/
/*F = 15 = 1111*/
cntr = 5000;
/*E = 14 = 1110*/
do waitloop until ce;
/*D = 13 = 1101*/
nop;
nop;
/*bit 4,5 data type right justified zero filled MSB*/
/*bit 6 INVRFS = 0*/
nop;
/*bit 7 INVTFS = 0*/
nop;
/*bit 8 IRFS=1 receive internal frame sync*/
/*bit 9,10,11 are for TFS (don’t care)*/
/*bit 12 RFSW=0 receive is Normal mode*/
/*bit 13 RTFS=1 receive is framed mode*/
/*bit 14 ISCLK=0 SCLK is external */
/*bit 15 multichannel mode = 0*/
/*normal mode, bit 12=0*/
nop;
nop;
waitloop: nop;
rts;
.endmod;
ax0 = 0x2F0D;
/*if alternate mode bit 12=1, ax0=0x3F0E*/
dm (0x3FF6) =ax0;
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21
LTC1404
TYPICAL APPLICATIONS
U
Quick Look Circuit for Converting Data to Parallel Format
5V
1
8
V
V
CC
SS
5V
+
CONV
10µF
0.1µF
10
SRCLR
LTC1404
7
6
5
12
11
14
13
15
1
2
3
4
5
6
7
9
CONV
CLK
QA
QB
QC
QD
QE
RCK
D0
D1
D2
D3
D4
D5
D6
D7
ANALOG INPUT
(0V TO 4.096V)
2
3
A
V
IN
2.43V
REFERENCE
OUTPUT
SRCK
74HC595
REF
+
4
GND
D
OUT
SER
10µF
0.1µF
QF
G
QG
QH
QH'
3-WIRE SERIAL
INTERFACE LINK
10
SRCLR
12
11
14
13
15
1
2
3
4
5
6
7
9
RCK
QA
QB
QC
QD
QE
D8
D9
D10
D11
REFRDY
SRCK
74HC595
CLK
SER
QF
G
QG
QH
QH'
1404 TA03
1404fa
22
LTC1404
U
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 ±.005
.160 ±.005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
1404fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1404
TYPICAL APPLICATIONS
U
LTC1404 Interface to TMS320C50 Running at 5MHz without External Clock
TMS320C50
5V
TCLKX
TCLKR
TFSX
1
2
6
7
V
A
CLK
CC
UNIPOLAR
INPUT
+
CONV
LTC1404
TFSR
IN
0.1µF
10µF
5
3
TDR
V
V
D
OUT
REF
+
GND
4
SS
8
0.1µF
10µF
1404 TA07
LTC1404 Interface to ADSP2181 Running at 8.3MHz without External Clock
ADSP2181
5V
1
2
6
7
SCLKO
CLK
V
A
CC
IN
(8.3MHz)
UNIPOLAR
INPUT
+
CONV
LTC1404
RFSO
10µF
0.1µF
3
5
DR0
V
V
D
REF
OUT
+
GND
SS
8
0.1µF
10µF
4
1404 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1285/LTC1288
LTC1286/LTC1298
LTC1290
12-Bit, 3V, 7.5/6.6ksps, Micropower Serial ADCs
0.48mW, 1-/2-Channel Input, SO-8
12-Bit, 5V, 12.5/11.16ksps, Micropower Serial ADCs
12-Bit, 50ksps 8-Channel Serial ADC
12-Bit, 46.5ksps 8-Channel Serial ADC
12-/14-Bit 2.8Msps Serial ADCs
1.25mW, 1-/2-Channel Input, SO-8
5V or ±5V Input Range, 30mW, Full-Duplex
5V or ±5V Input Range, 30mW, Half-Duplex
3V, 15mW, MSOP-10 Package, Unipolar Input
3V, 15mW, MSOP-10 Package, Bipolar Input
3V, 14mW, 2-Channel Unipolar Differential Inputs, MSOP-10
3V, 14mW, 2-Channel Bipolar Differential Inputs, MSOP-10
5V or ±5V, 20mW, Internal Reference, SSOP-16
5V, Configurable Bipolar or Unipolar Inputs to ±10V
1.22mW, 1-/2-Channel Input, MSOP-8 and SO-8
4.25mW, 1-/2-Channel Input, MSOP-8 and SO-8
1.22mW, 1-/2-Channel Input, MSOP-8 and SO-8
4.25mW, 1-/2-Channel Input, MSOP-8 and SO-8
LTC1296
LTC1403/LTC1403A
LTC1403-1/LTC1403A-1
LTC1407/LTC1407A
LTC1407-1/LTC1407A-1
LTC1417
12-/14-Bit, 2.8Msps Serial ADCs
12-/14-Bit, 3Msps Simultaneous Sampling ADCs
12-/14-Bit, 3Msps Simultaneous Sampling ADCs
14-Bit, 400ksps Serial ADC
LTC1609
16-Bit, 200ksps Serial ADC
LTC1860L/LTC1861L
LTC1860/LTC1861
LTC1864L/LTC1865L
LTC1864/LTC1865
12-Bit, 3V, 150ksps Serial ADCs
12-Bit, 5V, 250ksps Serial ADCs
16-Bit, 3V, 150ksps Serial ADCs
16-Bit, 5V, 250ksps Serial ADCs
1404fa
LT 0506 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
© LINEAR TECHNOLOGY CORPORATION 1998
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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