LTC1407-1_15_技术文档

LT1375/LT1376

1.5A, 500kHz Step-Down

Switching Regulators

FEATURES

■

Constant 500kHz Switching Frequency

is current mode for fast transient response and good loop

stability.Bothfixedoutputvoltageandadjustablepartsare

available.

Uses All Surface Mount Components

Inductor Size Reduced to 5µH

Easily Synchronizable

A special high speed bipolar process and new design

techniques achieve high efficiency at high switching fre-

quency. Efficiency is maintained over a wide output cur-

rent range by using the output to bias the circuitry and by

utilizing a supply boost capacitor to saturate the power

switch. A shutdown signal will reduce supply current to

20µA on both parts. The LT1375 can be externally syn-

chronized from 580kHz to 900kHz with logic level inputs.

Saturating Switch Design: 0.4Ω

Effective Supply Current: 2.5mA

Shutdown Current: 20µA

Cycle-by-Cycle Current Limiting

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APPLICATIO S

■

Portable Computers

Battery-Powered Systems

Battery Charger

The LT1375/LT1376 fit into standard 8-pin PDIP and SO

packages, as well as a fused lead 16-pin SO with much

lower thermal resistance. Full cycle-by-cycle short-cir-

cuit protection and thermal shutdown are provided.

Standard surface mount external parts are used, includ-

ing the inductor and capacitors.

Distributed Power

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DESCRIPTIO

The LT^®1375/LT1376 are 500kHz monolithic buck mode

switching regulators. A 1.5A switch is included on the die

along with all the necessary oscillator, control and logic

circuitry. High switching frequency allows a considerable

reductioninthesizeofexternalcomponents.Thetopology

For low input voltage applications with 3.3V output, see

LT1507. This is a functionally identical part that can

operate with input voltages between 4.5V and 12V.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

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TYPICAL APPLICATIO

5V Buck Converter

Efficiency vs Load Current

D2

1N914

100

V

= 5V

OUT

IN

= 10V

C2

L = 10µH

90

80

70

60

50

0.1µF

BOOST

INPUT

OUTPUT**

5V, 1.25A

V

†

SW

IN

6V TO 25V

L1**

5µH

+

C3*

10µF TO

50µF

BIAS

FB

LT1376-5

DEFAULT

= ON

SHDN

GND

V

C1

C

+

100µF, 10V

SOLID

D2

1N5818

C

3.3nF

TANTALUM

* RIPPLE CURRENT ≥ I /2

OUT

0

0.25

0.50

0.75

1.00

1.25

** INCREASE L1 TO 10µH FOR LOAD CURRENTS ABOVE 0.6A AND TO 20µH ABOVE 1A

†

LOAD CURRENT (A)

FOR INPUT VOLTAGE BELOW 7.5V, SOME RESTRICTIONS MAY APPLY.

1375/76 TA01

SEE APPLICATIONS INFORMATION.

1375/76 TA02

13756fd

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LT1375/LT1376

W W

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ABSOLUTE MAXIMUM RATINGS _{(Note 1)}

FB Pin Current (Adjustable Part)............................ 1mA

Sense Voltage (Fixed 5V Part) .................................. 7V

SYNC Pin Voltage ..................................................... 7V

Operating Junction Temperature Range

LT1375C/LT1376C ............................... 0°C to 125° C

LT1375I/LT1376I............................. –40°C to 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

Input Voltage

LT1375/LT1376 .................................................. 25V

LT1375HV/LT1376HV ........................................ 30V

BOOST Pin Voltage

LT1375/LT1376 .................................................. 35V

LT1375HV/LT1376HV ........................................ 40V

SHDN Pin Voltage..................................................... 7V

BIAS Pin Voltage ...................................................... 7V

FB Pin Voltage (Adjustable Part)............................ 3.5V

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PACKAGE/ORDER INFORMATION

TOP VIEW

BOOST

1

2

3

4

8

7

6

5

V

C

BOOST

1

2

3

4

8

7

6

5

V

C

GND

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

NC

V

IN

FB/SENSE

GND

V

IN

FB/SENSE

GND

V

SW

BOOST

V

C

V

SW

V

IN

FB/SENSE

GND

SHDN

SYNC

BIAS

SHDN

V

SW

N8 PACKAGE

8-LEAD PDIP

S8 PACKAGE

8-LEAD PLASTIC SO

N8 PACKAGE

8-LEAD PDIP

S8 PACKAGE

8-LEAD PLASTIC SO

BIAS

NC

SHDN

NC

θ

_JA= 100°C/ W (N8)

θ

_JA= 100°C/ W (N8)

_JA= 120°C/ W TO 150°C/W DEPENDING ON

GND

PC BOARD LAYOUT (S8)

S PACKAGE

ORDER PART

NUMBER

S8 PART

MARKING

ORDER PART

NUMBER

S8 PART

MARKING

16-LEAD PLASTIC NARROW SO

θ

_JA= 50°C/ W WITH FUSED CORNER PINS

CONNECTED TO GROUND PLANE OR LARGE

LANDS

LT1375CN8

LT1375CN8-5

LT1375IN8

LT1376CN8

LT1376CN8-5

LT1376IN8

ORDER PART NUMBER

LT1375IN8-5

LT1375CS8

LT1375CS8-5

LT1375HVCS8

LT1375IS8

LT1375IS8-5

LT1375HVIS8

LT1376IN8-5

LT1376CS8

LT1376CS8-5

LT1376HVCS8

LT1376IS8

LT1376IS8-5

LT1376HVIS8

LT1376CS

1375

1376

LT1376IS

13755

1375HV

1375I

13765

1376HV

1376I

LT1376HVCS

LT1376HVIS

1375I5

375HVI

1376I5

376HVI

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

13756fd

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LT1375/LT1376

ELECTRICAL CHARACTERISTICS ^The

unless otherwise noted.

●

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. T = 25°C, V = 15V, V = 1.5V, boost open, switch open,

A

J

IN

C

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Reference Voltage (Adjustable)

2.39

2.36

2.42

2.45

2.48

V

●

Sense Voltage (Fixed 5V)

4.94

4.90

5.0

10

5.06

5.10

V

Sense Pin Resistance

7

14

kΩ

Reference Voltage Line Regulation

5V ≤ V ≤ 25V

0.01

0.03

%/V

IN

5V ≤ V ≤ 30V (LT1375HV/LT1376HV)

IN

Feedback Input Bias Current

Error Amplifier Voltage Gain

Error Amplifier Transconductance

●

0.5

400

1.5

µA

V

= 1V (Notes 2, 8)

200

SHDN

= 1V, ∆I (V ) = ± 10µA (Note 8)

1500

1100

2000

2700

3000

µMho

SHDN

C

●

V Pin to Switch Current Transconductance

C

2

225

2

A/V

µA

mA

V

Error Amplifier Source Current

Error Amplifier Sink Current

V

= 1V, V = 2.1V or V

= 4.4V

= 5.6V

150

320

SHDN

FB

SENSE

= 1V, V = 2.7V or V

SHDN

FB

V Pin Switching Threshold

C

Duty Cycle = 0

= 1V

0.9

2.1

V Pin High Clamp

C

V

SHDN

V

Switch Current Limit

V Open, V = 2.1V or V

= 4.4V,

C

FB

SENSE

V

= V + 5V

DC ≤ 50%

DC = 80%

●

1.50

1.35

2

3

A

BOOST

IN

Switch On Resistance (Note 7)

I

= 1.5A, V

= V + 5V

0.3

0.4

0.5

Ω

SW

BOOST

IN

●

Maximum Switch Duty Cycle

Switch Frequency

V

= 2.1V or V

= 4.4V

SENSE

86

93

%

FB

V Set to Give 50% Duty Cycle

460

440

500

540

560

570

kHz

C

0°C ≤ T ≤ 125°C

J

●

Switch Frequency Line Regulation

5V ≤ V ≤ 25V

●

0.05

0.15

%/V

IN

5V ≤ V ≤ 30V (LT1375HV/LT1376HV)

IN

Frequency Shifting Threshold on FB Pin

Minimum Input Voltage (Note 3)

Minimum Boost Voltage (Note 4)

Boost Current (Note 5)

∆f = 10kHz

●

0.8

1.0

5.0

3

1.3

5.5

3.5

V

I

≤ 1.5A

SW

V

= V + 5V

I = 500mA

SW

●

12

25

22

35

mA

BOOST

IN

I

= 1.5A

SW

Input Supply Current (Note 6)

Output Supply Current (Note 6)

Shutdown Supply Current

V

BIAS

V

BIAS

V

SHDN

= 5V

●

0.9

3.2

15

1.4

4.0

mA

= 5V

= 0V, V ≤ 25V, V = 0V, V Open

50

75

µA

IN

SW

C

●

V

= 0V, V ≤ 30V, V = 0V, V Open

IN SW C

SHDN

(LT1375HV/LT1376HV)

20

75

100

µA

●

Lockout Threshold

V Open

C

2.3

2.38

2.46

V

13756fd

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LT1375/LT1376

ELECTRICAL CHARACTERISTICS

unless otherwise noted.

The

●

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. T = 25°C, V = 15V, V = 1.5V, boost open, switch open,

A

J

IN

C

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Shutdown Thresholds

V Open

C

Device Shutting Down

Device Starting Up

●

0.15

0.25

0.37

0.45

0.60

V

V Open

C

LT1375HV/LT1376HV Device Shutting Down

LT1375HV/LT1376HV Device Starting Up

●

0.15

0.25

0.37

0.45

0.70

V

Minimum Synchronizing Amplitude (LT1375 Only)

Synchronizing Range (LT1375 Only)

SYNC Pin Input Resistance

V

IN

= 5V

●

1.5

40

2.2

V

kHz

kΩ

580

900

5V. Total input referred supply current is calculated by summing input

supply current (I ) with a fraction of output supply current (I ):

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

SI

SO

I

= I + (I )(V /V )(1.15)

SI SO OUT IN

TOT

With V = 15V, V

= 5V, I = 0.9mA, I = 3.6mA, I = 2.28mA.

TOT

IN

OUT

SI

SO

Note 2: Gain is measured with a V swing equal to 200mV above the low

C

For the LT1375, quiescent current is equal to:

= I + I (1.15)

clamp level to 200mV below the upper clamp level.

I

TOT

SI

SO

Note 3: Minimum input voltage is not measured directly, but is guaranteed

by other tests. It is defined as the voltage where internal bias lines are still

regulated so that the reference voltage and oscillator frequency remain

constant. Actual minimum input voltage to maintain a regulated output will

depend on output voltage and load current. See Applications Information.

Note 4: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 5: Boost current is the current flowing into the BOOST pin with the

pin held 5V above input voltage. It flows only during switch-on time.

Note 6: Input supply current is the bias current drawn by the input pin

when the BIAS pin is held at 5V with switching disabled. Output supply

current is the current drawn by the BIAS pin when the bias pin is held at

because the BIAS pin is internally connected to V .

IN

For LT1375 or BIAS open circuit, input supply current is the sum of input

+ output supply currents.

Note 7: Switch-on resistance is calculated by dividing V to V voltage

IN

SW

by the forced current (1.5A). See Typical Performance Characteristics for

the graph of switch voltage at other currents.

Note 8: Transconductance and voltage gain refer to the internal amplifier

exclusive of the voltage divider. To calculate gain and transconductance

refer to sense pin on fixed voltage parts. Divide values shown by the ratio

V

OUT

/2.42.

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TYPICAL PERFORMANCE CHARACTERISTICS

Inductor Core Loss

Feedback Pin Voltage and Current

Switch Peak Current Limit

2.5

2.0

1.5

1.0

0.5

0

2.44

2.43

2.42

2.41

2.40

2.0

1.5

1.0

0.5

0

1.0

20

12

8

V

= 5V, V = 10V, I

= 1A

OUT

IN

OUT

TYPICAL

4

2

1.2

0.8

TYPE 52

POWDERED IRON

0.1

GUARANTEED MINIMUM

Kool Mµ^®

VOLTAGE

CURRENT

0.4

PERMALLOY

µ = 125

0.2

0.01

0.001

CORE LOSS IS

INDEPENDENT OF LOAD

CURRENT UNTIL LOAD CURRENT FALLS

LOW ENOUGH FOR CIRCUIT TO GO INTO

DISCONTINUOUS MODE

0.12

0.08

0.04

0.02

0

20

40

60

80

100

–50 –25

0

25

50

75

100 125

0

5

10

15

20

25

INDUCTANCE (µH)

DUTY CYCLE (%)

JUNCTION TEMPERATURE (°C)

1375/76 G08

1375/76 G09

1375/76 G01

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LT1375/LT1376

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TYPICAL PERFORMANCE CHARACTERISTICS

Standby and Shutdown Thresholds

Shutdown Pin Bias Current

Shutdown Supply Current

30

25

20

15

10

5

500

400

300

200

8

2.40

2.36

2.32

0.8

0.4

0

V

= 0V

SHUTDOWN

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

CURRENT DROPS TO A FEW µA

STANDBY

START-UP

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

4

SHUTDOWN

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

50

75

100 125

0

5

10

15

20

25

–50 –25

0

25

75

INPUT VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

1375/76 G04

1375/76 G05

1375/76 G06

Shutdown Supply Current

Error Amplifier Transconductance

2500

2000

1500

1000

500

150

125

100

75

3000

2500

2000

1500

1000

500

200

PHASE

GAIN

150

100

50

V

= 25V

IN

V

C

OUT

12pF

R

OUT

200k

–3

V

FB

2 •10

(

)

V

= 10V

50

IN

ERROR AMPLIFIER EQUIVALENT CIRCUIT

= 50Ω

0

25

R

LOAD

0

–50

0

–50

0

25

50

75 100 125

100

1k

10k

100k

1M

10M

0

0.1

0.2

0.3

0.4

0.5

–25

SHUTDOWN VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

FREQUENCY (Hz)

1375/76 G03

1375/76 G07

1375/76 G02

LT1376 Minimum Input Voltage

with 5V Output

Frequency Foldback

Switching Frequency

500

400

300

200

100

0

600

550

500

450

400

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

MINIMUM INPUT VOLTAGE CAN BE

REDUCED BY ADDING A SMALL EXTERNAL

PNP. SEE APPLICATIONS INFORMATION

SWITCHING

FREQUENCY

MINIMUM

VOLTAGE TO

START WITH

STANDARD

CIRCUIT

MINIMUM VOLTAGE

TO RUN WITH

STANDARD CIRCUIT

FEEDBACK PIN

CURRENT

0

0.5

1.0

1.5

2.0

2.5

–25

0

25

50

75

125

–50

100

0

10

100

1000

FEEDBACK PIN VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

LOAD CURRENT (mA)

1375/76 G10

1375/76 G11

1375/76 G12

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LT1375/LT1376

TYPICAL PERFORMANCE CHARACTERISTICS

W

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Maximum Load Current

at V = 10V

at V

= 5V

at V

= 3.3V

OUT

1.50

1.25

1.00

0.75

0.50

0.25

0

1.50

1.25

1.00

0.75

0.50

0.25

0

1.50

1.25

1.00

0.75

0.50

0.25

0

L = 20µH

L = 10µH

V

= 10V

OUT

L = 20µH

L = 10µH

L = 20µH

L = 10µH

L = 5µH

V

OUT

= 5V

V

= 3.3V

OUT

0

5

10

15

20

25

0

5

10

15

20

25

0

5

10

15

20

25

INPUT VOLTAGE (V)

1375/76 G15

1375/76 G13

1375/76 G14

BOOST Pin Current

V Pin Shutdown Threshold

Switch Voltage Drop

C

1.4

1.2

1.0

0.8

0.6

0.4

0.8

0.6

0.4

0.2

0

12

10

8

SHUTDOWN

T

= 25°C

T = 25°C

J

6

4

2

0

–25

0

25

50

75

125

–50

100

0

0.25

0.50

0.75

1.00

1.25

0

0.25 0.50 0.75 1.00 1.25 1.50

SWITCH CURRENT (A)

JUNCTION TEMPERATURE (°C)

SWITCH CURRENT (A)

1375/76 G11

1375/76 G16

1375/76 G18

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PIN FUNCTIONS

BOOST: The BOOST pin is used to provide a drive voltage,

higher than the input voltage, to the internal bipolar NPN

power switch. Without this added voltage, the typical

switch voltage loss would be about 1.5V. The additional

boost voltage allows the switch to saturate and voltage

loss approximates that of a 0.3Ω FET structure, but with

much smaller die area. Efficiency improves from 75% for

conventionalbipolardesignsto>87%forthesenewparts.

with the external catch diode. Maximum negative switch

voltage allowed is –0.8V.

SHDN: The shutdown pin is used to turn off the regulator

and to reduce input drain current to a few microamperes.

Actually, this pin has two separate thresholds, one at

2.38V to disable switching, and a second at 0.4V to force

complete micropower shutdown. The 2.38V threshold

functions as an accurate undervoltage lockout (UVLO).

This is sometimes used to prevent the regulator from

operating until the input voltage has reached a predeter-

mined level.

V

_SW: The switch pin is the emitter of the on-chip power

NPN switch. It is driven up to the input pin voltage during

switch on time. Inductor current drives the switch pin

negativeduringswitchofftime.Negativevoltageisclamped

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LT1375/LT1376

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PIN FUNCTIONS

V_IN: This is the collector of the on-chip power NPN switch.

Thispinpowerstheinternalcircuitryandinternalregulator

whentheBIASpinisnotpresent.AtNPNswitchonandoff,

high dl/dt edges occur on this pin. Keep the external

bypass and catch diode close to this pin. All trace induc-

tance on this path will create a voltage spike at switch off,

adding to the V_CEvoltage across the internal NPN.

pin is used as a SENSE pin, connected directly to the 5V

output. Two additional functions are performed by the FB

pin. When the pin voltage drops below 1.7V, switch

current limit is reduced. Below 1V, switching frequency is

also reduced. See Feedback Pin Function section in Appli-

cations Information for details.

V_C: The V_Cpin is the output of the error amplifier and the

input of the peak switch current comparator. It is normally

used for frequency compensation, but can do double duty

as a current clamp or control loop override. This pin sits

at about 1V for very light loads and 2V at maximum load.

It can be driven to ground to shut off the regulator, but if

driven high, current must be limited to 4mA.

BIAS (LT1376 Only): The BIAS pin is used to improve

efficiency when operating at higher input voltages and

light load current. Connecting this pin to the regulated

output voltage forces most of the internal circuitry to draw

its operating current from the output voltage rather than

the input supply. This is a much more efficient way of

doing business if the input voltage is much higher than the

output. Minimum output voltage setting for this mode of

operation is 3.3V. Efficiency improvement at V_IN= 20V,

V_OUT= 5V, and I_OUT= 25mA is over 10%.

GND: The GND pin connection needs consideration for

tworeasons. First, itactsasthereferencefortheregulated

output, so load regulation will suffer if the “ground” end of

the load is not at the same voltage as the GND pin of the

IC. This condition will occur when load current or other

currents flow through metal paths between the GND pin

and the load ground point. Keep the ground path short

between the GND pin and the load, and use a ground plane

when possible. The second consideration is EMI caused

by GND pin current spikes. Internal capacitance between

the V_SWpin and the GND pin creates very narrow (<10ns)

current spikes in the GND pin. If the GND pin is connected

to system ground with a long metal trace, this trace may

radiate excess EMI. Keep the path between the input

bypass and the GND pin short.

SYNC (LT1375 Only): The SYNC pin is used to synchro-

nizetheinternaloscillatortoanexternalsignal.Itisdirectly

logic compatible and can be driven with any signal be-

tween 10% and 90% duty cycle. The synchronizing range

is equal to initial operating frequency, up to 900kHz. See

Synchronizing section in Applications Information for

details.

FB/SENSE: The feedback pin is used to set output voltage,

using an external voltage divider that generates 2.42V at

the pin with the desired output voltage. The fixed voltage

(-5) parts have the divider included on the chip, and the FB

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BLOCK DIAGRAM

The LT1376 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

twofeedbackloopsthatcontrolthedutycycleofthepower

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscilla-

tor pulse which sets the R_Sflip-flop to turn the switch on.

When switch current reaches a level set by the inverting

input of the comparator, the flip-flop is reset and the

switch turns off. Output voltage control is obtained by

using the output of the error amplifier to set the switch

current trip point. This technique means that the error

amplifier commands current to be delivered to the output

rather than voltage. A voltage fed system will have low

phase shift up to the resonant frequency of the inductor

and output capacitor, then an abrupt 180° shift will occur.

The current fed system will have 90° phase shift at a much

lower frequency, but will not have the additional 90° shift

until well beyond the LC resonant frequency. This makes

itmucheasiertofrequencycompensatethefeedbackloop

and also gives much quicker transient response.

Most of the circuitry of the LT1376 operates from an

internal 2.9V bias line. The bias regulator normally draws

power from the regulator input pin, but if the BIAS pin is

13756fd

7

LT1375/LT1376

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BLOCK DIAGRAM

connected to an external voltage higher than 3V, bias

powerwillbedrawnfromtheexternalsource(typicallythe

regulated output voltage). This will improve efficiency if

the BIAS pin voltage is lower than regulator input voltage.

than the input voltage, allowing switch to be saturated.

This boosted voltage is generated with an external capaci-

tor and diode. Two comparators are connected to the

shutdownpin. Onehasa2.38Vthresholdforundervoltage

lockout and the second has a 0.4V threshold for complete

shutdown.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

0.05Ω

INPUT

+

–

CURRENT

SENSE

AMPLIFIER

2.9V BIAS

REGULATOR

INTERNAL

CC

BIAS

V

VOLTAGE GAIN = 10

SLOPE COMP

BOOST

Σ

0.9V

500kHz

OSCILLATOR

S

R

SYNC

Q1

POWER

SWITCH

R

DRIVER

CIRCUITRY

S

FLIP-FLOP

+

–

SHUTDOWN

COMPARATOR

V

SW

+

–

CURRENT

COMPARATOR

0.37V

FREQUENCY

SHIFT CIRCUIT

SHDN

3.5µA

FOLDBACK

CURRENT

LIMIT

Q2

+

–

CLAMP

–

FB

LOCKOUT

COMPARATOR

+

ERROR

AMPLIFIER

2.38V

g

m

= 2000µMho

2.42V

V

C

GND

1375/76 BD

Figure 1. Block Diagram

U

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APPLICATIONS INFORMATION

FEEDBACK PIN FUNCTIONS

resistors and the FB pin is renamed SENSE, connected

directly to the output.

The feedback (FB) pin on the LT1376 is used to set output

voltage and also to provide several overload protection

features. The first part of this section deals with selecting

resistorstosetoutputvoltageandtheremainingparttalks

about foldback frequency and current limiting created by

the FB pin. Please read both parts before committing to a

final design. The fixed 5V LT1376-5 has internal divider

The suggested value for the output divider resistor (see

Figure 2) from FB to ground (R2) is 5k or less, and a

formula for R1 is shown below. The output voltage error

caused by ignoring the input bias current on the FB pin is

less than 0.25% with R2 = 5k. A table of standard 1%

values is shown in Table 1 for common output voltages.

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V

SW

FB

LT1375/LT1376

TO FREQUENCY

SHIFTING

OUTPUT

5V

1.6V

Q1

ERROR

AMPLIFIER

2.4V

+

–

R1

R3

1k

R4

1k

+

R5

5k

Q2

R2

5k

V

C

GND

1375/76 F02

Figure 2. Frequency and Current Limit Foldback

Please read the following if divider resistors are increased equal to the short-circuit current limit of the switch (typi-

above the suggested values.

cally 2A for the LT1376, folding back to less than 1A).

Minimum switch on time limitations would prevent the

switcher from attaining a sufficiently low duty cycle if

switching frequency were maintained at 500kHz, so fre-

quency is reduced by about 5:1 when the feedback pin

voltage drops below 1V (see Frequency Foldback graph).

This does not affect operation with normal load condi-

tions; one simply sees a gear shift in switching frequency

during start-up as the output voltage rises.

R2 V − 2.42

(

)

OUT

R1=

2.42

Table 1

OUTPUT

VOLTAGE

(V)

R1

% ERROR AT OUTPUT

R2

(NEAREST 1%) DUE TO DISCREET 1%

(k

Ω

4.99

)

(kΩ

)

RESISTOR STEPS

+0.23

3

3.3

5

1.21

1.82

5.36

7.32

11.5

15.8

19.6

26.1

In addition to lower switching frequency, the LT1376 also

operates at lower switch current limit when the feedback

pin voltage drops below 1.7V. Q2 in Figure 2 performs this

function by clamping the V_Cpin to a voltage less than its

normal 2.3V upper clamp level. This foldback current limit

greatly reduces power dissipation in the IC, diode and

inductor during short-circuit conditions. Again, it is nearly

transparent to the user under normal load conditions. The

only loads which may be affected are current source loads

which maintain full load current with output voltage less

than 50% of final value. In these rare situations the

Feedback pin can be clamped above 1.5V with an external

diode to defeat foldback current limit. Caution: clamping

thefeedbackpinmeansthatfrequencyshiftingwillalsobe

defeated, so a combination of high input voltage and dead

shorted output may cause the LT1376 to lose control of

current limit.

+0.08

+0.39

6

–0.5

8

–0.04

10

12

15

+0.83

–0.62

+0.52

More Than Just Voltage Feedback

The feedback (FB) pin is used for more than just output

voltage sensing. It also reduces switching frequency and

current limit when output voltage is very low (see the

Frequency Foldback graph in Typical Performance Char-

acteristics). This is done to control power dissipation in

both the IC and in the external diode and inductor during

short-circuit conditions. A shorted output requires the

switching regulator to operate at very low duty cycles, and

the average current through the diode and inductor is

The internal circuitry which forces reduced switching

frequency also causes current to flow out of the feedback

13756fd

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formula assumes continuous mode operation, implying

that the term on the right is less than one-half of I_P.

pin when output voltage is low. The equivalent circuitry is

shown in Figure 2. Q1 is completely off during normal

operation. If the FB pin falls below 1V, Q1 begins to

conduct current and reduces frequency at the rate of

approximately 5kHz/µA. To ensure adequate frequency

foldback (under worst-case short-circuit conditions), the

external divider Thevinin resistance must be low enough

to pull 150µA out of the FB pin with 0.6V on the pin (R_DIV

≤ 4k). The net result is that reductions in frequency and

current limit are affected by output voltage divider imped-

ance. Although divider impedance is not critical, caution

should be used if resistors are increased beyond the

suggested values and short-circuit conditions will occur

with high input voltage. High frequency pickup will in-

crease and the protection accorded by frequency and

current foldback will decrease.

V

V − V

IN OUT

(

_OUT)(

)

I_OUT(MAX)

=

I_P−

Continuous Mode

2 L f V

( )(

)( )

IN

For the conditions above and L = 10µH,

5 8 − 5

( )(

)

I_{OUT MAX}= 1.44 −

(

)

−5

3

⎛

⎞⎛

⎠⎝

⎞

⎠

2 10

⎝

500•10

8

( )

= 1.44 − 0.19 = 1.25A

AtV_IN=15V, dutycycleis33%, soI_Pisjustequaltoafixed

1.5A, and I_OUT(MAX)is equal to:

MAXIMUM OUTPUT LOAD CURRENT

Maximum load current for a buck converter is limited by

the maximum switch current rating (I_P) of the LT1376.

This current rating is 1.5A up to 50% duty cycle (DC),

decreasing to 1.35A at 80% duty cycle. This is shown

graphically in Typical Performance Characteristics and as

shown in the formula below:

5 15 − 5

( )(

)

1.5 −

= 1.5 − 0.33 = 1.17A

−5

3

⎛

⎞⎛

⎠⎝

⎞

2 10

⎝

500•10 15

( )

⎠

Note that there is less load current available at the higher

input voltage because inductor ripple current increases.

This is not always the case. Certain combinations of

inductor value and input voltage range may yield lower

available load current at the lowest input voltage due to

reduced peak switch current at high duty cycles. If load

current is close to the maximum available, please check

maximum available current at both input voltage ex-

tremes. To calculate actual peak switch current with a

given set of conditions, use:

I_P= 1.5A for DC ≤ 50%

I_P=1.65A–0.15(DC)–0.26(DC)²for50%<DC<90%

DC = Duty cycle = V_OUT/V_IN

Example: with V_OUT= 5V, V_IN= 8V; DC = 5/8 = 0.625, and;

I_SW(MAX)= 1.64 – 0.15 (0.625) – 0.26 (0.625)²= 1.44A

Current rating decreases with duty cycle because the

LT1376 has internal slope compensation to prevent cur-

rent mode subharmonic switching. For more details, read

Application Note 19. The LT1376 is a little unusual in this

regardbecauseithasnonlinearslopecompensationwhich

gives better compensation with less reduction in current

limit.

V_OUTV − V

(

)

IN

OUT

I_{SW PEAK}= I_OUT

+

(

)

2 L f V

( )( )( )

IN

For lighter loads where discontinuous operation can be

used, maximum load current is equal to:

Maximum load current would be equal to maximum

switch current for an infinitely large inductor, but with

finite inductor size, maximum load current is reduced by

one-half peak-to-peak inductor current. The following

2

I

f L V

OUT

( _P) ( )( )(

)

I_OUT(MAX)

=

2 V

V − V

Discontinuous mode

(

_OUT)(

)

IN

OUT

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Example: with L = 2µH, V_OUT= 5V, and V_IN(MAX) = 15V,

must withstand continuous fault conditions. If maxi-

mum load current is 0.5A, for instance, a 0.5A inductor

may not survive a continuous 1.5A overload condition.

Dead shorts will actually be more gentle on the induc-

tor because the LT1376 has foldback current limiting.

2

3

−6

⎛

⎞⎛

⎞

⎠

1.5 500 •10 2 •10

15

( )

(

)

⎝

⎠⎝

I_{OUT MAX}

=

= 338mA

(

)

2 5 15 − 5

( )(

)

2. Calculate peak inductor current at full load current to

ensure that the inductor will not saturate. Peak current

can be significantly higher than output current, espe-

cially with smaller inductors and lighter loads, so don’t

omit this step. Powdered iron cores are forgiving

because they saturate softly, whereas ferrite cores

saturate abruptly. Other core materials fall in between

somewhere. The following formula assumes continu-

ous mode of operation, but it errs only slightly on the

high side for discontinuous mode, so it can be used for

all conditions.

The main reason for using such a tiny inductor is that it is

physically very small, but keep in mind that peak-to-peak

inductorcurrentwillbeveryhigh. Thiswillincreaseoutput

ripplevoltage.Iftheoutputcapacitorhastobemadelarger

to reduce ripple voltage, the overall circuit could actually

wind up larger.

CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR

For most applications the output inductor will fall in the

range of 3µH to 20µH. Lower values are chosen to reduce

physical size of the inductor. Higher values allow more

output current because they reduce peak current seen by

the LT1376 switch, which has a 1.5A limit. Higher values

also reduce output ripple voltage, and reduce core loss.

GraphsintheTypicalPerformanceCharacteristicssection

show maximum output load current versus inductor size

andinputvoltage. Asecondgraphshowscorelossversus

inductor size for various core materials.

V_OUTV − V

(

)

IN

OUT

I_PEAK= I_OUT

+

2 f L V

( )( )( )

IN

V_IN= Maximum input voltage

f = Switching frequency, 500kHz

3. Decide if the design can tolerate an “open” core geom-

etry like a rod or barrel, which have high magnetic field

radiation, orwhetheritneedsaclosedcorelikeatoroid

to prevent EMI problems. One would not want an open

core next to a magnetic storage media, for instance!

Thisisatoughdecisionbecausetherodsorbarrelsare

temptingly cheap and small and there are no helpful

guidelines to calculate when the magnetic field radia-

tion will be a problem.

When choosing an inductor you might have to consider

maximum load current, core and copper losses, allowable

component height, output voltage ripple, EMI, fault cur-

rent in the inductor, saturation, and of course, cost. The

following procedure is suggested as a way of handling

thesesomewhatcomplicatedandconflictingrequirements.

1. Choose a value in microhenries from the graphs of

maximumloadcurrentandcoreloss.Choosingasmall

inductor with lighter loads may result in discontinuous

mode of operation, but the LT1376 is designed to work

well in either mode. Keep in mind that lower core loss

means higher cost, at least for closed core geometries

like toroids. The core loss graphs show both absolute

lossandpercentlossfora5Woutput,soactualpercent

losses must be calculated for each situation.

4. Start shopping for an inductor (see representative

surface mount units in Table 2) which meets the re-

quirements of core shape, peak current (to avoid satu-

ration), average current (to limit heating), and fault

current(iftheinductorgetstoohot, wireinsulationwill

melt and cause turn-to-turn shorts). Keep in mind that

allgoodthingslikehighefficiency,lowprofile,andhigh

temperature operation will increase cost, sometimes

dramatically. Get a quote on the cheapest unit first to

calibrate yourself on price, then ask for what you really

want.

Assume that the average inductor current is equal to

load current and decide whether or not the inductor

13756fd

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Tor = Toroid

5. After making an initial choice, consider the secondary

things like output voltage ripple, second sourcing, etc.

Use the experts in the Linear Technology’s applica-

tions department if you feel uncertain about the final

choice. They have experience with a wide range of

inductor types and can tell you about the latest devel-

opments in low profile, surface mounting, etc.

SC = Semi-closed geometry

Fer = Ferrite core material

52 = Type 52 powdered iron core material

KMµ = Kool Mµ

Output Capacitor

The output capacitor is normally chosen by its Effective

Series Resistance (ESR), because this is what determines

output ripple voltage. At 500kHz, any polarized capacitor

is essentially resistive. To get low ESR takes volume, so

physically smaller capacitors have high ESR. The ESR

range for typical LT1376 applications is 0.05Ω to 0.5Ω. A

typical output capacitor is an AVX type TPS, 100µF at 10V,

with a guaranteed ESR less than 0.1Ω. This is a “D” size

surface mount solid tantalum capacitor. TPS capacitors

are specially constructed and tested for low ESR, so they

give the lowest ESR for a given volume. The value in

microfarads is not particularly critical, and values from

22µF to greater than 500µF work well, but you cannot

cheat mother nature on ESR. If you find a tiny 22µF solid

tantalumcapacitor, itwillhavehighESR, andoutputripple

voltage will be terrible. Table 3 shows some typical solid

tantalum surface mount capacitors.

Table 2

SERIES

RESIS-

CORE

VENDOR/

PART NO.

VALUE

DC

CORE

MATER- HEIGHT

(µH) (Amps) TYPE TANCE(

Ω)

IAL

(mm)

Coiltronics

CTX5-1

5

2.3

1.9

1.0

1.8

1.5

2.2

1.8

1.6

1.2

1.0

1.3

1.8

Tor

0.027

KMµ

52

4.2

6.0

4.7

6.4

4.2

6.0

6.35

CTX10-1

CTX20-1

CTX15-2

CTX20-3

CTX20-4

CTX5-1P

CTX10-1P

CTX15-1P

CTX20-1P

CTX20-2P

CTX20-4P

Sumida

10

20

15

20

5

0.039

0.137

0.058

0.093

0.059

0.021

0.030

0.046

0.081

0.052

0.039

10

15

20

52

Table 3. Surface Mount Solid Tantalum Capacitor ESR

and Ripple Current

52

E Case Size

AVX TPS, Sprague 593D

AVX TAJ

ESR (Max.,

Ω

)

Ripple Current (A)

0.7 to 1.1

0.4

0.1 to 0.3

CDRH64

CDRH74

CDRH73

CD73

10

22

10

22

10

18

10

18

1.7

1.2

1.7

1.1

1.4

1.1

2.4

1.7

SC

0.084

0.077

0.055

0.15

Fer

4.5

3.4

3.5

4.0

0.7 to 0.9

D Case Size

AVX TPS, Sprague 593D

AVX TAJ

SC

0.1 to 0.3

0.9 to 2.0

0.7 to 1.1

SC

0.36 to 0.24

Open

0.062

0.085

0.041

0.062

C Case Size

AVX TPS

CD73

0.2 (typ)

0.5 (typ)

CD104

AVX TAJ

1.8 to 3.0

0.22 to 0.17

CD104

B Case Size

AVX TAJ

Gowanda

SM20-102K

SM20-152K

SM20-222K

Dale

2.5 to 10

0.16 to 0.08

10

15

22

1.3

Open

0.038

0.049

0.059

Fer

7.0

Many engineers have heard that solid tantalum capacitors

are prone to failure if they undergo high surge currents.

This is historically true, and type TPS capacitors are

speciallytestedforsurgecapability,butsurgeruggedness

is not a critical issue with the output capacitor. Solid

tantalum capacitors fail during very high turn-on surges,

which do not occur at the output of regulators. High

IHSM-4825

IHSM-5832

IHSM-7832

10

22

10

22

3.1

1.7

4.3

2.8

3.8

Open

0.071

0.152

0.053

0.12

Fer

5.6

7.1

0.054

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discharge surges, such as when the regulator output is

dead shorted, do not harm the capacitors.

dI

dt

V

IN

L

Σ

=

Unlike the input capacitor, RMS ripple current in the

output capacitor is normally low enough that ripple cur-

rent rating is not an issue. The current waveform is

triangular with a typical value of 200mA_RMS. The formula

to calculate this is:

Peak-to-peak output ripple voltage is the sum of a triwave

created by peak-to-peak ripple current times ESR, and a

square wave created by parasitic inductance (ESL) and

ripple current slew rate. Capacitive reactance is assumed

to be small compared to ESR or ESL.

Output Capacitor Ripple Current (RMS):

dI

dt

V_RIPPLE= I

ESR + ESL Σ

0.29 V

V − V

IN OUT

(

_P-P)(

) (

)

(

_OUT)(

)

I_{RIPPLE RMS}

=

(

)

L f V

( )( )( )

IN

Example: withV_IN=10V,V_OUT=5V,L=10µH,ESR=0.1Ω,

ESL = 10nH:

Ceramic Capacitors

Higher value, lower cost ceramic capacitors are now

becomingavailableinsmallercasesizes.Thesearetempt-

ing for switching regulator use because of their very low

ESR. Unfortunately, the ESR is so low that it can cause

loop stability problems. Solid tantalum capacitor’s ESR

generatesaloop“zero”at5kHzto50kHzthatisinstrumen-

tal in giving acceptable loop phase margin. Ceramic ca-

pacitors remain capacitive to beyond 300kHz and usually

resonate with their ESL before ESR becomes effective.

They are appropriate for input bypassing because of their

highripplecurrentratingsandtoleranceofturn-onsurges.

For further information on ceramic and other capacitor

types please refer to Design Note 95.

5 10 − 5

( )(

)

I_P-P

=

= 0.5A

−6

3

⎛

⎞⎛

⎠⎝

⎞

⎠

10 10 •10

500 •10

( )

⎝

dI

dt

10

Σ

=

= 10⁶

10 •10⁻⁶

−9

6

⎛

⎞ ⎛

⎞

⎠

V_RIPPLE= 0.5A 0.1 + 10 •10

10

(

)( )

⎝

⎠ ⎝

= 0.05 + 0.01= 60mV_P-P

V_OUTAT I_OUT= 1A

20mV/DIV

V_OUTAT I_OUT= 50mA

OUTPUT RIPPLE VOLTAGE

INDUCTOR CURRENT

AT I_OUT= 1A

Figure 3 shows a typical output ripple voltage waveform

for the LT1376. Ripple voltage is determined by the high

frequency impedance of the output capacitor, and ripple

current through the inductor. Peak-to-peak ripple current

through the inductor into the output capacitor is:

0.5A/DIV

INDUCTOR CURRENT

AT I_OUT= 50mA

0.5µs/DIV

1375/76 F03

Figure 3. LT1376 Ripple Voltage Waveform

V

V − V

IN OUT

(

_OUT)(

)

I_P-P

=

CATCH DIODE

The suggested catch diode (D1) is a 1N5818 Schottky, or

V

L f

( )( )( )

IN

For high frequency switchers, the sum of ripple current its Motorola equivalent, MBR130. It is rated at 1A average

slew rates may also be relevant and can be calculated forward current and 30V reverse voltage. Typical forward

from:

voltage is 0.42V at 1A. The diode conducts current only

during switch off time. Peak reverse voltage is equal to

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pin voltage is equal to input voltage plus output voltage,

but when the boost diode is connected to the regulator

input, peak BOOST pin voltage is equal to twice the input

voltage. Be sure that BOOST pin voltage does not exceed

its maximum rating.

regulatorinputvoltage.Averageforwardcurrentinnormal

operation can be calculated from:

I_OUTV − V

(

)

IN

OUT

I_D₍_AVG

=

)

V

IN

For nearly all applications, a 0.1uF boost capacitor works

just fine, but for the curious, more details are provided

here. The size of the boost capacitor is determined by

switch drive current requirements. During switch on time,

drain current on the capacitor is approximately 10mA +

This formula will not yield values higher than 1A with

maximum load current of 1.25A unless the ratio of input

tooutputvoltageexceeds5:1. Theonlyreasontoconsider

a larger diode is the worst-case condition of a high input

voltageandoverloaded(notshorted)output.Undershort-

circuit conditions, foldback current limit will reduce diode

current to less than 1A, but if the output is overloaded and

does not fall to less than 1/3 of nominal output voltage,

foldback will not take effect. With the overloaded condi-

tion, output current will increase to a typical value of 1.8A,

determined by peak switch current limit of 2A. With

V_IN= 15V, V_OUT= 4V (5V overloaded) and I_OUT= 1.8A:

I

_OUT/75. At peak load current of 1.25A, this gives a total

drain of 27mA. Capacitor ripple voltage is equal to the

product of on time and drain current divided by capacitor

value; ∆V = t_ON• 27mA/C. To keep capacitor ripple voltage

tolessthan0.5V(aslightlyarbitrarynumber)attheworst-

case condition of t_ON= 1.8µs, the capacitor needs to be

0.1µF. Boost capacitor ripple voltage is not a critical

parameter, but if the minimum voltage across the capaci-

tor drops to less than 3V, the power switch may not

saturate fully and efficiency will drop. An approximate

formula for absolute minimum capacitor value is:

1.8 15 − 4

(

)

I_D₍_AVG

=

= 1.32A

)

15

10mA + I / 75 V_OUT/ V

(

)(

)

OUT

IN

This is safe for short periods of time, but it would be

prudent to check with the diode manufacturer if continu-

ous operation under these conditions must be tolerated.

C_MIN

=

f V − 3V

( )(

)

OUT

f = Switching frequency

BOOST PIN CONSIDERATIONS

V_OUT= Regulated output voltage

V_IN= Minimum input voltage

For most applications, the boost components are a 0.1µF

capacitor and a 1N914 or 1N4148 diode. The anode is

connected to the regulated output voltage and this gener-

ates a voltage across the boost capacitor nearly identical

to the regulated output. In certain applications, the anode

may instead be connected to the unregulated input volt-

age. This could be necessary if the regulated output

voltage is very low (< 3V) or if the input voltage is less than

6V.Efficiencyisnotaffectedbythecapacitorvalue,butthe

capacitor should have an ESR of less than 2Ω to ensure

that it can be recharged fully under the worst-case condi-

tion of minimum input voltage. Almost any type of film or

ceramic capacitor will work fine.

This formula can yield capacitor values substantially less

than 0.1µF, but it should be used with caution since it does

not take into account secondary factors such as capacitor

series resistance, capacitance shift with temperature and

output overload.

SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT1376. Typically, UVLO is used in situations where

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

WARNING! Peak voltage on the BOOST pin is the sum of

unregulated input voltage plus the voltage across the

boost capacitor. This normally means that peak BOOST

loadtothesourceandcancausethesourcetocurrentlimit

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R

FB

LT1375/LT1376

OUTPUT

V

SW

2.38V

+

–

IN

INPUT

STANDBY

R

HI

3.5µA

+

SHDN

+

–

TOTAL

SHUTDOWN

R

LO

C1

0.37V

GND

1375/76 F04

Figure 4. Undervoltage Lockout

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

R_LOV − 2.38 ∆V/ V + 1 + ∆V

(

)

IN

OUT

[

]

R_HI=

2.38 −R2 3.5µA

(

)

Threshold voltage for lockout is about 2.38V, slightly less

than the internal 2.42V reference voltage. A 3.5µA bias

current flows out of the pin at threshold. This internally

generated current is used to force a default high state on

the shutdown pin if the pin is left open. When low shut-

down current is not an issue, the error due to this current

can be minimized by making R_LO10k or less. If shutdown

currentisanissue, R_LOcanberaisedto100k, buttheerror

due to initial bias current and changes with temperature

should be considered.

R = R

V

/

∆V

(

_HI)(

)

FB

OUT

25k suggested for R_LO

V_IN= Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

Example: output voltage is 5V, switching is to stop if input

voltage drops below 12V and should not restart unless

input rises back to 13.5V. ∆V is therefore 1.5V and V_IN=

12V. Let R_LO= 25k.

R = 10k to 100k 25k suggested

(

)

LO

25k 12 − 2.38 1.5/ 5 + 1 + 1.5

(

)

[

]

R_HI=

R_LOV − 2.38V

(

)

IN

2.38 − 25k 3.5µA

R_HI=

(

)

2.38V −R_LO3.5µA

(

)

25k 10.41

(

)

=

= 114k

V_IN= Minimum input voltage

2.29

R = 114k 5/ 1.5 = 380k

(

)

FB

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface capaci-

tance to the switching nodes are minimized. If high resis-

tor values are used, the shutdown pin should be bypassed

with a 1000pF capacitor to prevent coupling problems

from the switch node. If hysteresis is desired in the

undervoltage lockout point, a resistor R_FBcan be added to

the output node. Resistor values can be calculated from:

SWITCH NODE CONSIDERATIONS

For maximum efficiency, switch rise and fall times are

made as short as possible. To prevent radiation and high

frequency resonance problems, proper layout of the com-

ponents connected to the switch node is essential. B field

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(magnetic) radiation is minimized by keeping catch diode,

switch pin, and input bypass capacitor leads as short as

possible. E field radiation is kept low by minimizing the

length and area of all traces connected to the switch pin

and BOOST pin. A ground plane should always be used

under the switcher circuitry to prevent interplane cou-

pling. A suggested layout for the critical components is

shown in Figure 5. Note that the feedback resistors and

compensation components are kept as far as possible

from the switch node. Also note that the high current

groundpathofthecatchdiodeandinputcapacitorarekept

very short and separate from the analog ground line.

the only one containing nanosecond rise and fall times. If

you follow this path on the PC layout, you will see that it is

irreducibly short. If you move the diode or input capacitor

away from the LT1376, get your resumé in order. The

other paths contain only some combination of DC and

500kHz triwave, so are much less critical.

SWITCH NODE

L1

5V

HIGH

FREQUENCY

CIRCULATING

PATH

V

IN

LOAD

Thehighspeedswitchingcurrentpathisshownschemati-

cally in Figure 6. Minimum lead length in this path is

essential to ensure clean switching and low EMI. The path

including the switch, catch diode, and input capacitor is

1375/76 F06

Figure 6. High Speed Switching Path

INPUT

MINIMIZE AREA OF

CONNECTIONS TO THE

D2

C2

SWITCH NODE AND

BOOST NODE

MINIMIZE SIZE OF

FEEDBACK PIN

CONNECTIONS TO

AVOID PICKUP

C

V

BOOST

IN

C

C3

R

FB

GND

C

KEEP INPUT CAPACITOR

AND CATCH DIODE CLOSE

SW

D1

TO REGULATOR AND

TERMINATE THEM

TO SAME POINT

R1

R2

BIAS

SHDN

TERMINATE

FEEDBACK RESISTORS

AND COMPENSATION

COMPONENTS

L1

DIRECTLY TO SWITCHER

GROUND PIN

SHUTDOWN

C1

OUTPUT

GROUND RING NEED

NOT BE AS SHOWN.

(NORMALLY EXISTS AS

INTERNAL PLANE)

1375/76 F05

CONNECT OUTPUT CAPACITOR

DIRECTLY TO HEAVY GROUND

TAKE OUTPUT DIRECTLY FROM END OF OUTPUT

CAPACITOR TO AVOID PARASITIC RESISTANCE

AND INDUCTANCE (KELVIN CONNECTION)

Figure 5. Suggested Layout

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PARASITIC RESONANCE

voltages over 1V lasting longer than 10ns should be

avoided. Note that 100MHz oscilloscopes are barely fast

enough to see the details of the falling edge overshoot in

Figure 7.

Resonance or “ringing” may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

following switch rise time is caused by switch/diode/input

capacitor lead inductance and diode capacitance. Schot-

tky diodes have very high “Q” junction capacitance that

can ring for many cycles when excited at high frequency.

Iftotalleadlengthfortheinputcapacitor, diodeandswitch

path is 1 inch, the inductance will be approximately 25nH.

Schottky diode capacitance of 100pF will create a reso-

nance at 100MHz. This ringing is not harmful to the

LT1376 and can normally be ignored.

A second, much lower frequency ringing is seen during

switch off time if load current is low enough to allow the

inductor current to fall to zero during part of the switch off

time (see Figure 8). Switch and diode capacitance reso-

nate with the inductor to form damped ringing at 1MHz to

10 MHz. Again, this ringing is not harmful to the regulator

and it has not been shown to contribute significantly to

EMI. Any attempt to damp it with a resistive snubber will

degrade efficiency.

Overshoot or ringing following switch fall time is created

by switch capacitance rather than diode capacitance. This

ringing per se is not harmful, but the overshoot can cause

problems if the amplitude becomes too high. The negative

voltage can forward bias parasitic junctions on the IC chip

and cause erratic switching. The LT1376 has special

circuitry inside which mitigates this problem, but negative

INPUT BYPASSING AND VOLTAGE RANGE

Input Bypass Capacitor

Step-down converters draw current from the input supply

in pulses. The average height of these pulses is equal to

load current, and the duty cycle is equal to V_OUT/V_IN. Rise

and fall time of the current is very fast. A local bypass

capacitor across the input supply is necessary to ensure

proper operation of the regulator and minimize the ripple

current fed back into the input supply. The capacitor also

forces switching current to flow in a tight local loop,

minimizing EMI.

RISE AND FALL

WAVEFORMS ARE

SUPERIMPOSED

5V/DIV

(PULSE WIDTH IS

NOT 120ns)

Do not cheat on the ripple current rating of the Input

bypass capacitor, but also don’t get hung up on the value

in microfarads. The input capacitor is intended to absorb

all the switching current ripple, which can have an RMS

value as high as one half of load current. Ripple current

ratings on the capacitor must be observed to ensure

reliable operation. The actual value of the capacitor in

microfarads is not particularly important because at

500kHz, any value above 5µF is essentially resistive. RMS

ripple current rating is the critical parameter. Actual RMS

current can be calculated from:

20ns/DIV

1375/76 F07

Figure 7. Switch Node Resonance

5V/DIV

SWITCH NODE

VOLTAGE

2

INDUCTOR

CURRENT

100mA/DIV

I_{RIPPLE RMS}= I_OUTV_OUTV − V

/

V

IN

(

)

IN

OUT

(

)

20ns/DIV

1375/76 F11

The term inside the radical has a maximum value of 0.5

when input voltage is twice output, and stays near 0.5 for

a relatively wide range of input voltages. It is common

0.5µs/DIV

1375/76 F08

Figure 8. Discontinuous Mode Ringing

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practice therefore to simply use the worst-case value and

assumethatRMSripplecurrentisonehalfofloadcurrent.

At maximum output current of 1.5A for the LT1376, the

input bypass capacitor should be rated at 0.75A ripple

current. Note however, that there are many secondary

considerations in choosing the final ripple current rating.

These include ambient temperature, average versus peak

load current, equipment operating schedule, and required

product lifetime. For more details, see Application Notes

19 and 46, and Design Note 95.

below the minimum specification. Problems can also

occur if the input-to-output voltage differential is near

minimum. The amplitude of these dips is normally a

function of capacitor ESR and ESL because the capacitive

reactance is small compared to these terms. ESR tends to

be the dominate term and is inversely related to physical

capacitor size within a given capacitor type.

Minimum Input Voltage (After Start-Up)

Minimum input voltage to make the LT1376 “run” cor-

rectly is typically 5V, but to regulate the output, a buck

converter input voltage must always be higher than the

output voltage. To calculate minimum operating input

voltage, switch voltage loss and maximum duty cycle

must be taken into account. With the LT1376, there is the

additional consideration of proper operation of the boost

circuit. The boost circuit allows the power switch to

saturate for high efficiency, but it also sometimes results

in a start-up or operating voltage that is several volts

higher than the standard running voltage, especially at

lightloads. Anapproximateformulatocalculateminimum

running voltage at load currents above 100mA is:

Input Capacitor Type

Some caution must be used when selecting the type of

capacitor used at the input to regulators. Aluminum

electrolytics are lowest cost, but are physically large to

achieve adequate ripple current rating, and size con-

straints (especially height), may preclude their use. Ce-

ramic capacitors are now available in larger values, and

their high ripple current and voltage rating make them

ideal for input bypassing. Cost is fairly high and footprint

may also be somewhat large. Solid tantalum capacitors

would be a good choice, except that they have a history of

occasionalspectacularfailureswhentheyaresubjectedto

large current surges during power-up. The capacitors can

short and then burn with a brilliant white light and lots of

nasty smoke. This phenomenon occurs in only a small

percentage of units, but it has led some OEM companies

to forbid their use in high surge applications. The input

bypass capacitor of regulators can see these high surges

when a battery or high capacitance source is connected.

Several manufacturers have developed a line of solid

tantalum capacitors specially tested for surge capability

(AVX TPS series for instance, see Table 3), but even these

units may fail if the input voltage surge approaches the

maximum voltage rating of the capacitor. AVX recom-

mends derating capacitor voltage by 2:1 for high surge

applications. The highest voltage rating is 50V, so 25V

may be a practical upper limit when using solid tantalum

capacitors for input bypassing.

V_OUT+ I

0.4Ω

(

_OUT)(

)

V

=

IN MIN

(

)

0.88

Minimum Start-Up Voltage and Operation at

Light Loads

The boost capacitor supplies current to the BOOST pin

during switch on time. This capacitor is recharged only

during switch off time. Under certain conditions of light

load and low input voltage, the capacitor may not be

recharged fully during the relatively short off time. This

causes the boost voltage to collapse and minimum input

voltage is increased. Start-up voltage at light loads is

higher than normal running voltage for the same reasons.

The graph in Figure 9 shows minimum input voltage for a

5V output, both for start-up and for normal operation.

Larger capacitors may be necessary when the input volt-

age is very close to the minimum specified on the data

sheet. Small voltage dips during switch on time are not

normallyaproblem, butatverylowinputvoltagetheymay

cause erratic operation because the input voltage drops

The circuit in Figure 10 will allow operation at light load

with low input voltages. It uses a small PNP to charge the

boost capacitor C2, and an extra diode D3 to complete the

power path from V_SWto the boost capacitor.

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8.0

Compensation section for a discussion of an entirely

different cause of subharmonic switching before assum-

ing that the cause is insufficient slope compensation.

ApplicationNote19hasmoredetailsonthetheoryofslope

compensation.

(A) MINIMUM VOLTAGE

TO START WITH

7.5

7.0

6.5

6.0

5.5

5.0

STANDARD CIRCUIT

(A)

(B)

(B) MINIMUM VOLTAGE

TO RUN WITH

STANDARD CIRCUIT

(C)

(C) MINIMUM VOLTAGE

TO START WITH

PNP

There is a sync-supply sequence issue with the LT1375. If

power is supplied to the regulator after the external sync

signal is supplied, the regulator may not start. This is

caused by the internal frequency foldback condition that

occurs when the FB pin is below 1V (see block diagram

description in the data sheet). The oscillator tries to run at

100kHz when the FB pin is below 1V, and a high frequency

sync signal will then create an extremely low amplitude

oscillatorwaveform.Thisamplitudemaybesolowthatthe

switch logic is not triggered to create switching. Under the

normal regulated condition, the oscillator runs at much

higher amplitude with plenty of drive for the switch logic.

Notethatforfixedvoltageparts, theFBpinisreplacedwith

a SENSE pin, and the voltage divider resistors are internal.

In that case, the FB pin drops below 1V when the output

voltage is less than 40% of its regulated value.

(D)

(D) MINIMUM VOLTAGE

TO RUN WITH

PNP

0.001

0.01

0.1

1

1375/76 F09

LOAD CURRENT (A)

Figure 9. Minimum Input Voltage

D1

1N914

C2

0.1µF

D3

1N914

L1

BOOST

OUTPUT

INPUT

V

SW

IN

Q1

2N3905

LT1376-5

+

SENSE

GND

V

C

+

There are no sequence problems if the power supply for

the sync signal comes from the output of the LT1375. If

this is not the case, and the sync signal could be present

when power is applied to the regulator, a gate should be

used to block sync signals as shown in Figure 11. Any

other technique which prevents sync signals when the

regulator output is low will work just as well. It does not

matter whether the sync signal is forced high or low; the

internal circuitry is edge triggered.

C1

C

1375/76 F10

Figure 10. Reducing Minimum Input Voltage

SYNCHRONIZING (Available on LT1375 Only)

The LT1375 has the BIAS pin replaced with a SYNC pin,

which is used to synchronize the internal oscillator to an

external signal. It is directly logic compatible and can be

driven with any signal between 10% and 90% duty cycle.

The synchronizing range is equal to initial operating fre-

quency up to 900kHz. This means that minimum practical

sync frequency is equal to the worst-case high self-

oscillating frequency (560kHz), not the typical operating

frequency of 500kHz. Caution should be used when syn-

chronizing above 700kHz because at higher sync frequen-

cies the amplitude of the internal slope compensation

used to prevent subharmonic switching is reduced. This

type of subharmonic switching only occurs at input volt-

ages less than twice output voltage. Higher inductor

values will tend to eliminate problems. See Frequency

V

IN

LT1375

V

OUT

SYNC

1375/76 F11

Figure 11. Gating the Sync Signal

FREQUENCY COMPENSATION

Loop frequency compensation of switching regulators

can be a rather complicated problem because the reactive

components used to achieve high efficiency also

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introduce multiple poles into the feedback loop. The

inductor and output capacitor on a conventional step-

down converter actually form a resonant tank circuit that

can exhibit peaking and a rapid 180° phase shift at the

resonant frequency. By contrast, the LT1376 uses a “cur-

rent mode” architecture to help alleviate phase shift cre-

ated by the inductor. The basic connections are shown in

Figure 12. Figure 13 shows a Bode plot of the phase and

gain of the power section of the LT1376, measured from

the V_Cpin to the output. Gain is set by the 2A/V transcon-

ductance of the LT1376 power section and the effective

complex impedance from output to ground. Gain rolls off

smoothly above the 100Hz pole frequency set by the

100µF output capacitor. Phase drop is limited to about

85°. Phase recovers and gain levels off at the zero fre-

quency (≈16kHz) set by capacitor ESR (0.1Ω).

Erroramplifiertransconductancephaseandgainareshown

in Figure 14. The error amplifier can be modeled as a

transconductance of 2000µMho, with an output imped-

ance of 200kΩ in parallel with 12pF. In all practical

applications, the compensation network from V_Cpin to

ground has a much lower impedance than the output

impedance of the amplifier at frequencies above 500Hz.

This means that the error amplifier characteristics them-

selvesdonotcontributeexcessphaseshifttotheloop,and

the phase/gain characteristics of the error amplifier sec-

tion are completely controlled by the external compensa-

tion network.

In Figure 15, full loop phase/gain characteristics are

shown with a compensation capacitor of 0.0033µF, giving

the error amplifier a pole at 240Hz, with phase rolling off

to 90° and staying there. The overall loop has a gain of

3000

2500

2000

1500

1000

500

200

150

100

50

LT1375

LT1376

CURRENT MODE

POWER STAGE

PHASE

GAIN

V

SW

FB

OUTPUT

g

= 2A/V

ERROR

m

AMPLIFIER

R1

R2

–

V

C

ESR

C1

+

C

R

OUT

12pF

OUT

200k

2.42V

V

2 •10^–3

(

)

FB

+

V

C

GND

ERROR AMPLIFIER EQUIVALENT CIRCUIT

= 50Ω

0

R

LOAD

1k

R

C

–50

F

100

10k

100k

1M

10M

C

FREQUENCY (Hz)

1375/76 F14

1375/76 F12

Figure 12. Model for Loop Response

Figure 14. Error Amplifier Gain and Phase

40

20

0

40

80

60

200

150

100

50

V

I

= 10V

IN

GAIN

= 5V

OUT

= 500mA

0

GAIN

40

–40

–80

–120

20

PHASE

V

C

= 10V

OUT

–20

–40

IN

0

= 5V, I

= 500mA

= 100µF, 10V, AVX TPS

OUT

= 3.3nF, R = 0, L = 10µH

C

–20

–50

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

1375/76 F13

1375/76 F15

Figure 15. Overall Loop Characteristics

Figure 13. Response from V Pin to Output

C

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77dB at low frequency, rolling off to unity-gain at 20kHz.

Phase shows a two-pole characteristic until the ESR of the

output capacitor brings it back above 10kHz. Phase mar-

gin is about 60° at unity-gain.

proper operation of the regulator. In the marginal case,

subharmonic switching occurs, as evidenced by alternat-

ing pulse widths seen at the switch node. In more severe

cases,theregulatorsquealsorhissesaudiblyeventhough

the output voltage is still roughly correct. None of this will

show on a theoretical Bode plot because Bode is an

amplitude insensitive analysis. Tests have shown that if

ripple voltage on the V_Cis held to less than 100mV_P-P, the

LT1376 will be well behaved. The formula below will give

an estimate of V_Cripple voltage when R_Cis added to the

loop, assuming that R_Cis large compared to the reactance

of C_Cat 500kHz.

Analogexpertswillnotethataround1kHz, phasedipsvery

closetothezerophasemarginline.Thisistypicalofswitch-

ing regulators, especially those that operate over a wide

range of loads. This region of low phase is not a problem

aslongasitdoesnotoccurnearunity-gain.Inpractice,the

variability of output capacitor ESR tends to dominate all

other effects with respect to loop response. Variations in

ESR will cause unity-gain to move around, but at the same

time phase moves with it so that adequate phase margin

is maintained over a very wide range of ESR (≥ ±3:1).

R G

V − V

ESR 2.4

( )( _MA)(

_OUT)(

)(

)

C

IN

V_C₍_RIPPLE

=

)

V

L f

( )( )( )

IN

What About a Resistor in the Compensation Network?

It is common practice in switching regulator design to add

a “zero” to the error amplifier compensation to increase

loop phase margin. This zero is created in the external

network in the form of a resistor (R_C) in series with the

compensation capacitor. Increasing the size of this resis-

tor generally creates better and better loop stability, but

there are two limitations on its value. First, the combina-

tion of output capacitor ESR and a large value for R_Cmay

cause loop gain to stop rolling off altogether, creating a

gain margin problem. An approximate formula for R_C

where gain margin falls to zero is:

G_MA= Error amplifier transconductance (2000µMho)

If a computer simulation of the LT1376 showed that a

series compensation resistor of 3k gave best overall loop

response, with adequate gain margin, the resulting V_Cpin

ripple voltage with V_IN= 10V, V_OUT= 5V, ESR = 0.1Ω,

L = 10µH, would be:

−3

⎛

⎞

⎠

3k 2 •10

10 − 5 0.1 2.4

( )

(

)( )(

)

⎝

V_C₍_RIPPLE

=

= 0.144V

)

−6

3

⎛

⎞⎛

⎠⎝

⎞

⎠

10 10 •10

500 •10

( )

⎝

This ripple voltage is high enough to possibly create

subharmonic switching. In most situations a compromise

value (<2k in this case) for the resistor gives acceptable

phase margin and no subharmonic problems. In other

cases, the resistor may have to be larger to get acceptable

phaseresponse, andsomemeansmustbeusedtocontrol

ripple voltage at the V_Cpin. The suggested way to do this

istoaddacapacitor(C_F)inparallelwiththeR_C/C_Cnetwork

on the V_Cpin. Pole frequency for this capacitor is typically

set at one-fifth of switching frequency so that it provides

significant attenuation of switching ripple, but does not

addunacceptablephaseshiftatloopunity-gainfrequency.

With R_C= 3k,

V_OUT

R Loop Gain = 1 =

(

)

C

G

(

G

ESR 2.42

_MP)( _MA)(

)(

)

G_MP= Transconductance of power stage = 2A/V

G_MA= Error amplifier transconductance = 2 × 10^–3

ESR = Output capacitor ESR

2.42 = Reference voltage

With V_OUT= 5V and ESR = 0.1Ω, a value of 5.17k for R_C

would yield zero gain margin, so this represents an upper

limit. There is a second limitation however which has

nothing to do with theoretical small signal dynamics. This

resistor sets high frequency gain of the error amplifier,

including the gain at the switching frequency. If switching

frequency gain is high enough, output ripple voltage will

appear at the V_Cpin with enough amplitude to muck up

5

C_F=

=

= 531pF

3

⎛

⎞

2π f R

( )( )( ) 2π 500 •10 3k

C

( )

⎝

⎠

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How Do I Test Loop Stability?

of high frequency (500kHz) ripple. The ripple makes it

difficult to observe the small transient, so a two-pole,

100kHz filter has been added. This filter is not particularly

critical; even if it attenuated the transient signal slightly,

this wouldn’t matter because amplitude is not critical.

The “standard” compensation for LT1376 is a 3.3nF

capacitor for C_C, with R_C= 0. While this compensation will

work for most applications, the “optimum” value for loop

compensationcomponentsdepends,tovariousextent,on

parameters which are not well controlled. These include

inductor value (±30% due to production tolerance, load

current and ripple current variations), output capacitance

(±20% to ±50% due to production tolerance, tempera-

ture, aging and changes at the load), output capacitor ESR

(±200% due to production tolerance, temperature and

aging), and finally, DC input voltage and output load

current . This makes it important for the designer to check

outthefinaldesigntoensurethatitis“robust”andtolerant

of all these variations.

After verifying that the setup is working correctly, I start

varying load current and input voltage to see if I can find

any combination that makes the transient response look

suspiciously “ringy.” This procedure may lead to an ad-

justment for best loop stability or faster loop transient

response. Nearly always you will find that loop response

looks better if you add in several kΩ for R_C. Do this only

if necessary, because as explained before, R_Cabove 1k

may require the addition of C_Fto control V_Cpin ripple. If

everythinglooksOK, Iuseaheatgunandcoldsprayonthe

circuit (especially the output capacitor) to bring out any

temperature-dependent characteristics.

I check switching regulator loop stability by pulse loading

the regulator output while observing transient response at

the output, using the circuit shown in Figure 16. The

regulator loop is “hit” with a small transient AC load

current at a relatively low frequency, 50Hz to 1kHz. This

causes the output to jump a few millivolts, then settle back

totheoriginalvalue,asshowninFigure17. Awellbehaved

loop will settle back cleanly, whereas a loop with poor

phase or gain margin will “ring” as it settles. The number

ofringsindicatesthedegreeofstability, andthefrequency

of the ringing shows the approximate unity-gain fre-

quency of the loop. Amplitude of the signal is not particu-

larlyimportant, aslongastheamplitudeisnotsohighthat

the loop behaves nonlinearly.

V_OUTAT I_OUT

500mA

=

BEFORE FILTER

V_OUTAT I_OUT

500mA

=

10mV/DIV

5A/DIV

AFTER FILTER

V_OUTAT I_OUT= 50mA

AFTER FILTER

LOAD PULSE

THROUGH 50Ω

f ≈ 780Hz

0.2ms/DIV

1375/76 F17

Figure 17. Loop Stability Check

The output of the regulator contains both the desired low

frequency transient information and a reasonable amount

RIPPLE FILTER

TO X1

OSCILLOSCOPE

PROBE

470Ω

4.7k

SWITCHING

REGULATOR

+

100µF TO

1000µF

3300pF

330pF

50Ω

ADJUSTABLE

INPUT SUPPLY

ADJUSTABLE

DC LOAD

TO

OSCILLOSCOPE

SYNC

100Hz TO 1kHz

100mV TO 1V

P-P

1375/76 F16

Figure 16. Loop Stability Test Circuit

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Quiescent current loss:

Keep in mind that this procedure does not take initial

component tolerance into account. You should see fairly

cleanresponseunderallloadandlineconditionstoensure

that component variations will not cause problems. One

note here: according to Murphy, the component most

likely to be changed in production is the output capacitor,

because that is the component most likely to have manu-

facturer variations (in ESR) large enough to cause prob-

lems. It would be a wise move to lock down the sources of

the output capacitor in production.

2

⎛

⎞

V

0.002

⎜

⎝

⎟

⎠

(

)

OUT

P = V 0.001 + V

0.005 +

(

)

(

)

Q

IN

OUT

V

IN

R_SW= Switch resistance (≈0.4)

16ns = Equivalent switch current/voltage overlap time

f = Switch frequency

Example: with V_IN= 10V, V_OUT= 5V and I_OUT= 1A:

0.4 1 ²5

Apossibleexceptiontothe“cleanresponse”ruleisatvery

light loads, as evidenced in Figure 17 with I_LOAD= 50mA.

Switching regulators tend to have dramatic shifts in loop

response at very light loads, mostly because the inductor

current becomes discontinuous. One common result is

very slow but stable characteristics. A second possibility

is low phase margin, as evidenced by ringing at the output

with transients. The good news is that the low phase

margin at light loads is not particularly sensitive to com-

ponentvariation, soifitlooksreasonableunderatransient

test, it will probably not be a problem in production. Note

that frequency of the light load ringing may vary with

componenttolerancebutphasemargingenerallyhangsin

there.

(

)( ) ( )

−9

3

⎛

⎞

⎠

⎛

⎞

⎠

P_SW

=

+ 16 •10

1 10 500 •10

( )(

)

⎝

10

= 0.2 + 0.08 = 0.28W

2

5

0.008 + 1/75

( ) (

)

P_BOOST

=

= 0.053W

10

2

5

( ) (

0.002

)

P_Q= 10 0.001 + 5 0.005 +

= 0.04W

(

)

(

)

10

Total power dissipation is 0.28 + 0.053 + 0.04 = 0.37W.

Thermal resistance for LT1376 package is influenced by

the presence of internal or backside planes. With a full

plane under the SO package, thermal resistance will be

about120°C/W. Noplanewillincreaseresistancetoabout

160°C/W. To calculate die temperature, use the proper

thermal resistance number for the desired package and

add in worst-case ambient temperature:

THERMAL CALCULATIONS

Power dissipation in the LT1376 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current,andinputquiescentcurrent.Thefollowingformu-

las show how to calculate each of these losses. These

formulas assume continuous mode operation, so they

should not be used for calculating efficiency at light load

currents.

T_J= T_A+ θ_JA(P_TOT

)

With the SO-8 package (θ_JA= 120°C/W), at an ambient

temperature of 70°C,

T_J= 70 + 120 (0.37) = 114.4°C

Switch loss:

Die temperature is highest at low input voltage, so use

lowest continuous input operating voltage for thermal

calculations.

2

R_{SW OUT}

I

V

OUT

(

) (

)

P

=

+ 16ns I

V

f

(

_OUT)( )( )

SW

IN

V

IN

Boost current loss:

2

V_OUT0.008 + I

/ 75

(

)

OUT

P_BOOST

=

V

IN

13756fd

23

LT1375/LT1376

U

W U U

APPLICATIONS INFORMATION

POSITIVE-TO-NEGATIVE CONVERTER

Maximum load current:

The circuit in Figure 18 is a classic positive-to-negative

topology using a grounded inductor. It differs from the

standard approach in the way the IC chip derives its

feedback signal, however, because the LT1376 accepts

onlypositivefeedbacksignals,thegroundpinmustbetied

to the regulated negative output. A resistor divider to

ground or, in this case, the sense pin, then provides the

proper feedback voltage for the chip.

⎡

⎤

⎥

V

OUT

( )(

)

IN

⎢

I_P−

V

V − 0.5

IN

(

_OUT)(

)

⎢

⎣

⎥

2 V + V f L

(

_IN)( )( )

OUT

⎦

I_MAX

=

V

+ V − 0.5 V + V

(

)(

)

OUT

IN

OUT

F

I_P= Maximum rated switch current

V_IN= Minimum input voltage

V_OUT= Output voltage

V_F= Catch diode forward voltage

0.5 = Switch voltage drop at 1.5A

D1

1N4148

C2

0.1µF

L1*

5µH

INPUT

4.5V TO

20V

C3

10µF TO

50µF

BOOST

Example: with V_IN(MIN)= 4.7V, V_OUT= 5V, L = 10µH, V_F=

0.5V, I_P= 1.5A: I_MAX= 0.52A. Note that this equation does

not take into account that maximum rated switch current

(I_P) on the LT1376 is reduced slightly for duty cycles

above 50%. If duty cycle is expected to exceed 50% (input

voltage less than output voltage), use the actual I_Pvalue

from the Electrical Characteristics table.

V

SW

IN

LT1376-5

+

SENSE

GND

V

C

+

C1

100µF

10V TANT

D2

1N5818

C

R

OUTPUT**

–5V, 0.5A

* INCREASE L1 TO 10µH OR 20µH FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

Operating duty cycle:

1375/76 F18

V_OUT+ V_F

DC =

V − 0.3 + V_OUT+ V_F

IN

Figure 18. Positive-to-Negative Converter

(This formula uses an average value for switch loss, so it

may be several percent in error.)

Inverting regulators differ from buck regulators in the

basicswitchingnetwork. Currentisdeliveredtotheoutput With the conditions above:

as square waves with a peak-to-peak amplitude much

5 + 0.5

4.7 − 0.3 + 5 + 0.5

greater than load current. This means that maximum load

current will be significantly less than the LT1376’s 1.5A

maximumswitchcurrent, evenwithlargeinductorvalues.

The buck converter in comparison, delivers current to the

output as a triangular wave superimposed on a DC level

equal to load current, and load current can approach 1.5A

withlargeinductors.Outputripplevoltageforthepositive-

to-negative converter will be much higher than a buck

converter. Ripple current in the output capacitor will also

be much higher. The following equations can be used to

calculateoperatingconditionsforthepositive-to-negative

converter.

DC =

= 56%

This duty cycle is close enough to 50% that I_Pcan be

assumed to be 1.5A.

OUTPUT DIVIDER

If the adjustable part is used, the resistor connected to

V_OUT(R2) should be set to approximately 5k. R1 is

calculated from:

R2 V − 2.42

(

)

OUT

R1=

2.42

13756fd

24

LT1375/LT1376

U

W U U

APPLICATIONS INFORMATION

INDUCTOR VALUE

Minimum inductor discontinuous mode:

Unlike buck converters, positive-to-negative converters

cannot use large inductor values to reduce output ripple

voltage. At 500kHz, values larger than 25µH make almost

no change in output ripple. The graph in Figure 19 shows

peak-to-peak output ripple voltage for a 5V to –5V con-

verter versus inductor value. The criteria for choosing the

inductor is therefore typically based on ensuring that peak

switch current rating is not exceeded. This gives the

lowest value of inductance that can be used, but in some

cases (lower output load currents) it may give a value that

creates unnecessarily high output ripple voltage. A com-

promise value is often chosen that reduces output ripple.

As you can see from the graph, large inductors will not

give arbitrarily low ripple, but small inductors can give

high ripple.

2 V

I

(

_OUT)( _OUT

)

L_MIN

=

2

f I

( )( _P)

Minimum inductor continuous mode:

V

OUT

( )(

)

IN

L_MIN

=

⎡

⎤

⎥

⎦

⎛

⎜

⎝

⎞

⎟

⎠

V

+ V_F

(

)

OUT

⎢

2 f V + V

( )(

I −I

1+

)

IN

OUT

P

OUT

⎢

⎣

V

IN

For the example above, with maximum load current of

0.25A:

150

5V TO –5V CONVERTER

OUTPUT CAPACITOR

5 ²1.5 ²

ESR = 0.1Ω

( ) (

)

120

I_CONT

=

= 0.37A

4 5 + 5 5 + 5 + 0.5

(

)(

)

90

I

= 0.25A

= 0.1A

LOAD

This says that discontinuous mode can be used and the

minimum inductor needed is found from:

60

30

0

I

LOAD

2 5 0.25

( )(

)

L_MIN

=

= 2.2µH

2

)

0

5

10

15

20

25

3

⎛

⎝

⎞

500 •10 1.5

INDUCTOR SIZE (µH)

(

⎠

1375/76 F19

Figure 19. Ripple Voltage on Positive-to-Negative Converter

In practice, the inductor should be increased by about

30% over the calculated minimum to handle losses and

variations in value. This suggests a minimum inductor of

3µH for this application, but looking at the ripple voltage

chartshowsthatoutputripplevoltagecouldbereducedby

a factor of two by using a 15µH inductor. There is no rule

of thumb here to make a final decision. If modest ripple is

needed and the larger inductor does the trick, go for it. If

ripple is noncritical use the smaller inductor. If ripple is

extremely critical, a second filter may have to be added in

any case, and the lower value of inductance can be used.

Keep in mind that the output capacitor is the other critical

factor in determining output ripple voltage. Ripple shown

on the graph (Figure 19) is with a capacitor ESR of 0.1Ω.

This is reasonable for an AVX type TPS “D” or “E” size

The difficulty in calculating the minimum inductor size

needed is that you must first know whether the switcher

will be in continuous or discontinuous mode at the critical

point where switch current is 1.5A. The first step is to use

the following formula to calculate the load current where

the switcher must use continuous mode. If your load

current is less than this, use the discontinuous mode

formula to calculate minimum inductor needed. If load

current is higher, use the continuous mode formula.

Output current where continuous mode is needed:

2

V

²I

( ) ( _P)

IN

I_CONT

=

4 V + V

V + V + V

IN OUT F

(

_OUT)(

)

IN

13756fd

25

LT1375/LT1376

U

W U U

APPLICATIONS INFORMATION

surface mount solid tantalum capacitor, but the final

capacitor chosen must be looked at carefully for ESR

characteristics.

Peak diode current:

Continuous Mode =

V + V

V

(

)

( )(

)

IN

OUT

IN OUT

Ripple Current in the Input and Output Capacitors

I_OUT

+

V

2 L f V + V

( )( )(

IN

)

IN

OUT

Positive-to-negativeconvertershavehighripplecurrentin

both the input and output capacitors. For long capacitor

lifetime, the RMS value of this current must be less than

the high frequency ripple current rating of the capacitor.

The following formula will give an approximate value for

RMS ripple current. This formula assumes continuous

mode and large inductor value. Small inductors will give

somewhat higher ripple current, especially in discontinu-

ous mode. The exact formulas are very complex and

appear in Application Note 44, pages 30 and 31. For our

purposes here I have simply added a fudge factor (ff). The

value for ff is about 1.2 for higher load currents and

L ≥10µH. It increases to about 2.0 for smaller inductors at

lower load currents.

2 I

V

(

_OUT)(

)

OUT

Discontinuous Mode =

L f

( )( )

Keep in mind that during start-up and output overloads,

average diode current may be much higher than with

normalloads.Careshouldbeusedifdiodesratedlessthan

1A are used, especially if continuous overload conditions

must be tolerated.

Dual Output SEPIC Converter

The circuit in Figure 20 generates both positive and

negative 5V outputs with a single piece of magnetics. The

two inductors shown are actually just two windings on a

standard Coiltronics inductor. The topology for the 5V

output is a standard buck converter. The –5V topology

would be a simple flyback winding coupled to the buck

converter if C4 were not present. C4 creates the SEPIC

(Single-Ended Primary Inductance Converter) topology

which improves regulation and reduces ripple current in

L1. For details on this circuit see Design Note 100.

V_OUT

Capacitor I_RMS= ff I

( )( _OUT

)

V

IN

ff = Fudge factor¹(1.2 to 2.0)

Diode Current

Average diodecurrentisequaltoloadcurrent. Peak diode

current will be considerably higher.

D2

1N914

C2

0.1µF

BOOST

INPUT

OUTPUT

5V

V

SW

IN

6V TO 25V

L1*

10µH

BIAS

LT1376-5

SHDN

GND

SENSE

C

V

+

C1**

+

C3

22µF

100µF

R

C

10V TANT

35V TANT

470Ω

D1

1N5818

C

0.01µF

GND

+

C4**

C5**

* L1 IS A SINGLE CORE WITH TWO WINDINGS

COILTRONICS #CTX10-2P

L1*

D3

1N5818

100µF

10V TANT

** AVX TPSD107M010

OUTPUT

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL

†

–5V

PRELOAD OF 1k TO 5k MAY BE USED TO

IMPROVE LOAD REGULATION

1375/76 F20

Figure 20. Dual Output SEPIC Converter

¹Normally, Jamoca Almond

13756fd

26

LT1375/LT1376

U

PACKAGE DESCRIPTION

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

.400*

(10.160)

MAX

8

7

6

5

4

.255 ± .015*

(6.477 ± 0.381)

1

2

3

.130 ± .005

.300 – .325

.045 – .065

(3.302 ± 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

.065

(1.651)

TYP

.008 – .015

(0.203 – 0.381)

.120

.020

(0.508)

MIN

(3.048)

MIN

+.035

.325

–.015

.018 ± .003

(0.457 ± 0.076)

.100

(2.54)

BSC

+0.889

8.255

(

)

N8 1002

–0.381

NOTE:

INCHES

1. DIMENSIONS ARE

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

.189 – .197

(4.801 – 5.004)

.045 ±.005

NOTE 3

.050 BSC

7

5

8

6

.245

MIN

.160 ±.005

.150 – .157

(3.810 – 3.988)

NOTE 3

.228 – .244

(5.791 – 6.197)

.030 ±.005

TYP

1

3

4

2

RECOMMENDED SOLDER PAD LAYOUT

.010 – .020

(0.254 – 0.508)

× 45°

.053 – .069

(1.346 – 1.752)

.004 – .010

(0.101 – 0.254)

.008 – .010

(0.203 – 0.254)

0°– 8° TYP

.016 – .050

(0.406 – 1.270)

.050

(1.270)

BSC

.014 – .019

(0.355 – 0.483)

TYP

NOTE:

INCHES

1. DIMENSIONS IN

(MILLIMETERS)

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

SO8 0303

13756fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LT1375/LT1376

U

PACKAGE DESCRIPTION

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

.386 – .394

(9.804 – 10.008)

.045 ±.005

NOTE 3

.050 BSC

N

16

N

15

14

13

12

11

10

9

.245

MIN

.160 ±.005

.150 – .157

(3.810 – 3.988)

NOTE 3

.228 – .244

(5.791 – 6.197)

1

2

3

N/2

8

.030 ±.005

TYP

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

.010 – .020

(0.254 – 0.508)

× 45°

.053 – .069

(1.346 – 1.752)

.004 – .010

(0.101 – 0.254)

.008 – .010

(0.203 – 0.254)

0° – 8° TYP

.050

(1.270)

BSC

.014 – .019

(0.355 – 0.483)

TYP

.016 – .050

(0.406 – 1.270)

S16 0502

NOTE:

1. DIMENSIONS IN

INCHES

(MILLIMETERS)

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1370

High Efficiency DC/DC Converter

42V, 6A, 500kHz Switch

35V, 3A, 500kHz Switch

Boost Topology

LT1371

LT1372/LT1377 500kHz and 1MHz High Efficiency 1.5A Switching Regulators

LT1374 High Efficiency Step-Down Switching Regulator

LT1375/LT1376 1.5A Step-Down Switching Regulators

25V, 4.5A, 500kHz Switch

500kHz, Synchronizable in SO-8 Package

500kHz, 4V to 16V Input, SO-8 Package

200kHz, Reduced EMI Generation

LT1507

LT1576

LT1578

LT1616

1.5A Step-Down Switching Regulator

600mA Step-Down Switching Regulator

200kHz, Reduced EMI Generation

1.4MHz, 4V to 25V Input, SOT-23 Package

60V Input, 700mA Internal Switches

Burst Mode^®Operation, 16-Pin Narrow SSOP

Output Fault Protection, 16-Pin SSOP and SO-8

Higher Current, 8-Lead MSOP Package

Higher Current, High Effieciency: Up to 94%

Lower Current, 100% Duty Cycle

LT1676/LT1776 Wide Input Range Step-Down Switching Regulators

LTC1735

LTC1735-1

LT1767

High Efficiency Synchronous Step-Down, N-Ch Drive

High Efficiency Step-Down Controller with Power Good

1.5A, 1.4MHz Step-Down DC/DC Converter

LTC1772

LTC1779

LTC1877

LTC1878

LTC3404

Constant Frequency Step-Down Controller in SOT-23

0.25A Micropower Step-Down in SOT-23

High Efficiency Monolithic Step-Down Regulator

550kHz, MS8, V Up to 10V, I =10µA, I

to 600mA at V = 5V

IN

Q

OUT

550kHz, MS8, V Up to 6V, I = 10µA, I

to 600mA at V = 3.3V

IN

Q

1.4MHz High Efficiency, Monolithic Synchronous Step-Down

Regulator

Up to 95% Efficiency, 100% Duty Cycle, IQ = 10µA,

= 2.65V to 6V

V

IN

Burst Mode is a registered trademark of Linear Technology Corporation.

13756fd

LT 0306 REV D • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1407-1_15
厂家：	Linear
描述：	Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown
文件：	总28页 (文件大小：511K)
中文：	中文翻译
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