LTC1410 [Linear]
12-Bit, 1.25Msps Sampling A/D Converter with Shutdown; 12位， 1.25MSPS采样A / D转换器，带有关断
| 型号： | LTC1410 |
| 厂家： | 
Linear |
| 描述： | 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown |
| 文件： | 总16页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1410
12-Bit, 1.25Msp s Sa m p ling
A/D Co nve rte r with Shutd o wn
U
DESCRIPTIO
EATURE
S
F
The LTC®1410 is a 0.65µs, 1.25Msps, 12-bit sampling
A/D converter that draws only 160mW from ±5V supplies.
This easy-to-use device includes a high dynamic range
sample-and-hold, a precision reference and requires no
external components. Two digitally selectable power shut-
down modes provide flexibility for low power systems.
■
■
■
■
■
■
1.25Msps Sample Rate
Power Dissipation: 160mW
71dB S/(N + D) and 82dB THD at Nyquist
No Pipeline Delay
Nap (7mW) and Sleep (10µW) Shutdown Modes
Operates with Internal 15ppm/°C Reference
or External Reference
True Differential Inputs Reject Common Mode Noise
20MHz Full Power Bandwidth Sampling
±2.5V Bipolar Input Range
The LTC1410’s full-scale input range is ±2.5V. Maximum
DC specifications include±1LSB INL and±1LSB DNL over
temperature. Outstanding AC performance includes 71dB
S/(N + D) and 82dB THD at the Nyquist input frequency of
625kHz.
■
■
■
■
28-Pin SO Wide Package
O U
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 20MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
PPLICATI
S
A
■
Telecommunications
■
■
■
■
■
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
The ADC has a µP compatible, 12-bit parallel output port.
There is no pipeline delay in the conversion results. A
separateconvertstartinputandadatareadysignal(BUSY)
ease connections to FIFOs, DSPs and microprocessors.
Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
Complete 1.25MHz, 12-Bit Sampling A/D Converter
LTC1410
5V
DIFFERENTIAL
ANALOG INPUT
(–2.5V TO 2.5V)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
12
10
8
74
68
62
56
50
+A
AV
DD
IN
+
–5V
–A
IN
DV
DD
0.1µF
10µF
3
NYQUIST
2.50V
OUTPUT
V
REF
V
SS
V
REF
4
0.1µF
10µF
REFCOMP
AGND
BUSY
CS
+
5
0.1µF
10µF
6
D11(MSB) CONVST
µP CONTROL
LINES
7
6
D10
D9
RD
SHDN
NAP/SLP
OGND
D0
8
9
4
D8
10
11
12
13
14
D7
12-BIT
PARALLEL
BUS
2
D6
f
= 1.25MHz
SAMPLE
D5
D1
0
D4
D2
1k
10k
100k
1M
10M
DGND
D3
INPUT FREQUENCY (Hz)
LTC1410 • TA02
1410 TA01
1
LTC1410
W
U
W W W
U
/O
PACKAGE RDER I FOR ATIO
ABSOLUTE AXI U RATI GS
AVDD = DVDD = VDD (Notes 1, 2)
TOP VIEW
ORDER
PART NUMBER
Supply Voltage (VDD)................................................ 6V
+A
1
2
3
4
5
6
7
8
9
28 AV
IN
DD
Negative Supply Voltage (V ) ............................... –6V
SS
–A
IN
27 DV
DD
Total Supply Voltage (VDD to V ) .......................... 12V
SS
V
REF
26
V
SS
LTC1410CG
LTC1410CSW
LTC1410IG
Analog Input Voltage
REFCOMP
AGND
D11(MSB)
D10
25 BUSY
24 CS
(Note 3) .................................. V – 0.3V to VDD + 0.3V
SS
Digital Input Voltage (Note 4) ............ V – 0.3V to 10V
23 CONVST
22 RD
SS
LTC1410ISW
Digital Output Voltage................... – 0.3V to VDD + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1410C .............................................. 0°C to 70°C
LTC1410I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
D9
21 SHDN
20 NAP/SLP
19 OGND
18 D0
D8
D7 10
D6 11
D5 12
17 D1
D4 13
16 D2
DGND 14
15 D3
G PACKAGE
SW PACKAGE
28-LEAD PLASTIC SSOP 28-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 90°C/W (SW)
TJMAX = 110°C, θJA = 95°C/W (G)
Consult factory for Military grade parts.
U
CO VERTER
CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6)
PARAMETER
CONDITIONS
(Note 7)
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
12
±0.3
±0.3
±2
±1
±1
LSB
LSB
(Note 8)
±6
±8
LSB
LSB
●
●
Full-Scale Error
±15
LSB
Full-Scale Tempco
I
= 0
±15
ppm/°C
OUT(REF)
U
U
The ● denotes specifications which apply over the full operating temperature range, otherwise
A ALOG I PUT
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –4.75V
MIN
TYP
MAX
UNITS
V
V
Analog Input Range (Note 9)
Analog Input Leakage Current
Analog Input Capacitance
●
●
±2.5
IN
DD
SS
I
IN
CS = High
±1
µA
C
IN
Between Conversions
During Conversions
17
5
pF
pF
t
t
t
Sample-and-Hold Acquisition Time
●
50
–1.5
5
100
ns
ns
ACQ
AP
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
ps
jitter
RMS
CMRR
–2.5V < (–A = A ) < 2.5V
60
dB
IN
IN
2
LTC1410
W
U
The ● denotes specifications which apply over the full operating temperature range,
DY
A IC
ACCURACY
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal (Note 12)
600kHz Input Signal (Note 12)
●
●
70
68
72.5
71.0
dB
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
600kHz Input Signal, First 5 Harmonics
–85
–82
dB
dB
●
●
–74
–74
Peak Harmonic or Spurious Noise
Intermodulation Distortion
Full Power Bandwidth
600kHz Input Signal
–84
–84
20
dB
dB
IMD
f
IN1
= 29.37kHz, f = 32.446kHz
IN2
MHz
MHz
Full Linear Bandwidth
(S/(N + D) ≥ 68dB)
2.5
U U
U
I TER AL REFERE CE CHARACTERISTICS The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
MIN
TYP
2.500
±15
MAX
UNITS
V
V
Output Voltage
Output Tempco
Line Regulation
I
= 0
= 0
2.480
2.520
REF
OUT
V
REF
I
ppm/°C
OUT
V
REF
4.75V ≤ V ≤ 5.25V
0.01
0.01
LSB/V
LSB/V
DD
–5.25V ≤ V ≤ –4.75V
SS
V
REF
Output Resistance
I
≤ 0.1mA
2
kΩ
OUT
COMP Output Voltage
I
= 0
4.06
V
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
= 5.25V
= 4.75V
DD
●
●
●
2.4
IH
DD
V
IL
V
0.8
V
I
IN
V
IN
= 0V to V
DD
±10
µA
pF
C
Digital Input Capacitance
High Level Output Voltage
5
IN
V
OH
V
DD
= 4.75V
I = –10µA
I = –200µA
O
4.5
V
V
O
●
4.0
V
Low Level Output Voltage
V
= 4.75V
I = 160µA
I = 1.6mA
OL
DD
0.05
0.10
V
V
O
●
●
●
0.4
±10
15
O
I
OZ
High-Z Output Leakage D11 to D0
High-Z Output Capacitance D11 to D0
Output Source Current
V
OUT
= 0V to V , CS High
µA
pF
DD
C
OZ
CS High (Note 9 )
= 0V
I
V
–10
10
mA
mA
SOURCE
OUT
I
Output Sink Current
V
= V
SINK
OUT DD
W U
POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
(Notes 10, 11)
(Note 10)
MIN
4.75
TYP
MAX
5.25
UNITS
V
V
Positive Supply Voltage
Negative Supply Voltage
DD
V
SS
–4.75
–5.25
V
I
Positive Supply Current
Nap Mode
Sleep Mode
CS = RD = CONVST = 5V
SHDN = 0V, NAP/SLP = 5V
SHDN = 0V, NAP/SLP = 0V
●
●
12
1.5
1
16
2.3
100
mA
mA
µA
DD
I
SS
Negative Supply Current
Nap Mode
Sleep Mode
CS = RD = CONVST = 5V
SHDN = 0V, NAP/SLP = 5V
SHDN = 0V, NAP/SLP = 0V
20
10
1
30
200
100
mA
µA
µA
3
LTC1410
W U
POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
P
Power Dissipation
Nap Mode
Sleep Mode
160
7.5
0.01
230
12
1
mW
mW
mW
D
SHDN = 0V, NAP/SLP = 5V
SHDN = 0V, NAP/SLP = 0V
W U
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
f
Maximum Sampling Frequency
Conversion Time
●
●
●
●
1.25
SAMPLE(MAX)
t
t
t
650
50
750
100
800
CONV
Acquisition Time
ns
ACQ
Throughput Time
ns
ACQ+CONV
(Acquisition + Conversion)
t
t
t
t
t
t
CS to RD Setup Time
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
●
●
●
0
ns
ns
ns
ns
ns
1
2
3
4
5
6
CS↓ to CONVST↓ Setup Time
NAP/SLP↓ to SHDN↓ Setup Time
10
10
SHDN↑ to CONVST↓ Wake-Up Time (Note 10)
200
CONVST Low Time
(Notes 10, 11)
●
●
40
CONVST to BUSY Delay
C = 25pF
L
10
35
ns
ns
50
t
Data Ready Before BUSY↑
20
15
ns
ns
7
●
●
●
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 10)
(Note 10)
40
ns
ns
8
–5
9
C = 25pF
L
15
20
25
35
35
50
ns
ns
ns
ns
10
●
●
C = 100pF
L
t
Bus Relinquish Time
8
20
25
30
ns
ns
ns
11
Commercial
Industrial
●
●
t
t
t
RD Low Time
●
●
t
ns
ns
ns
12
13
14
10
CONVST High Time
40
Aperture Delay of Sample-and-Hold
–1.5
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
and AGND wired together unless otherwise noted.
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 3: When these pin voltages are taken below V or above V , they
SS
DD
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V or above V without latchup.
SS
DD
Note 4: When these pin voltages are taken below V , they will be clamped
by internal diodes. This product can handle input currents greater than
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 425ns after the
start of the conversion or after BUSY rises.
SS
100mA below V without latchup. These pins are not clamped to V
.
SS
DD
Note 5: V = 5V, V = –5V, f
= 1.25MHz, t = t = 5ns unless
r f
DD
SS
SAMPLE
otherwise specified.
Note 12: Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
is measured at 600kHz. These results are used to calculate signal-to-noise
plus distortion (SINAD).
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A input with – A grounded.
IN
IN
4
LTC1410
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio vs
Input Frequency
Distortion vs Input Frequency
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
80
70
60
50
40
30
20
10
0
V
IN
= 0dB
V
IN
= –20dB
THD
3RD
V
IN
= –60dB
2ND
f
= 1.25MHz
10k
SAMPLE
1k
100k
1M
10M
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1410 G01
1410 G03
1410 G02
Spurious-Free Dynamic Range vs
Input Frequency
Differential Nonlinearity vs
Output Code
Intermodulation Distortion Plot
0
–20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1.0
0.5
f
= 1.25MHz
= 88.19580078kHz
= 111.9995117kHz
SAMPLE
f
IN1
f
IN2
–40
–60
0
–80
–0.5
–1.0
–100
–120
0
200
300 400 500
600
100
10k
100k
1M
10M
0
512
1536 2560 3072
2048
4096
3504
1024
INPUT FREQUENCY (Hz)
OUTPUT CODE
FREQUENCY (kHz)
1410 G04
1410 G06
1410 G05
Integral Nonlinearity vs
Output Code
Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
0
–20
80
70
60
50
40
30
20
10
0
1.0
0.5
V
RIPPLE
= 0.1V
–40
–60
0
V
SS
–80
V
DD
–0.5
–1.0
DGND
–100
–120
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
0
512
1536 2048 2560 3072
OUTPUT CODE
4096
3504
1024
RIPPLE FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1410 G08
1410 G09
1410 G07
5
LTC1410
U U
U
PI FU CTIO S
+A (Pin 1): Positive Analog Input, ±2.5V.
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin.
IN
–A (Pin 2): Negative Analog Input, ±2.5V.
IN
V
REF
(Pin 3): 2.50V Reference Output.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
REFCOMP (Pin 4): 4.06V Reference Bypass Pin. By-
pass to AGND with 10µF tantalum in parallel with 0.1µF
ceramic.
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
AGND (Pin 5): Analog Ground.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
OGND (Pin 19): Digital Ground for Output Drivers. Tie
to AGND.
V (Pin 26): –5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel 0.1µF ceramic.
SS
NAP/SLP (Pin 20): Power Shutdown Mode. Selects the
mode invoked by the SHDN pin. Low selects Sleep
mode and high selects quick wake-up Nap mode.
DV (Pin 27): 5V Positive Supply. Short to Pin 28.
DD
AV (Pin 28): 5V Positive Supply. Bypass to AGND
DD
with 10µF tantalum in parallel with 0.1µF ceramic.
U
U
W
FU CTIO AL BLOCK DIAGRA
C
SAMPLE
+A
IN
AV
DD
C
SAMPLE
–A
IN
DV
DD
2k
ZEROING SWITCHES
V
REF
2.5V REF
REF AMP
V
SS
+
COMP
12-BIT CAPACITIVE DAC
–
REFCOMP
(4V)
12
D11
D0
SUCCESSIVE APPROXIMATION
REGISTER
•
•
•
OUTPUT LATCHES
AGND
DGND
INTERNAL
CLOCK
CONTROL LOGIC
LTC1410 • BD
NAP/SLP SHDN CONVST RD CS BUSY
6
LTC1410
TEST CIRCUITS
Load Circuits for Output Float Delay
Load Circuits for Access Timing
5V
5V
1k
1k
DBN
DBN
DBN
DBN
1k
100pF
100pF
1k
C
L
C
L
(A) V TO Hi-Z
OH
(B) V TO Hi-Z
OL
(A) Hi-Z TO V AND V TO V
(B) Hi-Z TO V AND V TO V
OL OH OL
OH
OL
OH
1410 TC02
1410 TC01
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APPLICATIONS INFORMATION
CONVERSION DETAILS
onto the summing junctions. This input charge is succes-
sively compared with the binarily-weighted charges sup-
plied by the differential capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
The LTC1410 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
conversion, the differential DAC output balances the +A
IN
and –A input charges. The SAR contents (a 12-bit data
IN
word) which represent the difference of +A and –A are
IN
IN
loaded into the 12-bit output latches.
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
+C
SAMPLE
SAMPLE
SAMPLE
+A
IN
HOLD
HOLD
ZEROING SWITCHES
HOLD
–C
SAMPLE
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the +A and –A inputs are
–A
IN
HOLD
+C
DAC
+
IN
IN
connected to the sample-and-hold capacitors (CSAMPLE
)
–C
DAC
COMP
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum duration of 100ns will provide enough time for
the sample-and-hold capacitors to acquire the analog
signal. During the convert phase the comparator zeroing
switches open, putting the comparator into compare
mode. The input switches connect the CSAMPLE capacitors
toground, transferringthedifferentialanaloginputcharge
–
+V
DAC
–V
DAC
12
D11
OUTPUT
•
•
•
SAR
LATCHES
D0
1410 F01
Figure 1. Simplified Block Diagram
7
LTC1410
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APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
tofrequencies fromaboveDCandbelowhalfthesampling
frequency. Figures 2a and 2b shows a typical spectral
content with a 1.25MHz sampling rate for 100kHz and
600kHz inputs. The dynamic performance is excellent for
input frequencies up to the Nyquist limit of 625kHz and
beyond.
The LTC1410 has excellent high speed sampling capabil-
ity. Fast Four Transform (FFT) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement
of the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
0
–20
–40
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 1.25MHz the LTC1410 maintains very good ENOBs
up to the Nyquist input frequency of 625kHz and beyond.
Refer to Figure 3.
–60
–80
–100
–120
12
10
8
74
68
62
56
50
0
200
300 400 500
600
100
NYQUIST
FREQUENCY (kHz)
1410 F02a
Figure 2a. LTC1410 Nonaveraged 4096 Point FFT, 100kHz Input
6
0
4
–20
–40
2
f
= 1.25MHz
SAMPLE
0
1k
10k
100k
1M
10M
–60
INPUT FREQUENCY (Hz)
LTC1410 • TA02
–80
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
–100
–120
0
200
300 400 500
600
100
Total Harmonic Distortion (THD)
FREQUENCY (kHz)
1410 F02b
Total harmonic distortion is the ratio of the RMS sum of all
harmonics oftheinputsignaltothefundamentalitself.The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
Figure 2b. LTC1410 Nonaveraged 4096 Point FFT, 600kHz Input
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
2
2
2
V + V + V2 +. . .V
2
3
4
n
THD = 20 log
V
1
8
LTC1410
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APPLICATIONS INFORMATION
0
–20
where V is the RMS amplitude of the fundamental fre-
1
f
= 1.25MHz
= 88.19580078kHz
= 111.9995117kHz
SAMPLE
f
IN1
quency and V through V are the amplitudes of the
2
n
f
IN2
secondthroughnthharmonics.THDvs InputFrequencyis
shown in Figure 4. The LTC1410 has good distortion
performance up to the Nyquist frequency and beyond.
–40
–60
(2f –f )
a
b
0
–10
–20
–30
–40
–50
–60
(3f )
(3f )
b
–80
a
–100
–120
100
0
200
300
FREQUENCY (MHz)
400
500
600
1410 F05
THD
3RD
–70
–80
Figure 5. Intermodulation Distortion Plot
2ND
–90
Peak Harmonic or Spurious Noise
–100
1k
10k
100k
1M
10M
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibel relative to the RMS value of
a full-scale input signal.
INPUT FREQUENCY (Hz)
1410 G03
Figure 4. Distortion vs Input Frequency
Full Power and Full Linear Bandwidth
Intermodulation Distortion (IMD)
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input signal.
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce Intermodulation Distortion in addition to THD.
IMD is the change in one sinusoidal input caused by the
presence of another sinusoidal input at a different
frequency.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1410 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist frequency. The
noise floor stays very low at high frequencies; S/(N + D)
does not become dominated by distortion until frequen-
cies far beyond Nyquist.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa +fb).Ifthetwoinputsinewaves areequalinmagnitude,
the value (in decibels) of the 2nd order IMD products can
be expressed by the following formula:
Driving the Analog Input
The differential analog inputs of the LTC1410 are easy to
drive. The inputs may be driven differentially or as a
single-ended input (i.e., the –A input is grounded). The
IN
Amplitude at f ± f
(
)
a
b
+A and –A inputs are sampled at the same instant.
IN
IN
IMD f + f = 20 log
(
)
a
b
Any unwanted signal that is common mode to both
inputs will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
Amplitude at fa
9
LTC1410
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APPLICATIONS INFORMATION
capacitors at the end of conversion. During conversion
theanaloginputs drawonlyasmallleakagecurrent. Ifthe
source impedance of the driving circuit is low then the
LTC1410 inputs can be driven directly. As source imped-
ance increases so will acquisition time (see Figure 6). For
minimum acquisition time with high source impedance,
a buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settleafterthesmallcurrentspikebeforethenextconver-
sion starts (settling time must be 100ns for full through-
put rate).
sample-and-holdcircuitis 20MHz.Anynoisethatis present
at the analog inputs will be summed over this entire
bandwidth. Noisy input circuitry should be filtered prior to
the analog inputs to minimize noise. A simple 1-pole RC
filter is usually sufficient. For example, Figure 7 shows a
1000pF capacitor from +A toground and a 100Ωsource
IN
resistor will limit the input bandwidth to 1.6MHz. Simple
RC filters work well for AC applications, but they will limit
thetransientresponse.Forfullspeedoperation,amplifiers
with fast settling and low noise should be chosen.
100Ω
1
2
3
4
5
ANALOG
INPUT
10
+A
IN
1000pF
–A
IN
V
REF
1
REFCOMP
AGND
10µF
0.1µF
0.1
0.01
LTC1410
1410 F07
Figure 7. RC Input Filter
1k
10k
100k
10
100
SOURCE RESISTANCE (Ω)
1410 F06
Internal Reference
Figure 6. Acquisition Time vs Source Resistance
The LTC1410 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmedto2.500V.Itis connectedinternallytoareference
amplifier and is available at VREF (Pin 3). See Figure 8a. A
2k resistor is in series with the output so that it can be
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier
that has a low output impedance (<100Ω) at the closed-
loop bandwidth frequency. For example, if an amplifier is
used in a gain of +1 and has a closed-loop bandwidth of
50MHz, then the output impedance at 50MHz must be
less than 100Ω. The second requirement is that the
closed-loop bandwidth must be greater than 20MHz to
ensure adequate small-signal settling for full throughput
rate. If slower op amps are used, more settling time can
beprovidedbyincreasingthetimebetweenconversions.
Suitable devices capable of driving the ADC’s inputs
include the LT®1360, LT1220, LT1223, LT1224 and
LT1227 op amps.
1
2
3
ANALOG
INPUT
+A
LTC1410
IN
–A
IN
R1
2k
V
REF
BANDGAP
REFERENCE
2.500V
+
–
4.06V
REFCOMP
4
R2
40k
10µF
0.1µF
AGND
5
R3
64k
The noise and the distortion of the input amplifier must
also be considered since they will add to the LTC1410
noise and distortion. The small-signal bandwidth of the
1410 F08a
Figure 8a. LTC1410 Reference Circuit
10
LTC1410
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APPLICATIONS INFORMATION
easily overdriven in applications where an external refer-
ence is required. The reference amplifier provides buffer-
ing between the internal reference and the capacitive DAC.
The reference amplifier compensation pin REFCOMP
(Pin 4), must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 1µF or
greater. For the best noise performance, a 10µF tantalum
in parallel with 0.1µF ceramic is recommended.
applied to A and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
IN
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
The VREF pin can be driven with an external reference
(Figure 8b), a DAC or other means to provide input span
adjustment. The VREF should be kept in the range of 2.25V
to 2.75V for specified linearity.
FS = 2.5V
2FS
100...001
100...000
1LSB =
4096
1
LSB
–1 0V
LSB
–FS
FS – LSB
5V
1
2
3
4
5
INPUT VOLTAGE, (+A ) – (–A ) (V)
+A
IN
IN
IN
ANALOG
INPUT
1410 F09
V
IN
–A
IN
LT1019A-2.5
Figure 9. LTC1410 Transfer Characteristics
V
OUT
V
REF
REFCOMP
AGND
0.1µF
10µF
–5V
ANALOG
INPUT
R3
47k
1
2
+A
IN
LTC1410
R1
50k
1410 F08b
R4
100Ω
–A
IN
3
4
R5 R2
47k 50k
V
Figure 8b. Using the LT1019-2.5 as an External Reference
REF
R6
24k
REFCOMP
AGND
Full-Scale and Offset Adjustment
5
0.1µF
10µF
Figure 9 shows the ideal input/output characteristics for
theLTC1410. Thecodetransitions occurmidwaybetween
successive integer LSB values (i.e., –FS + 0.5LSB,
–FS + 1.5LSB, – FS + 2.5LSB, . . . FS – 1.5LSB,
FS – 0.5LSB).The output is two’s complement binary
with 1LSB = [(+FS) – (–FS)]/4096 = 5V/4096 = 1.22mV.
LTC1410
1410 F10
Figure 10. Offset and Full-Scale Adjust Circuit
BOARD LAYOUT AND BYPASSING
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 10
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1410, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. Particular care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
applied to the –A input. For zero offset error apply
IN
–0.61mV (i.e., –0.5LSB) at +A and adjust the offset at
IN
the –A input until the output code flickers between 0000
IN
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS – 1.5LSBs) is
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LTC1410
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ADC data outputs and control signals are connected to a
continuously active microprocessor bus, it is possible to
get errors in the conversion results. These errors are due
tofeedthroughfromthemicroprocessortothesuccessive
approximation comparator. The problem can be elimi-
nated by forcing the microprocessor into a wait state
during conversion or by using three-state buffers to iso-
late the ADC data bus.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD, V and REFCOMP pins as
SS
shown in the Typical Application on the first page of this
data sheet. Bypass capacitors must be located as close to
the pins as possible. The traces connecting the pins and
bypass capacitors must be kept short and should be made
as wide as possible.
The LTC1410 has differential inputs to minimize noise
coupling. Common mode noise on the +A and –A
IN
IN
DIGITAL INTERFACE
leads will be rejected by the input CMRR. The –A input
IN
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
can be used as a ground sense for the +A input; the
LTC1410 will hold and convert the difference voltage
IN
between+A and–A .Theleads to+A (Pin1)and–A
IN
IN
IN
IN
(Pin 2) should be kept as short as possible. In applications
wherethis is notpossible,the+A and–A traces should
IN
IN
be run side by side to equalize coupling.
Internal Clock
A single point analog ground separate from the logic
system ground should be established with an analog
groundplaneatPin5(AGND)oras closeas possibletothe
ADC. Pin14andPin19(ADC’s DGND)andallotheranalog
grounds shouldbeconnectedtothis singleanalogground
point.Nootherdigitalgrounds shouldbeconnectedtothis
analog ground point. Low impedance analog and digital
power supply common returns are essential to low noise
operation of the ADC and the foil width for these tracks
should be as wide as possible. In applications where the
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.65µs and a maximum conversion time over the
full operating temperature range of 0.75µs. No external
adjustments are required. The guaranteed maximum ac-
quisition time is 100ns. In addition, throughput time of
800ns and a minimum sampling rate of 1.25Msps is
guaranteed.
1
+
A
IN
DIGITAL
SYSTEM
LTC1410
–
A
IN
+
–
2
V
AV DV DGND OGND
REFCOMP
4
AGND
ANALOG
INPUT
CIRCUITRY
SS
DD
28
DD
27
26
14
19
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF
1410 F11
Figure 11. Power Supply Grounding Practice
12
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Power Shutdown
Timing and Control
TheLTC1410provides twopowershutdownmodes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 95% and leaves only the
digitallogicandreferencepoweredup. Thewake-uptime
from Nap to active is 200ns. In Sleep mode all bias
currents are shut down and only leakage current re-
mains ––about 1µA. Wake-up time from Sleep mode is
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
appliedtotheCONVSTpinwillstartaconversionafterthe
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
Figures 14 through 18 show several different modes of
operation. In modes 1a and 1b (Figures 14 and 15) CS
and RD are both tied low. The falling edge of CONVST
starts theconversion.Thedataoutputs arealways enabled
and data can be latched with the BUSY rising edge. Mode
1a shows operation with a narrow logic low CONVST
pulse. Mode 1b shows a narrow logic high CONVST pulse.
NAP/SLP
t
3
SHDN
1410 F12a
Figure 12a. NAP/SLP to SHDN Timing
In mode 2 (Figure 16) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
SHDN
t
4
CONVST
1410 F12b
In slow memory and ROM modes (Figures 17 and 18) CS
is tiedlowandCONVSTandRDaretiedtogether. TheMPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
Figure 12b. SHDN to CONVST Wake-Up Timing
much slower since the reference circuit must power up
and settle to 0.01% for full 12-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
10ms with the recommended 10µF capacitor.
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low
forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
Shutdown is controlled by Pin 21 (SHDN), the ADC is in
shutdown when it is low. The shutdown mode is selected
with Pin 20 (NAP/SLP); high selects Nap.
CS
In ROM mode, the processor takes RD (= CONVST) low,
startingaconversionandreadingtheprevious conversion
result. Aftertheconversionis complete, theprocessorcan
read the new result and initiate another conversion.
t
2
CONVST
t
1
RD
1410 F12
Figure 13. CS to CONVST Setup Timing
13
LTC1410
APPLICATIONS INFORMATION
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t
CONV
CS = RD = 0
CONVST
t
5
t
t
8
6
BUSY
DATA
t
7
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
1410 F14
Figure 14. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
CS = RD = 0
t
8
CONV
t
t
13
5
CONVST
BUSY
t
t
6
6
t
7
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
DATA
1410 F15
Figure 15. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
13
t
t
8
CONV
t
5
CONVST
BUSY
RD
t
6
t
t
11
9
t
12
t
10
DATA N
DB11 TO DB0
DATA
1410 F16
Figure 16. Mode 2. CONVST Starts a Conversion. Data is Read by RD
14
LTC1410
O U
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PPLICATI
A
S I FOR ATIO
t
t
8
CONV
RD = CONVST
t
t
11
6
BUSY
t
t
7
10
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11-DB0
DATA
1410 F17
Figure 17. Slow Memory Mode Timing
t
t
8
CONV
RD = CONVST
t
t
11
6
BUSY
DATA
t
10
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
1410 F18
Figure 18. ROM Mode Timing
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G28 SSOP 0694
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.
15
LTC1410
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 – 0.712*
(17.70 – 18.08)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10 11 12 13 14
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.014 – 0.019
(0.356 – 0.482)
TYP
0.016 – 0.050
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S28 (WIDE) 0996
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
12-Bit Sampling A/D Converters
PART NUMBER
DESCRIPTION
COMMENTS
Lower Power and Cost Effective for f
LTC1273/75/76
Complete 5V Sampling 12-Bit ADCs
with 70dB SINAD at Nyquist
≤ 300ksps
SAMPLE
LTC1274/77
LTC1278/79
LTC1282
Low Power 12-Bit ADCs with Nap
and Sleep Mode Shutdown
Lowest Power for f
≤ 100ksps
SAMPLE
High Speed Sampling 12-Bit ADCs
with Shutdown
Cost Effective 12-Bit ADCs –– Best for 2-Pair HDSL,
≤ 500ksps/600ksps
f
SAMPLE
Complete 3V 12-Bit ADCs with
12mW Power Dissipation
Fully Specified for 3V-Powered Applications, f
≤ 140ksps
SAMPLE
1410fa LT/TP 0399 2K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1995
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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