LTC1414CGN#TRPBF [Linear]
LTC1414 - 14-Bit, 2.2 Msps,Sampling A/D Converter; Package: SSOP; Pins: 28; Temperature Range: 0°C to 70°C;
| 型号： | LTC1414CGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1414 - 14-Bit, 2.2 Msps,Sampling A/D Converter; Package: SSOP; Pins: 28; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1414
14-Bit, 2.2Msps,
Sampling A/D Converter
U
FEATURES
DESCRIPTIO
The LTC®1414 is a 14-bit, 2.2Msps, sampling A/D con-
verter which draws only 175mW from ±5V supplies. This
high performance ADC includes a high dynamic range
sample-and-hold, a precision reference and requires no
external components.
■
Sample Rate: 2.2Msps
Outstanding Spectral Purity:
■
80dB S/(N + D) and 95dB SFDR at 100kHz
78dB S/(N + D) and 84dB SFDR at Nyquist
■
Ultralow Distortion with Single-Ended or
Differential Inputs
The LTC1414’s high performance sample-and-hold has a
full-scale input range of ±2.5V. Outstanding AC perfor-
mance includes 80dB S/(N + D) and 95dB SFDR with a
100kHzinput.TheperformanceremainshighattheNyquist
input frequency of 1.1MHz with 78dB S/(N + D) and 84dB
SFDR.
■
±2.5V Bipolar Input Range Eliminates Level Shifting
and Rail-to-Rail Op Amp Requirements
■
Easy Hookup for External or Internal Reference
■
No Pipeline Delay
■
Power Dissipation: 175mW on ±5V Supplies
■
28-Pin Narrow SSOP Package
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 40MHz
bandwidth. The 70dB common mode rejection can elimi-
nategroundloopsandcommonmodenoisebymeasuring
signal differentially from the source
U
APPLICATIO S
■
Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
■
■
The ADC has a microprocessor compatible, 14-bit parallel
output port. There is no pipline delay in the conversion
results.
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
OPTIONAL 3V
LOGIC SUPPLY
5V
Effective Bits and Signal-to-Noise + Distortion
vs Input Frequency
10µF
14
13
12
11
10
9
86
80
74
68
AV
DV
OV
DD
DD
DD
LTC1414
S/H
+
–
A
A
D13 (MSB)
D0 (LSB)
IN
14
•
•
•
OUTPUT
BUFFERS
14-BIT ADC
8
IN
7
4.0625V
BUFFER
6
COMP
5
10µF
4
2k
BUSY
3
f
= 2.2MHz
2.5V
REFERENCE
TIMING AND
LOGIC
SAMPLE
V
REF
2
CONVST
1k
10k
100k
1M
10M
1µF
INPUT FREQUENCY (Hz)
V
SS
AGND
OGND
DGND
1414 TA02
1414 TA01
10µF
–5V
1
LTC1414
W W U W
U
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
AVDD = OVDD = DVDD = VDD (Notes 1, 2)
TOP VIEW
ORDER PART
Supply Voltage (VDD)................................................. 6V
Negative Supply Voltage (VSS) ................................ –6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..........(VSS – 0.3V) to 10V
Digital Output Voltage........ (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1414C ............................................... 0°C to 70°C
LTC1414I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
+
NUMBER
1
2
AV
DD
28
27
26
25
24
23
22
21
20
19
18
17
A
A
IN
IN
–
AGND
LTC1414CGN
LTC1414IGN
3
V
V
SS
REF
4
BUSY
REFCOMP
AGND
D13 (MSB)
D12
5
CONVST
DGND
6
7
DV
DD
8
OV
DD
D11
9
D0
D1
D2
D3
D10
10
11
12
13
14
D9
D8
D7
16 D4
D5
D6
15
OGND
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 110°C/ W
Consult factory for Industrial, Military and A grade parts.
U
(Notes 5, 6)
CO VERTER
CHARACTERISTICS
LTC1414
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
13
(Note 7)
(Note 8)
±0.75
±0.75
±5
±2.0
LSB
±1.75
LSB
±20
±24
LSB
LSB
●
Full-Scale Error
Internal Reference
External Reference = 2.5V
±10
±5
±60
±25
LSB
LSB
Full-Scale Tempco
Internal Reference
External Reference = 2.5V
±15
±1
ppm/°C
ppm/°C
U
U
(Note 5)
A ALOG I PUT
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Analog Input Range
4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –4.75V
●
●
±2.5
IN
DD
SS
I
Analog Input Leakage Current
Analog Input Capacitance
Between Conversions
±1
µA
IN
C
Between Conversions
During Conversions
8
4
pF
pF
IN
t
t
t
Sample-and-Hold Acquisition Time
●
40
–1
3
100
ns
ns
ACQ
AP
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
ps
jitter
RMS
–
+
CMRR
–2.5V < (A = A ) < 2.5V
70
dB
IN
IN
2
LTC1414
W
U
(Note 5)
DY
A IC
ACCURACY
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
100kHz Input Signal
1.1MHz Input Signal
80
78
dB
dB
THD
SFDR
IMD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
1.1MHz Input Signal, First 5 Harmonics
–95
–83
dB
dB
Spurious Free Dynamic Range
100kHz Input Signal, First 5 Harmonics
1.1MHz Input Signal, First 5 Harmonics
95
84
dB
dB
Intermodulation Distortion
Full Power Bandwidth
Full Linear Bandwidth
f
= 29.37kHz, f = 32.446kHz
–86
40
3
dB
MHz
MHz
IN1
IN2
S/(N + D) ≥ 74dB
U U
U
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
2.500
±15
MAX
UNITS
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
I
I
= 0
= 0
2.480
2.520
REF
REF
REF
OUT
OUT
ppm/°C
4.75V ≤ V ≤ 5.25V
–5.25V ≤ V ≤ –4.75V
0.01
0.01
LSB/V
LSB/V
DD
SS
V
Output Resistance
I
≤ 0.1mA
OUT
2
kΩ
REF
COMP Output Voltage
I
= 0
4.06
V
OUT
U
U
(Note 5)
DIGITAL I PUTS AND OUTPUTS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
1.2
IN
V
V
= 4.75V, I = –10µA
= 4.75V, I = –200µA
4.74
V
V
OH
DD
DD
O
O
●
●
4.0
V
Low Level Output Voltage
V
V
= 4.75V, I = 160µA
= 4.75V, I = 1.6mA
0.05
0.10
V
V
OL
DD
DD
O
O
0.4
I
I
Output Source Current
Output Sink Current
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
= V
DD
U
W
(Note 5)
POWER REQUIRE E TS
SYMBOL PARAMETER
CONDITIONS
(Note 9)
MIN
TYP
MAX
UNITS
V
V
DD
V
SS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
4.75
5.25
–5.25
16
(Note 9)
–4.75
V
I
I
CS High
●
●
12
23
mA
mA
mW
DD
SS
CS High
30
P
D
175
230
3
LTC1414
W U
(Note 5)
TI I G CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
2.2
TYP
MAX
UNITS
MHz
ns
f
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
●
SAMPLE(MAX)
220
330
40
400
100
454
CONV
Acquisition Time
ns
ACQ
Throughput Time (Acquisition + Conversion)
CONVST to BUSY Delay
Data Ready Before BUSY↑
Delay Between Conversions
CONVST Low Time
370
10
ns
THROUGHPUT
C = 25pF
L
ns
1
2
3
4
5
6
±20
ns
(Note 9)
●
●
●
100
40
ns
(Note 10)
(Note 10)
ns
CONVST High Time
40
ns
Aperture Delay of Sample-and-Hold
–1
ns
Note 6: Linearity, offset and full-scale specifications apply for a single-
The
● denotes specifications which apply over the full operating
+
–
ended A input with A grounded.
temperature range; all other limits and typicals T = 25°C.
IN
IN
A
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below V or above V , they
will be clamped by internal diodes. This product can handle input currents
SS
DD
Note 9: Recommended operating conditions.
greater than 100mA below V or above V without latchup.
SS
DD
Note 10: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 225ns after the
start of the conversion or after BUSY rises.
Note 4: When these pin voltages are taken below V , they will be clamped
by internal diodes. This product can handle input currents greater than
SS
100mA below V without latchup. These pins are not clamped to V
.
SS
DD
Note 5: V = 5V, V = –5V, f
= 2.2MHz and t = t = 5ns unless
r f
DD
SS
SAMPLE
otherwise specified.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Signal-to-Noise Ratio vs Input
Frequency
S/(N + D) vs Input Frequency
Distortion vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
14
13
12
11
10
9
90
80
70
60
50
40
30
20
10
0
86
80
74
68
8
THD
7
6
5
3rd
4
2nd
3
f
= 2.2MHz
10k
SAMPLE
2
10k
100k
1M
10M
10k
100k
1M
10M
1k
100k
1M
10M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1414 TA02
1414 G03
1414 G02
4
LTC1414
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Spurious-Free Dynamic Range vs
Differential Nonlinearity vs
Output Code
Input Frequency
Intermodulation Distortion Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2.0
1.0
0
–20
f
f
f
= 2.2MHz
= 80.566kHz
= 97.753kHz
SAMPLE
IN1
IN2
–40
0
–60
–80
–1.0
–2.0
–100
–120
10k
100k
1M
10M
0
4096
8192
OUTPUT CODE
12288
16384
0
200
400
600
800
1000
INPUT FREQUENCY (Hz)
FREQUENCY (kHz)
1414 G04
1414 G06
1414 F05a
Integral Nonlinearity vs Output
Code
Power Supply Feedthrough vs
Ripple Frequency
Input Common Mode Rejection vs
Input Frequency
2.0
1.0
80
70
60
50
40
30
20
10
0
0
–20
V
V
(V
= 0.02V)
= 0.2V)
SS RIPPLE
(V
DD RIPPLE
OGND (V
DD RIPPLE
= 0.5V)
= 0.5V)
RIPPLE
OV (V
–40
0
–60
–80
–1.0
–2.0
–100
–120
0
4096
8192
12288
16384
1k
10k
100k
1M
10M
0
2M
4M
6M
8M
10M
INPUT FREQUENCY (Hz)
OUTPUT CODE
RIPPLE FREQUENCY (Hz)
1414 G07
LTC1414 • F12
1414 G08
U
U
U
PIN FUNCTIONS
+
AIN (Pin 1): Positive Analog Input. ±2.5V input range
OGND (Pin 14): Digital Ground for the Output Drivers. Tie
to AGND
whenAIN– isgrounded. ±2.5VdifferentialifAIN– isdriven
+
differentially with AIN
.
D5 to D0 (Pins 15 to 20): Data Outputs.
–
AIN (Pin 2): Negative Analog Input. Can be grounded or
OVDD (Pin21):PositiveSupplyfortheOutputDrivers. Tie
toPin28whendriving5Vlogic. For3Vlogic, tietosupply
of the logic being driven.
+
driven differentially with AIN
.
VREF (Pin 3): 2.5V Reference Output.
REFCOMP (Pin 4): 4.06V Reference Bypass Pin.
Bypass to AGND with 10µF ceramic or 10µF tantalum in
parallel with 0.1µF ceramic.
DVDD (Pin 22): 5V Positive Supply. Tie to Pin 28.
DGND (Pin 23): Digital Ground. Tie to AGND.
CONVST(Pin24):ConversionStartSignal.Thisactivelow
signal starts a conversion on its falling edge.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Data Outputs.
5
LTC1414
U
U
U
PIN FUNCTIONS
BUSY (Pin 25): The BUSY Output Shows the Converter
AGND (Pin 27): Analog Ground.
Status. It is low when a conversion is in progress.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with
10µF ceramic or 10µF tantalum in parallel with 0.1µF
ceramic.
V
SS (Pin 26): –5V Negative Supply. Bypass to AGND with
10µF ceramic or 10µF tantalum in parallel with 0.1µF
ceramic.
U
U
W
FUNCTIONAL BLOCK DIAGRA
C
C
SAMPLE
+
A
IN
AV
DD
SAMPLE
DV
DD
–
A
IN
V
SS
2k
ZEROING SWITCHES
V
2.5V REF
REF
+
REF AMP
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
(4.06V)
OV
DD
14
D13
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT
LATCHES
•
•
•
D0
AGND
DGND
OGND
INTERNAL
CLOCK
CONTROL LOGIC
CONVST
1414 BD
BUSY
W U
W
TI I G DIAGRA
t
CONV
t
t
5
4
CONVST
BUSY
t
t
1
3
t
2
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
1414 TD
6
LTC1414
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APPLICATIONS INFORMATION
CONVERSION DETAILS
+
–
C
SAMPLE
SAMPLE
SAMPLE
+
–
A
A
IN
ZEROING SWITCHES
The LTC1414 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The device is easy to interface with microprocessors and
DSPs. (Please refer to the Digital Interface section for the
data format.)
HOLD
C
SAMPLE
HOLD
HOLD
IN
HOLD
+
C
DAC
+
–
–
C
DAC
COMP
+
V
DAC
Conversion start is controlled by the CONVST input. At the
start of the conversion the successive approximation
register(SAR)isreset. Onceaconversioncyclehasbegun
it cannot be restarted.
–
14
V
DAC
D13
OUTPUT
LATCH
SAR
D0
1414 F01
Figure 1. Simplified Block Diagram
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
Signal-to-Noise Ratio
connected to the sample-and-hold capacitors (CSAMPLE
)
The signal-to-(noise + distortion) ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 2a shows a typical spectral content with
a 2.2MHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 1.1MHz. (See Figure 2b)
during the acquire phase, and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 70ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
Duringtheconvertphasethecomparatorzeroingswitches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summingjunction. Thisinputchargeissuccessivelycom-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 14-bit output latches.
0
SINAD = 80dB
SFDR = 96dB
–20
f
f
= 2.2MHz
= 97.753kHz
SAMPLE
IN
–40
–60
–80
–100
–120
DYNAMIC PERFORMANCE
The LTC1414 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1414 FFT plot.
0
200
400
600
800
1000
FREQUENCY (kHz)
1414 F02a
Figure 2a. LTC1414 Nonaveraged, 2048 Point FFT,
Input Frequency = 100kHz
7
LTC1414
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APPLICATIONS INFORMATION
14
13
12
11
10
9
86
80
74
68
0
SINAD = 78dB
SFDR = 84dB
–20
f
f
= 2.2MHz
= 997.949kHz
SAMPLE
IN
–40
–60
8
7
6
–80
5
4
–100
–120
3
f
= 2.2MHz
10k
SAMPLE
2
1k
100k
1M
10M
0
200
400
600
800
1000
INPUT FREQUENCY (Hz)
FREQUENCY (kHz)
1414 TA02
1414 F02b
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
Figure 2b. LTC1414 2048 Point FFT,
Input Frequency = 1MHz
0
–10
–20
–30
–40
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
–50
THD
–60
ENOBS = [S/(N + D) – 1.76]/6.02
–70
–80
2nd
where S/(N + D) is expressed in dB. At the maximum
samplingrateof2.2MHztheLTC1414maintainsnearideal
ENOBsuptotheNyquistinputfrequencyof1.1MHz. Refer
to Figure 3.
–90
3rd
–100
1
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
1414 F04
Figure 4. Distortion vs Input Frequency
Total Harmonic Distortion
Intermodulation Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
the THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
2
2
2
2
V + V + V +…V
N
2
3
4
THD = 20log
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3
etc. Forexample, the2ndorderIMDtermsinclude(fa ±fb).
If the two input sine waves are equal in magnitude, the
value (in dB) of the 2nd order IMD products can be
expressed by the following formula:
V
1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
secondthrough Nth harmonics. THD vsinputfrequency is
shown in Figure 4. The LTC1414 has good distortion
performance up to the Nyquist frequency and beyond.
8
LTC1414
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APPLICATIONS INFORMATION
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 74dB (12 effective bits). The
LTC1414 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far be-
yond Nyquist.
amplitude at f ± f
(
)
a
b
IMD f ± f = 20log
(
)
a
b
amplitude at f
a
0
f
f
f
= 2.2MHz
= 80.566kHz
= 97.753kHz
SAMPLE
IN1
IN2
–20
–40
Driving the Analog Input
–60
The differential analog inputs of the LTC1414 are easy to
drive.Theinputsmaybedrivendifferentiallyorasasingle-
–80
–
endedinput(i.e.,theAIN inputisgrounded).TheAIN+ and
–100
–120
–
AIN inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low then the LTC1414
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts(settlingtimemustbe70nsforfullthroughputrate).
0
200
400
600
800
1000
FREQUENCY (kHz)
1414 F05a
Figure 5a. Intermodulation Distortion Plot
with Inputs at 80kHz and 97kHz
0
f
f
f
= 2.2MHz
SAMPLE
= 970.019kHz
= 1.492MHz
IN1
IN2
–20
–40
–60
–80
–100
–120
0
200
400
600
800
1000
10
FREQUENCY (kHz)
1414 F05b
Figure 5b. Intermodulation Distortion Plot
with Input Signals of 1MHz and 1.5MHz
1
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in dB relative to the RMS value of a full-
scale input signal.
0.1
0.01
10
100
1k
10k
100k
SOURCE RESISTANCE (Ω)
Full-Power and Full-Linear Bandwidth
1414 FO6
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3db for a full-scale input signal.
Figure 6. Acquisition Time vs Source Resistance
9
LTC1414
U
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APPLICATIONS INFORMATION
Choosing an Input Amplifier
AC Coupled Inputs
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth
must be greater than 40MHz to ensure adequate small-
signal settling for full throughput rate. If slower op amps
areused, moresettlingtimecanbeprovidedbyincreasing
the time between conversions.
InapplicationswhereonlytheACcomponentoftheanalog
input is important, it may be desirable to AC couple the
input. This is easily accomplished by DC biasing the
LTC1414 analog input with a resistor to ground and using
a coupling capacitor to the input. Figure 7 shows a simple
AC coupled input circuit for the LTC1414 using only two
additional components. C1 is a 10µF ceramic capacitor
and R1 is a 1000Ω resistor to ground. R1 and C1 form a
highpassfilterwithalowercutofffrequencyof1/2π(C1)R1
or 15.9Hz.
C1
10µF
1
+
–
A
ANALOG INPUT
IN
R1
1k
The best choice for an op amp to drive the LTC1414 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifica-
tionsaremostcriticalandtimedomainapplicationswhere
DC accuracy and settling time are most critical. The
followinglistisasummaryoftheopampsthataresuitable
for driving the LTC1414. More detailed information is
available in the Linear Technology Databooks and on the
LinearViewTM CD-ROM.
2
3
A
V
IN
LTC1414
REF
1µF
4
5
REFCOMP
AGND
10µF
LTC1414 • F07
Figure 7. AC Coupled Input
LT®1223: 100MHz Video Current Feedback Amplifier.
6mA supply current. ±5V to ±15V supplies. Low noise.
Good for AC applications.
Differential Drive
In some applications the ADC drive circuitry is differential.
ThedifferentialdrivecanbeapplieddirectlytotheLTC1414
without any special translation circuitry. Differential drive
can be advantageous at high frequencies (>1MHz) since it
provides improved THD and SFDR. Transformers can be
used to provide AC coupling, input scaling and single
ended to differential conversion as shown in Figure 8. The
resistor RS across the secondary will determine the input
impedance on the primary. The input impedance of the
primaryRP willberelatedtothesecondaryloadresistorRS
by the equation
LT1227:140MHzVideoCurrentFeedbackAmplifier.10mA
supply current. ±5V to ±15V supplies. Low noise. Best for
AC applications.
LT1229/LT1230: Dual and Quad 100MHz Current Feed-
back Amplifiers. ±2V to ±15V supplies. Low noise. Good
AC specifications, 6mA supply current each amplifier.
LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA sup-
plycurrent.GoodACandDCspecs.±5Vto±15Vsupplies.
70ns settling to 0.5LSB.
RP = RS/n2
LT1363: 70MHz, 1000V/µs Op Amps. 6.3mA supply cur-
rent. Good AC and DC specifications. 60ns settling to
0.5LSB.
For example, if a Minicircuits T4-6T transformer is used,
the turns ratio is 2; if RS is 200Ω then RP is equal to 50Ω.
The center tap of the secondary will set the common
mode voltage and should be grounded for optimal AC
performance.
LT1364/LT1365: Dual and Quad 70MHz, 1000V/µs Op
Amps. 6.3mA supply current per amplifier. 60ns settling
to 0.5LSB.
LinearView is a trademark of Linear Technology Corporation.
10
LTC1414
U
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APPLICATIONS INFORMATION
R1
Input Range
50Ω
1:N
1
+
R
A
P
IN
C1
ANALOG
INPUT
R
The±2.5VinputrangeoftheLTC1414isoptimizedforlow
noise and low distortion. Most op amps also perform best
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
S
500pF
2
3
–
A
V
IN
R2
LTC1414
50Ω
REF
1µF
4
5
REFCOMP
AGND
10µF
Some applications may require other input ranges. The
LTC1414 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
LTC1414 • F08
Figure 8. If a Transformer Coupled Input is Required,
this Circuit Provides a Simple Solution
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1414 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 40MHz. Any noise
ordistortionproductsthatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.
Internal Reference
The LTC1414 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmedto2.500V.Itisconnectedinternallytoareference
amplifier and is available at VREF (Pin 3), see Figure 10. A
2k resistor is in series with the output so that it can be
easily overdriven by an external reference or other cir-
cuitry. The reference amplifier multiplies the voltage at the
VREF pin by 1.625 to create the required internal reference
voltage. This provides buffering between the VREF pin and
the high speed capacitive DAC. The reference amplifier
compensation pin, REFCOMP (Pin 4) must be bypassed
with a capacitor to ground. The reference amplifier is
stable with capacitors of 1µF or greater. For the best noise
performance, a 10µF ceramic or 10µF tantalum in parallel
with a 0.1µF ceramic is recommended.
+
For example, Figure 9 shows a 500pF capacitor from AIN
to ground and a 100Ω source resistor to limit the input
bandwidth to 3.2MHz. The 500pF capacitor also acts as a
charge reservoir for the input sample-and-hold and iso-
lates the ADC input from sampling glitch-sensitive cir-
cuitry. High quality capacitors and resistors should be
used since poor quality components can add distortion.
NPO and silver mica type dielectric capacitors have excel-
lent linearity. Carbon surface mount resistors can also
generate distortion from self heating and from damage
thatmayoccurduringsoldering. Metalfilmsurfacemount
resistors are much less susceptible to both problems.
R1
2k
V
3
4
REF
BANDGAP
REFERENCE
2.500V
+
100Ω
REFCOMP
1
+
REFERENCE
A
INPUT
4.0625V
IN
AMP
500pF
–
2
3
4
5
–
A
IN
R2
40k
10µF
LTC1414
V
R3
64k
REF
AGND
5
LTC1414
REFCOMP
AGND
1414 F10
10µF
Figure 10. LTC1414 Reference Circuit
LTC1414 • F09
Figure 9. An RC Filter Reduces the ADC’s 40MHz
Bandwidth to 3.2MHz and Filters Out Wideband Noise
Which May Be Present in the Input Signal
11
LTC1414
U
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APPLICATIONS INFORMATION
80
70
60
50
40
30
20
10
0
The VREF pin can be driven with a DAC or other means
showninFigure11.Thisisusefulinapplicationswherethe
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1414 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed after a reference adjustment.
1
2
3
4
5
+
A
A
V
IN
ANALOG INPUT
±2V TO ±3V
1k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
DIFFERENTIAL
–
IN
LTC1414 • F12
LTC1414
Figure 12. CMRR vs Input Frequency
2V TO 3V
LTC1450
REF
The output is two’s complement binary with
1LSB = FS – (–FS)/16384 = 5V/16384 = 305.2µV.
REFCOMP
AGND
10µF
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 14
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
1414 F11
Figure 11. Driving VREF with a DAC
Differential Inputs
–
applied to the AIN input. For zero offset error apply
+
–152µV (i.e., –0.5LSB) at AIN and adjust the offset at the
The LTC1414 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
–
AIN input until the output code flickers between 0000
+
–
0000 0000 00 and 1111 1111 1111 11. For full-scale
adjustment, aninputvoltageof2.499544V(FS–1.5LSBs)
convert the difference of AIN – (AIN ) independent of the
common mode voltage. The common mode rejection
holdsuptoextremelyhighfrequencies, seeFigure12. The
only requirement is that neither input can exceed the AVDD
or AVSS power supply voltages. Integral nonlinearity er-
rors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
mode voltage. THD will degrade as the inputs approach
either power supply rail, from –84dB with a common
mode of 0V to –75dB with a common mode of 2.5V
or –2.5V.
+
is applied to AIN and R2 is adjusted until the output
code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
011…111
011…110
011…101
000…000
111…111
100…010
100…001
100…000
Full-Scale and Offset Adjustment
–(FS – 1LSB)
0
FS – 1LSB
INPUT RANGE
Figure 13 shows the ideal input/output characteristics for
theLTC1414. Thecodetransitionsoccurmidwaybetween
successive integer LSB values (i.e., –FS + 0.5LSB,
–FS+1.5LSB,–FS+2.5LSB,...FS–2.5LSB,FS–1.5LSB).
LTC1414 • F13
Figure 13. LTC1414 Transfer Characteristics
12
LTC1414
U
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APPLICATIONS INFORMATION
–5V
The LTC1414 has differential inputs to minimize noise
R3
1
2
3
4
5
+
ANALOG INPUT
A
A
V
24k
+
–
IN
coupling. Common mode noise on the AIN and AIN
R1
50k
–
R4
100Ω
inputs will be reflected by the input CMRR. The AIN input
–
IN
+
can be used as a ground sense for the AIN input; the
LTC1414
R5 R2
47k 50k
LTC1414 will hold and convert the difference voltage
REF
+
–
+
–
between AIN and AIN . The leads to AIN (Pin 1) and AIN
R6
24k
(Pin 2) should be kept as short as possible. In applications
REFCOMP
AGND
+
–
where this is not possible, the AIN and AIN traces should
be run side by side to equalize coupling.
10µF
LTC1414 • F14
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at AGND (Pin 5, 27) or as close as possible
to the ADC (see Figure 8). The ADC’s DGND (Pin 23) and
all other analog grounds should be connected to this
single analog ground point. No other digital grounds
should be connected to this analog ground point. Low
impedance analog and digital power supply common
returnsareessentialtolownoiseoperationoftheADCand
these traces should be as wide as possible. Excessive
capacitive loading on the ADC’s data output lines can
generate large transient currents on the ADC supplies
which may affect conversion results. In these cases, the
use of digital buffers is recommended to isolate the ADC
from the excessive loading.
Figure 14. Offset and Full-Scale Adjust Circuit
Board Layout and Bypassing
To obtain the best performance from the LTC1414, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital line alongside an analog signal line or underneath
the ADC. The analog input should be screened by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD, VSS and VREF pins. Bypass
capacitorsmustbelocatedasclosetothepinsaspossible.
The traces connecting the pins and bypass capacitors
must be kept short and should be made as wide as
possible.
EXAMPLE LAYOUT
Figures 16a, 16b, 16c and 16d show the schematic and
layoutofanevaluationboard.Thelayoutdemonstratesthe
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
1
+
DIGITAL
SYSTEM
LTC1414
A
IN
–
A
IN
REFCOMP
4
AGND
5, 27
V
AV
DV
OV
DGND OGND
SS
DD
28
DD
22
DD
21
ANALOG
INPUT
CIRCUITRY
2
26
10µF
23
14
+
–
10µF
10µF
ANALOG GROUND PLANE
1414 F15
Figure 15. Power Supply Grounding Practice
13
LTC1414
APPLICATIONS INFORMATION
U
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V
V
SS
V
V
LOGIC
CC
CC
R14
J2
GND
J3
5V
J1
20Ω
–5V
C2
+
D2
SS12
C2
22µF
10V
D1
SS12
0.125W
22µF
+
10V
AGND
DGND
+
C10
10µF
10V
C14
0.1µF
C12
0.1µF
C7
0.1µF
V
CC
DGND
J9
J4
C4
0.1µF
JP3
V
OUT
JP2
+
+
V
V
V
V
U3
LT1363
6
U1
LT1363
–
6
7
4
7
4
+
A
2
2
U5
R15
51Ω
–
R17
10k
74HC574
3
–
3
–
1
11
2
3
4
5
6
7
8
+
+
0E
B[00:13]
D[00:13]
8
1
SO-8
8
1
DIP-8
C11
470pF
19
18
17
16
15
14
13
12
B00
B01
B02
B03
B04
B05
B08
D00
D01
D02
D03
D04
D05
D08
R18
10k
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
JP4
(OPTIONAL)
J5
–
A
R16
51Ω
U4
C3
0.1µF
LTC1414CGN
V
SS
1
2
3
6
7
8
9
B13
B12
B11
B10
+
(MSB)D13
A
A
V
J10
IN
9
–
D12
D11
D10
D9
IN
V
REF
REF
4
U6
REFCOMP
BUSY
CONVST
DGND
25
24
23
22
21
28
26
27
5
10 B09
11 B08
12 B07
13 B06
15 B05
16 B04
17 B03
18 B02
19 B01
20 B00
74HC574
1
11
2
3
4
5
6
7
8
D8
D7
D6
D5
D4
D3
D2
D1
0E
C8
1µF
10V
C13
4.7µF
B07
B06
B09
B10
B11
B12
B13
19 D07
18 D06
17 D09
16 D10
15 D11
14 D12
13 D13
12
J8
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
OV
OV
AV
V
DD
CC
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D13
RDY
DGND
DGND
J6-13
J6-14
J6-11
J6-12
J6-9
10V
DD
DD
V
SS
J7
CLK
AGND
AGND
OGND
V
SS
R19
51Ω
14
J6-10
J6-7
D0
9
J6-8
C5
1µF
C9
1µF
C15
1µF
J6-5
DGND
J6-6
U7G, HC14
10V
10V
10V
D13 D10
D11
J6-3
14
7
U7E, HC14
V
LOGIC
PWR GND
J6-4
D12
D13
D13
RDY
11
10
J6-1
DGND
12
J6-2
R21
1k
J6-15
J6-16
J6-17
J6-18
DATA READY
13
U7F, HC14
9
8
C6
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5%
2. ALL CAPACITOR VALUES IN µF, 25V, 20% AND IN pF, 50V, 10%
U7D, HC14
15pF
HEADER
18-PIN
1414 F16a
Figure 16a. Evaluation Circuit Schematic
14
LTC1414
U
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APPLICATIONS INFORMATION
Figure 16b. Evaluation Circuit Board Component Side Silkscreen
15
LTC1414
APPLICATIONS INFORMATION
U
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Figure 16c. Evaluation Circuit Board Component Side Layout
16
LTC1414
U
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APPLICATIONS INFORMATION
Figure 16d. Evaluation Circuit Board Solder Side Layout
17
LTC1414
U
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APPLICATIONS INFORMATION
Digital Interface
The output data is updated at the end of the conversion as
BUSY rises. Output data is updated coincident with the
rising edge of BUSY. Data will be valid, and can be latched,
20ns after the rising edge of BUSY. Valid data can also be
latched with the falling edge of BUSY or with the rising
edge of CONVST. In the latter two cases the data latched
will be for the previous conversion.
The A/D converter has just one control input CONVST.
Data is output on 14-bit parallel bus. An additional output
BUSY indicates the converter status.
DIGITAL OUTPUTS
TheparalleldigitaloutputsoftheLTC1414aredesignedto
interface to TTL and CMOS logic. The output data is two’s
complement coded.
CONVST Drive Considerations
Timing jitter of the CONVST signal can adversely affect the
noise performance of the LTC1414 when the input signal
contains high slew rate components. The falling edge of
CONVST determines the sampling instant. Any uncer-
tainty in this sampling instant will translate to voltage
noise when a fast changing input signal is being sampled.
For a full amplitude sinusoidal input, the relationship
between timing jitter (tjitter) and SNRj is
The output drivers have a separate power pin (OVDD) and
ground pin (OGND). This allows relatively noisy output
ground and the output supply bypass ground to be sepa-
rated from the other ADC grounds. Additionally, the OVDD
pin may be driven by the supply of the logic that is being
driven. For example, the OVDD supply may be 3V while
LTC1414 DVDD and AVDD pins are 5V, allowing 3V logic to
be driven directly.
SNRj = 20log(1/2π • fIN • tjitter
)
Care should be taken to not load the digital outputs with
excessive capacitance. Large capacitive loads result in
large charging currents which can cause conversion er-
rors. It is recommended that the capacitive loading is kept
under 20pF. If it is not possible to keep the capacitance
low, a buffer or latch may be used to isolate the LTC1414
from the capacitive load.
where SNRj is the signal-to-jitter noise ratio.
The internal circuitry of the LTC1414 has been optimized
for ultralow jitter (typically 3ps RMS). The external clock
drive circuitry is equally important and must also have low
jitter to achieve low noise.
Internal Clock
Timing and Control
The internal clock is factory trimmed to achieve a typical
conversion time of 330ns and a maximum conversion
time over the full operating temperature range of 400ns.
No external adjustments are required. The guaranteed
maximumacquisitiontimeis100ns.Inaddition,athrough-
put time (acquisition + conversion) of 454ns and a mini-
mum sampling rate of 2.2Msps is guaranteed.
The conversion start is controlled by the CONVST input.
The falling edge of CONVST will start a conversion. Once
initiated, it cannot be restarted until the conversion is
complete. Converter status is indicated by the BUSY
output. BUSY is low during a conversion.
t
CONV
t
t
5
4
CONVST
BUSY
t
t
1
3
t
2
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
1414 F17
Figure 17. Timing Diagram
18
LTC1414
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP Narrow (0.150)
(LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
0.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.004 – 0.009
0.015 ± 0.004
(0.38 ± 0.10)
0.053 – 0.069
× 45°
(1.351 – 1.748)
(0.102 – 0.249)
0.0075 – 0.0098
(0.191 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.025
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
GN28 (SSOP) 0398
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
19
LTC1414
U
TYPICAL APPLICATIO
2.2MHz, 14-Bit Sampling ADC
5V
1
2
3
4
5
28
27
26
25
24
23
22
+
A
A
V
AV
DD
DIFFERENTIAL ANALOG INPUT
–2.5V TO 2.5V
IN
–5V
–
10µF
AGND
IN
10µF
LTC1414
V
SS
V
REF
OUT
2.5V
REF
REFCOMP
AGND
BUSY
CONVST
DGND
1µF
10µF
D13 (MSB)
D12
6
7
0.1µF
DV
DD
5V
D11
8
21
20
19
18
17
16
15
OV
DD
D10
9
D0
D1
D2
D3
D4
D5
D9
10
11
12
13
14
D8
14-BIT
PARALLEL
BUS
D7
D6
OGND
1414 TA03
RELATED PARTS
PART NUMBER
LTC1412
LTC1415
LTC1416
LTC1417
LTC1418
LTC1419
LTC1604
LT1460
DESCRIPTION
COMMENTS
Low Power, 12-Bit ,3Msps, ADC
Single 5V, 12-Bit, 1.25Msps, ADC
Low Power, 14-Bit, 400ksps, ADC
Nyquist Sampling, 150mW, 72dB SINAD
Single Supply, 55mW Dissipation
±5V Supplies, 75mW Dissipation
Very Low Power, 14-Bit, 400ksps, ADC
Very Low Power, 14-Bit, 200ksps, ADC
Low Power, 14-Bit, 800ksps, ADC
High Speed, 16-Bit, 333ksps, ADC
Micropower Precision Series Reference
20mW, 5V or ±5V Supply, Serial I/O in 16-Pin SSOP
15mW, 5V or ±5V Supply, Serial or Parallel I/O
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
90dB SINAD, –100dB THD, 220mW Dissipation
0.075% Accuracy, 10ppm/°C Drift
1414fs, sn1414 LT/TP 0399 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
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(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
相关型号：
LTC1414IGN
LTC1414 - 14-Bit, 2.2 Msps,Sampling A/D Converter; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
Linear
LTC1414IGN#PBF
LTC1414 - 14-Bit, 2.2 Msps,Sampling A/D Converter; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
Linear
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