LTC1416 [Linear]
Low Power 14-Bit, 400ksps Sampling ADC; 低功耗，14位， 400ksps采样ADC
| 型号： | LTC1416 |
| 厂家： | 
Linear |
| 描述： | Low Power 14-Bit, 400ksps Sampling ADC |
| 文件： | 总20页 (文件大小：509K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1416
Low Power 14-Bit, 400ksps
Sampling ADC
U
DESCRIPTIO
EATURE
Sample Rate: 400ksps
Power Dissipation: 70mW
Guaranteed ±1.5LSB DNL, ±2LSB INL (Max)
80.5dB S/(N + D) and 93dB THD at 100kHz
80dB S/(N + D) and 90dB THD at Nyquist
Nap and Sleep Shutdown Modes
S
F
The LTC®1416 is a 2.2µs, 400ksps, 14-bit sampling A/D
converter that draws only 70mW from ±5V supplies. This
easy-to-usedeviceincludesahighdynamicrangesample-
and-hold and a precision reference. Two digitally select-
able power shutdown modes provide flexibility for low
power systems.
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■
■
■
■
■
■
Operates with Internal or External Reference
True Differential Inputs Reject Common Mode Noise
15MHz Full Power Bandwidth Sampling
±2.5V Bipolar Input Range
The LTC1416’s full-scale input range is ±2.5V. Maximum
DC specifications include ±2LSB INL, ±1.5LSB DNL over
temperature.OutstandingACperformanceincludes80.5dB
S/(N + D) and 93dB THD with a 100kHz input, and 80dB
S/(N + D) and 90dB THD at the Nyquist input frequency of
200kHz.
28-Pin SSOP Package
O U
PPLICATI
A
S
The unique differential input sample-and-hold can ac-
quire single-ended or differential input signals up to its
15MHz bandwidth. The 60dB common mode rejection
allows users to eliminate ground loops and common
mode noise by measuring signals differentially from the
source.
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Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
The ADC has a µP compatible, 14-bit parallel output port.
There is no pipeline delay in the conversion results. A
separate convert start input and a data ready signal
(BUSY) ease connections to FIFOs, DSPs and micropro-
cessors.
Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Effective Bits and
Signal-to-(Noise + Distortion)
vs Input Frequency
Complete, 70mW, 14-Bit ADC with 80.5dB S/(N + D)
14
13
12
11
10
9
86
80
74
68
62
DV
AV
10µF
DD
DD
LTC1416
NYQUIST
FREQUENCY
14
+
A
IN
D13 (MSB)
D0 (LSB)
OUTPUT
BUFFERS
•
•
•
14-BIT ADC
S/H
–
8
7
A
IN
REFCOMP
22µF
6
5
4
3
2
1
BUFFER
4k
BUSY
CS
CONVST
RD
SHDN
TIMING
AND
LOGIC
2.5V
REFERENCE
V
REF
1µF
f
= 400kHz
10k
SAMPLE
V
0
SS
AGND
DGND
1416 TA01
1k
100k
1M 2M
INPUT FREQUENCY (Hz)
10µF
–5V
1416 TA02
1
LTC1416
W W W
U
/O
PACKAGE RDER I FOR ATIO
ABSOLUTE AXI U RATI GS
AVDD = DVDD = VDD (Notes 1, 2)
ORDER
TOP VIEW
Supply Voltage (VDD)................................................ 6V
Negative Supply Voltage (VSS)................................ –6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..........(VSS – 0.3V) to 10V
Digital Output Voltage....... (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation............................................. 500mW
Operating Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
PART NUMBER
+
A
A
1
2
3
4
5
6
7
8
9
28 AV
DD
IN
–
27 DV
IN
DD
LTC1416CG
LTC1416IG
V
26
V
SS
REF
REFCOMP
AGND
D13(MSB)
D12
25 BUSY
24 CS
23 CONVST
22 RD
D11
21 SHDN
20 D0
D10
D9 10
D8 11
19 D1
18 D2
D7 12
17 D3
D6 13
16 D4
DGND 14
15 D5
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
Consult factory for Military grade parts and for A grade parts.
U
CO VERTER
With Internal Reference (Notes 5, 6)
CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
13
(Note 7)
±0.8
±0.7
±5
±2
LSB
±1.5
±20
LSB
(Note 8)
LSB
Full-Scale Error
Internal Reference
External Reference = 2.5V
±20
±10
±60
±40
LSB
LSB
Full-Scale Tempco
I
= 0
±15
ppm/°C
OUT(REF)
U
U
(Note 5)
A ALOG I PUT
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Analog Input Range (Note 9)
4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –4.75V
●
●
±2.5
IN
DD
SS
I
Analog Input Leakage Current
Analog Input Capacitance
CS = High
±1
µA
IN
C
Between Conversions
During Conversions
15
5
pF
pF
IN
t
t
t
Sample-and-Hold Acquisition Time
(Note 9)
●
100
–1.5
2
400
ns
ns
ACQ
AP
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
ps
RMS
jitter
–
+
CMRR
–2.5V < (A = A ) < 2.5V
60
dB
IN
IN
2
LTC1416
U W
DY A IC ACCURACY (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal
200kHz Input Signal
●
●
●
77
80.5
80
dB
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
200kHz Input Signal, First 5 Harmonics
–93
–90
–86
–86
dB
dB
SFDR
IMD
Spurious-Free Dynamic Range
Intermodulation Distortion
Full Power Bandwidth
100kHz Input Signal
–95
–90
15
dB
dB
f
= 87.01172kHz, f = 113.18359kHz
IN2
IN1
MHz
MHz
Full Linear Bandwidth
(S/(N + D) ≥ 77dB)
0.8
U
U
U
I TER AL REFERE CE CHARACTERISTICS
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
2.500
±15
MAX
UNITS
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
I
I
= 0
= 0
2.480
2.520
REF
REF
REF
OUT
OUT
ppm/°C
4.75V ≤ V ≤ 5.25V
–5.25V ≤ V ≤ –4.75V
0.05
0.05
LSB/V
LSB/V
DD
SS
V
Output Resistance
–0.1mA ≤ I
≤ 0.1mA
OUT
4
kΩ
REF
COMP Output Voltage
I
= 0
4.06
V
OUT
U
U
(Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
V
= 4.75V
OH
DD
I
I
= –10µA
4.5
V
V
OUT
OUT
= –200µA
●
4.0
V
Low Level Output Voltage
= 4.75V
OL
DD
I
I
= 160µA
0.05
0.10
V
V
OUT
OUT
= 1.6mA
●
●
●
0.4
±10
15
I
Hi-Z Output Leakage D13 to D0
Hi-Z Output Capacitance D13 to D0
Output Source Current
= 0V to V , CS High
µA
pF
OZ
OUT
DD
C
CS High (Note 9 )
OZ
I
I
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
Output Sink Current
= V
DD
W U
POWER REQUIRE E TS
(Note 5)
SYMBOL PARAMETER
CONDITIONS
(Note 10)
MIN
4.75
TYP
MAX
5.25
UNITS
V
V
Positive Supply Voltage
Negative Supply Voltage
V
V
DD
SS
(Note 10)
–4.75
–5.25
I
Positive Supply Current
Nap Mode
●
●
7
0.8
1
10
mA
mA
µA
DD
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
1.2
Sleep Mode
I
Negative Supply Current
Nap Mode
7
20
15
10
mA
µA
µA
SS
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
Sleep Mode
3
LTC1416
W U
POWER REQUIRE E TS
(Note 5)
CONDITIONS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
P
Power Dissipation
Power Dissipation, Nap Mode
Power Dissipation, Sleep Mode
●
70
4
0.1
100
6
mW
mW
mW
DISS
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
W U
(Note 5, see Figures 15 to 21)
CONDITIONS
TI I G CHARACTERISTICS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
kHz
µs
f
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
●
●
●
●
400
1.5
SAMPLE(MAX)
1.9
100
2
2.2
400
2.5
CONV
Acquisition Time
(Note 9)
ns
ACQ
Acquisition + Conversion Time
CS to RD Setup Time
µs
ACQ+CONV
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
0
ns
1
2
3
4
5
6
CS↓ to CONVST↓ Setup Time
CS↓ to SHDN↓ Setup Time
SHDN↑ to CONVST↓ Wake-Up Time
CONVST Low Time
10
10
ns
ns
400
ns
(Notes 10, 11)
●
●
40
ns
CONVST to BUSY Delay
C = 25pF
L
25
ns
ns
50
t
Data Ready Before BUSY↑
75
50
100
ns
ns
7
●
●
●
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 10)
40
ns
ns
8
–5
9
C = 25pF
L
15
20
8
25
35
ns
ns
10
●
●
C = 100pF
L
35
50
ns
ns
t
Bus Relinquish Time
20
25
30
ns
ns
ns
11
0°C ≤ T ≤ 70°C
●
●
A
–40°C ≤ T ≤ 85°C
A
t
t
RD Low Time
●
●
t
ns
ns
12
13
10
CONVST High Time
40
The
●
denotes specifications which apply over the full operating
Note 6: Linearity, offset and full-scale specifications apply for a single-
+
–
temperature range; all other limits and typicals at T = 25°C.
ended A input with A grounded.
A
IN IN
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 900ns after the
start of the conversion or after BUSY rises.
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V or above V , they
SS
DD
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V or above V without latchup.
SS
DD
Note 4: When these pin voltages are taken below V , they will be clamped
SS
by internal diodes. This product can handle input currents greater than
100mA below V without latchup. These pins are not clamped to V
.
SS
DD
Note 5: V = 5V, V = –5V, f
= 400kHz, t = t = 5ns unless
r f
DD
SS
SAMPLE
otherwise specified.
4
LTC1416
U W
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio
vs Input Frequency
Distortion vs Input Frequency
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
= 0dB
IN
IN
V
= –20dB
V
= –60dB
IN
3RD
THD
2ND
1k
10k
100k
1M 2M
1k
1k
10k
100k
1M 2M
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1416 G02
1416 G01
1416 G03
Spurious-Free Dynamic Range
vs Input Frequency
Differential Nonlinearity
vs Output Code
Intermodulation Distortion Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1.0
0.5
0
–20
f
= 400kHz
V
= ±2.5V
= 2.5V
SAMPLE
OUT
REF
f =87.01171876kHz
a
V
f =113.1835938kHz
b
–40
–60
0
–80
–100
–120
–140
–0.5
–1.0
1k
10k
100k
1M 2M
8192
12288
0
60
100
120 140 160 180 200
0
16384
20 40
80
4096
INPUT FREQUENCY (Hz)
FREQUENCY (Hz)
OUTPUT CODE
1416 G04
1416 G05
1416 G06
Integral Nonlinearity
vs Output Code
Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
80
70
60
50
40
30
20
10
0
1.0
0.5
V
= ±2.5V
= 2.5V
OUT
REF
V
0
DGND (V = 100mV)
IN
–0.5
–1.0
V (V = 10mV)
SS IN
V
(V = 10mV)
DD IN
1k
10k
100k
1M 2M
1k
10k
100k
1M 2M
8192
12288
0
16384
4096
RIPPLE FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
OUTPUT CODE
1416 G08
1416 G09
1416 G07
5
LTC1416
U U
U
PI FU CTIO S
+
A
A
V
(Pin 1): ±2.5V Positive Analog Input.
(Pin 2): ±2.5V Negative Analog Input.
(Pin 3): 2.5V Reference Output. Bypass to AGND
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
IN
–
IN
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
is valid on the rising edge of BUSY.
REF
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 22µF tantalum in parallel with 0.1µF
ceramic, or 22µF ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
V
(Pin 26): –5V Negative Supply. Bypass to AGND
SS
AGND.
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs.
DV (Pin 27): 5V Positive Supply. Tie to Pin 28.
DD
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
AV (Pin 28): 5V Positive Supply. Bypass to AGND
DD
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
U
U
W
FU CTIO AL BLOCK DIAGRA
C
C
SAMPLE
SAMPLE
+
A
IN
AV
DD
DV
DD
–
A
V
IN
SS
4k
ZEROING SWITCHES
V
2.5V REF
REF AMP
REF
+
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
(4.06V)
14
D13
D0
SUCCESSIVE APPROXIMATION
REGISTER
•
•
•
OUTPUT LATCHES
AGND
DGND
INTERNAL
CLOCK
CONTROL LOGIC
1416 BD
SHDN CONVST
RD
CS
BUSY
6
LTC1416
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DBN
DBN
DBN
DBN
1k
C
C
1k
100pF
100pF
L
L
(A) Hi-Z TO V AND V TO V
(B) Hi-Z TO V AND V TO V
OL
(A) V TO Hi-Z
OH
(B) V TO Hi-Z
OL
OH
OL
OH
OL
OH
1416 TC01
1416 TC02
U
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APPLICATIONS INFORMATION
CONVERSION DETAILS
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
The LTC1416 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
connected to the sample-and-hold capacitors (CSAMPLE
)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 400ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
Duringtheconvertphasethecomparatorzeroingswitches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summingjunction. Thisinputchargeissuccessivelycom-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
+
C
SAMPLE
SAMPLE
SAMPLE
SAMPLE
+
–
A
A
IN
IN
HOLD
HOLD
–
C
HOLD
ZEROING SWITCHES
+
C
DAC
HOLD
+
+
–
V
DAC
C
DAC
COMP
–
–
V
DAC
14
D13
D0
•
•
•
OUTPUT
LATCH
SAR
+
differential DAC output balances the AIN and AIN– input
charges. The SAR contents (a 14-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 14-bit output latches.
1416 F01
Figure 1. Simplified Block Diagram
7
LTC1416
U
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APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
The LTC1416 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to testtheADC’sfrequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1416 FFT plot.
TheSignal-to-NoiseplusDistortionRatio[S/(N+D)]isthe
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 2a shows a typical spectral content with
a 400kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 200kHz, Figure 2b.
0
f
f
= 400kHz
SAMPLE
IN
= 101.5625kHz
–20
Effective Number of Bits
SFDR = 95.2dB
SINAD = 80.5dB
–40
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
–60
–80
ENOB = [S/(N + D) – 1.76]/6.02
–100
–120
–140
where ENOB is the Effective Number of Bits of resolution
and S/(N + D) is expressed in dB. At the maximum
samplingrateof400kHztheLTC1416maintainsnearideal
ENOBs up to the Nyquist input frequency of 200kHz (refer
to Figure 3).
0
25 50 75 100 125
FREQUENCY (kHz)
150
175 200
1416 F02a
Figure 2a. LTC1416 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
14
13
12
11
10
9
86
80
74
68
62
0
NYQUIST
FREQUENCY
f
f
= 400kHz
SAMPLE
= 189.9414kHz
IN
–20
SFDR = 94.8dB
SINAD = 80.2dB
8
7
–40
6
5
4
3
–60
–80
2
1
0
–100
–120
–140
f
= 400kHz
10k
SAMPLE
1k
100k
1M 2M
INPUT FREQUENCY (Hz)
1416 TA02
0
25 50 75 100 125
FREQUENCY (kHz)
150
175 200
1416 F02b
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
Figure 2b. LTC1416 Nonaveraged, 4096 Point FFT,
Input Frequency = 190kHz
8
LTC1416
U
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APPLICATIONS INFORMATION
Total Harmonic Distortion
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa +
fb). If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
Amplitude at fa+ fb
(
)
IMD fa + fb = 20 log
2
2
2
2
Amplitude at fa
V2 + V3 + V4 +...Vn
THD = 20 log
V1
0
–20
f
a
= 400kHz
SAMPLE
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD versus input fre-
quency is shown in Figure 4. The LTC1416 has good
distortion performance up to the Nyquist frequency and
beyond.
f =87.01171876kHz
f =113.1835938kHz
b
–40
–60
–80
–100
–120
–140
0
–10
–20
–30
–40
–50
–60
–70
0
60
20 40
80
100 120 140 160 180 200
FREQUENCY (Hz)
1416 G05
Figure 5. Intermodulation Distortion Plot
–80
3RD
–90
–100
–110
THD
Peak Harmonic or Spurious Noise
2ND
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
1k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
1416 G03
Figure 4. Distortion vs Input Frequency
Full-Power and Full-Linear Bandwidth
Intermodulation Distortion
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal. The full-linear
bandwidth is the input frequency at which the S/(N + D)
has dropped to 77dB (12.5 effective bits). The LTC1416
has been designed to optimize input bandwidth, allowing
the ADC to undersample input signals with frequencies
above the converter’s Nyquist frequency. The noise floor
stays very low at high frequencies; S/(N + D) becomes
dominatedbydistortionatfrequenciesfarbeyondNyquist.
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
9
LTC1416
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Driving the Analog Input
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz should be less than 100Ω.
Thesecondrequirementisthattheclosed-loopbandwidth
must be greater than 10MHz to ensure adequate small-
signal settling for full throughput rate. If slower op amps
areused, moresettlingtimecanbeprovidedbyincreasing
the time between conversions.
The differential analog inputs of the LTC1416 are easy to
drive.Theinputsmaybedrivendifferentiallyorasasingle-
endedinput(i.e., theAIN– inputisgrounded). TheAIN+ and
–
AIN inputs are sampled at the same instant. Any un-
wanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1416
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settle after the small current spike before the next
conversion starts (settling time must be 400ns for full
throughput rate).
The best choice for an op amp to drive LTC1416 will
depend on the application. Generally, applications fall into
two categories: AC applications where dynamic specifica-
tionsaremostcriticalandtimedomainapplicationswhere
DC accuracy and settling time are most critical. The
followinglistisasummaryoftheopampsthataresuitable
for driving the LTC1416. More detailed information is
available in the Linear Technology Databooks and the
LinearViewTM CD-ROM.
LT®1220: 30MHz unity-gain bandwidth voltage feedback
amplifier. ±5V to ±15V supplies, excellent DC specifica-
tions.
LT1223: 100MHz video current feedback amplifier. 6mA
supply current, ±5V to ±15V supplies, low distortion at
frequencies above 400kHz, low noise, good for AC appli-
cations.
10
1
LT1227: 140MHz video current feedback amplifier. 10mA
supply current, ±5V to ±15V supplies, lowest distortion at
frequencies above 400kHz, low noise, best for AC applica-
tions.
0.1
0.01
LT1229/LT1230:Dualandquad100MHzcurrentfeedback
amplifiers. ±2V to ±15V supplies, low noise, good AC
specs, 6mA supply current each amplifier.
10
100
1k
10k
100k
SOURCE RESISTANCE (Ω)
1416 F06
LT1360:50MHzvoltagefeedbackamplifier. 3.8mAsupply
current, good AC and DC specs, ±5V to ±15V supplies.
Figure 6. Acquisition Time vs Source Resistance
LT1363: 70MHz, 1000V/µs op amps. 6.3mA supply cur-
rent, good AC and DC specs.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
ofthevoltagespikeseenbytheamplifierfromchargingthe
sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
LT1364/LT1365:Dualandquad70MHz,100V/µsopamps.
6.3mA supply current per amplifier.
LinearView is a trademark of Linear Technology Corporation.
10
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Input Filtering
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1416 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 15MHz. Any noise
ordistortionproductsthatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 1000pF
capacitor from AIN+ to ground and a 200Ω source resistor
to limit the input bandwidth to 800kHz. The 1000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors
can also generate distortion from self-heating and from
damage that may occur during soldering. Metal film
surface mount resistors are much less susceptible to both
problems.
Internal Reference
The LTC1416 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmedto2.500V.Itisconnectedinternallytoareference
amplifier and is available at VREF (Pin 3). See Figure 8a. A
4k resistor is in series with the output so that it can be
easily overdriven by an external reference or other cir-
cuitry (see Figure 8b). The reference amplifier gains the
voltage at the VREF pin by 1.625 to create the required
internal reference voltage. This provides buffering be-
tween the VREF pin and the high speed capacitive DAC. The
R1
4k
V
REF
3
4
BANDGAP
REFERENCE
2.5V
4.0625V
REFCOMP
AGND
REF
AMP
R2
200Ω
1
80k
22µF
ANALOG
INPUT
+
–
A
A
V
IN
IN
1000pF
LTC1416
2
3
4
5
5
R3
128k
LTC1416
REF
1416 F08a
REFCOMP
AGND
22µF
Figure 8a. LTC1416 Reference Circuit
1416 F07
Figure 7. RC Input Filter
5V
1
2
3
4
5
+
–
A
A
V
IN
ANALOG
INPUT
V
IN
IN
LT1019A-2.5
Input Range
LTC1416
V
OUT
REF
The±2.5VinputrangeoftheLTC1416isoptimizedforlow
noise and low distortion. Most op amps also perform best
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
REFCOMP
AGND
22µF
1416 F08b
Some applications may require other input ranges. The
LTC1416 differential inputs and reference circuitry can
Figure 8b. Using the LT1019-2.5 as an External Reference
11
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80
70
60
50
40
30
20
10
0
reference amplifier compensation pin, REFCOMP (Pin 4),
must be bypassed with a capacitor to ground. The refer-
ence amplifier is stable with capacitors of 1µF or greater.
For the best noise performance, a 22µF ceramic or 22µF
tantaluminparallelwitha0.1µFceramicisrecommended.
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1416 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
1k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
1416 G09
Figure 10a. CMRR vs Input Frequency
1
+
1
+
A
ANALOG INPUT
A
IN
IN
ANALOG
2
3
INPUT
2
3
4
5
–
–
A
V
A
V
IN
IN
LTC1416
LTC1416
1.25V TO 3V
±2.5V
REF
LTC1450
REF
0V TO 5V
4
5
REFCOMP
AGND
REFCOMP
AGND
22µF
22µF
1416 F10b
1416 F09
Figure 9. Driving VREF with a DAC
Figure 10b. Selectable 0V to 5V or ±2.5V Input Range
converts a 0V to 5V analog input signal with no additional
translation circuitry.
Differential Inputs
The LTC1416 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
Full-Scale and Offset Adjustment
convert the difference of AIN – AIN– independent of the
+
Figure11ashowstheidealinput/outputcharacteristicsfor
theLTC1416. Thecodetransitionsoccurmidwaybetween
successive integer LSB values (i.e., –FS + 0.5LSB, –FS +
1.5LSB, –FS + 2.5LSB, . . . FS – 1.5LSB, FS – 0.5LSB). The
output is two’s complement binary with 1LSB = FS –
(–FS)/16384 = 5V/16384 = 305.2µV.
common mode voltage. The common mode rejection
holds up to extremely high frequencies (see Figure 10a).
Theonlyrequirementisthatbothinputscannotexceedthe
AVDD orAVSS powersupplyvoltages. Integralnonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
mode voltage. THD will degrade as the inputs approach
either power supply rail, from 90dB with a common mode
of 0V to 79dB with a common mode of 2.5V or –2.5V.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
–
applied to the AIN input. For zero offset error, apply
–152µV (i.e., –0.5LSB) at AIN+ and adjust the offset at the
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
–
AIN input until the output code flickers between 0000
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LTC1416
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applications, however, do not have a –5V supply readily
available and most ADCs have inadequate PSRR to suffi-
ciently attenuate the noise created by a switching or
charge pump supply. The LTC1416’s excellent PSRR
makesitpossibletoachievegoodperformance, evenat14
bits, using a switch based regulator for a –5V supply.
Figure 12a shows a circuit using an LT1373 configured as
a Cuk converter creating –5V from a 5V supply. The circuit
shown in Figure 12b uses an LT1054 regulated charge
pump to provide –5V. This circuit has the advantage of
reduced board space and fewer passive components. (For
further details refer to Linear Technology Magazine, June
1997, Page 29.)
0000 0000 00 and 1111 1111 1111 11. For full-scale
adjustment,aninputvoltageof2.499544V(FS/2–1.5LSB)
is applied to AIN and R2 is adjusted until the output code
flickers between 0111 1111 1111 10 and 0111 1111
1111 11.
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1416, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
linesareseparatedasmuchaspossible. Inparticular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
–(FS – 1LSB)
INPUT VOLTAGE (A – A
FS – 1LSB
+
–
)
IN
IN
1416 F11a
Figure 11a. LTC1416 Transfer Characteristics
–5V
ANALOG
INPUT
R3
24k
1
2
+
–
A
A
IN
IN
R1
50k
R4
100Ω
LTC1416
An analog ground plane separate from the logic system
ground should be established under and around the ADC
(see Figure 13). Pin 5 (AGND), Pins 14 and 19 (ADC’s
DGND) and all other analog grounds should be connected
to this single analog ground point. The REFCOMP bypass
capacitor and the DVDD bypass capacitor should also be
connected to this analog ground plane. No other digital
groundsshouldbeconnectedtothisanaloggroundplane.
Low impedance analog and digital power supply common
returnsareessentialtolownoiseoperationoftheADCand
the foil width for these tracks should be as wide as
possible. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
fromthemicroprocessortothesuccessiveapproximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus. The
3
4
R5 R2
47k 50k
V
REF
R6
24k
REFCOMP
AGND
5
22µF
1416 F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
Generating a –5V Supply
There are several advantages to using±5V supplies rather
than a single 5V supply. A larger signal magnitude is
possible which increases the dynamic range and
improves the signal-to-noise ratio. Operating on ±5V
supplies also offers increased headroom which eases the
requirements for signal conditioning circuitry, avoids the
limitations of rail-to-rail operation and widens the selec-
tion of high performance operational amplifiers. Some
13
LTC1416
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APPLICATIONS INFORMATION
5V
–5V
L1
2
1
3
4
C6
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
–
A
A
V
AV
DV
IN
DD
DD
ANALOG
INPUT
+
IN
C7
C11
100µF
10V
1µF CER
3
V
CUK*
REF
SS
C10
10µF
CER
CONVERTER
4
TANT
COMP
AGND
D13 (MSB)
D12
BUSY
CS
C5
5
5
4
7
6
8
V
V
SW
R4
4.99k
1%
IN
C8
22µF
10V
6
+
C12
0.1µF
CONVST
RD
MICROPROCESSOR/
MICROCONTROLLER
INTERFACE
S/S
U2
LT1373
7
3
1
TANT
GND
NFB
D1
8
D11
SHDN
D0
GND S
V
C
9
R5
4.99k
1%
R6
R3
4.99k
D10
LTC1416
499Ω
10
11
12
13
14
1%
D9
D1
C9
0.01µF
D8
D2
1416 F12a
D7
D3
C5 = µ2F2 CERAMIC
C6, C7 = µ1F0 CERAMIC
D6
D4
L1 = OCTAPAC CTX-100-1
D1 = 1N5818
DGND
D5
Figure 12a. Using the LT1373 to Generate a –5V Supply
5V
–5V
C6
C4
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
–
C2
A
A
V
AV
100µF
IN
DD
DD
ANALOG
INPUT
2µF
TANT
2
3
1
8
DV
IN
C7
+
FB/SHDN
V
+
1µF CER
2
3
4
7
6
5
V
REF
SS
+
CAP
OSC
U1
LT1054
4
R1, 30.1k
R2, 120k
C1
10µF
TANT
C3
0.002µF
+
COMP
AGND
D13 (MSB)
D12
BUSY
CS
GND
V
REF
C5
5
–
CAP
V
OUT
6
CONVST
RD
MICROPROCESSOR/
MICROCONTROLLER
INTERFACE
1416 F12b
7
8
D11
SHDN
D0
9
D10
LTC1416
10
11
12
13
14
D9
D1
D8
D2
D7
D3
C5 = 2µ2F CERAMIC
D6
D4
C6, C7 = 1µ0F CERAMIC
DGND
D5
Figure 12b. Using the LT1054 to Generate a –5V Supply
14
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1
+
–
A
A
IN
DIGITAL
SYSTEM
LTC1416
AV
IN
REFCOMP AGND
V
DV
DGND
14
SS
DD
27
2
DD
ANALOG
INPUT
CIRCUITRY
+
5
4
28
26
–
22µF
10µF
10µF
1416 F13
Figure 13. Power Supply Grounding Practice.
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
The LTC1416 has differential inputs to minimize noise
coupling. CommonmodenoiseontheAIN+ andAIN– leads
will be rejected by the input CMRR. The AIN– input can be
+
used as a ground sense for the AIN input; the LTC1416
+
will hold and convert the difference voltage between AIN
and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the AIN and AIN traces should be run side
by side to equalize coupling.
Internal Clock
The A/D converter has an internal clock that eliminates the
need for synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.8µs, and a maximum conversion time over the
full operating temperature range of 2.2µs. No external
adjustments are required. The guaranteed maximum
acquisition time is 400ns. In addition, a throughput time
of 2.5µs and a minimum sampling rate of 400ksps is
guaranteed.
+
–
Supply Bypassing
High quality, low series resistance ceramic, bypass
capacitorsshouldbeusedattheVDD (10µF)andREFCOMP
(22µF)pinsasshownintheTypicalApplicationonthefirst
page of this data sheet. Surface mount ceramic capacitors
such as Murata GRM235Y5V106Z016 provide excellent
bypassing in a small board space. Alternatively tantalum
capacitorsinparallelwith0.1µFceramiccapacitorscanbe
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Power Shutdown
TheLTC1416providestwopowershutdownmodes—nap
mode and sleep mode to save power during inactive
periods. The nap mode reduces the power by 95% and
leavesonlythedigitallogicandreferencepoweredup. The
wake-up time from nap to active is 200ns. In sleep mode
the reference is shut down and only a small current of
120µA remains. Wake-up time from sleep mode is much
slower since the reference circuit must power up and
settle to 0.005% for full 14-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
20ms with the recommended 22µF capacitor.
Example Layout
Figures 14a, 14b, 14c and 14d show the schematic and
layoutofanevaluationboard.Thelayoutdemonstratesthe
proper use of decoupling capacitors and ground plane
with a 2-layer printed circuit board.
15
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Figure 14b. Suggested Evaluation Circuit Board—
Component Side Silkscreen
Figure 14c. Suggested Evaluation Circuit Board—
Component Side Layout
CS
t
3
SHDN
1416 F15a
Figure 15a. CS to SHDN Timing
SHDN
t
3
CONVST
1416 F15b
Figure 15b. SHDN to CONVST Wake-Up Timing
Figure 14d. Suggested Evaluation Circuit Board—
Solder Side Layout
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Shutdown is controlled by Pin 21 (SHDN), the ADC is in
shutdown when it is low. The shutdown mode is selected
with Pin 20 (CS), low selects nap.
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor applies a logic low to
RD (=CONVST), starting the conversion. BUSY goes low,
forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD (=CONVST) back
high and reads the new conversion data.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
In ROM mode, the processor takes RD (=CONVST) low,
startingaconversionandreadingthepreviousconversion
result. Aftertheconversioniscomplete, theprocessorcan
read the new result and initiate another conversion.
Figures 16 through 21 show several different modes of
operation. In modes 1a and 1b (Figures 17 and 18) CS and
RDarebothtiedlow.ThefallingedgeofCONVSTstartsthe
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operationwithanarrowlogiclowCONVSTpulse. Mode1b
shows a narrow logic high CONVST pulse.
CS
t
2
In mode 2 (Figure 19) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU data
bus.
CONVST
RD
t
1
1416 F16
In slow memory and ROM modes (Figures 20 and 21), CS
istiedlowandCONVSTandRDaretiedtogether. TheMPU
Figure 16. CS to CONVST Setup Timing
t
CONV
CS = RD = 0
CONVST
(SAMPLE N)
t
5
t
t
8
6
BUSY
DATA
t
7
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1416 F17
Figure 17. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
18
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t
CS = RD = 0
t
8
CONV
t
13
t
5
CONVST
t
t
6
t
6
6
BUSY
DATA
t
7
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1416 F18
Figure 18. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
13
(SAMPLE N)
t
t
8
CS = 0
CONV
t
5
CONVST
t
6
BUSY
RD
t
t
11
9
t
12
t
10
DATA N
DB13 TO DB0
DATA
1416 F19
Figure 19. Mode 2. CONVST Starts a Conversion. Data Is Read by RD
t
t
8
CS = 0
CONV
(SAMPLE N)
RD = CONVST
t
t
11
6
BUSY
t
t
7
10
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
1416 F20
Figure 20. Slow Memory Mode Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1416
APPLICATIONS INFORMATION
U
W U U
t
t
8
CONV
CS = 0
(SAMPLE N)
RD = CONVST
t
t
11
6
BUSY
DATA
t
10
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
1416 F21
Figure 21. ROM Mode Timing
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0° – 8°
0.301 – 0.311
(7.65 – 7.90)
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
5
7
8
1
2
3
4
6
9
10 11 12 13 14
G28 SSOP 0694
RELATED PARTS
PART NUMBER
LTC1278/LTC1279
LTC1400
DESCRIPTION
COMMENTS
Single Supply, 12-Bit, 500ksps/600ksps ADCs
High Speed Serial 12-Bit ADC
Low Power, 5V or ±5V Supply
400ksps, Complete with V , CLK, Sample-and-Hold in SO-8
REF
LTC1409
Low Power, 12-Bit, 800ksps Sampling ADC
12-Bit, 1.25Msps Sampling ADC with Shutdown
12-Bit, 3Msps Sampling ADC
Best Dynamic Performance, f
≤ 800ksps, 80mW Dissipation
SAMPLE
LTC1410
Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist
Best Dynamic Performance, SINAD = 72dB at Nyquist
Single Supply, 55mW Dissipation
LTC1412
LTC1415
Single 5V, 12-Bit, 1.25Msps ADC
LTC1418
14-Bit, 200ksps Sampling ADC
16mW Dissipation, Serial and Parallel Outputs
81.5dB SINAD, 150mW from ±5V Supplies
±2.5V Input, SINAD = 90dB, THD = 100dB
Low Power, ±10V Inputs
LTC1419
14-Bit, 800ksps Sampling ADC with Shutdown
16-Bit, 333ksps Sampling ADC
LTC1604
LTC1605
Single 5V, 16-Bit, 100ksps ADC
1416f LT/TP 0598 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
LINEAR TECHNOLOGY CORPORATION 1997
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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