LTC1418IN#PBF_技术文档

LTC1418

Low Power, 14-Bit, 200ksps

ADC with Serial and Parallel I/O

FEATURES

DESCRIPTION

The LTC^®1418 is a low power, 200ksps, 14-bit A/D con-

verter. Data output is selectable for 14-bit parallel or serial

format. This versatile device can operate from a single 5V

or 5Vsupply.Anonboardhighperformancesample-and-

hold, a precision reference and internal timing minimize

external circuitry requirements. The low 15mW power

dissipation is made even more attractive with two user

selectable power shutdown modes.

n

Single Supply 5V or 5V ꢀperation

n

Sample Rate: 200ksps

n

1ꢁ25LSB ꢂIL anꢃ 1LSB DIL ꢄaM

n

Power Dissipation: 15mW (Typ)

n

Parallel or Serial Data ꢀutput

n

No Missing Codes Over Temperature

n

Power Shutdown: Nap and Sleep

n

External or Internal Reference

n

Differential High Impedance Analog Input

The LTC1418 converts 0V to 4.096V unipolar inputs from

a single 5V supply and 2.048V bipolar inputs from 5V

supplies. DC specs include 1.25LSB INL, 1LSB DNL

and no missing codes over temperature. Outstanding AC

performance includes 82dB S/(N + D) and 94dB THD at

the Nyquist input frequency of 100kHz.

n

Input Range: 0V to 4.096V or 2.048V

n

81.5dB S/(N + D) and –94dB THD at Nyquist

n

28-Lead SSOP Package

APPLICATIONS

The flexible output format allows either parallel or serial

I/O. The SPI/MICROWIRE compatible serial I/O port can

operate as either master or slave and can support clock

frequencies from DC to 10MHz. A separate convert start

input and a data ready signal (BUSY) allow easy control

of conversion start and data transfer.

n

Remote Data Acquisition

n

Battery Operated Systems

n

Digital Signal Processing

n

Isolated Data Acquisition Systems

n

Audio and Telecom Processing

n

Medical Instrumentation

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

Low Power, 200kHz, 14-Bit Sampling A/D Converter

Typical ꢂIL Curve

5V

1.0

10μF

V

DD

SER/PAR

LTC1418

S/H

0.5

D13

+

A

IN

D5

14

14-BIT ADC

SELECTABLE

SERIAL/

PARALLEL

PORT

–

A

IN

D4 (EXTCLKIN)

D3 (SCLK)

D2 (CLKOUT)

0

4.096V

BUFFER

D1 (D

)

OUT

REFCOMP

10μF

D0 (EXT/INT)

–0.5

–1.0

BUSY

CS

8k

TIMING AND

LOGIC

2.5V

REFERENCE

V

RD

REF

CONVST

SHDN

0

4096

8192

12288

16384

1μF

OUTPUT CODE

AGND

V

DGND

1418 TA02

SS

(0V OR –5V)

1418 TA01

1418fa

1

For more information www.linear.com/LTC1418

LTC1418

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Iote 1, 2)

TOP VIEW

+

Supply Voltage (V ) .................................................6V

DD

1

2

V

28

27

26

25

24

23

22

21

20

19

18

17

16

15

A

Negative Supply Voltage (V )

DD

IN

SS

–

SS

Bipolar Operation Only............................. –6V to GND

IN

3

BUSY

V

REF

Total Supply Voltage (V to V )

DD

SS

4

CS

REFCOMP

AGND

D13 (MSB)

D12

Bipolar Operation Only......................................... 12V

5

CONVST

RD

Analog Input Voltage (Note 3)

6

Unipolar Operation................... –0.3V to (V + 0.3V)

DD

7

SHDN

Bipolar Operation...........(V – 0.3V) to (V + 0.3V)

SS

DD

8

SER/PAR

D0 (EXT/INT)

D11

Digital Input Voltage (Note 4)

9

D10

Unipolar Operation................................. –0.3V to 10V

Bipolar Operation.........................(V – 0.3V) to 10V

10

11

12

13

14

D1 (D

)

D9

OUT

SS

D2 (CLKOUT)

D3 (SCLK)

D4 (EXTCLKIN)

D5

D8

Digital Output Voltage

D7

Unipolar Operation................... –0.3V to (V + 0.3V)

D6

DD

Bipolar Operation...........(V – 0.3V) to (V + 0.3V)

DGND

SS

Power Dissipation.............................................. 500mW

G PACKAGE

OBSOLETE PACKAGE

N PACKAGE

28-LEAD PLASTIC SSOP

Operation Temperature Range

28-LEAD NARROW PDIP

LTC1418C................................................. 0°C to 70°C

LTC1418I..............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

T

= 110°C, θ = 95°C/W (G)

JA

JMAX

= 110°C, θ = 100°C/W (N)

JA

ORDER INFORMATION

LEAD FREE FꢂIꢂSH

LTC1418ACG#PBF

LTC1418CG#PBF

LTC1418AIG#PBF

LTC1418IG#PBF

TAPE AID REEL

PART ꢄARKꢂIG

1418ACG

1418CG

PACKAGE DESCRꢂPTꢂꢀI

28-Lead Plastic SSOP

TEꢄPERATURE RAIGE

0°C to 70°C

LTC1418ACG#TRPBF

LTC1418CG#TRPBF

LTC1418AIG#TRPBF

LTC1418IG#TRPBF

0°C to 70°C

1418AIG

–40°C to 85°C

1418IG

ꢀBSꢀLETE PACKAGE

LTC1418ACN#PBF

LTC1418CN#PBF

LTC1418AIN#PBF

LTC1418IN#PBF

LTC1418ACN#TRPBF

LTC1418CN#TRPBF

LTC1418AIN#TRPBF

LTC1418IN#TRPBF

1418ACN

1418CN

1418AIN

1418IN

28-Lead PDIP

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

1418fa

2

For more information www.linear.com/LTC1418

LTC1418

CONVERTER CHARACTERISTICS ^Thel ꢃenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°Cꢁ (Iotes 5, 6)

LTC1418

TYP

LTC1418A

TYP

PARAꢄETER

CꢀIDꢂTꢂꢀIS

(Note 7)

ꢄꢂI

ꢄAX

ꢄꢂI

ꢄAX

UIꢂTS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

13

14

0.8

0.7

5

2

0.5

0.35

2

1.25

1

LSB

1.5

20

LSB

(Note 8)

10

LSB

Full-Scale Error

Internal Reference

External Reference = 2.5V

10

5

60

30

20

5

60

15

LSB

l

Full-Scale Tempco

I

= 0, Internal Reference, Commercial

= 0, Internal Reference, Industrial

= 0, External Reference

15

10

20

1

45

ppm/°C

OUT(REF)

5

ANALOG INPUT

The l ꢃenotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°Cꢁ (Iote 5)

SYꢄBꢀL PARAꢄETER

CꢀIDꢂTꢂꢀIS

4.75V ≤ V ≤ 5.25V (Unipolar)

ꢄꢂI

TYP

ꢄAX

UIꢂTS

l

V

Analog Input Range (Note 9)

0 to 4.096

2.048

V

IN

DD

4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –4.75V (Bipolar)

DD

SS

l

I

Analog Input Leakage Current

Analog Input Capacitance

CS = High

1

µA

IN

C

Between Conversions (Sample Mode)

During Conversions (Hold Mode)

25

5

pF

IN

l

t

Sample-and-Hold Acquisition Time Commercial

Industrial

300

1000

ns

ACQ

The l ꢃenotes the specifications which apply over the full operating temperature range,

DYNAMIC ACCURACY

otherwise specifications are at T_A= 25°Cꢁ (Iote 5)

SYꢄBꢀL

S/(N + D)

THD

PARAꢄETER

CꢀIDꢂTꢂꢀIS

ꢄꢂI

TYP

81.5

–94

95

ꢄAX

UIꢂTS

dB

l

Signal-to-Noise Plus Distortion Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range

Intermodulation Distortion

Full Power Bandwidth

97.5kHz Input Signal

79

100kHz Input Signal, First 5 Harmonics

100kHz Input Signal

–86

dB

SFDR

86

dB

IMD

f

= 97.7kHz, f = 104.2kHz

–90

5

dB

IN1

IN2

MHz

Full Linear Bandwidth

S/(N + D) ≥ 77dB

0.5

1418fa

3

For more information www.linear.com/LTC1418

LTC1418

INTERNAL REFERENCE CHARACTERISTICS

The l ꢃenotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°Cꢁ (Iote 5)

PARAꢄETER

CꢀIDꢂTꢂꢀIS

ꢄꢂI

TYP

ꢄAX

2.520

45

UIꢂTS

V

REF

V

REF

Output Voltage

Output Tempco

I

= 0

2.480

2.500

V

OUT

l

I

= 0, Commercial

= 0, Industrial

10

20

ppm/°C

OUT

V

Line Regulation

4.75V ≤ V ≤ 5.25V

0.05

LSB/V

REF

DD

–5.25V ≤ V ≤ –4.75V

SS

Output Resistance

0.1mA ≤ | I

| ≤ 0.1mA

8

kΩ

OUT

DIGITAL INPUTS AND OUTPUTS

The l ꢃenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°Cꢁ (Iote 5)

SYꢄBꢀL

PARAꢄETER

CꢀIDꢂTꢂꢀIS

ꢄꢂI

TYP

ꢄAX

UIꢂTS

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

= 5.25V

= 4.75V

= 0V to V

2.4

V

IH

IL

DD

IN

0.8

10

I

µA

pF

IN

DD

C

V

1.4

IN

V

= 4.75V, I = –10μA

4.74

V

OH

DD

O

l

= 4.75V, I = –200µA

4.0

O

V

Low Level Output Voltage

V

= 4.75V, I = 160μA

0.05

0.10

V

OL

DD

O

l

= 4.75V, I = 1.6mA

0.4

10

15

O

I

OZ

Hi-Z Output Leakage D13 to D0

Hi-Z Output Capacitance D13 to D0

Output Source Current

V

= 0V to V , CS High

µA

pF

OUT

DD

C

CS High (Note 9)

OZ

I

V

= 0V

–10

10

mA

SOURCE

SINK

OUT

Output Sink Current

= V

DD

The l ꢃenotes the specifications which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise specifications are at T_A= 25°Cꢁ (Iote 5)

SYꢄBꢀL PARAꢄETER CꢀIDꢂTꢂꢀIS

ꢄꢂI

4.75

TYP

ꢄAX

5.25

UIꢂTS

V

Positive Supply Voltage (Notes 10, 11)

Negative Supply Voltage (Note 10)

Positive Supply Current

V

DD

Bipolar Only (V = 0V for Unipolar)

–4.75

–5.25

SS

l

I

Unipolar, RD High (Note 5 )

Bipolar, RD High (Note 5)

3.0

3.9

570

2

4.3

4.5

mA

µA

DD

Nap Mode

Sleep Mode

SHDN = 0V, CS = 0V (Note 12)

SHDN = 0V, CS = 5V (Note 12)

l

I

SS

Negative Supply Current

Nap Mode

Bipolar, RD High (Note 5)

SHDN = 0V, CS = 0V (Note 12)

SHDN = 0V, CS = 5V (Note 12)

1.4

0.1

1.8

mA

µA

Sleep Mode

l

P

DIS

Power Dissipation

Unipolar

Bipolar

15.0

26.5

21.5

31.5

mW

1418fa

4

For more information www.linear.com/LTC1418

LTC1418

TIMING CHARACTERISTICS ^Thel ꢃenotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°Cꢁ (Iote 5)

SYꢄBꢀL

PARAꢄETER

CꢀIDꢂTꢂꢀIS

ꢄꢂI

TYP

ꢄAX

UIꢂTS

kHz

µs

l

f

t

Maximum Sampling Frequency

Conversion Time

Acquisition Time

Acquisition Plus Conversion Time

CS to RD Setup Time

200

SAMPLE(MAX)

CONV

3.4

0.3

3.7

4

1

5

µs

ns

ACQ

+ t

ACQ

1

CONV

(Notes 9, 10)

(Note 10)

0

l

CS↓ to CONVST↓ Setup Time

CS↓ to SHDN↓ Setup Time to Ensure Nap Mode

SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode

CONVST Low Time

CONVST to BUSY Delay

Data Ready Before BUSY↑

40

ns

MHz

µs

ns

2

3

4

5

6

7

500

l

(Notes 10, 11)

40

C = 25pF

L

35

70

20

15

500

–5

l

t

Delay Between Conversions

Wait Time RD↓ After BUSY↑

Data Access Time After RD↓

(Note 10)

8

9

C = 25pF

L

15

20

8

30

40

55

20

25

30

10

l

C = 100pF

L

t

11

Bus Relinquish Time

l

Commercial

Industrial

t

f

t

RD Low Time

CONVST High Time

Delay Time, SCLK↓ to D

Time from Previous Data Remain Valid After SCLK↓

Shift Clock Frequency

External Conversion Clock Frequency

Delay Time, CONVST↓ to External Conversion Clock Input (Notes 9, 10)

SCLK High Time

SCLK Low Time

t

12

13

14

15

10

40

l

Valid

C = 25pF (Note 9)

35

25

70

OUT

L

C = 25pF (Note 9)

15

0

0.03

L

(Notes 9, 10)

12.5

4.5

533

SCLK

EXTCLKIN

dEXTCLKIN

H SCLK

(Notes 9, 10)

10

20

L SCLK

EXTCLKIN High Time

EXTCLKIN Low Time

250

H EXTCLKIN

L EXTCLKIN

Iote 6: Linearity, offset and full-scale specifications apply for a single-

Iote 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

–

ended input with A grounded.

IN

Iote 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Iote 2: All voltage values are with respect to ground with DGND and

AGND wired together (unless otherwise noted).

Iote 8: Bipolar offset is the offset voltage measured from –0.5LSB when the

output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11.

Iote 3: When these pin voltages are taken below V or above V , they

SS

DD

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below V or above V without latchup.

Iote 9: Guaranteed by design, not subject to test.

Iote 10: Recommended operating conditions.

Iote 11: The falling edge of CONVST starts a conversion. If CONVST

returns high at a critical point during the conversion, it can create small

errors. For best performance ensure that CONVST returns high either

within 2.1µs after the conversion starts or after BUSY rises.

SS

CC

Iote 4: When these pin voltages are taken below V they will be clamped

SS

by internal diodes. This product can handle input currents greater than

100mA below V without latchup. These pins are not clamped to V

.

DD

SS

Iote 5: V = 5V, V = 0V or –5V, f

= 200kHz, t = t = 5ns unless

r f

DD

SS

SAMPLE

otherwise specified.

Iote 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at

0V or 5V. See Power Shutdown.

1418fa

5

For more information www.linear.com/LTC1418

LTC1418

TYPICAL PERFORMANCE CHARACTERISTICS

Differential Ionlinearity

vs ꢀutput Coꢃe

S/(I + D) vs ꢂnput Frequency

anꢃ Amplituꢃe

Typical ꢂIL Curve

90

80

70

60

50

40

30

20

10

0

1.0

0.5

0

1.0

0.5

V

= 0dB

IN

V

= –20dB

IN

0

V

= –60dB

IN

–0.5

–1.0

1k

10k

100k

1M

0

4096

8192

OUTPUT CODE

12288

16384

0

4096

8192

OUTPUT CODE

12288

16384

INPUT FREQUENCY (Hz)

1418 G03

1418 G02

1418 G01

Signal-to-Ioise Ratio

vs ꢂnput Frequency

Spurious-Free Dynamic Range

vs ꢂnput Frequency

Distortion vs ꢂnput Frequency

90

80

70

60

50

40

30

20

10

0

–20

0

–20

–40

–60

3RD

THD

–80

2ND

–100

–120

–100

–120

1k

10k

100k

1M

1k

10k

100k

1M

10k

100k

1M

INPUT FREQUENCY (Hz)

1418 G06

1418 G05

1418 G04

Ionaverageꢃ, 4096 Point FFT,

ꢂnput Frequency = 10kHz

Ionaverageꢃ, 4096 Point FFT,

ꢂnput Frequency = 100kHz

ꢂntermoꢃulation Distortion Plot

0

–20

0

–20

0

–20

f

= 200kHz

f

= 200kHz

f

= 200kHz

SAMPLE

IN1

IN2

SAMPLE

IN

SAMPLE

IN

= 97.65625kHz

= 97.509765kHz

= 9.9609375kHz

= 104.248046kHz

SFDR = 94.29

SINAD = 81.4

SFDR = 99.32

SINAD = 82.4

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

10 20 30 40 50 60 70 80 90 100

FREQUENCY (kHz)

60 70

FREQUENCY (kHz)

0

10 20 30 40 50

80 90 100

1418 G09

0

10 20 30 40 50 60 70 80 90 100

FREQUENCY (kHz)

1418 G08

1418 G07

1418fa

6

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LTC1418

TYPICAL PERFORMANCE CHARACTERISTICS

Power Supply Feeꢃthrough

vs Ripple Frequency

ꢂnput Common ꢄoꢃe Rejection

vs ꢂnput Frequency

ꢂnput ꢀffset Voltage Shift

vs Source Resistance

0

–20

90

80

70

60

50

40

30

20

10

0

10

9

8

7

6

5

4

3

2

1

0

–40

–60

V

SS

DD

–80

DGND

–100

–120

10

100

1k

10k

100k

1M

1

10

100

1k

1M

10k 100k

1k

10k

100k

1M

10M

INPUT SOURCE RESISTANCE (Ω)

FREQUENCY (Hz)

INPUT FREQUENCY (Hz)

1418 G12

1418 G11

1418 G10

V_DDSupply Current vs

Temperature (Unipolar ꢄoꢃe)

V_DDSupply Current vs

V_SSSupply Current vs

Temperature (Bipolar ꢄoꢃe)

5

4

3

2

1

0

5

4

3

2

1

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

125

–75 –50

0

25 50

100

75

150

–25

125

–75 –50

0

25 50

100

75

150

–25

125

–75 –50

0

25 50

100

75

150

–25

TEMPERATURE (°C)

1418 G14

1418 G13

V_DDSupply Current vs Sampling

Frequency (Unipolar ꢄoꢃe)

V_DDSupply Current vs Sampling

Frequency (Bipolar ꢄoꢃe)

V_SSSupply Current vs Sampling

Frequency (Bipolar ꢄoꢃe)

5

4

3

2

1

0

5

4

3

2

1

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

50

150

200

250

300

0

100

150

200

250

300

100

50

0

50

150

200

250

300

100

SAMPLING FREQUENCY (kHz)

1418 G17

1418 G16

1418 G18

1418fa

7

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LTC1418

PIN FUNCTIONS

+

A

V

(Pin 1): Positive Analog Input.

D0(EXT/INT)(Pin20):Three-StateDataOutput(Parallel).

Conversion clock selector (serial). An input low enables

the internal conversion clock. An input high indicates

an external conversion clock will be assigned to Pin 16

(EXTCLKIN).

ꢂI

–

(Pin 2): Negative Analog Input.

ꢂI

(Pin 3): 2.50V Reference Output. Bypass to AGND

REF

with 1µF.

REFCꢀꢄP (Pin 4): 4.096V Reference Bypass Pin. Bypass

SER/PAR (Pin 21): Data Output Mode.

toAGNDwith10µFtantaluminparallelwith0.1µFceramic.

SHDN (Pin 22): Power Shutdown Input. Low selects

shutdown. Shutdown mode selected by CS. CS = 0 for

nap mode and CS = 1 for sleep mode.

AGID (Pin 5): Analog Ground.

D13 to D6(Pins6to13): Three-State Data Outputs(Paral-

lel). D13 is the most significant bit.

RD (Pin 23): Read Input. This enables the output drivers

when CS is low.

DGID (Pin 14): Digital Ground for Internal Logic. Tie to

AGND.

CONVST(Pin24):ConversionStartSignal.Thisactivelow

signal starts a conversion on its falling edge.

D5 (Pin 15): Three-State Data Output (Parallel).

CS (Pin 25): Chip Select. This input must be low for the

ADC to recognize the CONVST and RD inputs. CS also

sets the shutdown mode when SHDN goes low. CS and

SHDN low select the quick wake-up nap mode. CS high

and SHDN low select sleep mode.

D4 (EXTCLKꢂI) (Pin 16): Three-State Data Output (Par-

allel). Conversion clock input (serial) when Pin 20 (EXT/

INT) is tied high.

D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).

Data clock input (serial).

BUSY (Pin 26): The BUSY Output Shows the Converter

Status. It is low when a conversion is in progress.

D2(CLKꢀUT)(Pin18):Three-StateDataOutput(Parallel).

Conversion clock output (serial).

V

(Pin 27): Negative Supply, –5V for Bipolar Operation.

SS

D1 (D ) (Pin 19): Three-State Data Output (Parallel).

ꢀUT

Bypass to AGND with 10µF tantalum in parallel with 0.1µF

Serial data output (serial).

ceramic. Analog ground for unipolar operation.

V

(Pin 28): 5V Positive Supply. Bypass to AGND with

DD

10µF tantalum in parallel with 0.1µF ceramic.

TEST CIRCUITS

Loaꢃ Circuits for ꢀutput Float Delay

Loaꢃ Circuits for Access Timing

5V

1k

DBN

30pF

1k

30pF

1k

C

L

DGND

A) HI-Z TO V AND V TO V

DGND

B) HI-Z TO V AND V TO V

A) V TO HI-Z

OH

B) V TO HI-Z

OL

1418 TC02

OH

OL

OH

OL

OH

OL

1418 TC01

1418fa

8

For more information www.linear.com/LTC1418

LTC1418

BLOCK DIAGRAM

C

SAMPLE

+

A

IN

V

: 5V

DD

: 0V FOR UNIPOLAR MODE

–5V FOR BIPOLAR MODE

SS

–

A

IN

8k

2.5V

ZEROING SWITCHES

V

2.5V REF

REF

+

REF AMP

COMP

14-BIT CAPACITIVE DAC

–

4.096V

REFCOMP

AGND

14

D13

D0

SUCCESSIVE APPROXIMATION

REGISTER

SHIFT

REGISTER

•

D3/(SCLK)

D1/(D

INTERNAL

CLOCK

CONTROL LOGIC

MUX

DGND

)

OUT

1418 BD

D4 (EXTCLKIN) D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY

NOTE: PIN NAMES IN PARENTHESES

REFER TO SERIAL MODE

APPLICATIONS INFORMATION

+

CꢀIVERSꢂꢀI DETAꢂLS

C

SAMPLE

+

–

A

IN

ZEROING SWITCHES

HOLD

The LTC1418 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an ana-

log signal to a 14-bit parallel or serial output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs (please refer to Digital Interface section

for the data format).

HOLD

–

C

HOLD

+

C

DAC

+

–

C

DAC

COMP

+

V

DAC

–

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive ap-

proximation register (SAR) is reset. Once a conversion

cycle has begun it cannot be restarted.

–

14

V

D13

DAC

OUTPUT

LATCH

SAR

D0

1418 F01

During the conversion, the internal differential 14-bit

capacitive DAC output is sequenced by the SAR from the

mostsignificantbit(MSB)totheleastsignificantbit(LSB).

Figure 1ꢁ Simplifieꢃ Block Diagram

1418fa

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LTC1418

APPLICATIONS INFORMATION

+

–

0

–20

ReferringtoFigure1,theA andA inputsareconnected

IN

f

= 200kHz

SAMPLE

IN

to the sample-and-hold capacitors (C

) during the

SAMPLE

= 9.9609375kHz

SFDR = 99.32

SINAD = 82.4

acquire phase and the comparator offset is nulled by the

zeroing switches. In this acquire phase, a minimum delay

of 1µs will provide enough time for the sample-and-hold

capacitorstoacquiretheanalogsignal. Duringtheconvert

phase, the comparator zeroing switches open, putting the

comparator into compare mode. The input switches the

–40

–60

–80

–100

–120

C

capacitorstoground, transferringthedifferential

SAMPLE

analoginputchargeontothesummingjunction.Thisinput

chargeissuccessivelycomparedwiththebinaryweighted

charges supplied by the differential capacitive DAC. Bit

decisions are made by the high speed comparator. At the

end of a conversion, the differential DAC output balances

0

10 20 30 40 50 60 70 80 90 100

FREQUENCY (kHz)

1418 F02a

Figure 2aꢁ LTC1418 Ionaverageꢃ, 4096 Point FFT,

ꢂnput Frequency = 10kHz

+

–

the A and A input charges. The SAR contents (a

IN

+

0

14-bit data word) which represent the difference of A

IN

f

= 200kHz

SAMPLE

IN

–

and A are loaded into the 14-bit output latches.

= 97.509765kHz

IN

–20

–40

SFDR = 94.29

SINAD = 81.4

DYIAꢄꢂC PERFꢀRꢄAICE

–60

TheLTC1418hasexcellenthighspeedsamplingcapability.

FFT (Fast Fourier Transform) test techniques are used to

test the ADC’s frequency response, distortion and noise

at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined

for frequencies outside the fundamental. Figure 2a shows

a typical LTC1418 FFT plot.

–80

–100

–120

0

10 20 30 40 50 60 70 80 90 100

FREQUENCY (kHz)

1418 F02b

Figure 2bꢁ LTC1418 Ionaverageꢃ, 4096 Point FFT,

ꢂnput Frequency = 97ꢁ5kHz

Signal-to-Ioise Ratio

Effective Iumber of Bits

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 2b shows a typical spectral content with

a 200kHz sampling rate and a 10kHz input. The dynamic

performance is excellent for input frequencies up to and

beyond the Nyquist limit of 100kHz.

The effective number of bits (ENOBs) is a measurement

of the resolution of an ADC and is directly related to the

S/(N + D) by the equation:

N = [S/(N + D) – 1.76]/6.02

where N is the effective number of bits of resolution

and S/(N + D) is expressed in dB. At the maximum

sampling rate of 200kHz, the LTC1418 maintains near

ideal ENOBs up to the Nyquist input frequency of 100kHz

(refer to Figure 3).

1418fa

10

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

14

13

12

11

10

9

ꢂntermoꢃulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

8

7

6

5

4

If two pure sine waves of frequencies fa and fb are applied

totheADCinput,nonlinearitiesintheADCtransferfunction

can create distortion products at the sum and difference

frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 2nd order IMD terms include (fa + fb).

If the two input sine waves are equal in magnitude, the

value (in decibels) of the 2nd order IMD products can be

expressed by the following formula:

3

2

1k

10k

100k

1M

INPUT FREQUENCY (Hz)

1418 F03

Figure 3ꢁ Effective Bits anꢃ Signal/(Ioise + Distortion)

vs ꢂnput Frequency

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

Amplitude at fa + fb

(

)

IMD fa+fb =20Log

(

)

Amplitude at fa

0

f

= 200kHz

SAMPLE

IN1

IN2

= 97.65625kHz

–20

–40

= 104.248046kHz

2

V2²+V3²+V4²+...V_N

THD=20Log

V1

–60

where V1 is the RMS amplitude of the fundamental

frequency and V2 through V are the amplitudes of the

N

–80

second through nth harmonics. THD vs Input Frequency

is shown in Figure 4. The LTC1418 has good distortion

performance up to the Nyquist frequency and beyond.

–100

–120

60 70

80 90 100

FREQUENCY (kHz)

0

10 20 30 40 50

0

–20

–40

–60

1418 F05

Figure 5ꢁ ꢂntermoꢃulation Distortion Plot

Peak Harmonic or Spurious Ioise

3RD

Thepeakharmonicorspuriousnoiseisthelargestspectral

component excluding the input signal and DC. This value

is expressed in decibels relative to the RMS value of a

full-scale input signal.

–80

THD

2ND

–100

–120

1k

10k

100k

1M

INPUT FREQUENCY (Hz)

1418 F04

Figure 4ꢁ Distortion vs ꢂnput Frequency

1418fa

11

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LTC1418

APPLICATIONS INFORMATION

Full-Power anꢃ Full-Linear Banꢃwiꢃth

small-signal settling for full throughput rate. If slower op

amps are used, more settling time can be provided by

increasing the time between conversions.

The full-power bandwidth is that input frequency at which

theamplitudeofthereconstructedfundamentalisreduced

by 3dB for a full-scale input signal.

The best choice for an op amp to drive the LTC1418 will

depend on the application. Generally, applications fall into

two categories: AC applications where dynamic specifica-

tionsaremostcriticalandtimedomainapplicationswhere

DC accuracy and settling time are most critical. The fol-

lowing list is a summary of the op amps that are suitable

for driving the LTC1418. More detailed information is

available at www.linear.com.

LT^®1354: 12MHz, 400V/µs Op Amp. 1.25mA maximum

supply current. Good AC and DC specifications. Suitable

for dual supply application.

The full-linear bandwidth is the input frequency at

which the S/(N + D) has dropped to 77dB (12.5 effec-

tive bits). The LTC1418 has been designed to optimize

input bandwidth, allowing the ADC to undersample

input signals with frequencies above the converter’s

Nyquist Frequency. The noise floor stays very low at

high frequencies; S/(N + D) becomes dominated by

distortion at frequencies far beyond Nyquist.

DRꢂVꢂIG THE AIALꢀG ꢂIPUT

LT1357: 25MHz, 600V/µs Op Amp. 2.5mA maximum

supply current. Good AC and DC specifications. Suitable

for dual supply application.

The differential analog inputs of the LTC1418 are easy

to drive. The inputs may be driven differentially or as a

–

single-ended input (i.e., the A input is grounded). The

IN

+

–

A

IN

and A inputs are sampled at the same instant. Any

IN

LT1366/LT1367: Dual/Quad Precision Rail-to-Rail Input

and Output Op Amps. 375µA supply current per amplifier.

1.8V to 15V supplies. Low input offset voltage: 150µV.

Good for low power and single supply applications with

sampling rates of 20ksps and under.

unwanted signal that is common mode to both inputs will

be reduced by the common mode rejection of the sample-

and-hold circuit. The inputs draw only one small current

spikewhilechargingthesample-and-holdcapacitorsatthe

end of conversion. During conversion, the analog inputs

draw only a small leakage current. If the source imped-

ance of the driving circuit is low then the LTC1418 inputs

can be driven directly. As source impedance increases so

will acquisition time (see Figure 6). For minimum acquisi-

tion time, with high source impedance, a buffer amplifier

must be used. The only requirement is that the amplifier

driving the analog input(s) must settle after the small

current spike before the next conversion starts—1µs for

full throughput rate.

LT1498/LT1499: 10MHz, 6V/µs, Dual/Quad Rail-to-Rail

Input and Output Op Amps. 1.7mA supply current per

amplifier. 2.2V to 15V supplies. Good AC performance,

input noise voltage = 12nV/√Hz (typ).

100

10

1

Choosing an ꢂnput Amplifier

Choosing an input amplifier is easy if a few requirements

aretakenintoconsideration.First,chooseanamplifierthat

has a low output impedance (<100Ω) at the closed-loop

bandwidth frequency. For example, if an amplifier is used

in a gain of 1 and has a closed-loop bandwidth of 10MHz,

then the output impedance at 10MHz must be less than

100Ω. The second requirement is that the closed-loop

bandwidth must be greater than 5MHz to ensure adequate

0.1

1

10

100

1k

10k

100k

SOURCE RESISTANCE (Ω)

1418 F06

Figure 6ꢁ t_ACQvs Source Resistance

1418fa

12

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

LT1630/LT1631: 30MHz, 10V/µs, Dual/Quad Rail-to-Rail

Input and Output Precision Op Amps. 3.5mA supply cur-

rent per amplifier. 2.7V to 15V supplies. Best AC perfor-

mance, input noise voltage = 6nV/√Hz (typ), THD = –86dB

at 100kHz.

ꢂnput Range

The 2.048Vand0Vto4.096VinputrangesoftheLTC1418

are optimized for low noise and low distortion. Most op

amps also perform well over these ranges, allowing direct

coupling to the analog inputs and eliminating the need for

special translation circuitry.

ꢂnput Filtering

Some applications may require other input ranges. The

LTC1418 differential inputs and reference circuitry can

accommodate other input ranges often with little or no

additional circuitry. The following sections describe

the reference and input circuitry and how they affect

the input range.

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add

to the LTC1418 noise and distortion. The small-signal

bandwidth of the sample-and-hold circuit is 5MHz. Any

noise or distortion products that are present at the analog

inputs will be summed over this entire bandwidth. Noisy

input circuitry should be filtered prior to the analog inputs

to minimize noise. A simple 1-pole RC filter is sufficient

for many applications. For example, Figure 7 shows a

ꢂITERIAL REFEREICE

The LTC1418 has an on-chip, temperature compensated,

curvature corrected, bandgap reference which is factory

trimmed to 2.500V. It is internally connected to a refer-

ence amplifier and is available at Pin 3. A 8k resistor is in

series with the output so that it can be easily overdriven

in applications where an external reference is required,

see Figure 8. The reference amplifier compensation pin

(REFCOMP, Pin 4) must be connected to a capacitor to

ground. The reference is stable with capacitors of 1µF or

greater. For the best noise performance, a 10µF in parallel

with a 0.1µF ceramic is recommended.

2000pF capacitor from +A to ground and a 100Ω source

IN

resistor to limit the input bandwidth to 800kHz. The

2000pF capacitor also acts as a charge reservoir for the

input sample-and-hold and isolates the ADC input from

sampling glitch sensitive circuitry. High quality capacitors

and resistors should be used since these components

can add distortion. NPO and silver mica type dielectric

capacitors have excellent linearity. Carbon surface mount

resistors can also generate distortion from self heating

and from damage that may occur during soldering. Metal

film surface mount resistors are much less susceptible

to both problems.

The V pin can be driven with a DAC or other means to

REF

provide input span adjustment. The reference should be

100Ω

kept in the range of 2.25V to 2.75V for specified linearity.

1

2

3

4

5

+

–

A

V

ANALOG INPUT

IN

2000pF

5V

V

LTC1418

DD

REF

1

2

3

4

5

+

–

A

V

IN

5V

ANALOG

INPUT

REFCOMP

AGND

10μF

V

IN

LTC1418

V

1418 F07

OUT

REF

LT1460

REFCOMP

AGND

0.1μF

10μF

Figure 7ꢁ RC ꢂnput Filter

1418 F08

Figure 8ꢁ Using the LT1460 as an EMternal Reference

1418fa

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LTC1418

APPLICATIONS INFORMATION

UIꢂPꢀLAR/BꢂPꢀLAR ꢀPERATꢂꢀI AID ADJUSTꢄEIT

full-scale error adjustment. Zero offset is achieved by

–

adjusting the offset applied to the A input. For zero

IN

Figure 9a shows the ideal input/output characteristics for

theLTC1418. Thecodetransitionsoccurmidwaybetween

successive integer LSB values (i.e., 0.5LSB, 1.5LSB,

2.5LSB, … FS – 1.5LSB). The output code is natural

binary with 1LSB = FS/16384 = 4.096V/16384 = 250µV.

Figure 9b shows the input/output transfer characteristics

for the bipolar mode in two’s complement format.

offset error apply 125µV (i.e., 0.5LSB) at the input and

–

adjust the offset at the A input until the output code

IN

flickers between 0000 0000 0000 00 and 0000 0000

0000 01. For full-scale adjustment, an input voltage of

+

4.095625V (FS – 1.5LSBs) is applied to A and R2 is

IN

adjusteduntiltheoutputcodeflickersbetween11111111

1111 10 and 1111 1111 1111 11.

Unipolar ꢀffset anꢃ Full-Scale Error Aꢃjustment

Bipolar ꢀffset anꢃ Full-Scale Error Aꢃjustment

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figures

10a and 10b show the extra components required for

Bipolaroffsetandfull-scaleerrorsareadjustedinasimilar

fashion to the unipolar case. Again, bipolar offset error

must be adjusted before full-scale error. Bipolar offset

FS

4.096V

1LSB =

=

111...111

111...110

111...101

111...100

R7

R8

16384 16384

48k

5V

100Ω

ANALOG INPUT

R3

V

DD

1

R1

50k

+

–

A

IN

R4

2

3

4

5

24k

100Ω

A

V

LTC1418

R5 R2

47k 50k

UNIPOLAR

ZERO

REF

000...011

000...010

000...001

000...000

R6

24k

REFCOMP

AGND

V

SS

0.1μF

10μF

1418 F10a

0V

1

LSB

FS – 1LSB

INPUT VOLTAGE (V)

1418 F9a

Figure 9aꢁ LTC1418 Unipolar Transfer Characteristics

Figure 10aꢁ ꢀffset anꢃ Full-Scale Aꢃjust Circuit

ꢂf –5V ꢂs Iot Available

011...111

–5V

5V

BIPOLAR

ZERO

011...110

ANALOG INPUT

V

DD

1

2

3

4

5

R1

50k

+

–

A

V

IN

R3

24k

R4

100Ω

000...001

000...000

111...111

111...110

LTC1418

R5 R2

47k 50k

REF

R6

24k

REFCOMP

AGND

100...001

100...000

FS = 4.096V

1LSB = FS/16384

V

SS

0.1μF

10μF

1418 F10b

*

–1 0V

LSB

INPUT VOLTAGE (V)

1

–FS/2

FS/2 – 1LSB

1N5817

*ONLY NEEDED IF V GOES

SS

ABOVE GROUND

–5V

LSB

1418 F9b

Figure 10bꢁ ꢀffset anꢃ Full-Scale Aꢃjust Circuit

ꢂf –5V ꢂs Available

Figure 9bꢁ LTC1418 Bipolar Transfer Characteristics

1418fa

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LTC1418

APPLICATIONS INFORMATION

erroradjustmentisachievedbyadjustingtheoffsetapplied

power supply common returns are essential to low noise

operation of the ADC and the foil width for these tracks

should be as wide as possible. In applications where the

ADC data outputs and control signals are connected to

a continuously active microprocessor bus, it is possible

to get errors in the conversion results. These errors are

due to feedthrough from the microprocessor to the suc-

cessive approximation comparator. The problem can

be eliminated by forcing the microprocessor into a wait

state during conversion or by using three-state buffers to

isolate the ADC data bus. The traces connecting the pins

and bypass capacitors must be kept short and should be

made as wide as possible.

–

to the A input. For zero offset error apply –125µV (i.e.,

IN

+

–

–0.5LSB) at A and adjust the offset at the A input

IN

until the output code flickers between 0000 0000 0000

00 and 1111 1111 1111 11. For full-scale adjustment,

an input voltage of 2.047625V (FS – 1.5LSBs) is applied

+

to A

and R2 is adjusted until the output code flickers

IN

between 0111 1111 1111 10 and 0111 1111 1111 11.

BꢀARD LAYꢀUT AID GRꢀUIDꢂIG

Wire wrap boards are not recommended for high reso-

lution or high speed A/D converters. To obtain the best

performance from the LTC1418, a printed circuit board

with ground plane is required. The ground plane under

the ADC area should be as free of breaks and holes as

possible, such that a low impedance path between all ADC

grounds and all ADC decoupling capacitors is provided.

It is critical to prevent digital noise from being coupled to

the analog input, reference or analog power supply lines.

Layout should ensure that digital and analog signal lines

are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track.

The LTC1418 has differential inputs to minimize noise

+

–

coupling. CommonmodenoiseontheA andA leads

IN

–

will be rejected by the input CMRR. The A input can be

IN

+

used as a ground sense for the A

input; the LTC1418

IN

+

will hold and convert the difference voltage between A

IN

–

+

–

and A . The leads to A (Pin 1) and A (Pin 2) should

IN

be kept as short as possible. In applications where this is

+

–

not possible, the A

and A traces should be run side

IN

by side to equalize coupling.

SUPPLY BYPASSꢂIG

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 5 (AGND) and Pin 14 (DGND) and all other analog

groundsshouldbeconnectedtothissingleanalogground

High quality, low series resistance ceramic, 10µF bypass

capacitors should be used at the V and REFCOMP

DD

pins. Surface mount ceramic capacitors such as Murata

GRM235Y5V106Z016 provide excellent bypassing in a

small board space. Alternatively 10µF tantalum capacitors

in parallel with 0.1µF ceramic capacitors can be used.

plane.TheREFCOMPbypasscapacitorandtheV bypass

DD

capacitor should also be connected to this analog ground

plane.Nootherdigitalgroundsshouldbeconnectedtothis

analog ground plane. Low impedance analog and digital

1

+

DIGITAL

SYSTEM

LTC1418

REFCOMP AGND

A

IN

–

A

IN

V

DD

DGND

14

REF

SS

ANALOG

INPUT

CIRCUITRY

2

3

4

5

27

10μF

28

10μF

+

–

1μF

10μF

ANALOG GROUND PLANE

1418 F11

Figure 11ꢁ Power Supply Grounꢃing Practice

1418fa

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LTC1418

APPLICATIONS INFORMATION

1418fa

16

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LTC1418

APPLICATIONS INFORMATION

1418 F12b

Figure 12bꢁ Suggesteꢃ Evaluation Circuit Boarꢃ— Component Siꢃe Top Silkscreen

1418 F12c

Figure 12cꢁ Suggesteꢃ Evaluation Circuit Boarꢃ—Top Layer

1418fa

17

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

1418 F12d

Figure 12ꢃꢁ Suggesteꢃ Evaluation Circuit Boarꢃ—Solꢃer Siꢃe Layout

Bypass capacitors must be located as close to the pins as

serial output mode either the internal clock or an external

clockmaybeusedastheconversionclock(seeFigure20).

The internal clock is factory trimmed to achieve a typical

conversion time of 3.4µs and a maximum conversion

time over the full operating temperature range of 4µs. No

externaladjustmentsarerequired,andwiththeguaranteed

maximumacquisitiontimeof1µs,throughputperformance

of 200ksps is assured.

possible. The traces connecting the pins and the bypass

capacitors must be kept short and should be made as

wide as possible.

EMample Layout

Figures 12a, 12b, 12c and 12d show the schematic and

layout of a suggested evaluation board. The layout dem-

onstrates the proper use of decoupling capacitors and

ground plane with a 2-layer printed circuit board.

Power Shutꢃown

The LTC1418 provides two power shutdown modes, nap

and sleep, to save power during inactive periods. The nap

modereducesthepowerby80%andleavesonlythedigital

logic and reference powered up. The wake-up time from

nap to active is 500ns (see Figure 13a). In sleep mode

all bias currents are shut down and only leakage current

remains—about 2µA. Wake-up time from sleep mode is

much slower since the reference circuit must power up

and settle to 0.005% for full 14-bit accuracy. Sleep mode

wake-up time is dependent on the value of the capacitor

connected to the REFCOMP (Pin 4). The wake-up time is

30ms with the recommended 10µF capacitor. Shutdown

is controlled by Pin 22 (SHDN); the ADC is in shutdown

when it is low. The shutdown mode is selected with Pin 25

(CS); low selects nap (see Figure 13b), high selects sleep.

DꢂGꢂTAL ꢂITERFACE

The LTC1418 can operate in serial or parallel mode. In

parallel mode the ADC is designed to interface with mi-

croprocessors as a memory mapped device. The CS and

RD control inputs are common to all peripheral memory

interfacing. In serial mode only four digital interface lines

are required, SCLK, CONVST, EXTCLKIN and D . SCLK,

OUT

the serial data shift clock can be an external input or sup-

plied by the LTC1418 internal clock.

ꢂnternal Clock

TheADC has an internalclock. In paralleloutput mode, the

internal clock is always used as the conversion clock. In

1418fa

18

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LTC1418

APPLICATIONS INFORMATION

SHDN

CS

CONVST

RD

t

2

4

CONVST

1418 F13a

t

1

Figure 13aꢁ SHDN to CONVST Wake-Up Timing

1418 F14

CS

Figure 14ꢁ CS to CONVST Set-Up Timing

t

3

SHDN

data outputs are always enabled and data can be latched

with the BUSY rising edge. Mode 1a shows operation

with a narrow logic low CONVST pulse. Mode 1b shows

a narrow logic high CONVST pulse.

1418 F13b

Figure 13bꢁ CS to SHDN Timing

Conversion Control

In mode 2 (Figure 17) CS is tied low. The falling edge of

CONVST signal again starts the conversion. Data outputs

are in three-state until read by the MPU with the RD signal.

Mode 2 can be used for operation with a shared data bus.

Conversion start is controlled by the CS and CONVST

inputs. A falling edge of CONVST pin will start a conver-

sion after the ADC has been selected (i.e., CS is low, see

Figure 14). Once initiated, it cannot be restarted until the

conversion is complete. Converter status is indicated by

the BUSY output. BUSY is low during a conversion.

In slow memory and ROM modes (Figures 18 and 19),

CS is tied low and CONVST and RD are tied together. The

MPU starts the conversion and reads the output with the

RD signal. Conversions are started by the MPU or DSP

(no external sample clock).

Data ꢀutput

The data format is controlled by the SER/PAR input pin;

logic low selects parallel output format. In parallel mode,

the 14-bit data output word D0 to D13 is updated at the

end of each conversion on Pins 6 to 13 and Pins 15 to 20.

AlogichighappliedtoSER/PAR selectstheserialformatted

data output and Pins 16 to 20 assume their serial function,

Pins 6 to 13 and 15 are in the Hi-Z state. In either parallel

or serial data formats, outputs will be active only when

CS and RD are low. Any other combination of CS and RD

InslowmemorymodetheprocessortakesRD(=CONVST)

low and starts the conversion. BUSY goes low forcing

the processor into a wait state. The previous conversion

result appears on the data outputs. When the conversion

iscomplete,thenewconversionresultsappearonthedata

outputs; BUSY goes high releasing the processor and the

processor takes RD (= CONVST) back high and reads the

new conversion data.

will three-state the output. In unipolar mode (V = 0V)

SS

In ROM mode, the processor takes RD (= CONVST) low,

startingaconversionandreadingthepreviousconversion

result. After the conversion is complete, the processor

can read the new result and initiate another conversion.

thedatawillbeinstraightbinaryformat(correspondingto

the unipolar input range). In bipolar mode(V = –5V), the

SS

data will be in two’s complement format (corresponding

to the bipolar input range).

Serial ꢀutput ꢄoꢃe

Parallel ꢀutput ꢄoꢃe

Serial output mode is selected when the SER/PAR input

pin is high. In this mode, Pins 16 to 20, D0 (EXT/INT),

Parallel mode is selected with a logic 0 applied to the

SER/PAR pin. Figures 15 through 19 show different

modes of parallel output operation. In modes 1a and

1b (Figures 15 and 16) CS and RD are both tied low.

The falling edge of CONVST starts the conversion. The

D1 (D ), D2 (CLKOUT), D3 (SCLK) and D4 (EXTCLKIN)

OUT

assume their serial functions as shown in Figure 20. (Dur-

ing this discussion, these pins will be referred to by their

1418fa

19

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

CS = RD = 0

t

CONV

(SAMPLE N)

t

5

CONVST

t

8

6

BUSY

t

7

DATA (N – 1)

DB13 TO DB0

DATA N

DB13 TO DB0

DATA (N + 1)

DB13 TO DB0

1418 F15

DATA

Figure 15ꢁ ꢄoꢃe 1aꢁ CONVST Starts a Conversionꢁ Data ꢀutputs Always Enableꢃ

(CONVST =

)

t

13

t

CS = RD = 0

CONV

t

5

CONVST

t

8

6

t

6

BUSY

t

7

DATA (N – 1)

DB13 TO DB0

DATA N

DB13 TO DB0

DATA (N + 1)

DB13 TO DB0

DATA

1418 F16

(CONVST =

)

Figure 16ꢁ ꢄoꢃe 1bꢁ CONVST Starts a Conversionꢁ Data ꢀutputs Always Enableꢃ

t

12

(SAMPLE N)

CS = 0

t

8

CONV

t

5

CONVST

t

6

BUSY

RD

t

11

9

t

12

t

10

DATA N

DB13 TO DB0

DATA

1418 F17

Figure 17ꢁ ꢄoꢃe 2ꢁ CONVST Starts a Conversionꢁ Data is Reaꢃ by RD

1418fa

20

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

CS = 0

t

8

CONV

(SAMPLE N)

RD = CONVST

t

11

6

BUSY

t

7

10

DATA (N – 1)

DB13 TO DB0

DATA N

DB13 TO DB0

DATA N

DB13 TO DB0

DATA (N + 1)

DB13 TO DB0

DATA

1418 F18

Figure 18ꢁ Slow ꢄemory ꢄoꢃe Timing

CS = 0

t

8

CONV

(SAMPLE N)

RD = CONVST

BUSY

t

11

6

t

10

DATA (N – 1)

DB13 TO DB0

DATA N

DB13 TO DB0

DATA

1418 F19

Figure 19ꢁ Rꢀꢄ ꢄoꢃe Timing

serialfunctionnames:EXT/INT, D , CLKOUT, SCLKand

during a conversion, the SCLK should be used as the

external conversion clock to avoid the noise generated

by the asynchronous clocks. To maintain accuracy the

external conversion clock frequency must be between

30kHz and 4.5MHz.) The SAR sends an end of conversion

signal, EOC, that gates the external conversion clock so

that only 16 clock cycles can go into the SAR, even if the

external clock, EXTCLKIN, contains more than 16 cycles.

OUT

EXTCLKIN.)Asinparallelmode,conversionsarestartedby

a falling CONVST edge with CS low. After a conversion is

completed and the output shift register has been updated,

BUSY will go high and valid data will be available on D

OUT

(Pin 19). This data can be clocked out either before the

next conversion starts or it can be clocked out during the

next conversion. To enable the serial data output buffer

and shift clock, CS and RD must be low.

When CS and RD are low, these 16 cycles of conversion

clock (whether internally or externally generated) will ap-

pear on CLKOUT during each conversion and then CLK-

OUT will remain low until the next conversion. If desired,

CLKOUT can be used as a master clock to drive the serial

port. Because CLKOUT is running during the conversion,

it is important to avoid excessive loading that can cause

large supply transients and create noise. For the best

performance, limit CLKOUT loading to 20pF.

Figure 20 shows a function block diagram of the LTC1418

in serial mode. There are two pieces to this circuitry: the

conversionclockselectioncircuit(EXT/INT,EXTCLKINand

CLKOUT) and the serial port (SCLK, D , CS and RD).

OUT

Conversion Clock Selection (Serial ꢄoꢃe)

In Figure 20, the conversion clock controls the internal

ADCoperation.Theconversionclockcanbeeitherinternal

or external. By connecting EXT/INT low, the internal clock

is selected. This clock generates 16 clock cycles which

feed into the SAR for each conversion.

Serial Port

The serial port in Figure 20 is made up of a 16-bit shift

register and a three-state output buffer that are controlled

by three inputs: SCLK, RD and CS. The serial port has one

To select an external conversion clock, tie EXT/INT high

and apply an external conversion clock to EXTCLKIN

(Pin 16). (When an external shift clock (SCLK) is used

output, D , that provides the serial output data.

OUT

1418fa

21

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

• • •

17

23

25

SCLK*

RD

CLOCK

DATA

IN

14

INPUT

DATA

OUT

SHIFT

REGISTER

CS

THREE

STATE

BUFFER

19

D

OUT

*

SAR

16 CONVERSION CLOCK CYCLES

THREE

STATE

BUFFER

18

CLKOUT*

• • •

EOC

16

20

EXTCLKIN*

EXT/INT*

INTERNAL

CLOCK

26

BUSY

*PINS 16 TO 20 ARE LABELED WITH THEIR SERIAL FUNCTIONS

1418 F20

Figure 20ꢁ Functional Block Diagram for Serial ꢄoꢃe (SER/PAR = High)

The SCLK is used to clock the shift register. Data may be

clockedoutwiththeinternalconversionclockoperatingas

amaster byconnectingCLKOUT(Pin18) to SCLK(Pin 17)

or with an external data clock applied to D3 (SCLK). The

minimum number of SCLK cycles required to transfer a

data word is 14. Normally, SCLK contains 16 clock cycles

for a word length of 16 bits; 14 bits with MSB first, fol-

lowed by two trailing zeros.

will all the remaining bits. The data may be captured on

either edge. The largest hold time margin is achieved if

data is captured on the rising edge of SCLK.

BUSY gives the end of conversion indication. When the

LTC1418 is configured as a master serial device, BUSY

can be used as a framing pulse and to three-state the se-

rial port after transferring the serial output data by tying

it to the RD pin.

AlogichighonRDdisablesSCLKandthree-statesD .In

OUT

Figures 22 to 25 show several serial modes of operation,

demonstrating the flexibility of the LTC1418 serial port.

case of using a continuous SCLK, RD can be controlled to

limitthenumberofshiftclockstothedesirednumber(i.e.,

16 cycles) and to three-state D

after the data transfer.

OUT

SERꢂAL DATA ꢀUTPUT DURꢂIG A CꢀIVERSꢂꢀI

A logic high on CS three-states the D

output buffer.

OUT

It also inhibits conversion when it is tied high. In power

shutdown mode (SHDN = low), a high CS selects sleep

mode while a low CS selects nap mode. For normal serial

port operation, CS can be grounded.

Using ꢂnternal Conversion Clock for Conversion anꢃ

Data Transfer

Figure 22 shows data from the previous conversion be-

ing clocked out during the conversion with the LTC1418

internal clock providing both the conversion clock and the

SCLK. The internal clock has been optimized for the fast-

est conversion time, consequently this mode can provide

the best overall speed performance. To select an internal

conversion clock, tie EXT/INT (Pin 20) low. The internal

D

outputs the serial data; 14 bits, MSB first, on the

OUT

falling edge of each SCLK (see Figures 21 and 22). If

16 SCLKs are provided, the 14 data bits will be followed

by two zeros. The MSB (D13) will be valid on the first

rising and the first falling edge of the SCLK. D12 will be

valid on the second rising and the second falling edge as

1418fa

22

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

SCLK

V

IL

t

14

t

15

V

OH

OL

D

OUT

1418 F21

Figure 21ꢁ SCLK to D_ꢀUTDelay

BUSY (= RD)

24

26

23

17

CONVST

BUSY

RD

μP OR DSP

(CONFIGURED

AS SLAVE)

OR

SCLK

LTC1418

CLKOUT

SHIFT

CLKOUT ( = SCLK)

18

REGISTER

D

OUT

19

20

D

OUT

EXT/INT

CS

1418 F22a

25

(SAMPLE N)

CS = EXT/INT = 0

t

(SAMPLE N + 1)

5

CONVST

t

13

t

6

t

8

BUSY (= RD)

HOLD

SAMPLE

HOLD

2

t

10

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

3

CLKOUT (= SCLK)

t

7

Hi-Z

FILL

ZEROS

D

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D13

D12 D11

DATA N

OUT

DATA (N – 1)

t

CONV

t

1418 F22b

11

CLKOUT

(= SCLK)

V

IL

t

14

t

15

V

OH

OL

D

OUT

D13

D12

D11

CAPTURE ON

RISING CLOCK FALLING CLOCK

Figure 22ꢁ ꢂnternal Conversion Clock Selecteꢃꢁ Data Transferreꢃ During Conversion Using the ADC Clock ꢀutput as a ꢄaster

Shift Clock (SCLK Driven from CLKꢀUT)

1418fa

23

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

clock appears on CLKOUT (Pin 18) which can be tied to

SCLK (Pin 17) to supply the SCLK.

It is not recommended to clock data with an external clock

during a conversion that is running on an internal clock

because the asynchronous clocks may create noise.

Using EMternal Clock for Conversion anꢃ Data Transfer

Serial Data ꢀutput After a Conversion

In Figure 23, data from the previous conversion is output

during the conversion with an external clock providing

both the conversion clock and the shift clock. To select

an external conversion clock, tie EXT/INT high and apply

the clock to EXTCLKIN. The same clock is also applied to

SCLK to provide a data shift clock. To maintain accuracy

the conversion clock frequency must be between 30kHz

and 4.5MHz.

Using Internal Conversion Clock and External Data Clock.

In this mode, data is output after the end of each conver-

sion but before the next conversion is started (Figure 24).

The internal clock is used as the conversion clock and an

external clock is used for the SCLK. This mode is useful in

applications where the processor acts as a master serial

device. This mode is SPI and MICROWIRE compatible. It

alsoallowsoperationwhentheSCLKfrequencyisverylow

BUSY (= RD)

24

26

23

CONVST

BUSY

RD

EXTCLKIN ( = SCLK)

μP OR DSP

16

EXTCLKIN

LTC1418

SCLK

17

D

OUT

19

20

D

OUT

EXT/INT

CS

5V

1418 F23a

25

(SAMPLE N)

CS = 0, EXT/INT = 5

t

(SAMPLE N + 1)

5

CONVST

t

13

t

8

6

BUSY (= RD)

HOLD

SAMPLE

HOLD

2

t

dEXTCLKIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

3

EXTCLKIN (= SCLK)

t

10

t

7

Hi-Z

FILL

ZEROS

D

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D13

D12 D11

DATA N

OUT

DATA (N – 1)

t

CONV

t

1418 F23b

11

EXTCLKIN

(= SCLK)

t

LEXTCLKIN

V

t

IL

HEXTCLKIN

D12

t

14

t

15

V

OH

D

OUT

D13

D11

OL

CAPTURE ON

RISING CLOCK FALLING CLOCK

Figure 23ꢁ EMternal Conversion Clock Selecteꢃꢁ Data Transferreꢃ During Conversion Using the EMternal Clock (EMternal Clock

Drives Both EXTCLKꢂI anꢃ SCLK)

1418fa

24

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

24

26

23

17

INT

C0

CONVST

BUSY

RD

SCK

SCLK

LTC1418

μP OR DSP

MISO

19

20

D

OUT

EXT/INT

CS

25

1418 F24a

t

5

CS = EXT/INT = 0

CONVST

t

13

t

6

t

8

SAMPLE

BUSY

RD

HOLD

t

9

1

2

3

4

5

9

6

8

7

8

9

5

10 11 12 13 14 15 16

SCLK

t

10

t

11

Hi-Z

FILL

Hi-Z

D

D13 12 11 10

6

4

3

2

1

0

OUT

ZEROS

(SAMPLE N)

t

DATA N

CONV

1418 F24b

t

LSCLK

SCLK

V

t

IL

HSCLK

t

14

t

15

V

OH

OL

D

OUT

D13

D12

D11

CAPTURE ON

RISING CLOCK FALLING CLOCK

Figure 24ꢁ ꢂnternal Conversion Clock Selecteꢃꢁ Data Transferreꢃ After Conversion Using an EMternal SCLKꢁ BUSY↑

ꢂnꢃicates Enꢃ of Conversion

1418fa

25

For more information www.linear.com/LTC1418

LTC1418

APPLICATIONS INFORMATION

(less than 30kHz). To select the internal conversion clock

tie EXT/INT low. The external SCLK is applied to SCLK.

RD can be used to gate the external SCLK, such that data

identical to Figure 24 except that an external clock is used for

the conversion. This mode allows the user to synchronize the

A/D conversion to an external clock either to have precise

control of the internal bit test timing or to provide a precise

conversion time. As in Figure 24, this mode works when the

SCLK frequency is very low (less than 30kHz). However, the

externalconversionclockmustbebetween30kHzand4.5MHz

to maintain accuracy. If more than 16 SCLKs are provided,

more zeros will be filled in after the data word indefinitely. To

select the external conversion clock tie EXT/INT high. The

external SCLK is applied to SCLK. RD can be used to gate the

externalSCLKsuchthatdatawillclockonlyafterRDgoeslow.

will clock only after RD goes low and to three-state D

OUT

after data transfer. If more than 16 SCLKs are provided,

more zeros will be filled in after the data word indefinitely.

Using EMternal Conversion Clock anꢃ EMternal Data Clock

In Figure 25, data is also output after each conversion is com-

pleted and before the next conversion is started. An external

clock is used for the conversion clock and either another or

the same external clock is used for the SCLK. This mode is

24

16

26

23

CLKOUT

INT

CONVST

CONVST EXTCLKIN

BUSY

RD

C0

μP OR DSP

LTC1418

SCLK

17

19

20

SCK

MISO

D

OUT

EXT/INT

5V

1418 F25a

CS

25

1

5

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

1

2

3

4

CS = 0, EXT/INT = 5

t

dEXTCLKIN

EXTCLKIN

t

7

CONVST

t

13

t

6

8

SAMPLE

BUSY

RD

HOLD

t

9

1

2

3

4

5

6

8

7

8

6

9

5

10 11 12 13 14 15 16

SCLK

t

10

11

Hi-Z

FILL

Hi-Z

D

D13 12 11 10

9

4

3

2

1

0

OUT

ZEROS

(SAMPLE N)

t

CONV

DATA N

1418 F25b

t

LSCLK

SCLK

V

IL

t

HSCLK

t

14

t

15

V

OH

D

OUT

D13

D12

D11

V

OL

CAPTURE ON

RISING CLOCK FALLING CLOCK

Figure 25ꢁ EMternal Conversion Clock Selecteꢃꢁ Data Transferreꢃ After Conversion Using an EMternal SCLKꢁ BUSY↑

ꢂnꢃicates Enꢃ of Conversion

1418fa

26

For more information www.linear.com/LTC1418

LTC1418

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

9.90 – 10.50*

(.390 – .413)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

1.25 0.12

5.3 – 5.7

7.8 – 8.2

7.40 – 8.20

(.291 – .323)

0.42 0.03

RECOMMENDED SOLDER PAD LAYOUT

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12 13 14

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

0.55 – 0.95

(.0035 – .010)

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G28 SSOP 0204

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

1418fa

27

For more information www.linear.com/LTC1418

LTC1418

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

N Package

28-Lead Plastic PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510 Rev I)

1.400*

(35.560)

MAX

28

27 26 25 24

23 22 21 20

19 18 17 16

15

14

.240 – .295*

(6.096 – 7.493)

5

6

7

8

9

10 11 12 13

1

2

3

4

.045 – .065

.130 ±.005

(1.143 – 1.651)

(3.302 ±0.127)

.020

(0.508)

MIN

.065

(1.651)

TYP

N28 REV I 0711

.120

(3.048)

MIN

.005

(0.127)

MIN

.018 ±.003

(0.457 ±0.076)

.100

(2.54)

BSC

NOTE:

1. DIMENSIONS ARE

INCHES

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

OBSOLETE PACKAGE

1418fa

28

For more information www.linear.com/LTC1418

LTC1418

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUM BER

A

07/15 Obsoleted 28-Lead PDIP Package

2, 28

1418fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

For more information www.linear.com/LTC1418

LTC1418

TYPICAL APPLICATION

Single 5V Supply, 200kHz, 14-Bit Sampling A/D Converter

LTC1418

5V

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DIFFERENTIAL

ANALOG INPUT

(0V TO 4.096V)

+

–

A

V

DD

IN

V

10μF

V

SS

REF

3

OUTPUT

2.5V

BUSY

CS

REF

1N5817*

4

REFCOMP

AGND

D13(MSB)

D12

5

1μF

10μF

CONVST

RD

μP CONTROL

LINES

6

7

SHDN

8

D11

SER/PAR

(EXT/INT)D0

9

D10

*REQUIRED ONLY IF V CAN BECOME

SS

POSITIVE WITH RESPECT TO GROUND

10

11

12

13

14

D9

(D )D1

OUT

D8

(CLKOUT)D2

(SCLK)D3

(EXTCLKIN )D4

D5

14-BIT

PARALLEL

BUS

D7

D6

DGND

1418 TA03

RELATED PARTS

PART NUM BER

DESCRIPTION

COM M ENTS

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10mW Power Dissipation, Parallel/Byte Interface

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Single 5V, 16-Bit, 100ksps ADC

70mW Power Dissipation, 80.5dB SINAD

True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation

2.5V Input, SINAD = 90dB, THD = 100dB

Low Power, 10V Inputs, Parallel/Byte Interface

LTC1595

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Reference

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16-Bit CMOS Multiplying DAC in SO-8

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1LSB Max INL/DNL, 1nV • sec Glitch, DAC8043 Upgrade

1LSB Max INL/DNL, DAC8143/AD7543 Upgrade

Precision Bandgap Reference

0.05% Max, 5ppm/°C Max

1418fa

LT 0715 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

For more information www.linear.com/LTC1418

●

 LINEAR TECHNOLOGY CORPORATION 1998

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC1418


型号：	LTC1418IN#PBF
厂家：	Linear
描述：	LTC1418 - Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O; Package: PDIP; Pins: 28; Temperature Range: -40°C to 85°C 光电二极管转换器
文件：	总30页 (文件大小：464K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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