LTC1419AISW#TRPBF [Linear]
LTC1419 - 14-Bit, 800ksps Sampling A/D Converter with Shutdown; Package: SO; Pins: 28; Temperature Range: -40°C to 85°C;
| 型号： | LTC1419AISW#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1419 - 14-Bit, 800ksps Sampling A/D Converter with Shutdown; Package: SO; Pins: 28; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1419
14-Bit, 800ksps Sampling
A/D Converter with Shutdown
U
FEATURES
DESCRIPTIO
The LTC®1419 is a 1µs, 800ksps, 14-bit sampling
A/D converter that draws only 150mW from ±5V supplies.
This easy-to-use device includes a high dynamic range
sample-and-hold and a precision reference. Two digitally
selectable power shutdown modes provide flexibility for
low power systems.
■
Sample Rate: 800ksps
■
Power Dissipation: 150mW
■
81.5dB S/(N + D) and 93dB THD
■
No Missing Codes
No Pipeline Delay
■
■
Nap and Sleep Shutdown Modes
■
Operates with 2.5V Internal 15ppm/°C
The LTC1419 has a full-scale input range of ± 2.5V. Out-
standing AC performance includes 81.5dB S/(N + D) and
93dB THD with a 100kHz input; 80dB S/(N + D) and 86dB
THD at the Nyquist input frequency of 400kHz.
Reference or External Reference
■
True Differential Inputs Reject Common Mode Noise
■
20MHz Full-Power Bandwidth Sampling
Bipolar Input Range: ±2.5V
28-Pin SSOP and SO Packages
■
■
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 20MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
U
APPLICATIO S
■
Telecommunications
■
Digital Signal Processing
The ADC has a µP compatible, 14-bit parallel output port.
There is no pipeline delay in the conversion results. A
separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5581252.
■
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
■
■
■
U
TYPICAL APPLICATIO
800kHz, 14-Bit Sampling A/D Converter
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
LTC1419
5V
DIFFERENTIAL
ANALOG INPUT
(–2.5V TO 2.5V)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
86
80
74
68
62
+A
–A
AV
DV
IN
IN
DD
DD
–5V
V
REF
3
10µF
OUTPUT
2.50V
V
V
SS
REF
4
10µF
REFCOMP
AGND
BUSY
CS
5
10µF
1µF
6
µP CONTROL
LINES
D13(MSB) CONVST
7
8
D12
D11
D10
D9
RD
SHDN
D0
8
7
9
6
10
11
12
13
14
5
D1
14-BIT
PARALLEL
BUS
4
D8
D2
3
D7
D3
f
= 800kHz
10k
SAMPLE
2
D6
D4
1k
100k
1M 2M
DGND
D5
INPUT FREQUENCY (Hz)
1419 TA02
1419 TA01
1419fb
1
LTC1419
ABSOLUTE AXI U RATI GS
W W
U W
U W
U
PACKAGE/ORDER I FOR ATIO
AV = V = DV (Notes 1, 2)
DD
DD
DD
TOP VIEW
ORDER
PART NUMBER
Supply Voltage (VDD)................................................ 6V
Negative Supply Voltage (VSS) ............................... –6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3).............................(VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4) ......... (VSS – 0.3V) to 10V
Digital Output Voltage........ (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1419C .............................................. 0°C to 70°C
LTC1419I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
+A
–A
V
1
2
3
4
5
6
7
8
9
28
AV
DD
IN
27 DV
DD
IN
26
V
SS
REF
LTC1419ACG
LTC1419ACSW
LTC1419AIG
LTC1419AISW
LTC1419CG
LTC1419CSW
LTC1419IG
LTC1419ISW
REFCOMP
25 BUSY
24 CS
AGND
D13(MSB)
D12
23 CONVST
22 RD
D11
21 SHDN
20 D0
D10
D9 10
D8 11
19 D1
18 D2
D7 12
17 D3
D6 13
16 D4
DGND 14
15 D5
G PACKAGE
28-LEAD PLASTIC SSOP
SW PACKAGE
28-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 95°C/W (G)
TJMAX = 125°C, θJA = 130°C/W (SW)
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult factory for Military grade parts.
U
CO VERTER CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. With Internal Reference (Notes 5, 6)
A
LTC1419
TYP
LTC1419A
TYP
PARAMETER
CONDITIONS
(Note 7)
MIN
MAX
MIN
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
13
14
± 0.8
± 0.7
±5
± 2
± 1.5
±20
± 60
±0.6
±0.5
±5
± 1.25
±1
LSB
LSB
(Note 8)
± 20
± 60
LSB
Full-Scale Error
Internal Reference
External Reference = 2.5V
± 10
±5
±10
±5
LSB
LSB
Full-Scale Tempco
I
= 0
± 15
±15
ppm/°C
OUT(REF)
U
U
A ALOG I PUT The
●
denotes specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER
CONDITIONS
4.75V ≤ V ≤ 5.25V, –5.25 ≤ V ≤ –4.75V
MIN
TYP
MAX
UNITS
V
V
IN
Analog Input Range (Note 9)
Analog Input Leakage Current
Analog Input Capacitance
●
●
±2.5
DD
SS
I
CS = High
±1
µA
IN
C
IN
Between Conversions
During Conversions
15
5
pF
pF
t
t
t
Sample-and-Hold Acquisition Time
●
90
–1.5
2
300
ns
ns
ACQ
AP
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
ps
jitter
RMS
CMRR
–2.5V < (–A = A ) < 2.5V
60
dB
IN
IN
1419fb
2
LTC1419
U W
DY A IC ACCURACY The
●
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal
390kHz Input Signal
●
●
●
78
81.5
80.0
dB
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
390kHz Input Signal, First 5 Harmonics
–93
–86
–86
–86
dB
dB
SFDR
IMD
Spurious Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
100kHz Input Signal
–95
–86
20
dB
dB
f
= 29.37kHz, f = 32.446kHz
IN2
IN1
MHz
MHz
Full-Linear Bandwidth
S/(N + D) ≥ 77dB
1
U U
U
I TER AL REFERE CE CHARACTERISTICS
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
2.500
± 15
0.05
2
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
I
= 0
= 0
2.480
2.520
REF
REF
REF
REF
OUT
OUT
ppm/°C
LSB/V
kΩ
4.75V ≤ V ≤ 5.25V, –5.25 ≤ V ≤ –4.75V
DD
SS
–0.1mA ≤
= 0
⏐I
⏐ ≤ 0.1mA
OUT
REFCOMP Output VoltaU ge
U
I
4.06
V
OUT
DIGITAL I PUTS A D DIGITAL OUTPUTS The
●
denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
± 10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
V
= 4.75V
OH
DD
O
O
I = –10µA
4.5
V
V
I = –200µA
●
4.0
V
Low Level Output Voltage
= 4.75V
DD
OL
I = 160µA
0.05
0.10
V
V
O
I = 1.6mA
●
●
●
0.4
± 10
15
O
I
Hi-Z Output Leakage D13 to D0
Hi-Z Output Capacitance D13 to D0
Output Source Current
= 0V to V , CS High
µA
pF
OZ
OUT
DD
C
CS High (Note 9 )
OZ
I
I
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
Output Sink Current
= V
DD
W U
POWER REQUIRE E TS
The
otherwise specifications are at T = 25°C. (Note 5)
●
denotes specifications which apply over the full operating temperature range,
A
SYMBOL PARAMETER
CONDITIONS
(Note 10)
MIN
4.75
TYP
MAX
5.25
–5.25
20
UNITS
V
V
Positive Supply Voltage
Negative Supply Voltage
V
V
DD
SS
(Note 10)
–4.75
I
Positive Supply Current
Nap Mode
●
●
11
1.5
250
mA
mA
µA
DD
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
Sleep Mode
I
Negative Supply Current
Nap Mode
19
100
1
30
mA
µA
µA
SS
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
Sleep Mode
1419fb
3
LTC1419
POWER REQUIRE E TS
W U
The
otherwise specifications are at T = 25°C. (Note 5)
●
denotes specifications which apply over the full operating temperature range,
A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
P
Power Dissipation
Nap Mode
●
150
7.5
1.2
240
12
mW
mW
mW
DIS
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
Sleep Mode
W U
TI I G CHARACTERISTICS
The
●
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
ns
f
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
●
●
●
800
SAMPLE(MAX)
950
90
1150
300
CONV
Acquisition Time
ns
ACQ
Acquisition + Conversion Time
CS to RD Setup Time
CS↓ to CONVST↓ Setup Time
CS↓ to SHDN↓ Setup Time
1040
1250
ns
ACQ + CONV
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
0
ns
1
2
3
4
5
6
40
40
ns
ns
SHDN↑ to CONVST↓ Wake-Up Time (Note 10)
400
ns
CONVST Low Time
(Notes 10, 11)
●
●
40
ns
CONVST to BUSY Delay
C = 25pF
L
20
50
ns
ns
50
t
Data Ready Before BUSY↑
20
15
ns
ns
7
●
●
●
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 10)
(Note 9)
40
ns
ns
8
–5
9
C = 25pF
L
15
20
10
25
35
ns
ns
10
●
●
C = 100pF
L
35
50
ns
ns
t
Bus Relinquish Time
20
25
30
ns
ns
ns
11
0°C ≤ T ≤ 70°C
●
●
A
– 40°C ≤ T ≤ 85°C
A
t
t
RD Low Time
●
●
t
ns
ns
12
13
10
CONVST High Time
40
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A input with – A grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
IN
IN
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V or above V , they
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 650ns after the start of the conversion or after BUSY rises.
SS
DD
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V or above V without latchup.
SS
DD
Note 4: When these pin voltages are taken below V , they will be clamped
by internal diodes. This product can handle input currents greater than
SS
100mA below V without latchup. These pins are not clamped
SS
to V
.
DD
Note 5: V = 5V, V = –5V, f
= 800kHz, t = t = 5ns unless
r f
DD
SS
SAMPLE
otherwise specified.
1419fb
4
LTC1419
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio
vs Input Frequency
Distortion vs Input Frequency
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
V
= 0dB
IN
IN
= –20dB
V
= –60dB
IN
THD
3RD
2ND
1k
10k
100k
1M 2M
1k
10k
100k
1M 2M
1k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1419 G01
1419 G02
1419 G03
Spurious-Free Dynamic Range
vs Input Frequency
Differential Nonlinearity
vs Output Code
Intermodulation Distortion Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1.0
0.5
0
–20
f
f
f
= 800kHz
= 95.8984375kHz
= 104.1015625kHz
SAMPLE
IN1
IN2
–40
–60
0
–80
–0.5
–100
–120
–1.0
250 300
0
4096
8192
12288
16384
10k
100k
1M 2M
0
50 100 150 200
350 400
FREQUENCY (kHz)
OUTPUT CODE
INPUT FREQUENCY (Hz)
1419 G04
1419 G05
1419 G06
Integral Nonlinearity
vs Output Code
Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
80
70
60
50
40
30
20
10
0
1.0
0.5
0
–0.5
V
V
DD
SS
DGND
–1.0
0
4096
8192
12288
16384
1k
10k
100k
1M 2M
1
10
100
1000
10000
OUTPUT CODE
RIPPLE FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1419 G08
1419 G07
1419 G09
1419fb
5
LTC1419
U
U
U
PI FU CTIO S
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
+A (Pin 1): ±2.5V Positive Analog Input.
IN
–A (Pin 2): ±2.5V Negative Analog Input.
IN
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
V
(Pin 3): 2.5V Reference Output. Bypass to AGND
REF
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
AGND (Pin 5): Analog Ground.
D13toD6(Pins6to13):Three-StateDataOutputs.The
output format is 2’s complement.
V
(Pin 26): –5V Negative Supply. Bypass to AGND
SS
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
D5toD0(Pins15to20):Three-StateDataOutputs.The
DV (Pin 27): 5V Positive Supply. Short to Pin 28.
DD
output format is 2’s complement.
AV (Pin 28): 5V Positive Supply. Bypass to AGND
DD
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
U
U
W
FU CTIO AL BLOCK DIAGRA
C
C
SAMPLE
SAMPLE
+A
IN
AV
DD
–A
V
IN
DV
DD
2k
ZEROING SWITCHES
2.5V REF
REF AMP
REF
V
SS
+
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
(4.096V)
14
AGND
DGND
D13
D0
SUCCESSIVE APPROXIMATION
REGISTER
•
•
•
OUTPUT LATCHES
INTERNAL
CLOCK
CONTROL LOGIC
1419 BD
SHDN CONVST
RD
CS BUSY
1419fb
6
LTC1419
TEST CIRCUITS
Load Circuits for Output Float Delay
Load Circuits for Access Timing
5V
5V
1k
1k
DBN
DBN
DBN
DBN
1k
100pF
100pF
1k
C
C
L
L
(A) V TO Hi-Z
OH
(B) V TO Hi-Z
OL
(A) Hi-Z TO V
(B) Hi-Z TO V
O
OH
1419 TC02
1419 TC01
U
W U U
APPLICATIONS INFORMATION
CONVERSION DETAILS
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the +AIN and –AIN inputs are con-
nected to the sample-and-hold capacitors (CSAMPLE) dur-
ingtheacquirephase andthecomparatoroffsetisnulledby
the zeroing switches. In this acquire phase, a minimum
delay of 200ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the CSAMPLE capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the +AIN and –AIN input charges.
The SAR contents (a 14-bit data word) which represents
the difference of +AIN and –AIN are loaded into the 14-bit
output latches.
The LTC1419 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
+C
SAMPLE
SAMPLE
SAMPLE
+A
–A
IN
IN
HOLD
–C
ZEROING SWITCHES
HOLD
SAMPLE
HOLD
HOLD
+C
DAC
DAC
+
–C
COMP
DYNAMIC PERFORMANCE
+V
DAC
–
The LTC1419 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
totesttheADC’sfrequencyresponse, distortionandnoise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
–V
DAC
14
D13
D0
OUTPUT
LATCHES
•
•
•
SAR
1419 F01
Figure 1. Simplified Block Diagram
rithm, the ADC’s spectral content can be examined for
1419fb
7
LTC1419
U
W U U
APPLICATIONS INFORMATION
Effective Number of Bits
frequencies outside the fundamental. Figure 2 shows a
typical LTC1419 FFT plot.
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
0
–20
–40
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 800kHz, the LTC1419 maintains near ideal ENOBs
up to the Nyquist input frequency of 400kHz (refer to
Figure 3).
–60
–80
–100
–120
14
13
12
11
10
9
86
80
74
68
62
–140
50 100 150 200
350 400
0
250 300
FREQUENCY (kHz)
1419 F02a
Figure 2a. LTC1419 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
8
7
0
6
f
f
= 800kHz
SAMPLE
= 375kHz
5
IN
–20
–40
SFDR = 88.3dB
SINAD = 80.1
4
3
f
= 800kHz
10k
SAMPLE
2
1k
100k
1M 2M
–60
–80
INPUT FREQUENCY (Hz)
1419 TA02
–100
–120
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
–140
50 100 150 200
350 400
250 300
0
Total Harmonic Distortion
FREQUENCY (kHz)
1419 F02b
Total harmonic distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
Figure 2b. LTC1419 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 2 shows a typical spectral content with
a 800kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 400kHz.
V22 + V32 + V42 + …Vn2
THD = 20Log
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics.THDvsInputFrequencyis
shown in Figure 4. The LTC1419 has good distortion
performance up to the Nyquist frequency and beyond.
1419fb
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0
–10
–20
–30
–40
–50
–60
–70
(fa + fb). If the two input sine waves are equal in magni-
tude, thevalue(indecibels)ofthe2ndorderIMDproducts
can be expressed by the following formula:
Amplitude at (fa+ fb)
IMD fa + fb = 20Log
(
)
Amplitude at fa
–80
–90
THD
3RD
Peak Harmonic or Spurious Noise
2ND
–100
–110
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
1k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
1419 G03
Figure 4. Distortion vs Input Frequency
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1419 has been designed to optimize input band-
width, allowingtheADCtoundersampleinputsignalswith
frequenciesabovetheconverter’sNyquistFrequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
Driving the Analog Input
The differential analog inputs of the LTC1419 are easy to
drive.Theinputsmaybedrivendifferentiallyorasasingle-
ended input (i.e., the –AIN input is grounded). The +AIN
and –AIN inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1419
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 6). For mini-
mum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
0
f
f
f
= 800kHz
= 95.8984375kHz
= 104.1015625kHz
SAMPLE
IN1
IN2
–20
–40
–60
–80
–100
–120
250 300
0
50 100 150 200
350 400
FREQUENCY (kHz)
1419 G05
Figure 5. Intermodulation Distortion Plot
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that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 200ns for full throughput
rate).
LT®1220:30MHzunity-gainbandwidthvoltagefeedback
amplifier. ±5V to ±15V supplies. Excellent DC specifica-
tions.
LT1223: 100MHz video current feedback amplifier. ±5V
to ± 15V supplies, 6mA supply current. Low distortion at
frequencies above 400kHz. Low noise. Good for AC
applications.
10
1
LT1227: 140MHz video current feedback amplifier. ±5V
to ±15V supplies, 10mA supply current. Lowest distor-
tion at frequencies above 400kHz. Low noise. Best for AC
applications.
0.1
0.01
LT1229/LT1230: Dual/quad 100MHz current feedback
amplifiers. ±2V to ±15V supplies, 6mA supply current
each amplifier. Low noise. Good AC specs.
1
10
100
0.01
0.1
SOURCE RESISTANCE (kΩ)
LT1360: 50MHz voltage feedback amplifier. ±5V to ±15V
1419 F06
supplies, 3.8mA supply current. Good AC and DC specs.
Figure 6. t
vs Source Resistance
ACQ
LT1363: 70MHz, 1000V/µs op amps, 6.3mA supply cur-
rent. Good AC and DC specs.
Choosing an Input Amplifier
LT1364/LT1365: Dual and quad 70MHz, 1000V/µs op
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
lowoutputimpedance(<100Ω)attheclosed-loopband-
width frequency. For example, if an amplifier is used in a
gainof+1andhasaunity-gainbandwidthof50MHz,then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 20MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
amps. 6.3mA supply current per amplifier.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1419 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 20MHz. Any noise
ordistortionproductsthatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
50Ω
1
2
3
4
5
ANALOG INPUT
+A
IN
The best choice for an op amp to drive the LTC1419 will
dependontheapplication. Generallyapplicationsfallinto
two categories: AC applications where dynamic specifi-
cations are most critical and time domain applications
where DC accuracy and settling time are most critical.
The following list is a summary of the op amps that are
suitable for driving the LTC1419. More detailed informa-
tion is available in the Linear Technology databooks, the
LinearViewTM CD-ROM and on our web site at www.linear-
1000pF
–A
IN
LTC1419
V
REF
REFCOMP
AGND
10µF
1419 F07
tech. com.
Figure 7. RC Input Filter
LinearView is a trademark of Linear Technology Corporation.
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5V
1
2
3
many applications. For example, Figure 7 shows a 1000pF
capacitorfrom+AIN togroundanda100Ωsourceresistor
to limit the input bandwidth to 1.6MHz. The 1000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
haveexcellentlinearity.Carbonsurfacemountresistorscan
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
+A
–A
IN
IN
ANALOG
INPUT
V
IN
LT1019A-2.5
V
V
REF
OUT
LTC1419
4
REFCOMP
+
10µF
0.1µF
5
AGND
1419 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
2k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
circuitry, see Figure 8b. The reference amplifier gains the
voltage at the VREF pin by 1.625 to create the required
internal reference voltage. This provides buffering be-
tween the VREF pin and the high speed capacitive DAC. The
reference amplifier compensation pin (REFCOMP, Pin 4)
must be bypassed with a capacitor to ground. The refer-
ence amplifier is stable with capacitors of 1µF or greater.
For the best noise performance, a 10µF ceramic or 10µF
tantaluminparallelwitha0.1µFceramicisrecommended.
Input Range
The±2.5VinputrangeoftheLTC1419isoptimizedforlow
noise and low distortion. Most op amps also perform well
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
Some applications may require other input ranges. The
LTC1419 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1419 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
Internal Reference
The LTC1419 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmedto2.500V.Itisconnectedinternallytoareference
amplifier and is available at VREF (Pin 3) see Figure 8a. A
1
R1
2k
+A
IN
V
ANALOG INPUT
1.25V TO 3V
3
4
REF
BANDGAP
REFERENCE
2.500V
DIFFERENTIAL
2
3
4
5
–A
IN
LTC1419
REFCOMP
1.25V TO 3V
REFERENCE
AMP
4.0625V
LTC1450
V
REF
R2
40k
REFCOMP
AGND
10µF
10µF
R3
64k
AGND
5
LTC1419
1419 F09
1419 F08a
Figure 9. Driving V
with a DAC
Figure 8a. LTC1419 Reference Circuit
REF
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Differential Inputs
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
The LTC1419 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of +AIN – (–AIN) independent of the
common mode voltage (see Figure 11a). The common
mode rejection holds up to extremely high frequencies,
see Figure 10a. The only requirement is that both inputs
can not exceed the AVDD or AVSS power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
astheinputsapproacheitherpowersupplyrail,from86dB
with a common mode of 0V to 76dB with a common mode
of 2.5V or –2.5V.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics
for the LTC1419. The code transitions occur midway
between successive integer LSB values (i.e., –FS +
0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,
FS –0.5LSB). The output is two’s complement binary with
1LSB = FS – (–FS)/16384 = 5V/16384 = 305.2µV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
80
70
60
50
40
30
20
10
0
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
1
10
100
1000
10000
–(FS – 1LSB)
FS – 1LSB
INPUT FREQUENCY (Hz)
INPUT VOLTAGE [+A – (–A )]
IN
IN
1419 G09
1419 F11a
Figure 10a. CMRR vs Input Frequency
Figure 11a. LTC1419 Transfer Characteristics
5V
ANALOG
1
INPUT
R3
24k
ANALOG INPUT
+A
IN
1
2
+A
–A
2
IN
IN
R8
50k
–A
IN
R4
0V TO
5V
+
–
±2.5V
100Ω
3
V
LTC1419
REF
3
4
R5 R7
47k 50k
LTC1419
V
REF
R6
24k
REFCOMP
AGND
4
5
REFCOMP
AGND
5
+
10µF
0.1µF
10µF
1419 F11b
1419 F10
Figure 10b. Selectable 0V to 5V or ±2.5V Input Range
Figure 11b. Offset and Full-Scale Adjust Circuit
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applied to the –AIN input. For zero offset error, apply
–152µV (i.e., –0.5LSB) at +AIN and adjust the offset at the
–AIN input until the output code flickers between 0000
0000 0000 00 and 1111 1111 1111 11. For full-scale
adjustment,aninputvoltageof2.499544V(FS/2–1.5LSBs)
is applied to + AIN and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1419 has differential inputs to minimize noise
coupling. Common mode noise on the +AIN and –AIN
leads will be rejected by the input CMRR. The –AIN input
can be used as a ground sense for the +AIN input; the
LTC1419 will hold and convert the difference voltage
between+AIN and–AIN.Theleadsto+AIN (Pin1)and–AIN
(Pin 2) should be kept as short as possible. In applications
wherethisisnotpossible,the+AIN and–AIN tracesshould
be run side by side to equalize coupling.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1419, a printed circuit board
with ground plane is required. Layout should ensure that
digital and analog signal lines are separated as much as
possible. Particular care should be taken not to run any
digital track alongside an analog signal track or under-
neath the ADC.The analog input should be screened by
AGND.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins
as shown in the Typical Application on the fist page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively, 10µF tantalum
capacitorsinparallelwith0.1µFceramiccapacitorscanbe
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the DVDD bypass capacitor should also be connected to
this analog ground plane. No other digital grounds should
beconnectedtothisanaloggroundplane. Lowimpedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layoutofasuggestedevaluationboard.Thelayoutdemon-
stratestheproperuseofdecouplingcapacitorsandground
plane with a 2-layer printed circuit board.
1
DIGITAL
SYSTEM
LTC1419
+A
IN
–A
IN
REFCOMP
4
AGND
5
V
AV DV
DD
DGND
14
SS
DD
27
ANALOG
INPUT
CIRCUITRY
2
26
10µF
28
+
–
10µF
10µF
ANALOG GROUND PLANE
1419 F12
Figure 12. Power Supply Grounding Practice
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Figure 13b. Suggested Evaluation Circuit Board—Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board—Component Side Layout
1419fb
15
LTC1419
APPLICATIONS INFORMATION
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Figure 13d. Suggested Evaluation Circuit Board—Solder Side Layout
DIGITAL INTERFACE
mode reduces the power by 95% and leaves only the
digitallogicandreferencepoweredup. Thewake-uptime
from nap to active is 400ns. In sleep mode, the reference
is shut down and only a small current remains, about
250µA. Wake-up time from sleep mode is much slower
since the reference circuit must power up and settle to
0.005% for full 14-bit accuracy. Sleep mode wake-up
timeisdependentonthevalueofthecapacitorconnected
to the REFCOMP (Pin 4). The wake-up time is 10ms with
the recommended 10µF capacitor. Shutdown is con-
trolled by Pin 21 (SHDN); the ADC is in shutdown when it
is low. The shutdown mode is selected with Pin 20 (CS);
low selects nap.
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a
conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.95µs and a maximum conversion time over the
full operating temperature range of 1.15µs. No external
adjustments are required. The guaranteed maximum
acquisitiontimeis300ns.Inaddition,athroughputtimeof
1.25µs and a minimum sampling rate of 800ksps are
guaranteed.
CS
t
3
SHDN
1419 F14a
Power Shutdown
Figure 14a. CS to SHDN Timing
The LTC1419 provides two power shutdown modes, nap
andsleep, tosavepowerduringinactiveperiods. Thenap
1419fb
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In slow memory and ROM modes (Figures 19 and 20), CS
istiedlowandCONVSTandRDaretiedtogether. TheMPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
SHDN
t
3
CONVST
1419 F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
In slow memory mode, the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
appliedtotheCONVSTpinwillstartaconversionafterthe
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
In ROM mode, the processor takes RD (= CONVST) low,
startingaconversionandreadingthepreviousconversion
result. Aftertheconversioniscomplete, theprocessorcan
read the new result and initiate another conversion.
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17), CS
and RD are both tied low. The falling edge of CONVST
startstheconversion.Thedataoutputsarealwaysenabled
and data can be latched with the BUSY rising edge. Mode
1a shows operation with a narrow logic low CONVST
pulse. Mode 1b shows a narrow logic high CONVST pulse.
CS
t
1
RD
1419 F15
In mode 2 (Figure 18), CS is tied low. The falling edge of
the CONVST signal again starts the conversion. Data
outputs are in three-state until read by the MPU with the
RD signal. Mode 2 can be used for operation with a shared
MPU databus.
Figure 15. CS to CONVST Set-Up Timing
t
CONV
CS = RD = 0
CONVST
(SAMPLE N)
t
5
t
t
8
6
BUSY
DATA
t
7
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1419 F16
Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
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APPLICATIONS INFORMATION
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t
CS = RD = 0
t
8
CONV
t
t
13
5
CONVST
t
t
6
t
6
6
BUSY
DATA
t
7
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1419 F17
Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
13
(SAMPLE N)
t
t
8
CS = 0
CONV
t
5
CONVST
BUSY
RD
t
6
t
t
11
9
t
12
t
10
DATA N
DB13 TO DB0
DATA
1419 F18
Figure 18. Mode 2. CONVST Starts a Conversion. Data is Read by RD
t
t
8
CS = 0
CONV
(SAMPLE N)
RD = CONVST
t
t
11
6
BUSY
DATA
t
t
7
10
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1419 F19
Figure 19. Slow Memory Mode Timing
1419fb
18
LTC1419
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PPLICATI
A
S I FOR ATIO
t
t
8
CONV
CS = 0
(SAMPLE N)
RD = CONVST
BUSY
t
t
11
6
t
10
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA
1419 F20
Figure 20. ROM Mode Timing
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 – 10.33*
(0.397 – 0.407)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
7.65 – 7.90
(0.301 – 0.311)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.65
(0.0256)
BSC
0.13 – 0.22
0.55 – 0.95
(0.005 – 0.009)
(0.022 – 0.037)
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
G28 SSOP 1098
1419fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1419
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 – 0.712*
(17.70 – 18.08)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10 11 12 13 14
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
BSC
0.004 – 0.012
0.009 – 0.013
NOTE 1
(0.102 – 0.305)
(0.229 – 0.330)
0.014 – 0.019
(0.356 – 0.482)
TYP
S28 (WIDE) 1098
0.016 – 0.050
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
LTC1278/79
LTC1400
DESCRIPTION
COMMENTS
Single Supply, 500ksps/600ksps ADCs
High Speed, Serial 12-Bit ADC
Low Power, 12-Bit, 800ksps Sampling ADC
12-Bit, 1.25Msps Sampling ADC with Shutdown
Single 5V, 12-Bit 1.25Msps ADC
16-Bit 333ksps ADC
Low Power, 5V or ±5V Supply
400ksps, Complete with Internal Reference, SO-8 Package
Best Dynamic Performance, f ≤ 800ksps, 80mW Dissipation
LTC1409
SAMPLE
LTC1410
Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist
Single Supply, 55mW Dissipation
LTC1415
LTC1604
±2.5V Inputs, Pin Compatible with the LTC1608
Low Power, ±10V Inputs
LTC1605
Single 5V, 16-Bit 100ksps ADC
16-Bit 250ksps ADC
LTC1606
±10V Inputs, Pin Compatible with the LTC1605
±2.5V Inputs, Pin Compatible with the LTC1604
LTC1608
16-Bit 500ksps ADC
1419fb
LT 0506 REV B • PRINTED IN USA
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
20
●
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© LINEAR TECHNOLOGY CORPORATION 1997
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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