LTC1458LCSW#TR [Linear]

LTC1458 - Quad 12-Bit Rail-to-Rail Micropower DACs; Package: SO; Pins: 28; Temperature Range: 0°C to 70°C;


型号：	LTC1458LCSW#TR
厂家：	Linear
描述：	LTC1458 - Quad 12-Bit Rail-to-Rail Micropower DACs; Package: SO; Pins: 28; Temperature Range: 0°C to 70°C
文件：	总12页 (文件大小：252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail

Micropower DACs

DESCRIPTION

FEATURES

The LTC^®1458/LTC1458L are complete single supply,

quad rail-to-rail voltage output, 12-bit digital-to-analog

converters(DACs)inSO-28andSSOP-28packages. They

includeanoutputbufferamplifierwithvariablegain(×1or

×2)andaneasy-to-use3-wirecascadableserialinterface.

■

12-Bit Resolution

■

Buffered True Rail-to-Rail Voltage Output

■

5V Operation, I_CC: 1.1mA Typ (LTC1458)

3V Operation, I_CC: 800µA Typ (LTC1458L)

■

Built-In Reference: 2.048V (LTC1458)

1.220V (LTC1458L)

The LTC1458 has an onboard reference of 2.048V and a

full-scale output of 4.095V in a ×2 gain configuration. It

operates from a single 4.5V to 5.5V supply dissipating

only 5.5mW (I_CC= 1.1mA typ).

■

CLR Pin

■

Power-On Reset

■

SSOP-28 Package

■

3-Wire Cascadable Serial Interface

Maximum DNL Error: 0.5LSB

■

The LTC1458L has an onboard 1.22V reference and a full-

scale output of 2.5V in a×2 gain configuration. It operates

from a single supply of 2.7V to 5.5V dissipating 2.4mW.

Low Cost

APPLICATIONS

Excellent DNL, low supply current and a wide range of

built-in functions allow these parts to be used in a host of

applications when flexibility, power and single supply

operation are important.

■

Digital Calibration

■

Industrial Process Control

Automatic Test Equipment

Low Power Systems

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATION

Daisy-Chained Control Outputs

Functional Block Diagram: Quad 12-Bit Rail-to-Rail DAC

Differential Nonlinearity

FROM µP

2.048V (LTC1458)

1.22V (LTC1458L)

5V (LTC1458)

3V TO 5V (LTC1458L)

vs Input Code

0.5

0.4

REFOUT

CS/LD

CLK

REFHI C

REFHI B

0.3

0.2

0.1

OUT C

OUT B

DAC C

DAC B

DAC A

X1/X2 C

REFLO C

X1/X2 B

REFLO B

48-BIT

–0.1

–0.2

–0.3

–0.4

–0.5

SHIFT REGISTER

AND

REFHI D

REFHI A

DAC REGISTER

OUT A

OUT D

DAC D

X1/X2 A

REFLO A

X1/X2 D

REFLO D

512 1024 1536

2048

2560 4095

3072 3584

CODE

1458 G09

OUT

CLR

1458 BD01

LTC1458/LTC1458L

W W

U W

PACKAGE RDER I FOR ATIO

ABSOLUTE MAXIMUM RATINGS

V_CCto GND .............................................. –0.5V to 7.5V

TOP VIEW

ORDER PART

Logic Inputs to GND ................................ –0.5V to 7.5V

27 X1/X2 B

X1/X2 C

NUMBER

OUT C

CS/LD

_{OUT A}, V_{OUT B}, V_{OUT C}, V_{OUT D}

OUT B

X1/X2 A, X1/X2 B, X1/X2 C,

25 CLR

LTC1458CG

24 REFHI B

23 GND

REFHI C

GND

X1/X2 D ......................................... –0.5V to V_CC+ 0.5V

REFHI A, REFHI B, REFHI C, REFHI D,

REFLO A, REFLO B, REFLO C,

REFLO D ........................................ –0.5V to V_CC+ 0.5V

Maximum Junction Temperature ......................... 125°C

Operating Temperature Range

LTC1458C/LTC1458LC .......................... 0°C to 70°C

LTC1458I/LTC1458LI ...................... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

LTC1458CSW

LTC1458LCG

LTC1458LCSW

22 REFLO B

21 REFLO A

20 REFHI A

19 REFOUT

18 NC

REFLO C

REFLO D

REFHI D

OUT

CLK

16 X1/X2 A

OUT A

OUT D

X1/X2 D

G PACKAGE

SW PACKAGE

28-LEAD PLASTIC SSOP

28-LEAD PLASTIC SO WIDE

T_JMAX= 125°C, θ_JA= 100°C/W (G)

_JMAX= 125°C, θ_JA= 150°C/W (SW)

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

V_CC= 4.5V to 5.5V (LTC1458), 2.7V to 5.5V (LTC1458L), X1/X2 = REFLO = GND, REFHI = REFOUT, V_OUTunloaded, T_A= T_MINto T_MAX

unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DAC

Resolution

●

Bits

LSB

DNL

INL

Differential Nonlinearity

Guaranteed Monotonic (Note 1)

±0.5

Integral Nonlinearity

T = 25°C

(Note 1)

±1.75

±2.25

±4.0

±4.5

LSB

●

Offset Error

T = 25°C

±3.0

±6.0

±12

±18

Offset Error Temperature

Coefficient

±15

µV/°C

Full-Scale Voltage

When Using Internal Reference, LTC1458, T = 25°C

4.065

4.045

4.095

4.125

4.145

LTC1458

●

When Using Internal Reference, LTC1458L, T = 25°C

2.470

2.460

2.500

2.530

2.540

LTC1458L

Full-Scale Voltage

Temperature Coefficient

When Using Internal Reference

± 24

ppm/°C

Reference

Reference Output Voltage

LTC1458

LTC1458L

●

2.008

1.195

2.048

1.220

2.088

1.245

Reference Output

±20

ppm/°C

Temperature Coefficient

Reference Line Regulation

Reference Load Regulation

●

0.7

±2.0

LSB/V

0 ≤ I

≤ 100µA, LTC1458

●

0.2

0.6

1.5

3.0

LSB

OUT

LTC1458L

Reference Input Range

≤ V – 1.5V

V /2

REFHI

Reference Input Resistance

●

kΩ

LTC1458/LTC1458L

ELECTRICAL CHARACTERISTICS

V_CC= 4.5V to 5.5V (LTC1458), 2.7V to 5.5V (LTC1458L), X1/X2 = REFLO = GND, REFHI = REFOUT, V_OUTunloaded, T_A= T_MINto T_MAX

unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input Capacitance

Short-Circuit Current

Power Supply

REFOUT Shorted to GND

●

120

Positive Supply Voltage

For Specified Performance, LTC1458

LTC1458L

●

4.5

2.7

5.5

Supply Current

4.5V ≤ V ≤ 5.5V (Note 4) , LTC1458

●

1100

800

2400

2000

µA

2.7V ≤ V ≤ 5.5V (Note 4), LTC1458L

Op Amp DC Performance

Short-Circuit Current Low

Shorted to GND

●

120

Ω

OUT

Short-Circuit Current High

Output Impedance to GND

Shorted to V

Input Code = 0

AC Performance

Voltage Output Slew Rate

Voltage Output Settling Time

Digital Feedthrough

(Note 2)

●

0.5

1.0

V/µs

µs

(Notes 2, 3) to ±0.5LSB

0.3

–95

nV• s

AC Feedthrough

REFHI = 1kHz, 2V , (Code: All 0s)

P-P

SINAD

Signal-to-Noise + Distortion

REFHI = 1kHz, 2V , (Code: All 1s)

P-P

V_CC= 5V (LTC1458), 3V (LTC1458L), T_A= T_MINto T_MAX

LTC1458

TYP

LTC1458L

TYP

SYMBOL PARAMETER

Digital I/O

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

Digital Input High Voltage

Digital Input Low Voltage

Digital Output High Voltage

Digital Output Low Voltage

Digital Input Leakage

●

2.4

2.0

0.8

0.6

= –1mA

= 1mA

– 1.0

V – 0.7

OUT

0.4

±10

0.4

±10

= GND to V

µA

LEAK

Digital Input Capacitance

Guaranteed by Design,

Not Subject to Test

Switching

Valid to CLK Setup

Valid to CLK Hold

●

CLK High Time

CLK Low Time

CS/LD Pulse Width

LSB CLK to CS/LD

CS/LD Low to CLK

Output Delay

= 15pF

LOAD

150

220

OUT

CLK Low to CS/LD Low

LTC1458/LTC1458L

ELECTRICAL CHARACTERISTICS

Note 2: Load is 5kΩ in parallel with 100pF.

The

● denotes specifications which apply over the full operating

temperature range.

Note 3: DAC switched between all 1s and the code corresponding to V

for the part.

Note 4: Digital inputs at 0V or V

Note 1: Nonlinearity is defined from the first code that is greater than or

equal to the maximum offset specification to code 4095 (full scale).

U W

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1458

Minimum Supply Headroom for

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Full Output Swing vs Load Current

0.5

0.4

1.4

2.0

1.6

∆V

< 1LSB

OUT

1.2

1.0

0.8

0.6

0.4

0.2

REFLO = GND

X1/X2 = GND

CODE: ALL 1's

0.3

1.2

0.2

0.8

= 4.095V

OUT

0.1

0.4

–0.1

–0.2

–0.3

–0.4

–0.5

–0.4

–0.8

–1.2

–1.6

–2.0

2048

3072 3584

3584

4095

512 1024 1536

2560

4095

2048

3072

512 1024 1536

2560

LOAD CURRENT (mA)

CODE

1458 G03

1458 G09

1458 G08

Minimum Output Voltage vs

Output Sink Current

Output Swing vs Load Resistance

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

1000

900

800

700

600

500

400

300

200

100

0.1

REFLO = GND

X1/X2 = GND

REFLO = GND

X1/X2 = GND

REFLO = GND

X1/X2 = GND

25°C

125°C

–55°C

100

10k

100

10k

OUTPUT SINK CURRENT (mA)

LOAD RESISTANCE (Ω)

1458 G05A

1458 G06A

1458 G04

LTC1458/LTC1458L

U W

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1458

Supply Current vs Temperature

LTC1458 Full-Scale Voltage vs

Temperature

LTC1458

Offset Voltage vs Temperature

950

4.110

4.105

4.100

4.095

4.090

4.085

4.080

940

930

920

910

900

890

880

870

860

850

= 5.5V

= 5V

–1

–2

–3

–4

–5

= 4.5V

–55

125

–25

–55

125

–25

–55

125

–25

TEMPERATURE (°C)

1458 G05

1458 G06

1458 G07

PIN FUNCTIONS

X1/X2 C, X1/X2 D,X1/X2 A, X1/X2 B (Pins 1, 14, 16, 27):

The Input Pin that Sets the Gain for DAC C/D/A/B. When

grounded the gain will be 2, i.e., output full-scale will be

2 • REFHI. When connected to V_OUTthe gain will be 1, i.e.,

output full-scale will be equal to REFHI.

REFLO C, REFLO D, REFLO A, REFLO B, (Pins 7, 8, 21,

22): The Bottom of the DAC Resistor Ladders for the

DACs. These can be used to offset zero-scale above

ground. REFLO should be connected to ground when no

offset is required.

V_{OUT C}, V_{OUT D}, V_{OUT A}, V_{OUT B}(Pins 2, 13, 17, 26): The

Buffered DAC Outputs.

D_OUT(Pin 10): The Output of the Shift Register which

Becomes Valid on the Rising Edge of the Serial Clock.

CS/LD (Pin 3): The Serial Interface Enable and Load

CLK (Pin 11): The Serial Interface Clock Input.

Control Input.

V_CC(Pins 15, 28): The Positive Supply Input. 4.5V ≤ V_CC

≤ 5.5V (LTC1458), 2.7V ≤ V_CC≤ 5.5V (LTC1458L). Re-

quires a bypass capacitor to ground.

D_IN(Pin 4): The Serial Data Input.

REFHI C, REFHI D, REFHI A, REFHI B,(Pins 5, 9, 20, 24):

The Inputs to the DAC Resistor Ladder for DAC C/D/A/B.

REFOUT (Pin 19): The Output of the Internal Reference.

GND (Pins 6, 23): Ground.

CLR (Pin 25): The Clear Pin. Clears all DACs to zero-scale

when pulled low.

LTC1458/LTC1458L

BLOCK DIAGRA

X1/X2 C

12-BIT

DAC C

12-BIT

DAC B

DAC C

DAC B

X1/X2 B

OUT C

CS/LD

OUT B

POWER-ON

RESET

25 CLR

REFHI C

GND

24 REFHI B

23 GND

REFLO C

REFLO D

REFHI D

REFLO B

48-BIT SHIFT REGISTER

21 REFLO A

20 REFHI A

LTC1458: 2.048V

LTC1458L: 1.22V

REFOUT

OUT

CLK

18 NC

OUT A

12-BIT

DAC A

DAC D

DAC A

X1/X2 A

OUT D

X1/X2 D

REFHI

OUT

–

REFLO

X1/X2

1458 BD

LTC1458/LTC1458L

W U

TI I G DIAGRA

CLK

B0 D

PREVIOUS WORD

B11 A

MSB

B0 B

LSB

B11 C

MSB

B0 D

LSB

CS/LD

B11 A

PREVIOUS WORD

B0 B

B11 C

B0 D

PREVIOUS WORD

B11 A

CURRENT WORD

B10 A

PREVIOUS WORD

OUT

PREVIOUS WORD PREVIOUS WORD

1458 TD

U U

DEFI ITIO S

Resolution (n): Resolution is defined as the number of

digital input bits, n. It defines the number of DAC output

states (2ⁿ) that divide the full-scale range. The resolution

does not imply linearity.

The offset of the part is measured at the code that corre-

sponds to the maximum offset specification:

V_OS= V_OUT– [(Code)(V_FS)/(2ⁿ– 1)]

Least Significant Bit (LSB): One LSB is the ideal voltage

difference between two successive codes.

Full-Scale Voltage (V_FS): This is the output of the DAC

when all bits are set to 1.

LSB = (V_FS– V_OS)/(2ⁿ– 1) = (V_FS– V_OS)/4095

Nominal LSBs:

Voltage Offset Error (V_OS): The theoretical voltage at the

output when the DAC is loaded with all zeros. The output

amplifier can have a true negative offset, but because the

partisoperatedfromasinglesupply, theoutputcannotgo

below zero. If the offset is negative, the output will remain

near 0V resulting in the transfer curve shown in Figure 1.

LTC1458

LSB = 4.095V/4095 = 1mV

LTC1458L LSB = 2.5V/4095 = 0.610mV

Integral Nonlinearity (INL): End-point INL is the maxi-

mum deviation from a straight line passing through the

end-points of the DAC transfer curve. Because the part

operates from a single supply and the output cannot go

below zero, the linearity is measured between full scale

and the code corresponding to the maximum offset

specification. The INL error at a given input code is

calculated as follows:

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

DAC CODE

1458 F01

INL = [V_OUT– V_OS– (V_FS– V_OS)(code/4095)]/LSB

V_OUT= The output voltage of the DAC measured at

the given input code

Figure 1. Effect of Negative Offset

LTC1458/LTC1458L

U U

DEFI ITIO S

Differential Nonlinearity (DNL): DNL is the difference

between the measured change and the ideal 1LSB change

between any two adjacent codes. The DNL error between

any two codes is calculated as follows:

DigitalFeedthrough: Theglitchthatappearsattheanalog

outputcausedbyACcouplingfromthedigitalinputswhen

they change state. The area of the glitch is specified in

(nV)(sec).

DNL = (∆V_OUT– LSB)/LSB

∆V_OUT= The measured voltage difference between

two adjacent codes

OPERATIO

Serial Interface

Reference

The data on the D_INinput is loaded into the shift register

ontherisingedgeoftheclock. Dataisloadedasone48-bit

word, DACAfirst, thenDACB, DACCandDACD. TheMSB

is loaded first for each DAC. The DAC registers load the

datafromtheshiftregisterwhenCS/LDispulledhigh. The

CLK is disabled internally when CS/LD is high. Note: CLK

must be low before CS/LD is pulled low to avoid an extra

internal clock pulse.

The LTC1458L has an internal reference of 1.22V with a

full scale of 2.5V (gain of 2 configuration). The LTC1458

includes an internal 2.048V reference, making 1LSB equal

to 1mV (gain of 2 configuration). When the buffer gain is

2, the external reference must be less than V_CC/2 and be

capable of driving the 15k minimum DAC resistor ladder.

The external reference must always be less than

V_CC– 1.5V.

The buffered output of the 48-bit shift register is available

on the D_OUTpin which swings from ground to V_CC.

Voltage Output

The rail-to-rail buffered output of the LTC1458 family can

source or sink 5mA when operating with a 5V supply over

the entire operating temperature range while pulling to

within 300mV of the positive supply voltage or ground.

The output swings to within a few millivolts of either

supply rail when unloaded and has an equivalent output

resistance of 40Ω when driving a load to the rails. The

output can drive 1000pF without going into oscillation.

Multiple LTC1458/LTC1458Ls may be daisy-chained to-

getherbyconnectingtheD_OUTpintotheD_INpinofthenext

chip, while the CLK and CS/LD signals remain common to

all chips in the daisy-chain. The serial data is clocked to all

of the chips, then the CS/LD signal is pulled high to update

all of them simultaneously.

LTC1458/LTC1458L

W U U

APPLICATIONS INFORMATION

Using Two DACs to Digitally Program the Full Scale

and Offset of a Third

≤ 2,500 for V_CC= 5V, since DAC C is being operated in × 2

mode for full rail-to-rail output swing.

Figure 2 shows how to use one LTC1458 to make a 12-bit

DAC with a digitally programmable full scale and offset.

DAC A and DAC B are used to control the offset and full

scale of DAC C. DAC A is connected in a ×1 configuration

andcontrolstheoffsetofDACCbymovingREFLOCabove

ground. The minimum value to which this offset can be

programmed is 10mV. DAC B is connected in a × 2

configuration and controls the full scale of DAC C by

driving REFHI C. Note that the voltage at REFHI C must be

lessthanorequaltoV_CC/2,correspondingtoDACB’scode

The transfer characteristic is:

_OUTC= 2 • [D_C• (2 • D_B– D_A) + D_A] • REFOUT

where REFOUT = The Reference Output

D_A= (DAC A Digital Code)/4096

This sets the offset.

D_B= (DAC B Digital Code)/4096

This sets the full scale.

D_C= (DAC C Digital Code)/4096

X1/X2 C

0.1µF

X1/X2 B

OUT C

OUT

CS/LD

OUT B

CLR

REFHI B

GND

REFHI C

GND

LTC1458

LTC1458L

REFLO B

REFLO A

REFHI A

REFOUT

REFLO C

REFLO D

REFHI D

500Ω

OUT

CLK

OUT A

X1/X2 A

OUT D

X1/X2 D

1458 F02

Figure 2

LTC1458/LTC1458L

PACKAGE DESCRIPTION ^{Dimensions in inches (millimeters) unless otherwise noted.}

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

0.397 – 0.407*

(10.07 – 10.33)

28 27 26 25 24 23 22 21 20 19 18

16 15

0.301 – 0.311

(7.65 – 7.90)

9 10 11 12 13 14

0.205 – 0.212**

(5.20 – 5.38)

0.068 – 0.078

(1.73 – 1.99)

0° – 8°

0.0256

(0.65)

BSC

0.005 – 0.009

(0.13 – 0.22)

0.022 – 0.037

(0.55 – 0.95)

0.002 – 0.008

(0.05 – 0.21)

0.010 – 0.015

(0.25 – 0.38)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

G28 SSOP 0694

LTC1458/LTC1458L

PACKAGE DESCRIPTION ^{Dimensions in inches (millimeters) unless otherwise noted.}

SW Package

28-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

0.697 – 0.712*

(17.70 – 18.08)

28 27 26 25 24 23 22 21 20 19 18

16 15

0.394 – 0.419

(10.007 – 10.643)

NOTE 1

0.291 – 0.299**

(7.391 – 7.595)

10 11 12 13 14

0.037 – 0.045

(0.940 – 1.143)

0.093 – 0.104

(2.362 – 2.642)

0.010 – 0.029

(0.254 – 0.737)

× 45°

0° – 8° TYP

0.050

(1.270)

TYP

0.004 – 0.012

(0.102 – 0.305)

0.009 – 0.013

NOTE 1

(0.229 – 0.330)

0.014 – 0.019

(0.356 – 0.482)

TYP

0.016 – 0.050

(0.406 – 1.270)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

S28 (WIDE) 0996

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

LTC1458/LTC1458L

TYPICAL APPLICATION

LTC1458: 4.5V TO 5.5V

LTC1458L: 2.7V TO 5.5V

X1/X2 C

LTC1458: 0V TO 4.095V

LTC1458L: 0V TO 2.5V

0.1µF

X1/X2 B

OUT C

LTC1458: 0V TO 4.095V

LTC1458L: 0V TO 2.5V

CS/LD

OUT B

µP

CLR

REFHI B

GND

REFHI C

GND

REFLO B

REFLO A

REFHI A

REFOUT

REFLO C

REFLO D

REFHI D

LTC1458

LTC1458L

LTC1458: 2.048V

LTC1458L: 1.22V

OUT

CLK

LTC1458: 0V TO 4.095V

LTC1458L: 0V TO 2.5V

OUT A

LTC1458: 0V TO 4.095V

LTC1458L: 0V TO 2.5V

X1/X2 A

OUT D

X1/X2 D

1458 TA03

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1257

Single 12-Bit V

Reference Can Be Overdriven up to 12V, i.e., FS

DAC, Full Scale: 2.048V, V : 4.75V to 15.75V,

5V to 15V Single Supply, Complete V

SO-8 Package

DAC in

OUT

= 12V

MAX

LTC1446/LTC1446L

LTC1450/LTC1450L

Dual 12-Bit Rail-to-Rail Output DACs in SO-8 Package

LTC1446: V = 4.5V to 5.5V, V

= 0V to 4.095V

OUT

LTC1446L: V = 2.7V to 5.5V, V

= 0V to 2.5V

OUT

Single 12-Bit Rail-to-Rail Output DACs with Parallel Interface

LTC1450: V = 4.5V to 5.5V, V

= 0V to 4.095V

OUT

LTC1450L: V = 2.7V to 5.5V, V

= 0V to 2.5V

OUT

LTC1451

LTC1452

Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, V : 4.5V to 5.5V

Low Power, Complete V

DAC in SO-8 Package

OUT

Single Rail-to-Rail 12-Bit V

Multiplying DAC, V : 2.7V to 5.5V

Low Power, Multiplying V

Buffer Amplifier in SO-8 Package

3V, Low Power, Complete V

DAC with Rail-to-Rail

DAC in SO-8 Package

OUT

LTC1453

Single Rail-to-Rail 12-Bit V

DAC, Full Scale: 2.5V, V : 2.7V to 5.5V

OUT

LTC1454/LTC1454L

Dual 12-Bit V

DACs in SO-16 Package with Added Functionality

LTC1454: V = 4.5V to 5.5V, V

= 0V to 4.095V

OUT

LTC1454L: V = 2.7V to 5.5V, V

= 0V to 2.5V

OUT

LTC1456

Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,

Low Power, Complete V

with Clear Pin

DAC in SO-8 Package

OUT

Full Scale: 4.095V, V : 4.5V to 5.5V

14588lf LT/TP 0397 7K • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1996

12 ^{Linear Technology Corporation}

●

1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900

●

FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com

LTC1458LCSW#TR [Linear]

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