LTC1590IS#TR [Linear]
LTC1590 - Dual Serial 12-Bit Multiplying DAC; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC1590IS#TR |
| 厂家： | 
Linear |
| 描述： | LTC1590 - Dual Serial 12-Bit Multiplying DAC; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1590
Dual Serial 12-Bit
Multiplying DAC
U
FEATURES
DESCRIPTION
The LTC®1590 is a dual, serial input 12-bit multiplying
digital-to-analog converter (DAC). It includes two current
output multiplying CMOS DACs and an easy SPI compat-
ible serial interface with daisy-chain output. An asynchro-
nous CLR pin sets both DACs to zero scale.
■
DNL and INL Over Temperature: ±0.5LSB Max
■
Gain Error:
±
1LSB Max
■
■
■
■
■
■
Low Supply Current: 10
µA Max
4-Quadrant Multiplication
Power-On Reset
Asynchronous Clear Input
Daisy-Chain 3-Wire Serial Interface
16-Pin Narrow SUO and PDIP Packages
Excellent accuracy, stability and versatility are combined
with the smallest package available for a dual 12-bit
multiplying DAC.
Parts are available in 16-pin PDIP and narrow SO pack-
ages and are specified over the commercial and industrial
temperature ranges.
APPLICATIONS
■
Process Control and Industrial Automation
Software Controlled Gain Adjustment
Digitally Controlled Filter and Power Supplies
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Automatic Test Equipment
U
Integral Nonlinearity Over
Temperature DAC A
TYPICAL APPLICATION
1.0
THREE
SUPERIMPOSED
CURVES
Dual 12-Bit 2-Quadrant Multiplying DAC
0.5
0
T
= –40°C,
A
25°C, 85°C
V
IN A
V
IN B
±10V
5V
16
±10V
9
1
2
15V
V
CC
33pF
–0.5
–1.0
LT®1112
13
D
IN
V
R
REF B FB B
OUT1 B
OUT2 B
3
4
14 CLK
–
+
DAC B
V
OUT B
2560 3072
3584 4095
0
512 1024 1536 2048
µP
±10V
DIGITAL INPUT CODE
LTC1590 • TA02
24-BIT
SHIFT
REG
11 CS/LD
Integral Nonlinearity Over
Temperature DAC B
8
6
AND
LATCH
33pF
V
R
1.0
0.5
REF A FB A
OUT1 A
OUT2 A
–
+
THREE
SUPERIMPOSED
CURVES
V
±10V
DAC A
OUT A
5
T
= –40°C,
A
12
D
OUT
25°C, 85°C
LTC1590
CLR DGND
15
AGND
7
0
10
LTC1590 • TA01
–15V
5V
–0.5
–1.0
2560 3072
0
512 1024 1536 2048
3584 4095
DIGITAL INPUT CODE
LTC1590 • TA03
1
LTC1590
W W
U W
/O
PACKAGE RDER I FOR ATIO
ABSOLUTE MAXIMUM RATINGS
VCC to AGND............................................... –0.5V to 7V
TOP VIEW
ORDER PART
V
CC to DGND .............................................. –0.5V to 7V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
NUMBER
REF B
CC
AGND to DGND............................................. VCC + 0.5V
DGND to AGND..............................................VCC + 0.5V
R
CLR
CLK
FB B
OUT1 B
OUT2 B
OUT2 A
OUT1 A
AGND
LTC1590CN
LTC1590CS
LTC1590IN
LTC1590IS
V
REF to AGND ........................................................±25V
D
IN
RFB to AGND .......................................................... ±25V
D
OUT
CS/LD
DGND
Digital Inputs to DGND ...................–0.5V to VCC + 0.5V
V
OUT1, VOUT2 to AGND ....................–0.5V to VCC + 0.5V
R
V
FB A
REF A
Maximum Junction Temperature .......................... 150°C
Operating Temperature Range
N PACKAGE
S PACKAGE
16-LEAD PDIP 16-LEAD PLASTIC SO
LTC1590C................................................ 0°C to 70°C
LTC1590I............................................ –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TJMAX = 150°C, θJA = 100°C/W (N)
JMAX = 150°C, θJA = 150°C/W (S)
T
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
Accuracy
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
●
●
●
12
Bits
LSB
LSB
INL
DNL
GE
Integral Nonlinearity
Differential Nonlinearity
Gain Error
(Note 1)
± 0.5
± 0.5
Guaranteed Monotonic, T
to T
MAX
MIN
(Note 2), T = 25°C
±1
±2
LSB
LSB
A
T
to T
●
●
MIN
MAX
Gain Temperature Coefficient
(Note 3) ∆Gain/∆Temperature
1
5
ppm/°C
I
OUT1 A, OUT1 B Leakage Current
(Note 4), T = 25°C
±5
±25
nA
nA
LEAKAGE
A
T
to T
●
MIN
MAX
Zero-Scale Error
T = 25°C
±0.03
±0.15
LSB
LSB
A
T
to T
●
●
MIN
MAX
PSRR
Power Supply Rejection
V
= 5V ±10%
±0.0001 ±0.002
%/%
CC
Reference Input
R
REF
V
V
Input Resistance
REF
●
●
8
11
15
3
kΩ
, V
Input Resistance Match
%
REFA REFB
AC Performance (Note 3)
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Current Settling Time
Channel-to-Channel Isolation
Digital Crosstalk
(Notes 5, 6)
(Note 11)
1
nV-s
dB
–89
0.3
–80
0.8
(Note 5) To 0.01% for Full-Scale Change
µs
(Note 7)
–90
dB
(Notes 5, 8)
(Note 9)
1
13
nV-s
nV/√Hz
dB
Output Noise Voltage Density
Total Harmonic Distortion
Multiplying Bandwidth
THD
(Note 10)
(Note 12)
–108
1
–92
MHz
2
LTC1590
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER
Analog Outputs
CONDITIONS
MIN
TYP
MAX
UNITS
C
Output Capacitance (Note 3)
DAC Register Loaded to All 1s
DAC Register Loaded to All 0s
●
●
60
30
90
60
pF
pF
OUT
Digital Input
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
●
●
●
●
2.4
V
V
IH
IL
0.8
±1
8
I
0.001
µA
pF
IN
C
Digital Input Capacitance
(Note 3) V = 0V
IN
IN
Digital Output
V
V
Digital Output High Voltage
Digital Output Low Voltage
I
I
= 200µA
●
●
4
V
V
OH
OL
OH
OH
= 1.6mA
0.4
Timing Characteristics
t
t
t
t
t
t
t
t
t
D
D
to CLK Setup Time
●
●
●
●
●
●
●
●
●
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
9
IN
IN
to CLK Setup Hold Time
CLK High Time
40
40
50
40
20
20
10
CLK Low Time
CS/LD High Time
LSB CLK to CS/LD
CS/LD Low to CLK High
CLK Low to CS/LD Low
CLK to D
Delay
160
OUT
Power Supply
V
Operating Supply Range
Supply Current
●
●
4.5
5
5.5
10
V
CC
I
Digital Inputs = 0V or V
µA
CC
CC
The
● denotes specifications which apply over the full operating
Note 8: Glitch on DAC A or DAC B output when the other DAC makes a
temperature range.
full-scale transition.
Note 1: ±0.5LSB = ±0.012% of full scale.
Note 2: Using internal feedback resistor.
Note 3: Guaranteed by design, not subject to test.
Note 9: 10Hz to 100kHz. Calculation from e = √4KTRB where:
K = Boltzmann constant (J/K°); R = resistance (Ω); T = resistor temperature
(°K); B = bandwidth (Hz).
n
Note10: V = 6V
at 1kHz. DAC register loaded with all 1s, using
RMS
REF
Note 4: I
with DAC register loaded with all 0s.
OUT1
LT®1124 op amp.
Note 5: OUT1 load = 100Ω in parallel with 13pF.
Note 11: V = ±10V, 10kHz sine wave, DAC register loaded with all 0s,
REF
Note 6: V = 0V. DAC register contents changed from all 0s to all 1s or
REF
using LT1358 op amp.
Note 12: –3dB bandwidth using LT1358 op amp.
all 1s to all 0s.
Note 7: DAC A output with V
= 0V and V
= 10kHz 20V , or
REF A
REF B P-P
DAC B output with V
loaded with all 1s.
= 0V, V
= 10kHz 20V . Both DAC registers
REF A P-P
REF B
3
LTC1590
TYPICAL PERFORMANCE CHARACTERISTICS
U W
Full-Scale Settling Waveform
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.5
1.0
0.5
V
= 5V
DD
0V TO 5V OUTPUT RANGE
LT1363 OP AMP
C
30pF
FB
0
0
–0.5
–1.0
–0.5
–1.0
2560 3072
2560 3072
3584 4095
0
512 1024 1536 2048
3584 4095
0
512 1024 1536 2048
TIME (500ns/DIV)
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1590 G02
1590 G03
1590 G12
Differential Nonlinearity vs
Reference Voltage
Multiplying Mode Signal-to-
(Noise + Distortion) vs Frequency
Integral Nonlinearity vs
Reference Voltage
–50
–60
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
0.05
0
V
DD
= 5V
V
DD
= 5V
V
DD
= 5V
–70
–80
USING AN
–90
LT1363 WITH
500kHz FILTER
–100
–110
USING AN LT1007
WITH 22kHz FILTER
1
10
50
2
3
4
5
6
7
8
9
10
3
5
6
7
8
10
2
4
9
FREQUENCY (kHz)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1590 G10
1590 G06
1590 G05
Integral Nonlinearity vs
Supply Voltage
Multiplying Mode Frequency
Response vs Digital Code
Differential Nonlinearity vs
Supply Voltage
0
10
20
30
40
50
60
70
80
90
100
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALL BITS
ON
V
= 2V
REF
V
= 2V
REF
ALL BITS
OFF
V
REF
= 10V
V
= 10V
REF
100
1k
10k
100k
1M
10M
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
10
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1590 G07
1590 G08
1590 G09
4
LTC1590
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs
Logic Input Voltage
Logic Threshold vs
Supply Voltage
Midscale Glitch Impulse
4
3
2
1
0
V
= 5V
DD
1.0
0.5
LT1363 OP AMP
= 30pF
C
FB
0
0
5
10
15
0
1
2
3
4
5
TIME (500ns/DIV)
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
1590 G11
1590 G04
1590 G01
U
U
U
PIN FUNCTIONS
enabled so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
VREF B, VREF A (Pins 1, 9): Reference Inputs for DAC A/B.
Typically ±10V, accepts up to ±25V.
RFB B, RFB A (Pins 2, 8): Feedback Resistors for DAC A/B.
Normally tied to the output of current to voltage converter
op amp. Typically swings to ±10V. Swings from 0V to
DOUT (Pin 12): The Serial Data Output. Data becomes valid
on the rising edge of the CLK.
–VREF
.
DIN (Pin 13): The Serial Data Input. Data on the DIN pin is
latchedintotheshiftregisterontherisingedgeoftheserial
clock. Data is loaded as one 24-bit word. The first 12 bits
are for DAC A, MSB-first and the second 12 bits are for
DAC B, MSB-first.
OUT1 B, OUT1 A (Pins 3, 6): True Current Output for DAC
A/B. Normally tied to inverting input of current to voltage
converter op amp.
OUT2 B, OUT2 A (Pins 4, 5): Complement Current Output
for DAC A/B. Normally tied to ground.
CLK(Pin14):TheSerialInterfaceClockInput.
CLR (Pin 15):The Clear Pin for the DAC. Clears both DACs
to zero scale when pulled low. This pin should be tied to
VCC for normal operation.
AGND (Pin 7): Analog Ground Pin. Tie to ground.
DGND (Pin 10): Digital Ground Pin. Tie to ground.
CS/LD (Pin 11): The Serial Interface Enable and Load
Control Input. When CS/LD is low the CLK signal is
VCC (Pin 16): The Positive Supply Input. 4.5 ≤ VCC
≤ 5.5V. Requires a bypass capacitor to ground.
5
LTC1590
W
BLOCK DIAGRA
20k
40k
20k
40k
20k
V
R
FB B
1
2
REF B
10k
40k
40k
40k
40k
40k
3
4
OUT1 B
OUT2 B
DECODER
DAC B
D11
D10
D9
D8
D0
(LSB)
(MSB)
DAC REGISTER B
LOAD
12
8
R
FB A
V
9
REF A
6
5
OUT1 A
OUT2 A
DAC A
12
CS/LD
11
CLK
IN
CLK
14
13
INPUT 24-BIT SHIFT REGISTER
D
OUT
12
OUT
D
IN
1590 • BD
16
10
7
V
CC
DGND
AGND
W U
W
TIMING DIAGRAMS
OPERATING SEQUENCE
DAC A INPUT
DAC B INPUT
MSB
LSB MSB
LSB
24
D
D11 D10 D9 D8
D7 D6 D5
D4
D3
D2
D1 D0 D11 D10 D9 D8
D7 D6 D5
D4
D3
D2
D1 D0
IN
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CS/LD
(ENABLE CLOCK)
(UPDATE DAC OUTPUT)
LTC1590 • TD
6
LTC1590
W U
W
TIMING DIAGRAMS
TIMING DIAGRAM
t
t
6
t
t
t
7
2
1
8
3
t
CLK
23
24
1
2
t
3
4
D11 A
MSB
D0 B
LSB
D
IN
D10 A
D9 A
D1 B
CS/LD
t
5
t
9
D11 A
PREVIOUS WORD
D10 A
D9 A
D0 B
PREVIOUS WORD
D11 A
CURRENT WORD
D
OUT
PREVIOUS WORD PREVIOUS WORD
1590 TD02
U
W U U
APPLICATIONS INFORMATION
Equivalent Circuit
Description
The LTC1590 is a dual 12-bit multiplying DAC that has
serial inputs and current outputs. It uses precision R/2R
resistor ladder technology to provide exceptional linearity
and stability. The device operates from a single 5V supply
and provides a ±10V reference input and voltage output
range when used with an external op amp.
Figure1showsanequivalentanalogcircuitfortheLTC1590
DACs. R is the reference input, RREF, which is nominally
11k. The DAC output is represented by the Thevinin
equivalent current source with a value of:
(Code/4096)(VREF/R)
ThecurrentsourceILKG modelsthejunctionleakageofthe
DAC output switches. ILKG is typically less than 5nA at
85°C and decreases by roughly two times for every 10°C
reduction in temperature. COUT is the output capacitance,
anditalsocomesfromtheDACoutputswitchesandvaries
from 30pF at zero scale to 60pF at full scale. RO is the
equivalent output resistance, which varies with digital
input code (see Op Amp Selection section).
Serial I/O
The LTC1590 has a 3-wire SPI/MICROWIRETM compatible
serial port that accepts 24-bit serial words. Data is loaded
MSB first with the first 12 bits controlling DAC A and the
second 12 bits controlling DAC B. Data is shifted into the
DIN input on the rising edge of CLK. The CS/LD input must
be taken low before transferring data to enable the CLK
input. After transferring data, CS/LD is pulled high to load
data from the shift register to the DAC registers which
updates both DACs.
R
R
R
FB A
FB B
V
REF A
V
REF B
OUT1 A
OUT1 B
I
LKG
V
REF
R
CODE
4096
R
O
C
R
OUT
(
)(
)
The buffered output of the 24-bit shift register is available
on the DOUT pin. Multiple DACs can be daisy-chained on
one 3-wire interface by connecting the DOUT pin to the DIN
pin of the next DAC (see the Timing Diagrams section).
OUT2 A
OUT2 B
AGND
1590 F01
Figure 1. Equivalent Circuit
MICROWIRE is a trademark of National Semiconductor Corporation.
7
LTC1590
U
W U U
APPLICATIONS INFORMATION
Table 1. Unipolar Binary Code Table
Unipolar 2-Quadrant Multiplying Mode
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
(VOUT = 0V to –VREF
)
ANALOG OUTPUT
V
The LTC1590 can be used with a dual op amp to provide
a dual 2-quadrant multiplying DAC as shown in Figure 2.
The unipolar DAC transfer function is shown in Table 1.
The33pFfeedbackcapacitorisrecommendedtocompen-
sate for the pole caused by the internal feedback resistor
andtheOUT1outputcapacitance. Forhighspeedopamps
this feedback capacitor is required for stability, and a
smaller value, 8pF to 15pF, may be desired to get the
fastest transient response and shortest settling time. A
larger feedback capacitor can be used to reduce wideband
noise, glitch impulse and distortion for lower frequency
signals. A pole is introduced in the DAC transfer function
at approximately (CFB)(RFB). For example, a 100pF feed-
back capacitor will typically give a pole at:
OUT
MSB
LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
–V
–V
–V
0V
(4095/4096)
REF
(2048/4096) = –V /2
(1/4096)
REF
REF
REF
Bipolar 4-Quadrant Multiplying Mode
(VOUT = –VREF to +VREF
)
The circuit of Figure 3 can be used to provide a dual
4-quadrant multiplying DAC. This circuit starts with the
unipolarapplicationcircuitandaddsthreeresistorsandan
op amp. These extra devices provide a gain of–2 from the
unipolar output to the bipolar output, plus an offset of
(–1)(VREF)toproducethetransferfunctionshowninTable
2. A pack of matched 20k resistors, with two resistors in
parallel forming the 10k resistor, is recommended.
1
145kHz =
2π 100pF 11kΩ
(
)(
)
5V
V
Table 2. Bipolar Offset Binary Code Table
DIGITAL INPUT
REF
–10V TO 10V
0.1µF
BINARY NUMBER
IN DAC REGISTER
ANALOG OUTPUT
33pF
15V
V
OUT
V
V
R
CC
REF
FB
OUT1
–
+
MSB
LSB
1/2
LT1112
LTC1590
DAC A OR DAC B
V
OUT
0V TO –V
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000
+V
+V
0V
–V
–V
(2047/2048)
(1/2048)
REF
REF
REF
OUT2
DGND AGND
1590 F02
–15V
(1/2048)
(2048/2048) = – V
REF
REF
REF
Figure 2. Unipolar Operation (2-Quadrant Multiplication)
R2
20k
R3
20k
V
REF
–10V TO 10V
5V
0.1µF
15V
33pF
V
V
R
FB
OUT1
CC
REF
–
15V
R1
10k
1/2
LT1112
–
+
LTC1590
DAC A OR DAC B
+
1/2
LT1112
V
OUT
OUT2
–V
REF
TO V
REF
DGND AGND
–15V
–15V
1590 F03
Figure 3. Bipolar Operation (4-Quadrant Multiplication)
8
LTC1590
U
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APPLICATIONS INFORMATION
Op Amp Selection
amp bias current causes a 1.1mV DAC offset, or 0.45LSB
for a 10V full-scale range. It is important to note that
connecting the op amp noninverting input to ground
through a resistor will not cancel bias current errors and
should never be done! Similarly an offset caused by op
amp bias current should not be adjusted by using the op
amp null pins since this increases offset between DAC
OUT1 and OUT2 pins, causing INL, DNL and gain errors.
If op amp offset error adjustment is required, the op amp
input offset voltage (the voltage difference between OUT1
and OUT2) should be nulled.
To maintain the excellent accuracy and stability of the
LTC1590 thought should be given to op amp selection.
Fortunately,thesensitivityofINLandDNLtoopampoffset
has been significantly reduced compared to competing
parts of this type. The op amp’s VOS causes DAC output
offset. In addition, because the DAC’s equivalent output
resistance RO changes as a function of code, there is a
code-dependentDACoutputerrorproportionaltoVOS.For
fixed reference applicationsthiscausesgain, INLand DNL
error. For multiplying applications, a code-dependent, DC
output voltage error is seen. At zero scale the DAC output
error is equal to the op amp offset, and at full scale the
output error is equal to twice the op amp offset. For
example, a 1mV op amp offset will cause a 0.41LSB zero-
scale error and a 0.82LSB full-scale error with a 10V full-
scale range. The offset caused INL error is approximately
0.4 times the op amp VOS and DNL error is 0.07 times op
amp VOS. For the same example of 1mV op amp VOS and
10V full-scale range, the INL degradation will be 0.17LSB
and DNL degradation will be 0.03LSB.
Grounding
As with any high precision data converter, clean ground-
ing is important. A low impedance analog ground plane
and star grounding should be used. OUT2 carries the
complementary DAC output current and should be tied to
the star ground with as low a resistance as possible. Other
ground points that must be tied to the star ground point
include the VREF input ground, the op amp noninverting
input(s) and the VOUT ground reference point.
Op amp bias current causes only an offset error equal to
(IBIAS)(RFB) ≈ (IBIAS)(11kΩ). For example, a 100nA op
U
TYPICAL APPLICATIONS
Dual Programmable Attenuator
5V
V
IN B
±10V
15V
0.1µF
16
1
2
33pF
0.01µF
V
R
REF B
FB B
2
3
OUT1 B
OUT2 B
3
4
8
D
13
14
11
12
15
–
+
IN
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
1/2
1
CLK
DAC B
V
OUT B
LT1358
CS/LD
24-BIT
SHIFT
REG
D
OUT
CLR
D
4096
V
= –V
IN
LTC1590
DAC A
CLEAR
OUT
(
)
AND
LATCH
5
6
OUT2 A
OUT1 A
5
6
+
–
1/2
7
V
OUT A
LT1358
7
4
AGND
DGND
V
V
R
REF A
FB A
10
33pF
0.01µF
–15V
9
8
1590 TA07
IN A
±10V
9
LTC1590
U
TYPICAL APPLICATIONS
Very Low Power Single Supply Dual VOUT DAC
500k
50k
–
1/4
LT1179
V
V
OUT A
+
500k
50k
–
+
1/4
LT1179
V
OUT B
0V TO 2.2V
3.3V
+
16
1
9
V
CC
2
3
R
FB B
V
REF B
OUT1 B
OUT2 B
+
V
3.3V
DAC B
0.2V
4
120k
8
6
LTC1590
–
+
LT1004-1.2
V
R
OUT1 A
OUT2 A
REF A
1/4
LT1179
FB A
DAC A
210k
50k
5
0.1µF
I
= 100µA (TYP)
SUPPLY TOTAL
(WORSE-CASE CODE)
AGND
7
DGND
10
1590 TA06
Dual Programmable Gain Amplifier
V
IN B
±10V
5V
16
15V
0.1µF
1
2
33pF
0.01µF
V
REF B
R
FB B
2
3
OUT1 B
OUT2 B
3
4
8
D
13
14
11
12
15
–
IN
DATA IN
1/2
1
CLK
DAC B
V
OUT B
LT1358
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
CS/LD
+
24-BIT
SHIFT
REG
D
OUT
4096
D
CLR
V
= –V
IN
OUT
LTC1590
DAC A
(
)
CLEAR
AND
LATCH
5
6
OUT2 A
OUT1 A
5
6
+
–
1/2
7
V
OUT A
LT1358
7
4
AGND
DGND
V
R
REF A
9
FB A
10
33pF
0.01µF
–15V
8
1590 TA08
V
IN A
±10V
10
LTC1590
U
TYPICAL APPLICATIONS
Dual Programmable Gain Amplifier with Input Attenuation
V
IN B
±10V
1k
15k
5V
1k
15k
15V
8
0.1µF
16
1
2
33pF
0.01µF
V
R
REF B
FB B
2
OUT1 B
OUT2 B
3
4
D
13
14
11
12
15
–
+
IN
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
1/2
LT1358
1
CLK
DAC B
V
OUT B
3
CS/LD
24-BIT
SHIFT
REG
D
OUT
4096
16D
CLR
V
OUT
= –V
IN
(
)
LTC1590
DAC A
CLEAR
AND
LATCH
5
6
OUT2 A
OUT1 A
5
6
+
–
1/2
LT1358
7
V
OUT A
7
4
AGND
DGND
V
R
REF A
FB A
10
33pF
0.01µF
–15V
9
8
15k
1k
1k
1590 TA09
15k
V
IN A
±10V
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
14
12
10
9
8
15
13
11
16
0.255 ± 0.015*
(6.477 ± 0.381)
2
1
3
4
6
5
7
0.300 – 0.325
0.130 ± 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 ± 0.127)
(1.143 – 1.651)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
0.325
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
–0.015
0.125
(3.175)
MIN
0.018 ± 0.003
+0.635
8.255
(0.457 ± 0.076)
(
)
–0.381
N16 0695
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1590
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
16
15
14
13
12
11
10
9
× 45°
0.053 – 0.069
(1.346 – 1.752)
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
5
6
7
8
4
S16 0695
U
TYPICAL APPLICATION
Dual Programmable Attenuator with Gain
V
IN B
±10V
1k
15k
5V
15k
15V
8
0.1µF
16
1
2
33pF
1k
0.01µF
V
R
FB B
REF B
2
3
OUT1 B
OUT2 B
3
4
D
13
14
11
12
15
–
+
IN
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
1/2
LT1358
1
CLK
DAC B
V
OUT B
CS/LD
24-BIT
SHIFT
REG
D
OUT
16D
4096
CLR
V
OUT
= –V
IN
(
)
LTC1590
DAC A
CLEAR
AND
LATCH
5
6
OUT2 A
OUT1 A
5
6
+
–
1/2
LT1358
7
V
OUT A
7
4
AGND
DGND
V
R
REF A
9
FB A
10
0.01µF
1k
15k
33pF
–15V
8
1590 TA10
1k
15k
V
IN A
±10V
RELATED PARTS
PART NUMBER
LTC1595
DESCRIPTION
COMMENTS
True 16-Bit Upgrade for DAC8043
True 16-Bit Upgrade for DAC8143 and AD7543
12-Bit Wide Parallel Input
16-Bit Multiplying I
16-Bit Multiplying I
DAC in SO-8
DAC
12-Bit DAC
OUT
OUT
LTC1596
OUT
LTC7541A
Parallel I/O Multiplying I
LTC7543/LTC8143
LTC7545A
LTC8043
Serial I/O Multiplying I
Parallel I/O Multiplying I
Serial I/O Multiplying I
12-Bit DACs
Clear Pin and Serial Data Output (LTC8143)
12-Bit Wide Latched Parallel Input
8-Pin SO and PDIP
OUT
12-Bit DAC
OUT
12-Bit DAC
OUT
1590f LT/TP 1197 4K • PRINTED IN USA
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
12
●
●
LINEAR TECHNOLOGY CORPORATION 1997
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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