LTC1659CMS8-PBF [Linear]
12-Bit Rail-to-Rail Micropower DAC in MSOP Package; 12位轨至轨微DAC ，采用MSOP封装
| 型号： | LTC1659CMS8-PBF |
| 厂家： | 
Linear |
| 描述： | 12-Bit Rail-to-Rail Micropower DAC in MSOP Package |
| 文件： | 总12页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1659
12-Bit Rail-to-Rail
Micropower DAC in
MSOP Package
FEATURES
DESCRIPTION
TheLTC®1659isasinglesupply,rail-to-railvoltageoutput,
12-bitdigital-to-analogconverter(DAC)inanMSOPpack-
age. It includes a rail-to-rail output buffer amplifier and an
easy-to-use 3-wire cascadable serial interface.
■
Buffered True Rail-to-Rail Voltage Output
■
Maximum DNL Error: 0.5LSB
■
12-ꢀit Resolution
■
Supply Operation: 3V to 5V
■
Output Swings from 0V to V
REF
TheLTC1659outputswingsfrom0VtoREF. TheREFinput
■
■
V
REF
Can Tie to V
CC
can be tied to V which can range from 2.7V to 5.5V.
CC
Schmitt Trigger On Clock Input Allows Direct
This allows a rail-to-rail output swing from 0V to V . The
CC
Optocoupler Interface
LTC1659 draws only 250μA from a 5V supply.
■
■
■
■
Power-On Reset Clears DAC to 0V
3-Wire Cascadable Serial Interface
Low Cost
Itsguaranteed 0.5LSꢀmaꢁimumDꢂLmakestheLTC1659
eꢁcel in calibration, control and trim/adjust applications.
The low power supply current and the small MSOP
package make the LTC1659 ideal for battery-powered
applications.
8-Lead SO and MSOP Packages
APPLICATIONS
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Digital Calibration
■
Industrial Process Control
■
Automatic Test Equipment
Cellular Telephones
■
TYPICAL APPLICATION
Functional Block Diagram: 12-Bit Rail-to-Rail DAC
Differential Nonlinearity
vs Input Code
2.7V TO 5.5V
8
6
0.5
V
REF
CC
2
1
D
IN
+
–
V
OUT
RAIL-TO-RAIL
VOLTAGE
OUTPUT
7
CLK
12-BIT
SHIFT
REG
μP
12-BIT
DAC
3
CS/LD
0
AND
DAC
LATCH
4
D
OUT
POWER-ON
RESET
TO
OTHER
DACS
–0.5
GND
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1659 TA01
5
1659 TA02
1659fa
1
LTC1659
ABSOLUTE MAXIMUM RATINGS (Note 1)
V
to GꢂD ............................................... –0.5V to 7.5V
Operating Temperature Range
CC
Logic Inputs to GꢂD ................................. –0.5V to 7.5V
.................................................–0.5V to V + 0.5V
LTC1659CS8............................................ 0°C to 70°C
LTC1659IS8......................................... –40°C to 85°C
LTC1659CMS8......................................... 0°C to 70°C
LTC1659IMS8...................................... –40°C to 85°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
V
OUT
CC
Maꢁimum Junction Temperature .......................... 125°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
CLK
1
2
3
4
V
V
8
7
6
5
CC
CLK
1
2
3
4
8 V
7 V
6 REF
CC
OUT
D
IN
OUT
D
IN
CS/LD
CS/LD
REF
5 GND
D
OUT
D
GND
OUT
MS8 PACKAGE
8-LEAD PLASTIC MSOP
= 150°C, θ = 140°C/W
S8 PACKAGE
8-LEAD PLASTIC SO
= 125°C, θ = 160°C/W
T
JMAX
JA
T
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC1659CS8#PꢀF
LTC1659IS8#PꢀF
LTC1659CMS8#PꢀF
LTC1659IMS8#PꢀF
TAPE AND REEL
PART MARKING*
1659
PACKAGE DESCRIPTION
8-Lead Plastic SO
TEMPERATURE RANGE
0°C to 70°C
LTC1659CS8#TRPꢀF
LTC1659IS8#TRPꢀF
LTC1659CMS8#TRPꢀF
LTC1659IMS8#TRPꢀF
1659I
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
LTCK
8-Lead Plastic MSOP
8-Lead Plastic MSOP
LTCK
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX
unless otherwise noted.
SYMBOL
DAC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
Resolution
12
12
ꢀits
ꢀits
LSꢀ
Monotonicity
DꢂL
IꢂL
Differential ꢂonlinearity
Integral ꢂonlinearity
V
V
≤ V – 0.1V (ꢂote 2)
0.5
REF
CC
≤ V – 0.1V (ꢂote 2)
5.0
5.5
LSꢀ
LSꢀ
REF
CC
●
1659fa
2
LTC1659
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Offset Error
Measured at Code 20
12
18
mV
mV
OS
●
●
V
V
TC
Offset Error Temperature Coefficient
Full-Scale Voltage
15
μV/°C
OS
REF = 4.096V
4.070
4.060
4.095
4.095
4.120
4.130
V
V
FS
V
TC
Full-Scale Voltage Temperature Coefficient
10
ppm/°C
FS
Power Supply
●
●
V
Positive Supply Voltage
Supply Current
For Specified Performance
(ꢂote 5)
2.7
5.5
V
CC
I
240
450
μA
CC
Op Amp DC Performance
Short-Circuit Current Low
●
●
●
V
V
Shorted to GꢂD
70
65
40
0.1
120
120
150
1.5
mA
mA
OUT
Short-Circuit Current High
Output Impedance to GꢂD
Output Line Regulation
Shorted to V
CC
OUT
Ω
Input Code = 0
Input Code = 4095, V = 4.5V to 5.5V
LSꢀ/V
CC
AC Performance
●
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
(ꢂote 3)
0.5
1.0
14
V/μs
μs
(ꢂotes 3, 4) to 0.5LSꢀ
0.3
nV • s
Reference Input
●
●
R
REF Input Resistance
REF Input Range
17
0
28
40
kΩ
Iꢂ
REF
(ꢂotes 6, 7)
V
CC
V
Digital I/O
●
●
●
●
●
●
●
●
●
●
V
V
V
V
V
V
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
V
V
V
V
V
V
V
V
V
= 5V
2.4
V
V
IH
IL
CC
CC
CC
CC
CC
CC
CC
CC
Iꢂ
= 5V
0.8
0.4
0.6
= 5V, I
= 5V, I
= 3V
= –1mA, D
Only
V
– 1.0
CC
V
OH
OL
IH
OUT
OUT
OUT
= 1mA, D
Only
V
OUT
OUT
2.0
V
= 3V
V
IL
= 3V, I
= 3V, I
= –1mA, D
Only
Only
V
– 0.7
CC
V
OH
OL
LEAK
OUT
OUT
= 1mA, D
0.4
10
10
V
OUT
I
= GꢂD to V
μA
pF
CC
C
Iꢂ
Digital Input Capacitance
(ꢂote 7)
1659fa
3
LTC1659
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching (V = 4.5V to 5.5V
CC
●
●
●
●
●
●
●
●
●
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
D
D
Valid to CLK Setup
Valid to CLK Hold
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Iꢂ
Iꢂ
CLK High Time
(ꢂote 7)
(ꢂote 7)
(ꢂote 7)
(ꢂote 7)
(ꢂote 7)
40
40
50
40
20
5
CLK Low Time
CS/LD Pulse Width
LSꢀ CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
C
LOAD
= 15pF
150
CLK Low to CS/LD Low
(ꢂote 7)
20
Switching (V = 2.7V to 5.5V)
CC
●
●
●
●
●
●
●
●
●
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
D
D
Valid to CLK Setup
Valid to CLK Hold
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Iꢂ
Iꢂ
CLK High Time
(ꢂote 7)
(ꢂote 7)
(ꢂote 7)
(ꢂote 7)
(ꢂote 7)
60
60
80
60
30
10
30
CLK Low Time
CS/LD Pulse Width
LSꢀ CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
C
LOAD
= 15pF
220
CLK Low to CS/LD Low
(ꢂote 7)
Note 1: Stresses beyond those listed under Absolute Maꢁimum Ratings
may cause permanent damage to the device. Eꢁposure to any Absolute
Maꢁimum Rating condition for eꢁtended periods may affect device
reliability and lifetime.
Note 2: ꢂonlinearity is defined from code 20 to code 4095 (full scale). See
Applications Information.
Note 4: DAC switched between all 1s and the code corresponding to V
for the part.
OS
Note 5: Digital inputs at 0V or V
.
CC
Note 6: V
can only swing from (GꢂD + |V |) to (V – |V |) when
OUT
OS CC OS
output is unloaded.
Note 7: Guaranteed by design, not subject to test.
Note 3: Load is 5kΩ in parallel with 100pF.
1659fa
4
LTC1659
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Output Voltage vs
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Output Sink Current
0.5
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4
CODE = ALL ZEROS
V
= 5V
CC
3
2
1
0
0
125°C
–1
–2
–3
–4
–5
25°C
–55°C
–0.5
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
0
5
10
15
0
512 1824 1536 2048 2560 3072 3584 4095
CODE
OUTPUT SINK CURRENT (mA)
1659 • G02
1659 • G03
1659 • G01
Supply Headroom for Full Output
Swing vs Load Current
Supply Current vs
Logic Input Voltage
Supply Current vs Temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
300
290
280
270
260
250
240
230
220
V
= 5V
ΔV
< 1 LSB
CODE = ALL 1s
= 4.095V
CC
OUT
125°C
2
1.6
1.2
0.8
0.4
0
V
OUT
25°C
V
V
V
= 5.5V
= 5.0V
= 4.5V
CC
CC
CC
–55°C
0
5
10
15
0
1
2
3
4
5
–55 –35 –15
5
25 45 65 85 105 125
LOAD CURRENT (mA)
LOGIC INPUT VOLTAGE (V)
TEMPERATURE (C)
1659 • G04
1659 • G05
1659 • G06
1659fa
5
LTC1659
PIN FUNCTIONS
CLK(Pin1):SerialInterfaceClock.InternalSchmitttrigger
on this input allows direct optocoupler interface.
D
(Pin 4): Output of the Shift Register which ꢀecomes
OUT
Valid on the Rising Edge of the Serial Clock.
D (Pin 2): Serial Interface Data. Data on the D pin is
GND (Pin 5): Ground.
IN
Iꢂ
latched into the shift register on the rising edge of the
REF (Pin 6): Reference Input. This pin can be tied to V .
CC
serial clock.
The output will swing from 0V to REF. The typical input
CS/LD (Pin 3): Serial Interface Enable and Load Control.
When CS/LD is low the CLK signal is enabled, so the data
canbeclockedin.WhenCS/LDispulledhigh,dataisloaded
from the shift register into the DAC register, updating the
DAC output and the CLK is disabled internally.
resistance is 28k.
V
V
(Pin 7): ꢀuffered DAC Output.
OUT
(Pin 8): Positive Supply Input. 2.7V ≤ V ≤ 5.5V.
Requires a bypass capacitor to ground.
CC
CC
BLOCK DIAGRAM
CLK
V
V
1
8
CC
LD
D
IN
2
12-BIT
DAC
12-BIT
SHIFT
REGISTER
+
DAC
REGISTER
7
OUT
–
3
4
CS/LD
POWER-ON
RESET
REF
6
5
D
GND
OUT
1659 BD
1659fa
6
LTC1659
TIMING DIAGRAM
t
t
t
t
2
1
6
7
CLK
t
t
3
4
t
9
B11
MSB
B0
PREVIOUS WORD
B0
LSB
B10
B1
D
IN
CS/LD
t
t
5
8
B11
B11
PREVIOUS WORD
D
B1
B10
B0
OUT
CURRENT WORD
1659 TD
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSꢀ change for any
twoadjacentcodes. TheDꢂLerrorbetweenanytwocodes
is calculated as follows:
greater than zero. The IꢂL error at a given input code is
calculated as follows:
IꢂL = [V
– V – (V – V )(code/4095)]/LSꢀ
OS FS OS
OUT
where V
is the output voltage of the DAC measured at
OUT
DꢂL = (ΔV
– LSꢀ)/LSꢀ
OUT
the given input code.
where ΔV
is the measured voltage difference between
OUT
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
two adjacent codes.
Digital Feedthrough: The glitch that appears at the ana-
log output caused by AC coupling from the digital inputs
when they change state. The area of the glitch is specified
in (nV)(sec).
LSꢀ = V /4096
REF
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Full-ScaleError(FSE):Thedeviationoftheactualfull-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
Voltage Offset Error (V ): ꢂominally, the voltage at the
OS
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint IꢂL). ꢀecause the output cannot go
below zero, the linearity is measured between full scale
and the lowest code which guarantees the output will be
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
1659fa
7
LTC1659
OPERATION
Serial Interface
Voltage Output
The data on the D input is loaded into the shift register
The LTC1659’s rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40Ω when driving a load
to the rails. The output can drive 1000pF without going
into oscillation.
Iꢂ
on the rising edge of the clock. The MSꢀ is loaded first.
The DAC register loads the data from the shift register
when CS/LD is pulled high. The CLK is disabled internally
when CS/LD is high. ꢂote: CLK must be low before CS/LD
is pulled low to avoid an eꢁtra internal clock pulse.
The buffered output of the 12-bit shift register is available
on the D
pin which swings from GꢂD to V . Multiple
OUT
CC
LTC1659s may be daisy-chained together by connecting
The output swings from 0V to the voltage at the REF pin,
the D pin to the D pin of the neꢁt chip, while the CLK
i.e., there is a gain of 1 from the REF to V . Please
OUT
Iꢂ
OUT
and CS/LD signals remain common to all chips in the
daisy chain. The serial data is clocked to all of the chips,
then the CS/LD signal is pulled high to update all of them
simultaneously.
note if REF is tied to V the output can only swing to
CC
(V – V ). See Applications Information.
CC
OS
1659fa
8
LTC1659
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
error (FSE) is positive, the output for the highest codes
limits at V as shown is Figure 1c. ꢂo full-scale limiting
CC
In any rail-to-rail DAC, the output swing is limited to volt-
ages within the supply range.
can occur if V is less than V – FSE.
REF
CC
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V . If V
= V and the DAC full-scale
CC
REF
CC
POSITIVE
FSE
V
= V
CC
REF
OUTPUT
VOLTAGE
INPUT CODE
(1c)
V
REF
= V
CC
OUTPUT
VOLTAGE
0
2048
4095
INPUT CODE
(1a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(1b)
1659 F01
Figure 1. Effects of Rail-to-Rail Operation on a DAC Transfer Curve
(1a) Overall Transfer Function
(1b) Effect of Negative Offset for Codes Near Zero Scale
(1c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
1659fa
9
LTC1659
TYPICAL APPLICATION
12-Bit, 3V to 5V Single Supply, Rail-to-Rail Voltage Output DAC
2.7V TO 5.5V
0.1μF
V
REF
D
CC
IN
CLK
OUTPUT
0V TO REF
μP
V
LTC1659
GND
OUT
CS/LD
D
OUT
TO NEXT DAC FOR
DAISY-CHAINING
1659 TA03
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 .005
.160 .005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 .005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
1659fa
10
LTC1659
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
0.889 0.127
(.035 .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 0.102
(.118 .004)
(NOTE 3)
0.52
(.0205)
REF
0.65
(.0256)
BSC
0.42 0.038
(.0165 .0015)
TYP
8
7 6
5
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 0.152
(.021 .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
0.1016 0.0508
(.009 – .015)
(.004 .002)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0307 REV F
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1659fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on eꢁisting patent rights.
11
LTC1659
TYPICAL APPLICATION
Digitally Programmable Current Source
5V
V
+ 6V TO 100V
S
FOR R ≤ 50Ω
L
0.1μF
D
• 5
IN
R
L
I
=
≈ 0mA TO 10mA
V
REF
OUT
CC
CLK
4096 • R
A
μP
LTC1659
GND
+
D
V
OUT
IN
Q1
2N3440
LT®1077
CS/LD
–
R
A
510Ω
5%
1659 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-ꢀit V
DAC, Full Scale: 2.048V, V : 4.75V to 15.75V,
5V to 15V Single Supply, Complete V
DAC in
OUT
OUT
CC
Reference Can ꢀe Overdriven Up to 12V, i.e., FS
= 12V
SO-8 Package
MAX
LTC1446/LTC1446L Dual 12-ꢀit V
DACs in SO-8 Package
LTC1446: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
OUT
OUT
CC
OUT
LTC1446L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1448
Dual 12-ꢀit V
DAC, V : 2.7V to 5.5V
Output Swings from GꢂD to REF. REF Input Can ꢀe Tied
to V
CC
CC
LTC1450/LTC1450L Single 12-ꢀit V
DACs with Parallel Interface
LTC1450: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
OUT
CC
OUT
LTC1450L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1451
LTC1452
LTC1453
Single Rail-to-Rail 12-ꢀit DAC, Full Scale: 4.095V, V : 4.5V to 5.5V,
5V, Low Power Complete V
DAC in SO-8 Package
CC
OUT
Internal 2.048V Reference ꢀrought Out to Pin
Single Rail-to-Rail 12-ꢀit V
Multiplying DAC, V : 2.7V to 5.5V
Low Power, Multiplying V
DAC with Rail-to-Rail
OUT
OUT
CC
ꢀuffer Amplifier in SO-8 Package
Single Rail-to-Rail 12-ꢀit V
DAC, Full Scale: 2.5V, V : 2.7V to 5.5V
3V, Low Power, Complete V DAC in SO-8 Package
OUT
CC
OUT
LTC1454/LTC1454L Dual 12-ꢀit V
DACs in SO-16 Package with Added Functionality
LTC1454: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
OUT
CC
OUT
LTC1454L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1456
Single Rail-to-Rail Output 12-ꢀit DAC with Clear Pin, Full Scale: 4.095V, Low Power, Complete V
CC
DAC in SO-8 Package with
OUT
V
: 4.5V to 5.5V
Clear Pin
LTC1458/LTC1458L Quad 12 ꢀit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
OUT
CC
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
1659fa
LT 0507 REV A• PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 1997
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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