LTC1703CG#PBF [Linear]
LTC1703 - Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID; Package: SSOP; Pins: 28; Temperature Range: 0°C to 70°C;
| 型号： | LTC1703CG#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1703 - Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID; Package: SSOP; Pins: 28; Temperature Range: 0°C to 70°C 信息通信管理 开关 光电二极管 |
| 文件： | 总36页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1703
Dual 550kHz Synchronous
2-Phase Switching Regulator
Controller with 5-Bit VID
U
FEATURES
DESCRIPTIO
The LTC®1703 is a dual switching regulator controller opti-
mized for high efficiency with low input voltages. It includes
two complete, on-chip, independent switching regulator
controllers. Each is designed to drive a pair of external
N-channel MOSFET devices in a voltage mode feedback,
synchronous buck configuration. The LTC1703 includes
digital output voltage adjustment on side 1 that conforms to
the Intel Mobile VID specification. It uses a constant-
frequency, true PWM design switching at 550kHz, minimiz-
ing external component size and cost and optimizing load
transient performance. The synchronous buck architecture
automatically shifts to discontinuous and then to Burst
Mode® operation as the output load decreases, ensuring
maximum efficiency over a wide range of load currents.
■
Side 1 Output Is Compliant with IntelMobile
VID Specifications (Includes 5-Bit DAC)
■
0.9V to 2.0V Output Voltage with 25mV/50mV Steps
■
Two Sides Run Out-of-Phase to Minimize CIN
Precision Internal 0.8V ±1% Reference
■
■
■
■
■
Two Independent PWM Controllers in One Package
All N-Channel External MOSFET Architecture
No External Current Sense Resistor
550kHz Switching Frequency Minimizes External
Component Size
■
■
■
■
Very Fast Transient Response
Up to 25A Output Current per Channel
Low Shutdown Current: < 100µA
Small 28-Pin SSOP Package
U
The LTC1703 features an onboard reference trimmed to 1%
and delivers better than 1.5% regulation at the converter
outputs. An optional latching FAULT mode protects the load
if the output rises 15% above the intended voltage. Each
channel can be enabled independently; with both channels
disabled, the LTC1703 shuts down and supply current drops
below 100µA.
APPLICATIO S
Mobile Pentium® III Processor Systems
■
■
Microprocessor Core and I/O Supplies
■
Multiple Logic Supply Generator
High Efficiency Power Conversion
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
V
IN
4.5V TO 5.5V
Dual Output Mobile Pentium III Processor Supply
+
C
IN
DCP2
MBR0520LT1
DCP1
MBR0520LT1
QT2
1µF
150µF
10V
× 2
L1
1µH
L2
2.2µH
QT1
V
OUT1
0.9V
V
LTC1703
OUT2
1.5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TO 2V
15A
PV
BOOST1
BG1
TG1
SW1
I
MAX2
BOOST2
BG2
TG2
SW2
CC
3A
QB1B
CCP1
QB1A
C32
2200pF
CCP2
1µF
C
OUT1
+
1µF
+
C
OUT2
180µF
QB2
180µF
R12
10.2k
0.1%
4V
× 6
R32
1k
4V
R
10Ω
IMAX2
20k
R
,18.7k
IMAX1
GND
I
PGND
FAULT
MAX1
FCB
RB2
11.5k
0.1%
GND
RUN/SS1 RUN/SS2
C
GND
SS1
0.22µF
COMP1
SGND
FB1
SENSE
VID0
COMP2
FB2
R21
100k
C21
15pF
R22, 100k
C22
C11
220pF
C12
220pF
V
CC
15pF
VID4
VID3
VID2
C31
220pF
1703 TA01
R31, 10k
C
SS2
0.22µF
VID1
1µF
VID0
VID1
VID2
VID3
VID4
L1: MURATA LQT12535C1R5N12
L2: COILTRONICS UP2B-2R2
QT1, QB1A, QB1B: INTERNATIONAL RECTIFIER IRF7811
QT2, QB2: 1/2 FAIRCHILD NDS8926
1703fa
1
LTC1703
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Supply Voltage
1
2
28
I
MAX2
PV
CC
VCC........................................................................................... 7V
BOOSTn............................................................... 15V
BOOSTn – SWn .................................................... 7V
Input Voltage
27 BOOST2
26 BG2
BOOST1
BG1
3
LTC1703CG
LTC1703IG
4
25 TG2
TG1
5
24 SW2
SW1
6
23 PGND
22 FAULT
21 RUN/SS2
20 COMP2
19 FB2
I
MAX1
FCB
7
SWn .......................................................... –1V to 8V
VIDn ....................................................... –0.3V to 7V
All Other Inputs ......................... –0.3V to VCC + 0.3V
Peak Output Current < 10µs
TGn, BGn ............................................................... 5A
Operating Temperature Range
8
RUN/SS1
COMP1
SGND
FB1
9
10
11
12
13
14
18
V
CC
17 VID4
16 VID3
15 VID2
SENSE
VID0
VID1
LTC1703C .............................................. 0°C to 85°C
LTC1703I........................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 55°C/ W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
CC
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
V
= 5V unless otherwise specified. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
V
V
Supply Voltage
CC
●
●
●
3
3
7
7
7
V
V
V
CC
PV
BV
PV Supply Voltage
(Note 2)
CC
CC
CC
BOOST Pin Voltage
V
– V (Note 2)
2.7
BOOST
SW
I
V
Supply Current
CC
Test Circuit 1
RUN/SS1 = RUN/SS2 = 0V (Note 5)
●
●
2.2
30
8
100
mA
µA
CC
IPV
PV Supply Current
CC
Test Circuit 1 (Note 4)
RUN/SS1 = RUN/SS2 = 0V (Note 5)
●
●
2.2
6
6
100
mA
µA
CC
I
BOOST Pin Current
Feedback Voltage
Test Circuit 1 (Note 4)
●
●
1.3
0.1
3
mA
BOOST
RUN/SS1 = RUN/SS2 = 0V
10
µA
V
Test Circuit 1, LTC1703C
Test Circuit 1, LTC1703I
●
●
0.792
0.790
0.800
0.800
0.808
0.810
V
V
FB
∆V
Feedback Voltage Line Regulation
Feedback Current
V
= 3V to 7V
CC
●
●
●
●
±0.005
±0.001
0.1
± 0.05
±1
%/V
µA
FB
I
FB2 Only (Note 8)
(Note 6)
FB
∆V
OUT
Output Voltage Load Regulation
FCB Threshold
± 0.2
0.85
%
V
0.75
0.8
V
FCB
∆V
FCB Feedback Hysteresis
FCB Pin Current
20
mV
µA
FCB
I
●
●
±0.001
0.55
±1
FCB
V
RUN/SS Pin RUN Threshold
Soft Start Source Current
0.45
–1.5
0.65
–5.5
V
RUN
I
RUN/SSn = 0V
–3.5
µA
SS
1703fa
2
LTC1703
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T = 25°C. V = 5V unless otherwise specified. (Note 3)
CC
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Characteristics
V
Oscillator Amplitude
Oscillator Frequency
Controller 2 Oscillator Phase
Minimum Duty Cycle
Minimum Duty Cycle
Maximum Duty Cycle
Driver Nonoverlap
1
V
P-P
OSC
f
Test Circuit 1
●
475
550
180
10
750
kHz
DEG
%
OSC
Φ
Relative to Controller 1
OSC2
DC
V
V
< V
> V
●
●
●
●
●
7
0
MIN1
FB
FB
MAX
MAX
DC
DC
%
MIN2
87
90
40
12
93
100
80
%
MAX
t
Test Circuit 1 (Note 9)
Test Circuit 1 (Note 9)
ns
NOV
t , t
r
Driver Rise/Fall Time
ns
f
Feedback Amplifier
A
FB DC Gain
●
74
±3
85
25
dB
MHz
mA
VFB
GBW
FB Gain Bandwidth
I
FB Sink/Source Current
MIN Comparator Threshold
MAX Comparator Threshold
COMP Output
●
●
●
± 10
760
840
ERR
N
V
V
785
mV
MIN
815
mV
MAX
Current Limit Loop
A
I
I
Gain
40
dB
VILIM
IMAX
LIM
I
Source Current
I
I
= 0V, LTC1703C
= 0V, LTC1703I
●
●
–7
–7
–10
–10
–13
–14
µA
µA
MAX
MAX
MAX
Status Outputs
V
V
FAULT Trip Point
V
Relative to Regulated V
●
●
+10
+15
0.03
–10
25
+20
0.1
%
V
FAULT
OLF
FB
OUT
FAULT Output Low Voltage
FAULT Output Current
FAULT Delay Time
I
= 1mA
= 0V
FAULT
I
t
V
V
µA
µs
FAULT
FAULT
FAULT
> V
to FAULT
(Note 9)
FB
FAULT
VID Inputs
R11
Resistance Between SENSE and FB1
10
40
kΩ
%
V
Error % Output Voltage Accuracy (Side 1)
Programmed from 0.9V to 2V
●
–1.5
1.6
1.5
OUT
R
VID Input Pull-Up Resistance
VID Input Voltage Threshold
V
= 0.6V (Note 7)
DIODE
kΩ
PULLUP
VID
V
V
(2.7V ≤ V ≤ 5.5V)
0.4
V
V
T
IL
IH
CC
(2.7V ≤ V ≤ 5.5V)
CC
I
VID Input Leakage Current
VID Pull-Up Voltage
V
< VID < 7V (Note 7)
0.01
±1
µA
VID-LEAK
CC
V
V
V
= 3.3V
= 5V
2.8
4.5
V
V
PULLUP
CC
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Supply current in shutdown is dominated by external MOSFET
leakage and may be significantly higher than the quiescent current drawn
by the LTC1703, especially at elevated temperature.
Note 6: This parameter is guaranteed by correlation and is not tested
Note 2: PV and BV (V
– V ) must be greater than V of
directly.
CC
CC BOOST
SW
GS(ON)
the external MOSFETs used to ensure proper operation.
Note 7: Each built-in pull-up resistor attached to the VID inputs also has a
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
series diode connected to V to allow input voltages higher than the V
supply without damage or clamping. (See Block Diagram.)
Note 8: Feedback current at FB1 will be higher due to internal VID
CC
CC
Note 4: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
resistors.
Note 9: Rise and fall times are measured using 10% and 90% levels. Delay
and nonoverlap times are measured using 50% levels.
1703fa
3
LTC1703
TYPICAL PERFOR A CE CHARACTERISTICS
U W
MOSFET Driver Supply Current
vs Gate Capacitance
Efficiency vs Load Current
Transient Response
100
90
35
30
V
IN
= 5V
TEST CIRCUIT 1
ONE DRIVER LOADED
MULTIPLY BY # OF ACTIVE
DRIVERS TO OBTAIN TOTAL
DRIVER SUPPLY CURRENT
VIN = 5V
VOUT = 1.8V
V
= 3.3V
OUT
I
LOAD = 0A-10A-0A
±2.2% MAX DEVIATION
V
V
= 2.5V
= 1.6V
OUT
OUT
25
20
15
10
5
20mV/
DIV
80
70
0
1703 G02
10µs/DIV
0
5
10
15
2000
4000
10000
0
6000
8000
LOAD CURRENT (A)
GATE CAPACITANCE (pF)
1703 G01
1703 G03
Normalized Frequency
vs Temperature
Supply Current vs Temperature
Driver R vs Temperature
ON
2.5
2.0
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.6
V
= 5V
V
V
= 5V
BOOST
CC
PVCC
TEST CIRCUIT 1
L
– V = 5V
SW
C
= 0pF
2.4
2.2
PV
CC
1.5
1.0
V
CC
2.0
1.8
1.6
1.4
1.2
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
BOOST1, BOOST2
1.0
–25
0
50
75 100 125
–50
0
25
50
75
125
–50
0
25
50
75
125
–50
25
100
100
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1703 G04
1703 G05
1703 G06
RUN/SS Source Current
vs Temperature
Nonoverlap Time vs Temperature
Driver Rise/Fall vs Temperature
15
14
13
12
11
12
5.0
4.5
4.0
3.5
70
60
TEST CIRCUIT 1
V
= 5V
TEST CIRCUIT 1
CC
C
= 2000pF
C
L
= 2000pF
L
TG FALLING EDGE
BG RISING EDGE
50
40
30
20
10
BG FALLING EDGE
TG RISING EDGE
3.0
2.5
2.0
0
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
1703 G09
1703 G07
1703 G08
1703fa
4
LTC1703
U
U
U
PI FU CTIO S
PVCC (Pin 1): Driver Power Supply Input. PVCC provides
power to the two BGn output drivers. PVCC must be
connected to a voltage high enough to fully turn on the
external MOSFETs QB1 and QB2. PVCC should generally
be connected directly to VIN. PVCC requires at least a 1µF
bypass capacitor directly to PGND.
FCB (Pin 7): Force Continuous Bar. The FCB pin forces
both converters to maintain continuous synchronous
operation regardless of load when the voltage at FCB
drops below 0.8V. FCB is normally tied to VCC. To force
continuous operation, tie FCB to SGND. FCB can also be
connected to a feedback resistor divider from a secondary
winding on one converter’s inductor to generate a third
regulated output voltage. Do not leave FCB floating.
BOOST1 (Pin 2): Controller 1 Top Gate Driver Supply. The
BOOST1 pin supplies power to the floating TG1 driver.
BOOST1 should be bypassed to SW1 with a 1µF capacitor.
An additional Schottky diode from VIN to BOOST1 pin will
create a complete floating charge-pumped supply at
BOOST1. No other external supplies are required.
RUN/SS1 (Pin 8): Controller 1 Run/Soft-Start. Pulling
RUN/SS1 to SGND will disable controller 1 and turn off
both of its external MOSFET switches. Pulling both
RUN/SS pins down will shut down the entire LTC1703,
dropping the quiescent supply current below 100µA. A
capacitor from RUN/SS1 to SGND will control the turn-on
time and rate of rise of the controller 1 output voltage at
power-up. An internal 3.5µA current source pull-up at
RUN/SS1 pin sets the turn-on time at approximately
50ms/µF.
BG1 (Pin 3): Controller 1 Bottom Gate Drive. The BG1 pin
drives the gate of the bottom N-channel synchronous
switch MOSFET, QB1. BG1 is designed to drive up to
10,000pF of gate capacitance directly. If RUN/SS1 goes
low, BG1 will go low, turning off QB1. If FAULT mode is
tripped, BG1 will go high and stay high, keeping QB1 on
until the power is cycled.
COMP1 (Pin 9): Controller 1 Loop Compensation. The
COMP1 pin is connected directly to the output of the first
controller’s error amplifier and the input to the PWM
comparator. An RC network is used at the COMP1 pin to
compensate the feedback loop for optimum transient
response.
TG1 (Pin 4): Controller 1 Top Gate Drive. The TG1 pin
drives the gate of the top N-channel MOSFET, QT1. The
TG1driverdraws powerfromtheBOOST1pinandreturns
to the SW1 pin, providing true floating drive to QT1. TG1
is designed to drive up to 10,000pF of gate capacitance
directly. In shutdown or fault modes, TG1 will go low.
SGND (Pin 10): Signal Ground. All internal low power
circuitry returns to the SGND pin. Connect to a low
impedance ground, separated from the PGND node. All
feedback,compensationandsoft-startconnectionsshould
return to SGND. SGND and PGND should connect only at
a single point, near the PGND pin and the negative plate of
the CIN bypass capacitor.
SW1 (Pin 5): Controller 1 Switching Node. SW1 should be
connected to the switching node of converter 1. The TG1
driver ground returns to SW1, providing floating gate
drive to the top N-channel MOSFET switch, QT1. The
voltage at SW1 is compared to IMAX1 by the current limit
comparator while the bottom MOSFET, QB1, is on.
FB1 (Pin 11): Controller 1 Feedback Input. The loop
compensation network for controller 1 should be con-
nected to FB1. FB1 is connected internally to the VID
resistor network to set the output voltage at side 1.
IMAX1 (Pin 6): Controller 1 Current Limit Set. The IMAX1
pin sets the current limit comparator threshold for
controller1.IfthevoltagedropacrossthebottomMOSFET,
QB1, exceeds the magnitude of the voltage at IMAX1
,
controller 1 will go into current limit. The IMAX1 pin has an
internal 10µA current source pull-up, allowing the current
threshold to be set with a single external resistor to PGND.
ThiscurrentsettingresistorshouldbeKelvinconnectedto
the source of QB1. See the Current Limit Programming
SENSE (Pin 12): Output Sense. Connect to VOUT1
.
VID0 to VID4 (Pins 13 to 17): VID Programming Inputs.
These are logic inputs that set the output voltage at side 1
to a preprogrammed value (see Table 1). VID4 is the MSB,
VID0 is the LSB. The codes selected by the VIDn inputs
correspond to the Intel Mobile VID specification. Each
section for more information on choosing RIMAX
.
1703fa
5
LTC1703
U
U
U
PI FU CTIO S
VIDn pin includes an on-chip 40kΩ pull-up resistor in
disabled. When FAULT is high, both BG pins will go high,
turning on the bottom MOSFET switches and pulling down
the high output voltage. The LTC1703 will remain latched
in this state until the power is cycled. When FAULT mode
is active, the FAULT pin will be pulled up with an internal
10µA current source. Tying FAULT directly to SGND will
disable latched FAULT mode and will allow the LTC1703 to
resume normal operation when the overvoltage fault is
removed.
series with a diode (see Block Diagram).
VCC (Pin 18): Power Supply Input. All internal circuits
except the output drivers are powered from this pin. VCC
should be connected to a low noise power supply voltage
between 3V and 7V and should be bypassed to SGND with
at least a 1µF capacitor in close proximity to the LTC1703.
FB2 (Pin 19): Controller 2 Feedback Input. FB2 should be
connected through a resistor divider network to VOUT2 to
set the ouput voltage. The loop compensation network for
controller 2 also connects to FB2.
PGND (Pin 23): Power Ground. The BGn drivers return to
this pin. Connect PGND to a high current ground node in
close proximity to the sources of external MOSFETs, QB1
and QB2, and the VIN and VOUT bypass capacitors.
COMP2 (Pin 20): Controller 2 Loop Compensation. See
COMP1.
SW2 (Pin 24): Controller 2 Switching Node. See SW1.
TG2 (Pin 25): Controller 2 Top Gate Drive. See TG1.
BG2 (Pin 26): Controller 2 Bottom Gate Drive. See BG1.
RUN/SS2 (Pin 21): Controller 2 Run/Soft-Start. See RUN/
SS1.
FAULT (Pin 22): Output Overvoltage Fault (Latched). The
FAULT pin is an open-drain output with an internal 10µA
pull-up. If either regulated output voltage rises more than
15% above its programmed value for more than 25µs, the
FAULT output will go high and the entire LTC1703 will be
BOOST2 (Pin 27): Controller 2 Top Gate Driver Supply.
See BOOST1.
IMAX2 (Pin 28): Controller 2 Current Limit Set. See IMAX1
.
TEST CIRCUIT
Test Circuit 1
5V
+
I
I
I
I
BOOST2
BOOST1
CC
PVCC
0.1µF
100µF
V
PV
CC
CC
BOOST1
TG1
BOOST2
TG2
f
OSC
MEASURED
BG1
BG2
SW1
SW2
2000pF
2000pF
2000pF
2000pF
2k
I
I
MAX2
MAX1
LTC1703
FCB
V
VID0:4
FAULT
NC
NC
FAULT
RUN/SS1
COMP1
FB1
RUN/SS2
COMP2
FB2
NC
2k
V
V
FB2
FB1
SENSE
GND
PGND
1703 TC
1703fa
6
LTC1703
W
BLOCK DIAGRA
PV
FCB
CC
V
BOOST1,2
CC
BURST
LOGIC
TG1,2
SW1,2
BG1,2
PGND
SGND
DRIVE
LOGIC
90% DUTY CYCLE
OSC
550kHz
DIS
4µA
SOFT
START
10µA
RUN/SS1,2
FAULT
COMP1,2
0V
25µs
DELAY
I
LIM
10µA
FB
MIN
MAX
FLT
+
–
FROM
I
MAX1,2
OTHER
800mV
760mV
840mV
920mV
CONTROLLER
FB1,2
SHUTDOWN TO
THIS CONTROLLER
40k
40k
40k
40k
V
CC
V
CC
V
CC
V
CC
SHUTDOWN TO
ENTIRE CHIP
VID0
VID1
VID2
VID3
500mV
SENSE
R11
10k
FROM
OTHER
CONTROLLER
TO FB1
SWITCH
CONTROL
LOGIC
R
B1
40k
V
CC
VID4
1703 BD
W U U
U
APPLICATIO S I FOR ATIO
OVERVIEW
erly designed circuit. The 550kHz switching frequency
allows the use of physically small, low value external
components without compromising performance. An
onboard DAC sets the output voltage at channel 1, consis-
tent with the Intel mobile VID specification (Table 1).
The LTC1703 is a dual, step-down (buck), voltage mode
feedback switching regulator controller. It is designed to
be used in a synchronous switching architecture with two
external N-channel MOSFETs per channel. It is intended to
operate from a low voltage input supply (7V maximum)
and provide a high power, high efficiency, precisely regu-
lated output voltage. Several features make it particularly
suitedformicroprocessorsupplyregulation.Outputregu-
lation is extremely tight, with DC line and load regulation
and initial accuracy better than 1.5%, and total regulation
including transient response inside of 3.5% with a prop-
The LTC1703’s internal feedback amplifier is a 25MHz
gain-bandwidth op amp, allowing the use of complex
multipole/zero compensation networks. This allows the
feedback loop to maintain acceptable phase margin at
higher frequencies than traditional switching regulator
controllersallow,improvingstabilityandmaximizingtran-
sient response. The 800mV internal reference allows
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Table 1. VID Inputs and Corresponding Output Voltage for
Channel 1
CODE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111*
VID4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VID3
GND
GND
GND
GND
GND
GND
GND
GND
Float
Float
Float
Float
Float
Float
Float
Float
VID2
GND
GND
GND
GND
Float
Float
Float
Float
GND
GND
GND
GND
Float
Float
Float
Float
VID1
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
VID0
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
V
CODE
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111*
VID4
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
VID3
GND
GND
GND
GND
GND
GND
GND
GND
Float
Float
Float
Float
Float
Float
Float
Float
VID2
GND
GND
GND
GND
Float
Float
Float
Float
GND
GND
GND
GND
Float
Float
Float
Float
VID1
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
VID0
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
V
OUT1
OUT1
2.00V
1.95V
1.90V
1.85V
1.80V
1.75V
1.70V
1.65V
1.60V
1.55V
1.50V
1.45V
1.40V
1.35V
1.30V
1.25V
1.275V
1.250V
1.225V
1.200V
1.175V
1.150V
1.125V
1.100V
1.075V
1.050V
1.025V
1.000V
0.975V
0.950V
0.925V
0.900V
* 01111 and 11111 are defined by Intel to signify “no CPU.” The LTC1703
will generate the output voltages shown when these codes are selected.
regulated output voltages as low as 800mV without exter-
nal level shifting amplifiers.
circuit designs shift the current load to lower voltage
supplies.
The LTC1703’s synchronous switching logic transitions
automatically into Burst Mode operation, maximizing effi-
ciency with light loads. An onboard overvoltage (OV) fault
flag indicates when an OV fault has occurred. The OV flag
can be set to latch the device off when an OV fault has
occurred, or to automatically resume operation when the
fault is removed.
Each regulator in a typical 2-step system maintains a
relativelylowstep-downratio(5:1orless),runningathigh
efficiency while maintaining a reasonable duty cycle. In
contrast, a regulator taking a single step from a high input
voltage to a 1.xV output must run at a very narrow duty
cycle, mandating trade-offs in external component values
while compromising efficiency and transient response.
The efficiency loss can exceed that of using a 2-step
solution (see the 2-Step Efficiency Calculation section and
Figure 10). Further complicating the calculation is the fact
that many systems draw a significant fraction of their total
power off the intermediate 5V supply, bypassing the low
voltage supply. 2-step solutions using the LTC1703 usu-
ally match or exceed the total system efficiency of single-
step solutions, and provide the additional benefits of
improved transient response, reduced PCB area and sim-
plified power trace routing.
2-Step Conversion
“2-step” architectures use a primary regulator to convert
the input power source (batteries or AC line voltage) to an
intermediate supply voltage, often 5V. This intermediate
voltage is then converted to the low voltage, high current
supplies required by the system using a secondary regu-
lator—the LTC1703. 2-step conversion eliminates the
need for a single converter that converts a high input
voltage to a very low output voltage, often an awkward
design challenge. It also fits naturally into systems that
continue to use the 5V supply to power portions of their
circuitry, or have excess 5V capacity available as newer
2-step regulation can buy advantages in thermal manage-
ment as well. Power dissipation in the LTC1703 portion of
a 2-step circuit is lower than it would be in a typical 1-step
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converter, even in cases where the 1-step converter has
higher total efficiency than the 2-step system. In a typical
microprocessor core supply regulator, for example, the
regulator is usually located right next to the CPU. In a
1-step design, all of the power dissipated by the core
regulator is right there next to the hot CPU, aggravating
thermal management. In a 2-step LTC1703 design, a
significant percentage of the power lost in the core regu-
lation system happens in the 5V supply, which is usually
located away from the CPU. The power lost to heat in the
LTC1703 section of the system is relatively low, minimiz-
ing the added heat near the CPU.
Figure 7 shows example waveforms for a single switching
regulator channel versus a 2-phase LTC1703 system with
both sides switching. A single-phase dual regulator with
both sides operating would exhibit double the single side
numbers. In this example, 2-phase operation reduced the
RMS input current from 9.3ARMS (2 × 4.66ARMS) to
4.8ARMS. While this is an impressive reduction in itself,
2
rememberthatthepowerlossesareproportionaltoIRMS
,
meaning that the actual power wasted is reduced by a
factorof3.75.Thereducedinputripplevoltagealsomeans
less power is lost in the input power path, which could
include batteries, switches, trace/connector resistances
andprotectioncircuitry. Improvementsinbothconducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
See the Optimizing Performance section for a detailed
explanation of how to calculate system efficiency.
2-Phase Operation
Small Footprint
The LTC1703 dual switching regulator controller also
features the considerable benefits of 2-phase operation.
Notebookcomputers, handheldterminalsandautomotive
electronics all benefit from the lower input filtering
requirement, reduced electromagnetic interference (EMI)
and increased efficiency associated with 2-phase
operation.
The LTC1703 operates at a 550kHz switching frequency,
allowing it to use low value inductors without generating
excessive ripple currents. Because the inductor stores
less energy per cycle, the physical size of the inductor can
be reduced without risking core saturation, saving PCB
board space. The high operating frequency also means
less energy is stored in the output capacitors between
cycles, minimizing their required value and size. The
remaining components, including the SSOP-28 LTC1703,
are tiny, allowing an entire dual-output LTC1703 circuit to
be constructed in 1.5in2 of PCB space. Further, this space
is generally located right next to the microprocessor or in
some similarly congested area, where PCB real estate is at
a premium. The fact that the LTC1703 runs off the 5V
supply, often available from a power plane, is an added
benefit in portable systems —it does not require a dedi-
cated supply line running from the battery.
Whytheneedfor2-phaseoperation?UpuntiltheLTC1703,
constant-frequency dual switching regulators operated
bothchannelsinphase(i.e., single-phaseoperation). This
means that both topside MOSFETs turned on at the same
time, causing current pulses of up to twice the amplitude
of those for one regulator to be drawn from the input
capacitor. These large amplitude current pulses increased
the total RMS current flowing from the input capacitor,
requiring the use of more expensive input capacitors and
increasing both EMI and losses in the input capacitor and
input power supply.
Fast Transient Response
With 2-phase operation, the two channels of the LTC1703
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the switches,
greatlyreducingtheoverlaptimewheretheyaddtogether.
The result is a significant reduction in total RMS input
current, which in turn allows less expensive input capaci-
tors to be used, reduces shielding requirements for EMI
and improves real world operating efficiency.
The LTC1703 uses a fast 25MHz GBW op amp as an error
amplifier. This allows the compensation network to be
designed with several poles and zeros in a more flexible
configuration than with a typical gm feedback amplifier.
The high bandwidth of the amplifier, coupled with the high
switching frequency and the low values of the external
inductor and output capacitor, allow very high loop cross-
over frequencies. The low inductor value is the other half
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of the equation—with a typical value on the order of 1µH,
the inductor allows very fast di/dt slew rates. The result is
superior transient response compared with conventional
solutions.
chip and their corresponding external components act
independently of each other with the exception of the
common input bypass capacitor, the VID circuitry at side
1, and the FCB and FAULT pins, which affect both chan-
nels. In the following discussions, when a pin is referred
to without mentioning which side is involved, that discus-
sion applies equally to both sides.
High Efficiency
The LTC1703 uses a synchronous step-down (buck)
architecture, with two external N-channel MOSFETs per
output. A floating topside driver and a simple external
charge pump provide full gate drive to the upper MOSFET.
The voltage mode feedback loop and MOSFET VDS current
limit sensing remove the need for an external current
sense resistor, eliminating an external component and a
source of power loss in the high current path. Properly
designed circuits using low gate charge MOSFETs are
capable of efficiencies exceeding 90% over a wide range
of output voltages.
Switching Architecture
Each half of the LTC1703 is designed to operate as a
synchronous buck converter (Figure 1). Each channel
includes two high power MOSFET gate drivers to control
external N-channel MOSFETs QT and QB. These drivers
have 0.5Ω output impedances and can carry well over an
amp of continuous current with peak currents up to 5A to
slew large MOSFET gates quickly. The external MOSFETs
are connected with the drain of QT attached to the input
supply and the source of QT at the switching node SW. QB
is the synchronous rectifier with its drain at SW and its
source at PGND. SW is connected to one end of the
inductor,withtheotherendconnectedtoVOUT.Theoutput
capacitor is connected from VOUT to PGND.
VID Programming
The LTC1703 includes an onboard feedback network that
programs the output voltage at side 1 in accordance with
the Intel Mobile VID specification (Table 1). The network
includes a 10k resistor (R11) connected from SENSE to
FB1, andavariablevalueresistor(RB1)fromFB1toSGND,
with the value set by the digital code present at the VID0:4
pins. SENSE should be connected to VOUT1 to allow the
network to monitor the output voltage. No additional
feedback components are required to set the output volt-
age at controller 1, although loop compensation compo-
nents are still required. Each VIDn pin includes an internal
40k pull-up resistor, allowing it to float high if left uncon-
nected.Thepull-upresistorsareconnectedtoVCC through
diodes (see Block Diagram), allowing the VIDn pins to be
pulled above VCC without damage.
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to VIN and the
inductor current begins to increase. When the PWM pulse
finishes, QTturnsoffandonenonoverlapintervallater, QB
turnson. NowSWdropstoPGNDandtheinductorcurrent
decreases. The cycle repeats with the next tick of the
master clock. The percentage of time spent in each mode
is controlled by the duty cycle of the PWM signal, which in
turn is controlled by the feedback amplifier. The master
clockrunsata550kHzrateandturnsQTonceevery1.8µs.
In a typical application with a 5V input and a 1.5V output,
the duty cycle will be set at 1.5/5 × 100% or 30% by the
feedback loop. This will give roughly a 540ns on-time for
QT and a 1.26µs on-time for QB.
Note that codes 01111 and 11111, defined by Intel to
indicate “no CPU present,” do generate output voltages at
VOUT1 (1.25V and 0.9V, respectively). Note also that
controller 2 on the LTC1703 is not connected to the VID
circuitry, and works independently from controller 1.
V
IN
+
+
C
IN
L
EXT
QT
TG
LTC1703 SW
V
OUT
ARCHITECTURE DETAILS
QB
BG
PGND
C
OUT
The LTC1703 dual switching regulator controller includes
two independent regulator channels. The two sides of the
1703 F01
Figure 1. Synchronous Buck Architecture
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V
IN
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
leavethe455kHzIFbandfreeofinterference.Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1703.
+
D
C
CP
IN
PV
BOOST
TG
CC
C
1µF
CP
QT
L
EXT
SW
V
OUT
+
BG
QB
C
OUT
LTC1703
PGND
1703 F02
Figure 2. Floating TG Driver Supply
During the time that QT is on, its source (the SW pin) is at
VIN. VIN is also the power supply for the LTC1703. How-
ever, QT requires VIN + VGS(ON) at its gate to achieve
minimumRON.ThispresentsaproblemfortheLTC1703—
it needs to generate a gate drive signal at TG higher than
its highest supply voltage. To accomplish this, the TG
driver runs from floating supplies, with its negative supply
attachedtoSWanditspowersupplyatBOOST.Thisallows
ittoslewupanddownwiththesourceofQT.Incombination
with a simple external charge pump (Figure 2), this allows
theLTC1703tocompletelyenhancethegateofQTwithout
requiring an additional, higher supply voltage.
topology with the FB pin configured as a virtual ground.
This allows flexibility in choosing pole and zero locations
notavailablewithsimplegm configurations.Inparticular,
it allows the use of “type 3” compensation, which pro-
vides a phase boost at the LC pole frequency and signifi-
cantly improves loop phase margin (see Figure 3). The
Feedback Loop/Compensation section contains a de-
tailedexplanationoftype3feedbackloops. Notethatside
1 of the LTC1703 includes R1 and RB internally as part
of the VID DAC circuitry.
MIN/MAX COMPARATORS
The two channels of the LTC1703 run from a common
clock, with the phasing chosen to be 180° from side 1 to
side 2. This has the effect of doubling the frequency of the
switching pulses seen by the input bypass capacitor,
significantlyloweringtheRMScurrentseenbythecapaci-
tor and reducing the value required (see the 2-Phase
section).
Two additional feedback loops keep an eye on the primary
feedback amplifier and step in if the feedback node moves
± 5%fromitsnominal800mVvalue. TheMAXcomparator
(see Block Diagram) activates whenever FB rises more
than 5% above 800mV. It immediately turns the top
MOSFET (QT) off and the bottom MOSFET (QB) on and
keeps them that way until FB falls back within 5% of its
nominal value. This pulls the output down as fast as pos-
sible, preventing damage to the (often expensive) load. If
FB rises because the output is shorted to a higher supply,
QBwillstayonuntiltheshortgoesaway, thehighersupply
Feedback Amplifier
Each side of the LTC1703 senses the output voltage at
VOUT with an internal feedback op amp (see Block Dia-
gram). This is a real op amp with a low impedance output,
85dBopen-loopgainand25MHzgain-bandwidthproduct.
The positive input is connected internally to an 800mV
reference, while the negative input is connected to the FB
pin. The output is connected to COMP, which is in turn
connected to the soft-start circuitry and from there to the
PWM generator.
C3
0.8V
+
R3
COMP
FB
R1
FB
V
–
OUT
R
B
C2
Unlike many regulators that use a resistor divider con-
nected to a high impedance feedback input, the LTC1703
is designed to use an inverting summing amplifier
C1
R2
1703 F03
Figure 3. “Type 3” Feedback Loop (Side 2 Shown)
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current limits or QB dies trying to save the load. This
behavior provides maximum protection against overvolt-
age faults at the output, while allowing the circuit to re-
sume normal operation when the fault is removed. The
overvoltageprotectioncircuitcanoptionallybesettolatch
the output off permanently (see the Overvoltage Fault
section).
Maximizing feedback loop bandwidth will minimize these
delays and allow MIN and MAX to operate properly. See
the Feedback Loop/Compensation section.
SHUTDOWN/SOFT-START
Each half of the LTC1703 has a RUN/SS pin. The RUN/SS
pins perform two functions: when pulled to ground, each
shuts down its half of the LTC1703, and each acts as a
conventional soft-start pin, enforcing a maximum duty
cycle limit proportional to the voltage at RUN/SS. An
internal 3.5µA current source pull-up is connected to each
RUN/SS pin, allowing a soft-start ramp to be generated
with a single external capacitor to ground. The 3.5µA
current sources are active even when the LTC1703 is shut
down, ensuring the device will start when any external
pull-down at RUN/SS is released. Either side can be shut
down without affecting the operation of the other side. If
both sides are shut down at the same time, the LTC1703
goes into a micropower sleep mode, and quiescent cur-
rent drops typically below 50µA. Entering sleep mode also
resets the FAULT latch, if it was set.
The MIN comparator (see Block Diagram) trips whenever
FB is more than 5% below 800mV and immediately forces
the switch duty cycle to 90% to bring the output voltage
back into range. It releases when FB is within the 5%
window. MIN is disabled when the soft-start or current
limit circuits are active—the only two times that the
output should legitimately be below its regulated value.
Notice that the FB pin is the virtual ground node of the
feedback amplifier. A typical compensation network does
not include local DC feedback around the amplifier, so that
the DC level at FB will be an accurate replica of the output
voltage, divided down by R1 and RB (Figure 3). However,
the compensation capacitors will tend to attenuate AC
signals at FB, especially with low bandwidth type 1 feed-
back loops. This creates a situation where the MIN and
MAX comparators do not respond immediately to shifts in
the output voltage, since they monitor the output at FB.
EachRUN/SSpinshutsdownitshalfoftheLTC1703when
it falls below about 0.5V (Figure 4). Between 0.5V and
about 1V, that half is active, but the maximum duty cycle
V
OUT
0V
5V
4.5V
V
2.5V
2.5V
RUN/SS
1.0V
0.5V
0V
LTC1703 ENABLED
RUN/SS CONTROLS
DUTY CYCLE
RUN/SS CONTROLS
DUTY CYCLE
COMP CONTROLS DUTY CYCLE
MIN COMPARATOR ENABLED
START-UP
NORMAL OPERATION
CURRENT LIMIT
1703 F04
Figure 4. Soft-Start Operation in Start-Up and Current Limit
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regulation. The delay also acts as a pole in the current limit
loop to enhance loop stability. Larger overloads cause the
soft-start capacitor to pull down quickly, protecting the
output components from damage. The current limit gm
amplifier includes a clamp to prevent it from pulling RUN/
SS below 0.5V and shutting off the device.
is limited to 10%. The maximum duty cycle limit increases
linearly between 1V and 2.5V, reaching its final value of
90% when RUN/SS is above 2.5V. Somewhere before this
point, the feedback amplifier will assume control of the
loop and the output will come into regulation. When RUN/
SS rises to 0.5V below VCC, the MIN feedback comparator
is enabled, and the LTC1703 is in full operation.
Power MOSFET RDS(ON) varies from MOSFET to MOSFET,
limitingtheaccuracyobtainablefromtheLTC1703current
limit loop. Additionally, ringing on the SW node due to
parasitics can add to the apparent current, causing the
loop to engage early. The LTC1703 current limit is
designed primarily as a disaster prevention, “no blow up”
circuit, and is not useful as a precision current regulator.
It should typically be set around 50% above the maximum
expected normal output current to prevent component
tolerances from encroaching on the normal current range.
See the Current Limit Programming section for advice on
CURRENT LIMIT
TheLTC1703includesanonboardcurrentlimitcircuitthat
limitsthemaximumoutputcurrenttoauser-programmed
level. It works by sensing the voltage drop across QB
during the time that QB is on and comparing that voltage
to a user-programmed voltage at IMAX. Since QB looks like
a low value resistor during its on-time, the voltage drop
across it is proportional to the current flowing in it. In a
buckconverter,theaveragecurrentintheinductorisequal
to the output current. This current also flows through QB
during its on-time. Thus, by watching the voltage across
QB, the LTC1703 can monitor the output current.
choosing a value for RIMAX
.
DISCONTINUOUS/Burst Mode OPERATION
Theory of operation
Any time QB is on and the current flowing to the output is
reasonably large, the SW node at the drain of QB will be
somewhat negative with respect to PGND. The LTC1703
senses this voltage and inverts it to allow it to compare the
sensed voltage with a positive voltage at the IMAX pin. The
IMAX pin includes a trimmed 10µA pull-up, enabling the
The LTC1703 switching logic has three modes of opera-
tion. Under heavy loads, it operates as a fully synchro-
nous, continuous conduction switching regulator. In this
modeofoperation(“continuous”mode), thecurrentinthe
inductorflowsinthepositivedirection(towardtheoutput)
during the entire switching cycle, constantly supplying
current to the load. In this mode, the synchronous switch
(QB) is on whenever QT is off, so the current always flows
through a low impedance switch, minimizing voltage drop
and power loss. This is the most efficient mode of opera-
tion at heavy loads, where the resistive losses in the power
devices are the dominant loss term.
usertosetthevoltageatIMAX withasingleresistor, RIMAX
,
to ground. The LTC1703 compares the two inputs and
begins limiting the output current when the magnitude of
the negative voltage at the SW pin is greater than the
voltage at IMAX
.
The current limit detector is connected to an internal gm
amplifier that pulls a current from the RUN/SS pin propor-
tional to the difference in voltage magnitudes between the
SW and IMAX pins. This current begins to discharge the
soft-start capacitor at RUN/SS, reducing the duty cycle
and controlling the output voltage until the output current
drops below the limit. The soft-start capacitor needs to
move a fair amount before it has any effect on the duty
cycle, adding a delay until the current limit takes effect
(Figure 4). This allows the LTC1703 to experience brief
overload conditions without affecting the output voltage
Continuous mode works efficiently when the load current
is greater than half of the ripple current in the inductor. In
a buck converter like the LTC1703, the average current in
the inductor (averaged over one switching cycle) is equal
to the load current. The ripple current is the difference
between the maximum and the minimum current during a
switching cycle (see Figure 5a). The ripple current
depends on inductor value, clock frequency and output
voltage, but is constant regardless of load as long as the
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LTC1703 remains in continuous mode. See the Inductor
Selection section for a detailed description of ripple
current.
is most severe, and by including a few millivolts offset in
the comparator that monitors the SW node. Despite these
precautions, some combinations of inductor and layout
parasitics can cause the LTC1703 to enter discontinuous
mode erratically. In many cases, the time that QB turns off
will correspond to a peak in the ringing waveform at the
SW pin (Figure 6). This erratic operation isn’t pretty, but
retains much of the efficiency benefit of discontinuous
mode and maintains regulation at all times.
As the output load current decreases in continuous mode,
theaveragecurrentintheinductorwillreachapointwhere
it drops below half the ripple current. At this point, the
current in the inductor will reverse during a portion of the
switching cycle, or begin to flow from the output back to
the input. This does not adversely affect regulation, but
does cause additional losses as a portion of the inductor
current flows back and forth through the resistive power
switches, giving away a little more power each time and
lowering the efficiency. There are some benefits to allow-
ing this reverse current flow: the circuit will maintain
regulation even if the load current drops below zero (the
load supplies current to the LTC1703) and the output
ripple voltage and frequency remain constant at all loads,
easing filtering requirements. Circuits that take advantage
of this behavior can force the LTC1703 to operate in
continuous mode at all loads by tying the FCB (Force
Continuous Bar) pin to ground.
I
RIPPLE
I
AVERAGE
TIME
1703 F05a
Figure 5a. Continuous Mode
Discontinuous Mode
To minimize the efficiency loss due to reverse current flow
at light loads, the LTC1703 switches to a second mode of
operation:discontinuousmode(Figure5b).Indiscontinu-
ousmode, theLTC1703detectswhentheinductorcurrent
approaches zero and turns off QB for the remainder of the
switch cycle. During this time, the voltage at the SW pin
will float about VOUT, the voltage across the inductor will
be zero, and the inductor current remains zero until the
next switching cycle begins andQT turns on again. This
prevents current from flowing backwards in QB, eliminat-
ing that power loss term. It also reduces the ripple current
in the inductor as the output current approaches zero.
I
RIPPLE
I
AVERAGE
TIME
1703 F05b
Figure 5b. Discontinuous Mode
DISCONTINUOUS
COMPARATOR
TURNS OFF BG
V
SW
0V
TIME
TheLTC1703detectsthattheinductorcurrenthasreached
zero by monitoring the voltage at the SW pin while QB is
on. SinceQBactslikearesistor, SWshouldideallyberight
at0Vwhentheinductorcurrentreacheszero.Inreality,the
SW node will ring to some degree immediately after it is
switched to ground by QB, causing some uncertainty as to
the actual moment the average current in QB goes to zero.
The LTC1703 minimizes this effect by ignoring the SW
node for a fixed 50ns after QB turns on when the ringing
50ns
BLANK
TIME
5V
0V
V
BG
1703 F06
TIME
Figure 6. Ringing at SW Causes Discontinuous
Comparator to Trip Early
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Burst Mode Operation
Continuous Bar) pin allows the user to do this. When the
FCB pin is high, the LTC1703 is allowed to enter discon-
tinuous and Burst Mode operations at either side as
required. If FCB is taken low, discontinuous and Burst
Mode operations are disabled and both sides of the
LTC1703 run in continuous mode regardless of load. This
does not affect output regulation but does reduce effi-
ciency at low output currents. The FCB pin threshold is
specified at 0.8V ±50mV, and includes 20mV of hyster-
esis, allowing it to be used as a precision small-signal
comparator.
Discontinuous mode removes a loss term due to resistive
drop in QB, but the LTC1703 is still switching QT and QB
on and off once a cycle. Each time an external MOSFET is
turned on, the internal driver must charge its gate to VCC.
Each time it is turned off, that charge is lost to ground. At
the high switching frequencies that the LTC1703 operates
at, the charge lost to the gates can add up to tens of
milliampsfromVCC. Astheloadcurrentcontinuestodrop,
thisquicklybecomethedominantpowerlossterm, reduc-
ing efficiency once again.
Once again, the LTC1703 switches to a new mode to
minimize efficiency loss: Burst Mode operation. As the
circuit goes deeper and deeper into discontinuous mode,
thetotaltimeQTandQBareonreduces.However,theratio
of the time that QT is on to the time that QB is on must
remain constant for the output to stay in regulation. An
internal timer circuit forces QT to stay on for at least 10%
of a normal switching cycle. When the load drops to the
pointthattheoutputrequireslessthan10%on-timeatQT,
the output voltage will begin to rise. The LTC1703 senses
this rise and shuts both QT and QB off completely, skip-
ping several switching cycles until the output falls back
into range. It then resumes switching in discontinuous
mode with QT at 10% duty cycle and the burst sequence
repeats. The total deviation from the regulated output is
within the 1.5% regulation tolerance of the LTC1703.
Paralleling Outputs
Synchronous regulators (like the LTC1703) are known for
their bullheadedness when their outputs are paralleled
with other regulators. In particular, a synchronous regu-
lator paralleled with another regulator whose output is
slightlyhigher(perhapsjustbymillivolts)willhappilysink
amps of current attempting to pull its own output back
down to what it thinks is the right value.
The LTC1703 discontinuous mode allows it to be paral-
leled with another regulator without fighting. A typical
system might use the LTC1703 as a primary regulator and
a small LDO as a backup regulator to keep SRAM alive
when the main power is off. When the LTC1703 is shut
down(bypullingRUN/SStoground), bothQTandQBturn
off and the output goes into a high impedance state,
allowing the smaller regulator to support the output volt-
age. However, if the LTC1703 is powered back up in
continuous mode, it will begin a soft-start cycle with a low
duty cycle, pulling the output down and corrupting the
data stored in SRAM. The solution is to tie FCB high,
allowing the device to start in discontinuous mode. Any
reversecurrentflowinQBwilltripthediscontinuousmode
circuitry, preventing the LTC1703 from pulling down the
output.
InBurstModeoperation, bothresistivelossandswitching
loss are minimized while keeping the output in regulation.
The ripple current will be set by the 10% QT on-time and
the input supply voltage and is the lowest of all three
operating modes. As the load current falls to zero in Burst
Mode operation, the most significant loss term becomes
the 3mA quiescent current drawn by each side of the
LTC1703—usually much less than the minimum load
current in a typical low voltage logic system. Burst Mode
operation maximizes efficiency at low load currents, but
can cause low frequency ripple in the output voltage as the
cycle-skipping circuitry switches on and off.
OVERVOLTAGE FAULT
The LTC1703 includes a single overvoltage fault flag for
both channels: FAULT. FAULT is an open-drain output
with an internal 10µA pull-up. If either FB pin rises more
than 15% above the nominal 800mV value for more than
25µs, the overvoltage comparator will trip, setting an
1703fa
FCB Pin
Insomecircumstances, itisdesirabletocontrolordisable
discontinuousandBurstModeoperations.TheFCB(Force
15
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APPLICATIO S I FOR ATIO
internal latch. This latch releases the pull-down at FAULT,
allowing the 10µA pull-up to take it high. When FAULT
goes high, the LTC1703 stops all switching, turns both QB
(bottom synchronous) MOSFETs on continuously and
remainsinthisstateuntil bothRUN/SSpinsarepulledlow
simultaneously, the power supply is recycled, or the
FAULT pin is pulled low externally. This behavior is
intended to protect a potentially expensive load from
overvoltage damage at all costs. Under some conditions,
this behavior can cause the output voltage to undershoot
below ground. If latched FAULT mode is used, a Schottky
diode should be added with its cathode at the output and
its anode at ground to clamp the negative voltage to a safe
level and prevent possible damage to the load and the
output capacitors.
VID Considerations
Some applications change the VID codes at channel 1 on
thefly. ThisispossiblewiththeLTC1703, butcaremustbe
taken to avoid tripping the overvoltage fault circuit. Step-
ping the voltage upwards abruptly is safe, but stepping
down quickly by more than 15% can leave the system in a
statewheretheoutputvoltageisstillattheoldhigherlevel,
but the feedback node is set to expect a new, substantially
lower voltage. If this condition persists for more than
25µs, the overvoltage fault circuitry will fire and latch off
the LTC1703.
The simplest solution is to disable the fault circuit by
groundingtheFAULTpin.Systemsthatmustkeepthefault
circuitactiveshouldensurethattheoutputvoltageisnever
programmedtostepdownbymorethan15%inanysingle
step. A safe strategy is to step the output down by 10% or
less at a time and wait for the output to settle to the new
value before taking subsequent steps. Regardless of the
stateoftheFAULTpin, theloadisalwaysprotectedagainst
overvoltage faults by the +5% MAX comparator.
Note that in overvoltage conditions, the MAX comparator
will kick in at just +5%, turning QB on continuously long
before the output reaches +15%. Under most fault condi-
tions, this is adequate to bring the output back down
without firing the fault latch. Additionally, if MAX success-
fully keeps the output below +15%, the LTC1703 will
resume normal regulation as soon as the output overvolt-
age fault is resolved.
EXTERNAL COMPONENT SELECTION
POWER MOSFETs
In some circuits, the OV latch can be a liability. Consider
a circuit where the output voltage at one channel may be
changed on the fly by changing the VID code or switching
in different feedback resistors. A downward adjustment of
greater than 15% will fire the fault latch, disabling both
sidesoftheLTC1703untilthepowerisrecycled.Incircuits
such as this, the fault latch can be disabled by grounding
the FAULT pin. The internal latch will still be set the first
time the output exceeds +15%, but the 10µA current
source pull-up will not be able to pull FAULT high, and the
LTC1703 will ignore the latch and continue normal opera-
tion. The MAX comparator will act as usual, turning on QB
until output is within range and then allowing the loop to
resume normal operation. FAULT can also be pulled down
with external open-collector logic to restart a fault-latched
LTC1703 as an alternative to recycling the power. Note
that this will not reset the internal latch; if the external pull-
down is released, the LTC1703 will reenter FAULT mode.
To reset the latch, pull both RUN/SS pins low simulta-
neously or cycle the power.
GettingpeakefficiencyoutoftheLTC1703dependsstrongly
on the external MOSFETs used. The LTC1703 requires at
least two external MOSFETs per side—more if one or
more of the MOSFETs are paralleled to lower on-resis-
tance. To work efficiently, these MOSFETs must exhibit
low RDS(ON) at 5V VGS (3.3V VGS if the PVCC input supply
is 3.3V) to minimize resistive power loss while they are
conducting current. They must also have low gate charge
to minimize transition losses during switching. On the
other hand, voltage breakdown requirements in a typical
LTC1703 circuit are pretty tame: the 7V maximum input
voltage limits the VDS and VGS the MOSFETs can see to
safe levels for most devices.
Low RDS(ON)
RDS(ON) calculations are pretty straightforward. RDS(ON) is
the resistance from the drain to the source of the MOSFET
when the gate is fully on. Many MOSFETs have RDS(ON)
specified at 4.5V gate drive—this is the right number to
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U
use in LTC1703 circuits running from a 5V supply. As
current flows through this resistance while the MOSFET is
on, it generates I2R watts of heat, where I is the current
flowing (usually equal to the output current) and R is the
MOSFET RDS(ON). This heat is only generated when the
MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
lossterm.Old-fashionedswitchersthatranat20kHzcould
pretty much ignore gate charge as a loss term; in the
550kHz LTC1703, gate charge loss can be a significant
efficiency penalty. Gate charge loss can be the dominant
loss term at medium load currents, especially with large
MOSFETs. Gate charge loss is also the primary cause of
power dissipation in the LTC1703 itself.
TG Charge Pump
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter—both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost are at a maximum. Lowering
There’sanothernuanceofMOSFETdrivethattheLTC1703
needs to get around. The LTC1703 is designed to use
N-channel MOSFETs for both QT and QB, primarily
becauseN-channelMOSFETsgenerallycostlessandhave
lower RDS(ON) than similar P-channel MOSFETs. Turning
QB on is no big deal since the source of QB is attached to
PGND; the LTC1703 just switches the BG pin between
PGND and VCC. Driving QT is another matter. The source
of QT is connected to SW which rises to VCC when QT is
on. To keep QT on, the LTC1703 must get TG one MOSFET
VGS(ON) above VCC. It does this by utilizing a floating driver
with the negative lead of the driver attached to SW (the
source of QT) and the VCC lead of the driver coming out
separately at BOOST. An external 1µF capacitor (CCP)
connected between SW and BOOST (Figure 2) supplies
power to BOOST when SW is high, and recharges itself
through DCP when SW is low. This simple charge pump
keeps the TG driver alive even as it swings well above VCC.
The value of the bootstrap capacitor CCP needs to be at
least 100 times that of the total input capacitance of the
topside MOSFET(s). For very large external MOSFETs (or
multiple MOSFETs in parallel), CCP may need to be
increased beyond the 1µF value.
R
DS(ON) improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET RDS(ON) becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1703 circuit, allowing the use of small, surface
mount MOSFETs without heat sinks.
Gate Charge
Gate charge is amount of charge (essentially, the number
of electrons) that the LTC1703 needs to put into the gate
of an external MOSFET to turn it on. The easiest way to
visualize gate charge is to think of it as a capacitance from
the gate pin of the MOSFET to SW (for QT) or to PGND (for
QB). This capacitance is composed of MOSFET channel
charge, actual parasitic drain-source capacitance and
Miller-multiplied gate-drain capacitance, but can be
approximated as a single capacitance from gate to source.
Regardless of where the charge is going, the fact remains
that it all has to come out of VCC to turn the MOSFET gate
on, and when the MOSFET is turned back off, that charge
all ends up at ground. In the meanwhile, it travels through
the LTC1703’s gate drivers, heating them up. More power
lost!
INPUT SUPPLY
The BiCMOS process that allows the LTC1703 to include
large MOSFET drivers on-chip also limits the maximum
input voltage to 7V. This limits the practical maximum
input supply to a loosely regulated 5V or 6V rail. The
LTC1703willoperateproperlywithinputsuppliesdownto
about 3V, so a typical 3.3V supply can also be used if the
externalMOSFETsarechosenappropriately(seethePower
MOSFETs section).
Inthiscase,thepowerislostinlittlebite-sizedchunks,one
chunk per switch per cycle, with the size of the chunk set
bythegatechargeoftheMOSFET. EverytimetheMOSFET
switches, another chunk is lost. Clearly, the faster the
clock runs, the more important gate charge becomes as a
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At the same time, the input supply needs to supply several
amps of current without excessive voltage drop. The input
supply must have regulation adequate to prevent sudden
load changes from causing the LTC1703 input voltage to
dip. In most typical applications where the LTC1703 is
generating a secondary low voltage logic supply, all of
these input conditions are met by the main system logic
supply when fortified with an input bypass capacitor.
The two sides of the LTC1703 run off a single master clock
and are wired 180° out of phase with each other to
significantly reduce the total capacitance/ESR needed at
the input. Assuming 100mV of ripple and 10A output
current, we needed an ESR of 0.01Ω and 4.7A ripple
current capability for one side. Now, assume both sides
are running simultaneously with identical loading. If the
two sides switched in phase, all the loading conditions
would double and we’d need enough capacitance for
9.4ARMS and 0.005Ω ESR. With the two sides out of
phase, the input current is 4.8ARMS—barely larger than
the single case (Figure 7)! The peak current deltas are still
only10A, requiringthesame0.01ΩESRrating. Aslongas
the capacitor we chose for the single side application can
support the slightly higher 4.8ARMS current, we can add
the second channel without changing the input capacitor
at all. As a general rule, an input bypass capacitor capable
of supporting the larger output current channel can sup-
port both channels running simultaneously (see the
2-Phase Operation section for more information). Details
on how to calculate the maximum RMS input current can
be found in Application Note 77.
INPUT BYPASS CAPACITOR
A typical LTC1703 circuit running from a 5V logic supply
might provide 1.6V at 10A at one of its outputs. 5V to 1.6V
implies a duty cycle of 32%, which means QT is on 32%
of each switching cycle. During QT’s on-time, the current
drawn from the input equals the load current and during
the rest of the cycle, the current drawn from the input is
near zero. This 0A to 10A, 32% duty cycle pulse train adds
up to 4.7ARMS at the input. At 550kHz, switching cycles
last about 1.8µs—most system logic supplies have no
hope of regulating output current with that kind of speed.
A local input bypass capacitor is required to make up the
difference and prevent the input supply from dropping
drastically when QT kicks on. This capacitor is usually
chosen for RMS ripple current capability and ESR as well
as value.
Tantalum capacitors are a popular choice as input capaci-
tors for LTC1703 applications, but they deserve a special
caution here. Generic tantalum capacitors have a destruc-
tive failure mechanism when they are subjected to large
RMS currents (like those seen at the input of a LTC1703).
The input bypass capacitor in an LTC1703 circuit is
common to both channels. Consider our 10A example
casewiththeothersideoftheLTC1703disabled.Theinput
bypass capacitor gets exercised in three ways: its ESR
must be low enough to keep the initial drop as QT turns on
within reason (100mV or so); its RMS current capability
must be adequate to withstand the 4.7ARMS ripple current
at the input and the capacitance must be large enough to
maintain the input voltage until the input supply can make
up the difference. Generally, a capacitor that meets the
first two parameters will have far more capacitance than is
required to keep capacitance-based droop under control.
Inourexample, weneed0.01ΩESRtokeeptheinputdrop
under 100mV with a 10A current step and 4.7ARMS ripple
current capacity to avoid overheating the capacitor. These
requirements can be met with multiple low ESR tantalum
or electrolytic capacitors in parallel, or with a large mono-
lithic ceramic capacitor.
32%
10A
QT CURRENT, SIDE 1 ONLY
(FOR 1-PHASE, 2 SIDES:
MULTIPLY CURRENT BY 2)
68%
68%
0
32%
6.8A
CURRENT IN C , SIDE 1 ONLY
IN
I
= 4.66A
, (1-PHASE,
CIN
RMS
2 SIDES: I = 9.3A
CIN RMS
)
0
–3.2A
32% 18% 32% 18%
32% 18% 32% 18%
10A
0
QT1 CURRENT
QT2 CURRENT
BOTH SIDES EQUAL LOAD
2-PHASE OPERATION
3.6A
0
CURRENT IN C
IN
,
BOTH SIDES EQUAL LOAD
I
= 4.8A
CIN
RMS
1703 F07
–6.4A
Figure 7. Current Waveforms
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U
At some random time after they are turned on, they can
blow up for no apparent reason. The capacitor manufac-
turers are aware of this and sell special “surge tested”
tantalum capacitors specifically designed for use with
switching regulators. When choosing a tantalum input
capacitor, make sure that it is rated to carry the RMS
current that the LTC1703 will draw. If the data sheet
doesn’t give an RMS current rating, chances are the
capacitor isn’t surge tested. Don’t use it!
Calculating RMS Current in CIN
A buck regulator like the LTC1703 draws pulses of
current from the input capacitor during normal opera-
tion. The input capacitor sees this as AC current, and
dissipates power proportional to the RMS value of the
input current waveform. To properly specify the capaci-
tor, we need to know the RMS value of the input current.
Calculating the approximate RMS value of a pulse train
withafixeddutycycleis straightforward,buttheLTC1703
complicatesmattersbyrunningtwosidessimultaneously
and out of phase, creating a complex waveform at the
input.
OUTPUT BYPASS CAPACITOR
The output bypass capacitor has quite different require-
ments from the input capacitor. The ripple current at the
output of a buck regulator like the LTC1703 is much lower
than at the input, due to the fact that the inductor current
is constantly flowing at the output whenever the LTC1703
is operating in continuous mode. The primary concern at
the output is capacitor ESR. Fast load current transitions
at the output will appear as voltage across the ESR of the
output bypass capacitor until the feedback loop in the
LTC1703 can change the inductor current to match the
newloadcurrentvalue. ThisESRstepattheoutputisoften
the single largest budget item in the load regulation
calculation. As an example, our hypothetical 1.6V, 10A
switcher with a 0.01Ω ESR output capacitor would expe-
rience a 100mV step at the output with a 0 to 10A load
step—a 6.3% output change!
To calculate the approximate RMS value of the input
current, we first need to calculate the average DC value
with both sides of the LTC1703 operating at maximum
load. Over a single period, the system will spend some
time with one top switch on and the other off, perhaps
some time with both switches on, and perhaps some
time with both switches off. During the time each top
switch is on, the current will equal that side’s full load
output current. When both switches are on, the total
current will be the sum of the two full load currents, and
when both are off, the current is effectively zero. Multiply
each current value by the percentage of the period that
the current condition lasts, and sum the results—this is
the average DC current value.
As an example, consider a circuit that takes a 5V input
and generates 3.3V at 3A at side 1 and 1.6V at 10A at
side 2. When a cycle starts, TG1 turns on and 3A flows
Usually the solution is to parallel several capacitors at the
output. For example, to keep the transient response inside
of 3% with the previous design, we’d need an output ESR
better than 0.0048Ω. This can be met with three 0.014Ω,
470µF tantalum capacitors in parallel.
50%
16% 16% 18%
13
10
INDUCTOR
The inductor in a typical LTC1703 circuit is chosen prima-
rily for value and saturation current. The inductor value
sets the ripple current, which is commonly chosen at
around 40% of the anticipated full load current. Ripple
current is set by:
5.2
3
I
AVE
0
0
A
B
C
D
TIME
tON(QB)
V
OUT
(
)
1703 SB1
IRIPPLE
=
L
Figure SB1. Average Current Calculation
1703fa
19
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APPLICATIO S I FOR ATIO
from CIN (time point A). 50% of the way through, TG2
turns on and the total current is 13A (time point B).
Shortly thereafter, TG1 turns off and the current drops to
10A (time point C). Finally, TG2 turns off and the current
spends a short time at 0 before TG1 turns on again (time
point D).
current and resistive losses, but this approximate value is
adequate for input capacitor calculation purposes.
–2.182 • 0.5 + 7.822 • 0.16 +
(
(
) (
)
IRMS
=
4.822 • 0.16 + –5.182 • 0.18
) (
)
IAVG = 3A • 0.5 + 13A • 0.16 +
= 4.55ARMS
(
) (
)
10A • 0.16 + 0A • 0.18 = 5.18A
Ifthecircuitislikelytospendtimewithonesideoperating
and the other side shut down, the RMS current will need
to be calculated for each possible case (side 1 on, side 2
off; side 1 off, side 2 on; both sides on). The capacitor
must be sized to withstand the largest RMS current of the
three—sometimes this occurs with one side shut down!
(
) (
)
Now we can calculate the RMS current. Using the same
waveform we used to calculate the average DC current,
subtract the average current from each of the DC values.
Square each current term and multiply the squares by the
same period percentages we used to calculate the aver-
age DC current. Sum the results and take the square root.
The result is the approximate RMS current as seen by the
inputcapacitorwithbothsidesoftheLTC1703atfullload.
Actual RMS current will differ due to inductor ripple
Side1only:
IAVE1 = 3A • 0.67 + 0A • 0.33 = 2.01A
(
) (
)
2
IRMS1
=
1 • 0.67 + –22 • 0.33 = 1.42ARMS
(
) (
)
50%
16% 16% 18%
Side 2 only:
7.8
4.8
IAVE2 = 10A • 0.32 + 0A • 0.68 = 3.2A
(
) (
)
IRMS2
=
6.82 • 0.32 + –3.22 • 0.68
(
) (
)
0
= 4.66ARMS > 4.55ARMS
–2.2
C
onsider the case where both sides are operating at the
–5.2
same load, with a 50% duty cycle at each side. The RMS
current with both sides running is near zero, while the
RMS current with one side active is 1/2 the total load
current of that side.
0
A
B
TIME
C
D
1703 SB2
Figure SB2. AC Current Calculation
In our hypothetical 1.6V, 10A example, we'd set the ripple
current to 40% of 10A or 4A, and the inductor value would
be:
The inductor must not saturate at the expected peak
current. In this case, if the current limit was set to 15A, the
inductor should be rated to withstand 15A + 1/2 IRIPPLE
or 17A without saturating.
,
tON(QB)
V
1.2µs 1.6V
(
)
(
)(
)
= 0.64µH
OUT
L =
=
IRIPPLE
3A
1.6V
5V
⎛
⎝
⎞
⎟
⎠
with tON(QB) = 1−
/550kHz = 1.2µs
⎜
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FEEDBACK LOOP/COMPENSATION1
Feedback Loop Types
chosen based on the regulation and load current require-
ments without considering the AC loop response. The
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and some-
thing less than 360° phase shift at the point that the loop
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 9). This “type 1”
configuration is stable but transient response will be less
than exceptional if the LC pole is at a low frequency.
In a typical LTC1703 circuit, the feedback loop consists of
the modulator, the external inductor and output capacitor,
and the feedback amplifier and its compensation network.
All of these components affect loop behavior and need to
beaccountedforintheloopcompensation.Themodulator
consistsoftheinternalPWMgenerator,theoutputMOSFET
drivers and the external MOSFETs themselves. From a
feedback loop point of view, it looks like a linear voltage
transferfunctionfromCOMPtoSWandhasagainroughly
equal to the input voltage. It has fairly benign AC behavior
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency.
C1
R1
–
+
IN
OUT
R
B
Theexternalinductor/outputcapacitorcombinationmakes
a more significant contribution to loop behavior. These
componentscauseasecondorderLCroll-offattheoutput,
with the attendant 180° phase shift. This roll-off is what
filters the PWM waveform, resulting in the desired DC
output voltage, but the phase shift complicates the loop
compensationifthegainisstillhigherthanunityatthepole
frequency. Eventually (usually well above the LC pole
frequency), the reactance of the output capacitor will
approach its ESR, and the roll-off due to the capacitor will
stop, leaving 6dB/octave and 90° of phase shift (Figure 8).
1703 F09a
V
REF
Figure 9a. Type 1 Amplifier Schematic Diagram
GAIN
(dB)
PHASE
(DEG)
GAIN
0
0
So far, the AC response of the loop is pretty well out of the
user’scontrol.Themodulatorisafundamentalpieceofthe
LTC1703 design, and the external L and C are usually
–6dB/OCT
–90
–180
GAIN
(dB)
PHASE
(DEG)
PHASE
–270
1703 F09b
GAIN
A
V
0
–12dB/OCT
Figure 9b. Type 1 Amplifier Transfer Function
0
Figure 10 shows an improved “type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of
phase shift. This allows the loop to remain stable with 90°
more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
Type 2 loops work well in systems where the ESR zero in
–90
PHASE
–180
–6dB/OCT
1703 F08
1The information in this section is based on the paper “The K Factor: A New Mathematical Tool for
Stability Analysis and Synthesis” by H. Dean Venable, Venable Industries, Inc. For complete paper,
see “Reference Reading #4” at www.linear-tech.com.
Figure 8. Transfer Function of Buck Modulator
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C2
C2
C3
R3
C1
R2
C1
R2
R1
R1
–
–
+
IN
IN
OUT
OUT
+
R
B
R
B
1703 F10a
V
REF
1703 F11a
V
REF
Figure 10a. Type 2 Amplifier Schematic Diagram
Figure 11a. Type 3 Amplifier Schematic Diagram
GAIN
(dB)
PHASE
(DEG)
GAIN
(dB)
PHASE
(DEG)
–6dB/OCT
–6dB/OCT
+6dB/OCT
–6dB/OCT
GAIN
GAIN
0
0
0
0
–6dB/OCT
–90
–180
–90
–180
PHASE
PHASE
–270
–270
1703 F11b
1703 F10b
Figure 10b. Type 2 Amplifier Transfer Function
Figure 11b. Type 3 Amplifier Transfer Function
the LC roll-off happens close to the LC pole, limiting the
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
for an extended frequency range. LTC1703 circuits using
conventional switching grade electrolytic output capaci-
tors can often get acceptable phase margin with type 2
compensation.
need type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
Feedback Component Selection
Selecting the R and C values for a typical type 2 or type 3
loopisanontrivialtask.Theapplicationsshowninthisdata
sheet show typical values, optimized for the power com-
ponentsshown.Theyshouldgiveacceptableperformance
with similar power components, but can be way off if even
one major power component is changed significantly.
Applicationsthatrequireoptimizedtransientresponsewill
need to recalculate the compensation values specifically
forthecircuitinquestion.Theunderlyingmathematicsare
complex, but the component values can be calculated in a
straightforward manner if we know the gain and phase of
the modulator at the crossover frequency.
“Type 3” loops (Figure 11) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
wellabovetheinitialLCroll-off. Aswithatype2circuit, the
loop should cross through 0dB in the middle of the phase
bump to maximize phase margin. Many LTC1703 circuits
using low ESR tantalum or OS-CON output capacitors
Modulator gain and phase can be measured directly from
a breadboard, or can be simulated if the appropriate
parasitic values are known. Measurement will give more
1703fa
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U
accurateresults,butsimulationcanoftengetcloseenough V(OUT) in degrees. Refer to your SPICE manual for details
to give a working system. To measure the modulator gain of how to generate this plot.
and phase directly, wire up a breadboard with an LTC1703
*1703 modulator gain/phase
©
and the actual MOSFETs, inductor, and input and output
* 1999 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other SPICE
simulators
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
*MOSFETs
the LTC1703, no long wires connecting components,
rfet mod sw 0.02
;MOSFET rdson
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple type 1 loop, with a 10k resistor from
*inductor
lext sw out1 1u
rl out1 out 0.005
;inductor value
;inductor series R
V
OUT to FB and a 0.1µF feedback capacitor from COMP to
FB. Choose the bias resistor (RB) as required to set the
desired output voltage. Disconnect RB from ground and
connect it to a signal generator or to the source output of
anetworkanalyzer(Figure12)toinjectatestsignalintothe
loop. Measure the gain and phase from the COMP pin to
the output node at the positive terminal of the output
capacitor. Make sure the analyzer’s input is AC coupled so
that the DC voltages present at both the COMP and VOUT
nodes don’t corrupt the measurements or damage the
analyzer.
*output cap
cout out out2 1000u ;capacitor value
resr out2 0 0.01
;capacitor ESR
*1703 internals
emod mod 0 laplace {v(comp)} =
+ {5*exp(–s*909e–9)} ;5 -> 3.3 for 3.3 VCC
*emod mod 0 comp 0 5 ;use if above lines fail
vstim comp 0 0 ac 1 ;ac stimulus
.ac dec 100 1k 1meg
.probe
.end
5V
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 8. Choose the crossover frequency in the rising
or flat parts of the phase curve, beyond the external LC
poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be –GAIN to make the loop gain 0dB at this
frequency.Nowcalculatetheneededphaseboost,assum-
ing 60° as a target phase margin:
+
10Ω
C
IN
MBR0530T
+
10µF
V
PV
CC
CC
BOOST2
1µF
L
QT
QB
TG
EXT
V
V
1/2 LTC1703
COMP
TO
OUT
TO
COMP
SW
0.1µF
ANALYZER
ANALYZER
+
FB
BG
C
OUT
NC
RUN/SS
FCB
R
B
10k
FAULT
PGND
AC
SOURCE
FROM
SGND
BOOST = –(PHASE + 30°)
ANALYZER
1703 F12
If the required BOOST is less than 60°, a type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require type 3
loops for satisfactory performance.
Figure 12. Modulator Gain/Phase Measurement Set-Up
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and gener-
ate an AC plot of V(VOUT)/V(COMP) in dB and phase of
Finally, choose a convenient resistor value for R1 (10k is
usuallyagoodvalue).Notethatchannel1includesR1and
RB internally as part of the VID DAC circuitry. R1 is fixed
at 10kΩ and RB varies depending on the VID code
selected.
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Now calculate the remaining values:
(K is a constant used in the calculations)
ƒ = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in absolute
gain)
CURRENT LIMIT PROGRAMMING
ProgrammingthecurrentlimitontheLTC1703isstraight-
forward. The IMAX pin sets the current limit by setting the
maximum allowable voltage drop across QB (the bottom
MOSFET) before the current limit circuit engages. The
voltage across QB is set by its on-resistance and the
current flowing in the inductor, which is the same as the
output current. The LTC1703 current limit circuit inverts
the voltage at IMAX before comparing it with the negative
voltage across QB, allowing the current limit to be set with
a positive voltage.
Type 2 Loop:
⎛
⎞
BOOST
2
1
K = Tan
+ 45°
⎜
⎟
⎝
⎠
To set the current limit, calculate the expected voltage
drop across QB at the maximum desired current:
C2 =
2πƒGKR1
C1= C2 K2 – 1
V
PROG = (IILIM)(RDS(ON)) + CF
(
)
ILIM should be chosen to be quite a bit higher than the
expected operating current, to allow for MOSFET RDS(ON)
changes with temperature. Setting ILIM to 150% of the
maximumnormaloperatingcurrentisusuallysafeandwill
adequately protect the power components if they are
chosenproperly.TheCFtermisanapproximatefactorthat
corrects for errors caused by ringing on the switch node
(illustrated in Figure 6). This correction factor will change
depending on the layout and the components used, but
100mV is usually a good starting point. However, to
provide adequate margin and to accommodate for offsets
and external variations, it is recommended that VPROG be
calculated with CF = 100 ± 50mV. VPROG is then pro-
grammed at the IMAX pin using the internal 10µA pull-up
and an external resistor:
K
R2 =
RB =
2πƒC1
VREF R1
( )
VOUT – VREF
Type 3 Loop:
⎛
⎞
BOOST
4
K = Tan2
+ 45°
⎜
⎟
⎝
⎠
1
C2 =
2πƒGR1
C1= C2 K – 1
(
)
RILIM = VPROG/10µA
K
TheresultingvalueofRILIM shouldbecheckedinanactual
circuit to ensure that the ILIM circuit kicks in as expected.
MOSFET RDS(ON) specs are like horsepower ratings in
automobiles, and should be taken with a grain of salt.
Circuits that use very low values for RIMAX (<20k) should
be checked carefully, since small changes in RIMAX can
cause large ILIM changes when the 100mV correction
factor makes up a large percentage of the total VPROG
value. If VPROG is set too low, the LTC1703 may fail to
start up.
R2 =
R3 =
2πƒC1
R1
K – 1
(
)
1
C3 =
RB =
2πƒ K R3
VREF R1
( )
V
OUT – VREF
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Accuracy Trade-Offs
drops, the FCB pin will trip and the LTC1703 will resume
continuous operation regardless of the load on the main
output. The FCB pin removes the requirement that power
must be drawn from the inductor primary in order to
extractpowerfromtheauxiliarywindings. Withtheloopin
continuous mode, the auxiliary outputs may be loaded
withoutregardtotheprimaryload.NotethatiftheLTC1703
is already running in continuous mode and the auxiliary
output drops due to excessive loading, no additional
action can be taken by the LTC1703 to regulate the
auxiliary output.
The VDS sensing scheme used in the LTC1703 is not
particularly accurate, primarily due to uncertainty in the
R
DS(ON) from MOSFET to MOSFET. A second error term
arises from the ringing present at the SW pin, which
causes the VDS to look larger than (ILOAD)(RDS(ON)) at the
beginning of QB’s on-time. These inaccuracies do not
prevent the LTC1703 current limit circuit from protecting
itself and the load from damaging overcurrent conditions,
but they do prevent the user from setting the current limit
to a tight tolerance if more than one copy of the circuit is
being built. The 50% factor in the current setting equation
above reflects the margin necessary to ensure that the
circuitwillstayoutofcurrentlimitatthemaximumnormal
load, even with a hot MOSFET that is running quite a bit
higher than its RDS(ON) spec.
V
IN
V
OUT(AUX)
+
C
IN
+
+
C
C
QT
TG
LTC1703
BG
OUT(AUX)
V
OUT
QB
FCB
OUT
FCB OPERATION/SECONDARY WINDINGS
R
R
FCB1
The FCB pin can be used in conjunction with a secondary
winding on one side of the LTC1703 to generate a third
regulated voltage output. This output can be directly
regulated at the FCB pin. In theory, a fourth output could
be added, either unregulated or with additional external
circuitry at the FCB pin.
FCB2
1703 F13
Figure 13. Regulating an Auxiliary Output with the FCB Pin
FAULT FLAG
The extra auxiliary output is taken from a second winding
on the core of the inductor on one channel, converting it
intoatransformer(Figure13).Theauxiliaryoutputvoltage
is set by the main output voltage and the turns ratio of the
extra winding to the primary winding. Load regulation at
the auxiliary output will be relatively good as long as the
mainoutputisrunningincontinuousmode. Astheloadon
the main channel drops and the LTC1703 switches to
discontinuous or Burst Mode operation, the auxiliary
output will not be able to maintain regulation, especially if
the load at the auxiliary output remains heavy.
TheFAULTpinisanopen-drainoutputthatindicatesifone
or both of the outputs has exceeded 15% of its pro-
grammed output voltage. FAULT includes an internal
10µA pull-up to VCC and does not require an external pull-
up to interface to standard logic. FAULT pulls low in
normal operation, and releases when a overvoltage fault is
detected.
When an overvoltage fault occurs, an internal latch sets
and FAULT goes high, disabling the LTC1703 until the
latch is cleared by recycling the power or pulling both
RUN/SS pins low simultaneously. Alternately, the FAULT
pin can be pulled back low externally with an open-
collector/open-drain device or an N-channel MOSFET or
NPN, which will allow the LTC1703 to resume normal
operation, but will not reset the latch. If the pull-down is
later removed, the LTC1703 will latch off again unless the
latch is reset by cycling the power or RUN/SS pins.
To avoid this, the auxiliary output voltage is divided down
with a conventional feedback resistor string with the
divided auxiliary output voltage fed back to the FCB pin
(Figure 13). The FCB pin threshold is trimmed to 800mV
with 20mV of hysteresis, allowing fairly precise control of
the auxiliary voltage. If the LTC1703 is in discontinuous or
Burst Mode operation and the auxiliary output voltage
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OPTIMIZING PERFORMANCE
2-Step Conversion
Clearly, the 5V and 3.3V sections of the two schemes are
equivalent. The 2-step system draws additional power
from the 5V and 3.3V outputs, but the regulation tech-
niques and trade-offs at these outputs are similar. The
difference lies in the way the 1.5V and 1.3V supplies are
generated. For example, the 2-step system converts 3.3V
to 1.3V with a 39% duty cycle. During the QT on-time, the
voltage across the inductor is 2V and during the QB
on-time, the voltage is 1.3V, giving roughly symmetrical
transientresponsetopositiveandnegativeloadsteps.The
2Vmaximumvoltageacrosstheinductorallowstheuseof
a small 0.47µH inductor while keeping ripple current
under 4A (40% of the 10A maximum load). By contrast,
the 1-step converter is converting 15V to 1.3V, requiring
just a 9% duty cycle. Inductor voltages are now 13.7V
when QT is on and 1.3V when QB is on, giving vastly
different di/dt values and correspondingly skewed tran-
sient response with positive and negative current steps.
Thenarrow9%dutycycleusuallyrequiresalowerswitch-
ing frequency, which in turn requires a higher value
inductor and larger output capacitor. Parasitic losses due
to the large voltage swing at the source of QT cost
efficiency, eliminating any advantage the 1-step conver-
sion might have had.
The LTC1703 is ideally suited for use in 2-step conversion
systems. 2-step systems use a primary regulator to con-
vert the input power source (batteries or AC line voltage)
to an intermediate supply voltage, often 5V. The LTC1703
then converts the intermediate voltage to the low voltage,
high current supplies required by the system. Compared
to a 1-step converter that converts a high input voltage
directly to a very low output voltage, the 2-step converter
exhibits superior transient response, smaller component
size and equivalent efficiency. Thermal management and
layout complexity are also improved with a 2-step
approach.
A typical notebook computer supply might use a 4-cell
Li-Ion battery pack as an input supply with a 15V nominal
terminal voltage. The logic circuits require 5V/3A and
3.3V/5A to power system board logic, and 2.5V/0.5A,
1.5V/2A and 1.3V/10A to power the CPU. A typical 2-step
conversion system would use a step-down switcher (per-
haps an LTC1628 or two LTC1625s) to convert 15V to 5V
and another to convert 15V to 3.3V (Figure 14). One
channel of the LTC1703 would generate the 1.3V supply
using the 3.3V supply as the input and the other channel
would generate 1.5V using the 5V supply as the input. The
corresponding1-stepsystemwouldusefoursimilarstep-
down switchers, each using 15V as the input supply and
generating one of the four output voltages. Since the 2.5V
supply represents a small fraction of the total output
power, either system can generate it from the 3.3V output
using an LDO linear regulator, without the 75% linear
efficiency making much of an impact on total system
efficiency.
Note that power dissipation in the LTC1703 portion of a
2-step circuit is lower than it would be in a typical 1-step
converter, even in cases where the 1-step converter has
higher total efficiency than the 2-step system. In a typical
microprocessor core supply regulator, for example, the
regulator is usually located right next to the CPU. In a
1-step design, all of the power dissipated by the core
regulator is right there next to the hot CPU, aggravating
thermal management. In a 2-step LTC1703 design, a
significant percentage of the power lost in the core regu-
lation system happens in the 5V or 3.3V supply, which is
usually away from the CPU. The power lost to heat in the
LTC1703 section of the system is relatively low, minimiz-
ing the heat near the CPU.
V
BAT
15V
5V/3A
1.5V/2A
1.3V/10A
LTC1628*
LTC1703
LDO
2-Step Efficiency Calculation
3.3V/5A
Calculating the efficiency of a 2-step converter system
involves some subtleties. Simply multiplying the effi-
ciency of the primary 5V or 3.3V supply by the efficiency
2.5V/0.5A
*OR TWO LTC1625s
1703 F14
of the 1.5V or 1.3V supply underestimates the actual
Figure 14. 2-Step Conversion Block Diagram
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efficiency, since a significant fraction of the total power is
drawn from the 3.3V and 5V rails in a typical system. The
correct way to calculate system efficiency is to calculate
the power lost in each stage of the converter, and divide
the total output power from all outputs by the sum of the
output power plus the power lost:
The behavior of the load over time affects the efficiency
strategy. Parasitic resistances in the MOSFETs and the
inductor set the maximum output current the circuit can
supply without burning up. A typical efficiency curve
(Figure 15) shows that peak efficiency occurs near 30% of
this maximum current. If the load current will vary around
theefficiencypeakandwillspendrelativelylittletimeatthe
maximumload, choosingcomponentssothattheaverage
load is at the efficiency peak is a good idea. This puts the
maximum load well beyond the efficiency peak, but usu-
ally gives the greatest system efficiency over time, which
translates to the longest run time in a battery-powered
system. If the load is expected to be relatively constant at
the maximum level, the components should be chosen so
that this load lands at the peak efficiency point, well below
the maximum possible output of the converter.
Efficiency =
TotalOutputPower
TotalOutputPower+ TotalPowerLost
100%
(
)
In our example 2-step system, the total output power is:
Total output power =
15W + 16.5W + 1.25W + 3W + 13W = 48.75W
corresponding to 5V, 3.3V, 2.5V, 1.5V and 1.3V output
voltages.
Assuming the LTC1703 provides 90% efficiency at each
output, the additional load on the 5V and 3.3V supplies is:
100
V
IN
= 5V
V
= 3.3V
OUT
1.3V: 13W/90% = 14.4W/3.3V = 4.4A from 3.3V
1.5V: 3W/90% = 3.3W/5V = 0.67A from 5V
2.5V: 1.25W/75% = 1.66W/3.3V = 0.5A from 3.3V
V
V
= 2.5V
= 1.6V
OUT
OUT
90
80
70
If the 5V and 3.3V supplies are each 94% efficient, the
power lost in each supply is:
1.3V: 14.4W – 13W = 1.4W
1.5V: 3.3W – 3W = 0.3W
2.5V: 1.66W – 1.25W = 0.4W
3.3V: 16.5W + 3.3V (4.4A + 0.5A) = 32.67W load
(32.67W/94%) – 32.67W = 2.09W lost
5V: 15W + 5V (0.67A) = 18.4W load
(18.4W/94%) – 18.4W = 1.17W lost
0
5
10
15
LOAD CURRENT (A)
1703 G01
Figure 15. Typical LTC1703 Efficiency Curves
Total loss = 5.36W
Maximizing Low Load Current Efficiency
Total system efficiency =
48.75W/(48.75W + 5.36W) = 90.1%
Low load current efficiency depends strongly on proper
operation in discontinuous and Burst Mode operations. In
anideallyoptimizedsystem, discontinuousmodereduces
conduction losses but not switching losses, since each
power MOSFET still switches on and off once per cycle. In
a typical system, there is additional loss in discontinuous
mode due to a small amount of residual current left in the
inductor when QB turns off. This current gets dissipated
across the body diode of either QT or QB. Some LTC1703
systems lose as much to body diode conduction as they
save in MOSFET conduction. The real efficiency benefit of
Maximizing High Load Current Efficiency
Efficiency at high load currents (when the LTC1703 is
operating in continuous mode) is primarily controlled by
the resistance of the components in the power path
(QT, QB, LEXT) and power lost in the gate drive circuits due
to MOSFET gate charge. Maximizing efficiency in this
region of operation is as simple as minimizing these
terms.
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discontinuousmodehappenswhenBurstModeoperation
is invoked. At typical power levels, when Burst Mode
operation is activated, gate drive is the dominant loss
term. Burst Mode operation turns off all output switching
for several clock cycles in a row, significantly cutting gate
drive losses. As the load current in Burst Mode operation
falls toward zero, the current drawn by the circuit falls to
the LTC1703’s background quiescent level—about 3mA
per channel.
thatofallerrorsduetotheLTC1703combined.Using0.1%
resistorsinjustthosetwopositionscannearlyhalvetheDC
output error for very little additional cost. Side 1 uses the
internal VID network to set the output voltage, and is
specified to be within ±1.5% of the values shown in
Table 1.
Load Regulation
Load regulation is affected by feedback voltage, feedback
amplifier gain and external ground drops in the feedback
path. Feedback voltage is covered above and is within 1%
over temperature. A full-range load step might require a
10% duty cycle change to keep the output constant,
requiring the COMP pin to move about 100mV. With
amplifier gain at 85dB, this adds up to only a 10µV shift at
FB, negligible compared to the reference accuracy terms.
To maximize low load efficiency, make sure the LTC1703
is allowed to enter discontinuous and Burst Mode opera-
tion as cleanly as possible. FCB must be above its 0.8V
threshold. Minimize ringing at the SW node so that the
discontinuous comparator leaves as little residual current
in the inductor as possible when QB turns off. It helps to
connect the SW pin of the LTC1703 as close to the drain
of QB as possible. An RC snubber network can also be
added from SW to PGND.
External ground drops aren’t so negligible. The LTC1703
can sense the positive end of the output voltage by
attaching the feedback resistor directly at the load, but it
cannot do the same with the ground lead. Just 0.001Ω of
resistanceinthegroundleadat10Aloadwillcausea10mV
error in the output voltage—as much as all the other DC
errors put together. Proper layout becomes essential to
achieving optimum load regulation from the LTC1703. A
properly laid out LTC1703 circuit should move less than a
millivolt at the output from zero to full load.
REGULATION OVER COMPONENT TOLERANCE/
TEMPERATURE
DC Regulation Accuracy
The LTC1703 initial DC output accuracy depends mainly
on internal reference accuracy, op amp offset and external
resistor accuracy (side 2 only). Two LTC1703 specs come
into play: feedback voltage and feedback voltage line
regulation. The feedback voltage spec is 800mV ± 8mV
over the full temperature range, and is specified at the FB
pin, which encompasses both reference accuracy and any
op amp offset. This accounts for 1% error at the output
with a 5V input supply. The feedback voltage line regula-
tion spec adds an additional 0.05%/V term that accounts
for change in reference output with change in input supply
voltage. With a 5V supply, the errors contributed by the
LTC1703itselfadduptonomorethan1.5%DCerroratthe
output.
TRANSIENT RESPONSE
Transient response is the other half of the regulation
equation. The LTC1703 can keep the DC output voltage
constant to within 1% when averaged over hundreds of
cycles. Over just a few cycles, however, the external
components conspire to limit the speed that the output
can move. Consider our typical 5V to 1.5V circuit, sub-
jected to a 1A to 5A load transient. Initially, the loop is in
regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A start flowing out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A)(CESR)voltage step at
the output; with a typical 0.015Ω output capacitor ESR,
this is a 60mV step at the output, or 4% (for a 1.5V output
voltage).
At side 2, the output voltage setting resistors (R1 and RB
in Figure 3) are the other major contributor to DC error. At
a typical 1.xV output voltage, the resistors are of roughly
the same value, which tends to halve their error terms,
improving accuracy. Still, using 1% resistors for R1 and
RB will add 1% to the total output error budget, equal to
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Very quickly, the feedback loop will realize that something
has changed and will move at the bandwidth allowed by
the external compensation network towards a new duty
cycle. If the bandwidth is set to 50kHz, the COMP pin will
get to 60% of the way to 90% duty cycle in 3µs. Now the
inductor is seeing 3.5V across itself for a large portion of
the cycle, and its current will increase from 1A at a rate set
by di/dt = V/L. If the inductor value is 0.5µH, the di/dt will
be 3.5V/0.5µH or 7A/µs. Sometime in the next few micro-
secondsaftertheswitchcyclebegins,theinductorcurrent
will have risen to the 5A level of the load current and the
output capacitor will stop losing charge.
entirely into the capacitor, going through the ESR as it
does so (Figure 16). Positive di/dt in the inductor causes
positive dv/dt in the ESR, regardless of what the “pure”
capacitance is doing. The output voltage will turn around
when the positive dv/dt across the ESR exceeds the
negativedv/dtacrossthepurecapacitance.Iftheexpected
load step (∆I) is known, an optimum inductor value can be
chosen:
ESR
∆I
L ≤ V – VOUT •C •
IN
MakingLsmallerthanthisoptimumvalueyieldslittleorno
improvement in transient response. As the output voltage
recovers, the inductor current will briefly rise above the
leveloftheoutputcurrenttoreplenishthechargelostfrom
the output capacitor. With a properly compensated loop,
the entire recovery time will be inside of 10µs.
Note that the output voltage will stop dropping before the
inductor current reaches this new output current level.
Recall that any practical output capacitor looks like a pure
capacitance in series with some amount of ESR. When a
load transient hits, virtually all of the initial voltage drop at
the output is due to IR drop across the ESR. The output
capacitance begins to discharge at the same time and
continuesuntiltheinductorcurrentrisestomatchthenew
output current level.
Most loads care only about the maximum deviation from
ideal, whichoccurssomewhereinthefirsttwocyclesafter
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirelycontrolledbytheESRofthecapacitorandamounts
to most of the total voltage drop. To minimize this drop,
reduce the ESR as much as possible by choosing low ESR
The output voltage, however, will turn around and start
heading the right way before this happens. The next time
the top MOSFET turns on, the inductor current will begin
increasing linearly. This increasing current flows almost
I
L
I
OUT
I
L
I
OUT
V
ESR
V
ESR
V
CAP
V
V
CAP
I
L
OUT
V
V
SW
OUT
V
OUT
L
V
OUT(NOMINAL)
+
V
ESR
–
C
OUT
I
OUT
+
V
CAP
1703 F16b
–
TRANSIENT
HITS
V
I
L
> I
OUT
TIME
1703 F16a
OUT
TURNS
AROUND
Figure 16a. Capacitor Parasitics
Affecting Transient Recovery
Figure 16b. Transient Recovery Curves
1703fa
29
LTC1703
W U U
U
APPLICATIO S I FOR ATIO
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
goal is to intentionally compromise the DC regulation loop
such that the output rides near the maximum allowable
value (often +5%) with no load and near the minimum
allowable value at maximum load. With the load at zero,
any transient that comes along will be a current increase
whichwillcausetheoutputvoltagetofall. Sincetheoutput
voltage is initially at a high value, it can fall further before
itgoesoutofspec.Similarly,atfullload,theoutputcurrent
can only decrease, causing a positive shift in the output
voltage; the initial low value allows it to rise further before
the spec is exceeded. The primary benefit of voltage
positioning is it increases the allowable ESR of the output
capacitors, saving cost. An additional bonus is that at
maximum load, the output voltage is near the minimum
allowable, decreasing the power dissipated in the load.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC1703 to
recoveraftertheoutputvoltagehasdroppedduetooutput
capacitor ESR. Optimizing loop compensation entails
maintaining the highest possible loop bandwidth while
ensuring loop stability. The Feedback Component Selec-
tionsectiondescribesindetailhowtodesignanoptimized
feedback loop, appropriate for most LTC1703 systems.
Implementing voltage positioning is as simple as creating
an intentional resistance in the output path to generate the
required voltage drop. This resistance can be a low value
resistor, a length of PCB trace, or even the parasitic
resistance of the inductor if an appropriate filter is used. If
theLTC1703sensestheoutputvoltageupstreamfromthe
resistance (Figure 17c), the output voltage will move with
load as I • RVP, where I is the load current and RVP is the
value of the voltage positioning resistor. If the feedback
networkisthenresettoregulateneartheupperedgeofthe
Voltage Positioning
If the load transients consist primarily of load steps from
near zero load to full load and back, the transient response
can be traded off against DC regulation performance by
using a technique known as “voltage positioning.” The
V
IN
MAXIMUM
+5%
NOM
–5%
ALLOWABLE
V
OUT
TRANSIENT
LTC1703
FB
V
OUT
MAX
0
LOAD
CURRENT
1703 F17a
1703 F17b
Figure 17a. Standard Regulator
Figure 17b. Standard Regulator—Transient Response
V
IN
+5%
NOM
–5%
MAXIMUM
ALLOWABLE
TRANSIENT
V
OUT
R
VP
≈2× FIGURE 17b
LTC1703
FB
V
OUT
MAX
0
LOAD
CURRENT
1703 F17c
1703 F17d
Figure 17c. Voltage Positioning Regulator
Figure 17d. Positioning Regulator—Transient Response
1703fa
30
LTC1703
W U U
APPLICATIO S I FOR ATIO
U
specified tolerance, the output voltage will ride high when
ILOAD islowandwillridelowwhenILOAD ishigh.Compared
to a traditional regulator, a voltage positioning regulator
can theoretically stand as much as twice the ESR drop
across the output capacitor while maintaining output
voltage regulation. This means smaller, cheaper output
capacitors can be used while keeping the output voltage
within acceptable limits.
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC1703
circuits. SoldertheMOSFETandtheresistor(s)ascloseto
the output of the LTC1703 circuit as possible and set up
thesignalgeneratortopulseata100Hzratewitha5%duty
cycle. This pulses the LTC1703 with 500µs transients
10ms apart, adequate for viewing the entire transient
recovery time for both positive and negative transitions
while keeping the load resistor cool.
Measurement Techniques
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and gener-
ating a suitable transient to use to test the circuit. Output
measurements should be taken with a scope probe
directly across the output capacitor. Proper high fre-
quency probing techniques should be used. In particular,
don’t use the 6" ground lead that comes with the probe!
Use an adapter that fits on the tip of the probe and has a
short ground clip to ensure that inductance in the ground
path doesn’t cause a bigger spike than the transient signal
beingmeasured.Conveniently,thetypicalprobetipground
clipisspacedjustrighttospantheleadsofatypicaloutput
capacitor. Make sure the bandwidth limit on the scope is
turned off, since a significant portion of the transient
energy occurs above the 20MHz cutoff.
LTC1703
V
OUT
R
LOAD
LOCATE CLOSE
TO THE OUTPUT
IRFZ44 OR
EQUIVALENT
PULSE
GENERATOR
50Ω
1703 F18
0V TO 10V
100Hz, 5%
DUTY CYCLE
Figure 18. Transient Load Generator
Changing the Output Voltage on the Fly
Thevoltageatside1oftheLTC1703canbechangedonthe
fly by changing the VID code while the output is enabled,
but care must be taken to avoid tripping the overvoltage
faultcircuit.Steppingthevoltageupwardsabruptlyissafe,
butsteppingdownquicklybymorethan15%canleavethe
system in a state where the output voltage is still at the old
higher level, but the feedback node is set to expect a new,
substantially lower voltage. If this condition persists for
more than 10µs, the overvoltage fault circuitry will fire and
latch off the LTC1703.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test, and switch it on and off while
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC1703 and the transient generator
must be minimized.
The simplest solution is to disable the fault circuit by
grounding the FAULT pin. Systems that must keep the
fault circuit active should ensure that the output voltage is
never programmed to step down by more than 15% in any
single step. The safest strategy is to step the output down
by 10% or less at a time and wait for the output to settle
to the new value before taking subsequent steps.
Figure 18 shows an example of a simple transient genera-
tor. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
togetthedesiredvalue. Thisgivesanoninductiveresistive
1703fa
31
LTC1703
U
TYPICAL APPLICATIO S
1703fa
32
LTC1703
U
TYPICAL APPLICATIO S
1703fa
33
LTC1703
U
TYPICAL APPLICATIO S
Single Output, 2-Phase, 25A VID Converter
(V = 5V, V
= 0.9V to 2.0V)
IN
OUT
V
IN
5V ±10%
10Ω
0.1µF
10Ω
0.003Ω
0.5W
0.003Ω
0.5W
0.1µF
10k
–
+
LT®1006
470µF*
10k
+
+
0.1µF
470µF*
10µF
+
+
MBR0530T
470µF*
MBR
0530T
MBR0530T
V
CC
PV
CC
SENSE
330pF
330pF
11k
11k
BOOST1
FB1
L1
1µH
120pF
47k
1µF
1Ω
220pF
Q1
Q3
COMP1
TG1
V
OUT
SW1
1.3V TO 3.5V
25A
RUN/SS1
RUN/SS2
1Ω
0.1µF
MBR
330T
Q2
BG1
+
470µF*
× 2
LTC1703
BOOST2
TG2
FB2
20k
10k
120pF
47k
220pF
10k
1µF
L2
COMP2
SW2
Q4
Q6
1µH
BG2
I
I
MAX1
MAX2
FAULT
FAULT
VID4:0
22k
1Ω
1Ω
MBR
330T
Q5
VID4:0
FCB
PGND
SGND
1703 TA04
*KEMET T510X477M006AS
Q1 TO Q6: FAIRCHILD FDS6670A
L1, L2: MURATA LQT12535C1R5N12
1703fa
34
LTC1703
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
1.25 ±0.12
28 27 26 25 24 23 22 21 20 19 18
16 15
17
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
NOTE:
MIN
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
G28 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1703fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
35
LTC1703
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC1530
LTC1625
High Power Synchronous Step-Down Controller
No R
TM Current Mode Synchronous Step-Down Controller
SO-8 with Current Limit. No R
Required
SENSE
Above 95% Efficiency, Needs No R
Fits SO-8 Footprint
, 16-Lead SSOP Package
SENSE
SENSE
LTC1628
Dual High Efficiency 2-Phase Synchronous Step-Down Controller Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V ≤ V ≤ 36V
IN
LTC1702
Dual 550kHz Synchronous 2-Phase Switching Regulator Controller 550kHz, 25MHz GBW, No R
, V ≤ 7V
SENSE IN
LTC1706-81
VID Voltage Programmer
Adds 5-Bit VID to 0.8V Referenced Switching Regulators
for V Range of 1.3V to 3.5V
OUT
LTC1709
LTC1736
LTC1753
2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controller
Current Mode, V to 36V, I
Up to 42A
OUT
IN
Synchronous Step-Down Controller with 5-Bit Mobile VID Control Fault Protection, PowerGood, 3.5V to 36V Input, Current Mode
5-Bit Desktop VID Programmable Synchronous
Switching Regulator
1.3V to 3.5V Programmable Output Using Internal 5-Bit DAC
LTC1772
LTC1873
SOT-23 Step-Down Controller
550kHz, Up to 4A, 2.2V to 9.8V V , 100% Duty Cycle
IN
Dual 550kHz Synchronous 2-Phase Switching Regulator
Controller with VRM 8.4 5-Bit VID
5-Bit VID for 1.3V ≤ V ≤ 3.5V, V ≤ 7V
OUT IN
LTC1929
2-Phase, Synchronous High Efficiency Converter
Current Mode Ensures Accurate Current Sensing,
Up to 36V, I Up to 40A
V
IN
OUT
No R
is a trademark of Linear Technology Corporation.
SENSE
1703fa
LT 0306 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
© LINEAR TECHNOLOGY CORPORATION 1999
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