LTC1708-PG [Linear]
Dual Adjustable 5-Bit VID High Efficiency, 2-Phase Current Mode Synchronous Buck Regulator Controller; 可调式双5位VID高效率,两相电流模式同步降压稳压器控制器型号: | LTC1708-PG |
厂家: | Linear |
描述: | Dual Adjustable 5-Bit VID High Efficiency, 2-Phase Current Mode Synchronous Buck Regulator Controller |
文件: | 总32页 (文件大小:361K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Final Electrical Specifications
LTC1708-PG
Dual Adjustable 5-Bit VID
High Efficiency, 2-Phase Current Mode
Synchronous Buck Regulator Controller
February 2000
U
FEATURES
DESCRIPTIO
The LTC®1708 is a dual adjustable 5-bit VID program-
mablestep-downswitchingregulatorcontrollerthatdrives
all N-Channel power MOSFET stages. A constant fre-
quency current mode architecture allows adjustment of
the frequency up to 300kHz. Power loss and noise due to
the ESR of the input capacitance are minimized by oper-
ating the two main controller output stages out of phase.
■
Out-of-Phase Controllers Reduce Input Capacitance
and Power Supply Induced Noise
OPTI-LOOPTM Compensation Minimizes COUT
Power Good Output Monitors Both Outputs
5-Bit Mobile VID Control, VOUT: 0.9V to 2.0V
Dual N-Channel MOSFET Synchronous Drive
±1% Output Voltage Accuracy
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
DC Programmed Fixed Frequency 150kHz to 300kHz
Wide VIN Range: 3.5V to 36V Operation
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Soft-Start Current Ramping
Foldback Output Current Limiting
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The precision 0.8V reference is compat-
ible with future microprocessor generations, and a wide
3.5V to 30V (36V maximum) input supply range that
encompasses all battery chemistries. A power good out-
put indicates when the output voltages are within 7.5% of
their programmed value.
Latched Short-Circuit Shutdown with Defeat Option
Output Overvoltage Protection
Remote Output Voltage Sense
Low Shutdown Current: 20µA
A RUN/SS pin for each controller provides both soft-start
and an optional timed, short-circuit shutdown. Other
protection features include: internal foldback current lim-
iting and an output overvoltage crowbar. The force con-
tinuous control pin (FCB) can be used to inhibit Burst
Mode operation or to regulate a third, flyback output.
5V and 3.3V Standby Regulators
Selectable Constant Frequency, Burst ModeTM and
Continuous Operation
U
APPLICATIO S
■
Notebook and Palmtop Computers, PDAs
Portable Instruments
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.
■
U
TYPICAL APPLICATIO
V
IN
4.75V TO 28V
C
+
IN
1µF
10µF
4.7µF
D3
CERAMIC
D4
50V
V
VIDV INTV
CC
IN
CC
CERAMIC
M3a
M3b
TG1
TG2
M1
×4
L1
1µH
L2
C
0.47µF
C
B2
0.1µF
B1
BOOST1
SW1
BOOST2
SW2
LTC1708-PG
2.2µH
M2
BG1
BG2
D1
D2
VID0 TO VID4
PGND
5 VID BITS
+
+
SENSE1
SENSE2
R
R
SENSE2
0.01Ω
SENSE1
1000pF
1000pF
PGOOD
0.003Ω
–
–
SENSE1
SENSE2
V
1.5V
4A
OUT2
ATTNIN
V
OSENSE2
V
OUT1
R4
63.4k
1%
0.925V TO
2.00V
I
I
C
TH1
TH2
OUT1
C
OUT1a
C
C
C2
M1: IRF7811
+
C1
270µF
2V
C
OUT
RUN/SS1 SGND RUN/SS2
+
10µF
R3
20k
1%
1500pF
220pF
R
14.1A
M2: 1RF7809
180µF
4V
6.3V
CERAMIC
R
C1
M3a, M3b: FDS6982
L1: VISHAY 5050CE
ATTNOUT CONNECTED TO EAIN1
SP
×4
C
C
C2
15k
SS1
0.1µF
SS2
0.1µF
22k
SP
1628 F01
Figure 1. High Efficiency VID Controlled, 2-Output Step-Down Converter
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LTC1708-PG
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Input Supply Voltage (VIN).........................36V to –0.3V
ORDER PART
Topside Driver Voltages
1
2
PGOOD
TG1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RUN/SS1
NUMBER
+
(BOOST1, BOOST2) ...................................42V to –0.3V
Switch Voltage (SW1, SW2) .........................36V to –5V
INTVCC, EXTVCC, RUN/SS1, RUN/SS2,
SENSE1
LTC1708EG-PG
–
3
SW1
SENSE1
4
BOOST1
EAIN1
FREQSET
STBYMD
FCB
5
V
IN
(BOOST1-SW1), (BOOST2-SW2), ...............7V to –0.3V
SENSE1+, SENSE2+, SENSE1–,
6
BG1
7
EXTV
CC
SENSE2– Voltages....................... (1.1)INTVCC to –0.3V
FREQSET, STBYMD, FCB, VIDVCC, VID0-4,
PGOOD Voltages..........................................7V to –0.3V
8
INTV
CC
I
TH1
9
PGND
BG2
SGND
10
11
12
13
14
15
16
17
18
3.3V
OUT
ITH1, TH2, EAIN1, EAIN2, ATTNIN,
I
BOOST2
SW2
I
TH2
ATTNOUT Voltages ...................................2.7V to –0.3V
Peak Output Current <10µs (TG1, TG2, BG1, BG2) ... 3A
INTVCC Peak Output Current ................................ 50mA
Operating Ambient Temperature Range
EAIN2
–
TG2
SENSE2
+
RUN/SS2
SENSE2
VIDV
CC
ATTNOUT
ATTNIN
VID0
(Note 2) ...................................................–40°C to 85°C
Junction Temperature (Note 3)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
VID4
VID3
VID2
VID1
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 85°C/W
Consult factory for Industrial and Military grade parts.
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
V
Regulated Feedback Voltage
at EAIN Pin
(Note 4); I
(Note 4)
Voltage = 1.2V
TH1, 2
●
0.792
0.800
0.808
V
EAIN1, 2
I
Feedback Current
–5
–50
0.02
nA
EAIN1, 2
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 3.6V to 30V (Note 4)
IN
0.002
%/V
REFLNREG
LOADREG
(Note 4)
Measured in Servo Loop; I
Measured in Servo Loop; I
Voltage = 1.2V to 0.7V
Voltage = 1.2V to 2.0V
●
●
0.1
–0.1
0.5
–0.5
%
%
TH1, 2
TH1, 2
g
g
Transconductance Amplifier g
I
I
= 1.2V; Sink/Source 5µA; (Note 4)
1.3
3
mmho
MHz
m1, 2
m
TH1, 2
TH1, 2
Transconductance Amplifier GBW
= 1.2V; (g • Z , No Ext Load) (Note 4)
m L
mOL1, 2
I
Input DC Supply Current
Normal Mode
Standby
(Note 5)
EXTV Tied to GND; VID Inputs Open Circuit
Q
850
125
20
µA
µA
µA
CC
V
V
= 0V, V
= 0V, V
> 2V
= Open
RUN/SS1, 2
RUN/SS1, 2
STBYMD
STBYMD
Shutdown
35
0.840
–0.1
4.8
V
Forced Continuous Threshold
Forced Continuous Current
Burst Inhibit Threshold
●
0.760
–0.3
0.800
–0.18
4.3
V
µA
V
FCB
I
V
= 0.85V
FCB
FCB
V
Measured at FCB pin
Ramping Down
BINHIBIT
UVLO
Undervoltage Lockout
V
3.5
4
V
IN
2
LTC1708-PG
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
0.84
–85
0.4
TYP
0.86
–60
0.6
1.5
99.4
1.2
1.5
4.1
2
MAX
UNITS
V
V
Output Overvoltage Threshold
Sense Pins Total Source Current
Master Shutdown Threshold
Keep-Alive Power On-Threshold
Maximum Duty Factor
Measured at EAIN1, 2
0.88
OV
I
(Each Channel); V
–
– = V
+
+ = 0V
µA
V
SENSE
SENSE1 , 2
SENSE1 , 2
V
V
MS
KA
V
V
Ramping Down
STBYMD
STBYMD
STBYMD
STBYMD
Ramping Up, RUN
= 0V
2
V
SS1, 2
DF
MAX
In Dropout
98
0.5
1.0
%
I
Soft-Start Charge Current
V
V
V
= 1.9V
RUN/SS1, 2
µA
V
RUN/SS1, 2
V
V
ON RUN/SS Pin ON Threshold
LT RUN/SS Pin Latchoff Threshold
RUN/SS Discharge Current
V Rising
RUN/SS1, RUN/SS2
1.9
4.5
4
RUN/SS1, 2
RUN/SS1, 2
SCL1, 2
V
Rising from 3V
V
RUN/SS1, RUN/SS2
I
Soft Short Condition E
= 0.5V;
0.5
µA
AIN1, 2
V
= 4.5V
RUN/SS1, 2
I
Shutdown Latch Disable Current
Maximum Current Sense Threshold
EAIN1, 2 = 0.5V
1.6
5
µA
SDLHO
V
V
V
= 0.7V; V
= 0.7V; V
= 5V
= 5V
65
62
75
75
85
88
mV
mV
SENSE(MAX)
EAIN1, 2
EAIN1, 2
SENSE1, 2
SENSE1, 2
●
TG Transition Time:
Rise Time
Fall Time
TG1, 2 t
TG1, 2 t
C
C
= 3300pF (Note 10)
= 3300pF (Note 10)
50
50
90
90
ns
ns
r
f
LOAD
LOAD
BG Transition Time:
Rise Time
Fall Time
BG1, 2 t
BG1, 2 t
C
C
= 3300pF (Note 10)
= 3300pF (Note 10)
40
40
90
80
ns
ns
r
f
LOAD
LOAD
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C
= 3300pF Each Driver (Note 10)
90
ns
ns
ns
1D
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C
= 3300pF Each Driver (Note 10)
90
2D
LOAD
t
Minimum On-Time
Tested with a Square Wave (Notes 6, 10)
160
200
ON(MIN)
INTV Linear Regulator
CC
V
V
V
V
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
4.8
4.5
5.0
0.2
120
4.7
0.2
5.2
1.0
240
V
%
INTVCC
CC
IN
INT
INTV Load Regulation
I
I
I
= 0 to 20mA, V
= 4V
LDO
LDO
CC
CC
CC
CC
EXTVCC
EXT
EXTV Voltage Drop
= 20mA, V
= 5V
mV
V
CC
EXTVCC
EXTV Switchover Voltage
= 20mA, EXTV Ramping Positive
●
EXTVCC
LDOHYS
CC
CC
EXTV Hysteresis
V
CC
Oscillator
f
f
f
I
Oscillator Frequency
Lowest Frequency
V
V
V
V
= Open (Note 7)
= 0V
190
120
280
220
140
310
–2
250
170
350
– 1
kHz
kHz
kHz
µA
OSC
FREQSET
FREQSET
FREQSET
FREQSET
LOW
Highest Frequency
FREQSET Input Current
= 2.4V
HIGH
= 0V
FREQSET
3.3V Linear Regulator
V
V
V
3.3V Regulator Output Voltage
3.3V Regulator Load Regulation
3.3V Regulator Line Regulation
No Load
= 0 to 10mA
●
3.25
3.35
0.5
3.45
2
V
%
%
3.3OUT
3.3IL
I
3.3
6V < V < 30V
0.05
0.2
3.3VL
IN
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.1
0.3
1
V
PGL
PGOOD
I
V
µA
PGOOD
PGOOD
V
Relative to the 0.8V Regulated Feedback Voltage
EAIN1, 2 Ramping Negative from 0.8V
EAIN1, 2 Ramping Positive from 0.8V
PG
–10
5
–7.5
7.5
–5
10
%
%
3
LTC1708-PG
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VID Parameters
VIDV
VID Operating Supply Voltage
VID Supply Current
2.7
5.5
5
V
µA
kΩ
%
CC
I
VIDV = 3.3V (Note 8)
0.01
10
VIDVCC
CC
R
R
R
Resistance Between ATTNIN/ATTNOUT
Resistor Ratio Accuracy
5
FBOUT1/SENSE1
Programmed from 0.925V to 2.00V
0.25
40
RATIO
VID0 to VID4 Pull-Up Resistance
VID Voltage Threshold
(Note 9) V
= 0.7V
DIODE
kΩ
V
PULL-UP
IDT
V
0.4
2.5
1.0
0.1
2.8
1.6
1
I
VID Input Leakage Current
VID Pull-Up Voltage
(Note 9) VIDV < VIDV < 7V
µA
V
VIDLEAK
CC
CC
V
VIDV = 3V
3.1
PULL-UP
CC
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1708EG-PG is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 6: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of I (see minimum on-time
considerations in the Applications Information section).
MAX
Note 7: V pin internally tied to 1.19V reference through a large
FREQSET
resistance.
Note 8: With all five VID inputs floating (or tied to VIDV ) the VIDV
CC
CC
current is typically <1µA. However, the VIDV current will rise and be
approximately equal to the number of grounded VID input pins times
Note 3: T is calculated from the ambient temperature T and power
CC
J
A
dissipation P according to the following formulas:
D
(VIDV – 0.6V)/40k. (See the Applications Information section.)
CC
LTC1708EG-PG: T = T + (P • 85°C/W)
J
A
D
Note 9: Each built-in pull-up resistor attached to the VID inputs also has a
Note 4: The LTC1708-PG is tested in a feedback loop that servos V
to a specified voltage and measures the resultant EAIN1, 2.
Note 5: The supply current is higher due to the gate charge being delivered
at the switching frequency. See Applications Information.
ITH1, 2
series diode to allow input voltages higher than the VIDV supply without
CC
damage or clamping. (See Applications Information section.)
Note 10: Rise and fall times are measured at 20% to 80% levels. Delay
and nonoverlap times are measured using 50% levels.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current
and Mode (Figure 12)
Efficiency vs Output Current
(Figure 12)
Efficiency vs Input Voltage
(Figure 12)
100
90
80
70
60
50
40
30
20
10
0
100
90
100
90
80
70
60
50
EXTV = 0V
CC
V
= 1.6V
OUT
EXTV = 0V
CC
Burst Mode
V
= 5V
IN
15A
15A
OPERATION
80
70
60
I
I
= 7A
OUT
V
= 10V
IN
V
= 15V
IN
= 12A
OUT
50
40
CONSTANT FREQUENCY
MODE
V
= 20V
IN
PWM MODE
30
20
10
0
V
V
= 15V
V
V
= OPEN
= 1.6V
IN
OUT
FCB
= 1.6V
OUT
0.1
10
100
0.01
0.1
1
10
5
10
15
20
25 28
1
100
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
1708 G01
1708 G02
1708 G03
4
LTC1708-PG
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Input Voltage
and Mode (Figure 12)
INTVCC and EXTVCC Switch
Voltage vs Temperature
EXTVCC Voltage Drop
1000
800
600
400
200
0
250
200
150
100
50
5.05
5.00
4.95
4.90
4.85
4.80
4.75
4.70
INTV VOLTAGE
CC
BOTH
CONTROLLERS ON
EXTV SWITCHOVER THRESHOLD
CC
STANDBY
SHUTDOWN
0
0
5
10
15
20
25
30
35
0
10
20
30
40
50
–50 –25
0
25
50
TEMPERATURE (°C)
75
100 125
INPUT VOLTAGE (V)
CURRENT (mA)
1708 G05
1708 G04
1708 G06
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
Maximum Current Sense Threshold
vs Duty Factor
Internal 5V LDO Line Reg
75
50
25
0
5.1
5.0
80
70
60
50
40
30
20
10
0
I
= 1mA
LOAD
4.9
4.8
4.7
4.6
4.5
4.4
0
20
40
60
80
100
50
0
25
75
100
20
INPUT VOLTAGE (V)
30
35
0
5
10
15
25
DUTY FACTOR (%)
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
1708 G08
1708 G09
1708 G07
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start)
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Current Sense Threshold
vs ITH Voltage
90
80
80
76
72
68
64
60
80
60
40
20
V
= 1.6V
SENSE(CM)
70
60
50
40
30
20
10
0
–10
–20
–30
0
0
1
2
3
4
5
6
0
1
2
3
4
5
0
0.5
1
1.5
(V)
2
2.5
V
(V)
COMMON MODE VOLTAGE (V)
V
ITH
RUN/SS
1708 G10
1708 G11
1708 G12
5
LTC1708-PG
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
VITH vs VRUN/SS
SENSE Pins Total Source Current
0.0
–0.1
–0.2
–0.3
–0.4
2.5
2.0
1.5
1.0
100
50
V
EAIN
= 0.7V
FCB = 0V
= 15V
V
IN
FIGURE 1
V
OUT2
0
–50
–100
0.5
0
0
1
2
3
4
5
0
1
2
3
4
5
6
0
2
4
6
V
(V)
LOAD CURRENT (A)
V
COMMON MODE VOLTAGE (V)
RUN/SS
SENSE
1708 G14
1708 G13
1708 G15
Maximum Current Sense
Threshold vs Temperature
Dropout Voltage vs Output Current
RUN/SS Current vs Temperature
80
78
76
74
72
70
4
3
2
1
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
= 5V
OUT
R
= 0.015Ω
SENSE
R
= 0.010Ω
SENSE
0
0
50
75 100 125
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT CURRENT (A)
–50 –25
0
25
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
1708 G18
1708 G17
1708 G25
Load Step (Figure 12)
Load Step (Figure 12)
Load Step (Figure 12)
VOUT
100mV/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
IOUT
5A/DIV
IOUT
5A/DIV
IOUT
5A/DIV
VIN = 15V
10µs/DIV
1708 G22
V
IN = 15V
10µs/DIV
1708 G20
VIN = 15V
10µs/DIV
1708 G21
VOUT2 = 1.6V
VOUT2 = 1.6V
VOUT2 = 1.6V
LOAD STEP = 100mA – 15A
CONSTANT FREQUENCY MODE: VFCB = VINTVCC
ACTIVE VOLTAGE POSITIONING CIRCUIT
LOAD STEP = 100mA – 15A
Burst Mode OPERATION: VFCB = OPEN
ACTIVE VOLTAGE POSITIONING CIRCUIT
LOAD STEP = 100mA – 15A
CONTINUOUS MODE: VFCB = 0V
ACTIVE VOLTAGE POSITIONING CIRCUIT
6
LTC1708-PG
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Constant Frequency (Burst Inhibit)
Operation (Figure 12)
Burst Mode Operation (Figure 12)
Soft-Start Up (Figure 12)
VRUN/SS
2V/DIV
VOUT
20mV/DIV
VOUT
20mV/DIV
VOUT
1V/DIV
IOUT
5A/DIV
IOUT
5A/DIV
IOUT
2A/DIV
V
IN = 15V
100ms/DIV
1708 G19
V
IN = 15V
20µs/DIV
1708 G23
VIN = 15V
20µs/DIV
1708 G24
VOUT2 = 1.6V
VOUT2 = 1.6V
VFCB = OPEN
VOUT2 = 1.6V
VFCB = VINTVCC
IOUT = 250mA
I
OUT = 250mA
Current Sense Input Current
vs Temperature
EXTVCC Switch Resistance
vs Temperature
Oscillator Frequency
vs Temperature
10
8
35
33
31
29
27
25
350
300
V
= 5V
FREQSET
250
200
150
100
50
V
= OPEN
= 0V
FREQSET
6
V
FREQSET
4
2
0
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
1708 G27
1708 G26
1708 G28
Undervoltage Lockout
vs Temperature
Shutdown Latch Thresholds
vs Temperature
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.50
3.45
3.40
3.35
LATCH ARMING
LATCHOFF
THRESHOLD
3.30
3.25
3.20
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
125
–50 –25
0
25
75
50
75 100
TEMPERATURE (°C)
1708 G29
1708 G30
7
LTC1708-PG
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PI FU CTIO S
RUN/SS1, RUN/SS2 (Pins 1, 23): Combination of soft-
start,runcontrolinputsandshort-circuitdetectiontimers.
A capacitor to ground at each of these pins sets the ramp
time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overvolt-
age protection is also invoked via this pin as described in
the Applications Information section.
SENSE1+, SENSE2+ (Pins 2, 14): The (+) Input to the
Differential Current Comparators. The Ith pin voltage and
built-in offsets between the SENSE– and SENSE+ pins in
conjunction with RSENSE sets the current trip threshold.
3.3VOUT (Pin 10): Output of a linear regulator capable of
supplying 10mA DC with peak currents as high as 50mA.
ATTNOUT (Pin 15): Divided down output voltage feeding
the EAIN pin of the regulator. The VID inputs program a
resistive divider between ATTNIN and SGND. ATTNOUT is
the tap point on the divider. The voltage on ATTNOUT is
0.8V when the output is in regulation. This pin can be
bypassed to SGND with 50pF.
ATTNIN (Pin 16): Receives the remotely sensed feedback
voltage from the output.
VID0 to VID4 (Pins 17 to 21): Digital inputs for controlling
the output voltage from 0.925V to 2.0V. Table 1 specifies
the output voltage for the 32 combinations of digital
inputs. The LSB (VID0) represents 50mV increments in
the upper voltage range (2.00V to 1.30V) and 25mV
increments in the lower voltage range (1.275V to 0.925V).
Logic Low = GND, Logic High = VIDVCC or Float.
SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the
Differential Current Comparators.
EAIN1, EAIN2 (Pins 4, 12): Receives the remotely sensed
feedback voltage for each controller from a resistive
divideracrosstheoutput. TheVIDsectionmaybeusedfor
one resistive divider.
VIDVCC (Pin 22): VID Input Supply Voltage. Range from
2.7V to 5.5V. Typically this pin is tied to INTVCC.
FREQSET (Pin 5): Frequency Control Input to the Oscilla-
tor. Thispincanbeleftopen, tiedtoground, tiedtoINTVCC
or driven by an external voltage source. This pin can also
be used with an external phase detector to build a true
phase-locked loop.
PGND (Pin 28): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, an-
ode of the Schottky rectifier and the (–) terminal(s) of CIN.
INTVCC (Pin 29): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTVCC Switch. The driver and
control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor. The INTVCC regulator
standby function is determined by the STBYMD pin.
STBYMD (Pin 6): Control pin that determines which cir-
cuitry remains active when the controllers are shut down
and/or provides a common control point to shut down
both controllers. See the Operation section for details.
FCB (Pin 7): Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding using a resistive divider. An applied
input voltage below 0.8V will force continuous synchro-
nous operation on both controllers. Do not leave this pin
floating.
EXTVCC (Pin 30): External Power Input to an Internal
Switch Connected to INTVCC. This switch closes and
supplies VCC power, bypassing the internal low dropout
regulator, whenever EXTVCC is higher than 4.7V. See
EXTVCC connection in Applications Information section.
Do not exceed 7V on this pin.
ITH1, TH2 (Pins 8, 11): Error Amplifier Output and Switch-
I
ingRegulatorCompensationPoint.Eachassociatedchan-
nels’ current comparator trip point increases with this
control voltage.
BG1, BG2 (Pins 31, 27): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTVCC.
SGND (Pin 9): Small-Signal Ground. Common to both
controllers, this pin must be routed separately from high
current grounds to the common (–) terminals of the
COUT capacitors.
VIN (Pin 32): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
8
LTC1708-PG
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PI FU CTIO S
BOOST1, BOOST2 (Pins 33, 26): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the boost and switch pins and Schottky diodes
aretied betweentheboostandINTVCCpins.Voltageswing
at the boost pins is from INTVCC to (VIN + INTVCC).
TG1, TG2 (Pins 35, 24): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to INTVCC – 0.5V
superimposed on the switch node voltage SW.
PGOOD (Pin 36): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage at either EAIN pin is not
within 7.5% of the setpoint.
SW1, SW2 (Pins 34, 25): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to VIN.
U
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FU CTIO AL DIAGRA
FREQSET
1M
INTV
CC
V
IN
1.19V
CLK1
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
BOOST
TG
D
B
OSCILLATOR
CLK2
–
+
0.86V
C
B
DROP
OUT
DET
+
TOP
BOT
C
C
PGOOD
IN
D
1
BOT
FCB
V
FB1
SW
–
+
TOP ON
S
R
Q
Q
0.74V
0.86V
SWITCH
LOGIC
INTV
CC
BG
–
+
OUT
V
FB2
PGND
–
+
+
0.6V
V
OUT
0.74V
BINH
–
V
SEC
SHDN
R
SENSE
0.17µA
–
+
4.5V
0.8V
INTV
CC
FCB
I
1
I
2
+
–
+
+
–
–
+ +
–
FCB
+
–
SENSE
SENSE
D
C
SEC
SEC
30k
30k
3.3V
OUT
3mV
+
–
V
0.86V
FB
REF
–
4(V
)
SLOPE
COMP
V
45k
2.4V
45k
IN
V
IN
EAIN
V
FB
+
–
4.8V
–
+
5V
LDO
REG
EA
OV
EXTV
0.800V
0.860V
CC
+
–
INTV
CC
5V
+
C
C
1.2µA
I
TH
INTERNAL
SUPPLY
SGND
SHDN
RST
RUN
SOFT-
START
R
C
C
C2
6V
4(V
FB
)
STBYMD
ATTNIN
RUN/SS
C
SS
R2
10k
ATTNOUT
5-BIT VID DECODER
R1
VARIABLE
40k
EACH VID
INPUT
VID0 VID1 VID2 VID3 VID4
VIDV
CC
1708 F02
Figure 2
9
LTC1708-PG
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
controller 1 and 2) select between two modes of low
current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETsarealternatelyturnedontomaintaintheoutput
voltage independent of direction of inductor current.
When the FCB pin is below VINTVCC – 2V but greater than
0.8V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
beforeinhibitingthetopswitchandturnsoffthesynchro-
nous MOSFET(s) when the inductor current goes nega-
tive. This combination of requirements will, at low cur-
rents, force the ITH pin below a voltage threshold that will
temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the ITH pin. This hysteresis
produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by
having the hysteretic comparator after the error amplifier
gain block.
The LTC1708 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating180degreesoutofphase. Duringnormalopera-
tion, eachtopMOSFETisturnedonwhentheclockforthat
channel sets the RS latch, and turned off when the main
current comparator, I1, resets the RS latch. The peak
inductor current at which I1 resets the RS latch is con-
trolled by the voltage on the ITH pin, which is the output of
each error amplifier EA. The EAIN pin receives the voltage
feedback signal, which is compared to the internal refer-
ence voltage by the EA. When the load current increases,
it causes a slight decrease in EAIN relative to the 0.8V
reference, which in turn causes the ITH voltage to increase
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2, or
the beginning of the next cycle.
The top MOSFET drivers are biased from floating boot-
strap capacitor CB, which normally is recharged during
each off cycle through an external diode when the top
MOSFET turns off. As VIN decreases to a voltage close to
VOUT, the loop may enter dropout and attempt to turn on
the top MOSFET continuously. The dropout detector de-
tects this and forces the top MOSFET off for about 500ns
every tenth cycle to allow CB to recharge.
Constant Frequency Operation
When the FCB pin is tied to INTVCC, Burst Mode operation
is disabled and the forced minimum output current re-
quirement is removed. This provides constant frequency,
discontinuous (preventing reverse inductor current) cur-
rent operation over the widest possible output current
range.Thisconstantfrequencyoperationisnotasefficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approxi-
mately 1% of designed maximum output current.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches1.5V,themaincontrolloopisenabledwiththe
ITH voltageclampedatapproximately30%ofitsmaximum
value. As CSS continues to charge, the ITH pin voltage is
gradually released allowing normal, full-current opera-
tion. When both RUN/SS1 and RUN/SS2 are low, all
LTC1708 controller functions are shut down, and the
STBYMD pin determines if the standby 5V and 3.3V
regulators are kept alive.
Continuous Current (PWM) Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost-
ing the input supply to dangerous voltage levels—
BEWARE!
Low Current Operation
The FCB pin is a multifunction pin providing two func-
tions:1)toprovideregulationforasecondarywindingby
temporarily forcing continuous PWM operation on
10
LTC1708-PG
U
(Refer to Functional Diagram)
OPERATIO
Frequency Setting
VID Control
The FREQSET pin provides frequency adjustment of the
internal oscillator from approximately 140kHz to 310kHz.
This input is nominally biased through an internal resistor
to the 1.19V reference, setting the oscillator frequency to
approximately 220kHz. This pin can be driven from an
external AC or DC signal source to control the instanta-
neous frequency of the oscillator.
Logic inputs VID0 to VID4 program an internal resistive
divider. The output voltage can be programmed in 50mV
and 25mV increments from 0.925V to 2.0V (see Table 1).
These logic input pins are internally pulled up to the
VIDVCC pin using separate internal series resistor/diode
paths. The diodes provide electrical isolation when the
logic pins are externally pulled up to a higher voltage
supply than VIDVCC.
INTVCC/EXTVCC Power
Power Good (PGOOD)
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open, an internal 5V low
dropoutlinearregulatorsuppliesINTVCC power.IfEXTVCC
is taken above 4.7V, the 5V regulator is turned off and an
internalswitchisturnedonconnectingEXTVCC toINTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information.
ThePGOODpinisconnectedtoanopendrainofaninternal
MOSFET. The MOSFET turns on when the outputs are not
both within ±7.5% of their nominal output levels as
determinedbytheirfeedbackdividers. Whenbothoutputs
are within ±7.5% of their nominal values, the MOSFET is
turned off within 10µs and the pin is pulled up by an
external source
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
Standby Mode Pin
TheRUN/SScapacitorsareusedinitiallytolimittheinrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrentand/orshort-circuitcondition.Ifthecondition
lasts for a long enough period as determined by the size of
the RUN/SS capacitor, both controllers will be shut down
until the RUN/SS pin’s voltages are recycled. This built-in
latchoff can be overridden by providing a >5µA pull-up at
a compliance of 5V to the RUN/SS pin(s). This current
shortens the soft-start period but also prevents net dis-
charge of the RUN/SS capacitor(s) during an overcurrent
and/orshort-circuitcondition. Foldbackcurrentlimitingis
also activated when the output voltage falls below 70% of
its nominal level whether or not the short-circuit latchoff
circuit is enabled. Even if a short is present and the short-
circuit latchoff is not enabled, a safe, low output current is
providedduetointernalcurrentfoldbackandactualpower
The STBYMD pin is a three-state input that controls
common circuitry within the IC as follows: When the
STBYMD pin is held at ground, both controller RUN/SS
pins are pulled to ground providing a single control pin to
shut down both controllers. When the pin is left open, the
internal RUN/SS currents are enabled to charge the
RUN/SS capacitor(s), allowing the turn-on of either con-
troller and activating necessary common internal biasing.
When the STBYMD pin is taken above 2V, both internal
linear regulators are turned on independent of the state on
the RUN/SS pins of the two switching regulator control-
lers, providing an output power source for “wake-up”
circuitry. Decouple the pin with a small capacitor (0.01µF)
to ground if the pin is not connected to a DC potential.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFETisturnedoffandthebottomMOSFETisturnedon
until the overvoltage condition is cleared.
11
LTC1708-PG
U
(Refer to Functional Diagram)
OPERATIO
wasted is low due to the efficient nature of the current
mode switching regulator.
expensive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.
THEORY AND BENEFITS OF 2-PHASE OPERATION
Figure 3 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the new
LTC1628 2-phase dual switching regulator. An actual
measurement of the RMS input current under these con-
ditions shows that 2-phase operation dropped the input
current from 2.53ARMS to 1.55ARMS. While this is an
impressive reduction in itself, remember that the power
losses are proportional to IRMS2, meaning that the actual
power wasted is reduced by a factor of 2.66. The reduced
input ripple voltage also means less power is lost in the
inputpowerpath, whichcouldincludebatteries, switches,
trace/connector resistances and protection circuitry. Im-
provements in both conducted and radiated EMI also
directly accrue as a result of the reduced RMS input
current and voltage.
TheLTC1708dualhighefficiencyDC/DCcontroller,likethe
LTC1628, brings the considerable benefits of 2-phase
operation to portable applications for the first time. Note-
book computers, PDAs, handheld terminals and automo-
tiveelectronicswillallbenefitfromthelowerinputfiltering
requirement, reduced electromagnetic interference (EMI)
andincreasedefficiencyassociatedwith2-phaseoperation.
Whytheneedfor2-phaseoperation?UpuntiltheLTC1628,
constant-frequency dual switching regulators operated
both channels in phase (i.e., single-phase operation). This
means that both switches turned on at the same time,
causing current pulses of up to twice the amplitude of
those for one regulator to be drawn from the input capaci-
tor and battery. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitorsandincreasingbothEMIandlossesintheinput
capacitor and battery.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how
theRMSinputcurrentvariesforsingle-phaseand2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
With 2-phase operation, the two channels of the dual-
switching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses
drawn by the switches, greatly reducing the overlap time
where they add together. The result is a significant reduc-
tion in total RMS input current, which in turn allows less
It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS
IIN(MEAS) = 1.55ARMS
DC236 F03a
DC236 F03b
(a)
(b)
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation
for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The
Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive
Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
12
LTC1708-PG
U
(Refer to Functional Diagram)
OPERATIO
for most applications is that 2-phase operation will reduce
theinputcapacitorrequirementtothatforjustonechannel
operating at maximum current and 50% duty cycle.
The LTC1708 is proof that these hurdles have been sur-
mounted.Thenewdeviceoffersuniqueadvantagesforthe
ever-expanding number of high efficiency power supplies
required in portable electronics.
A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived “slope compensation” signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in single-
phasedualswitchingregulators,butrequiredthedevelop-
ment of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.
15.0
SINGLE PHASE
DUAL CONTROLLER
12.5
10.0
7.5
5.0
2.5
0
2-PHASE
DUAL CONTROLLER
V
V
= 5V/15A
O1
O2
= 3.3V/15A
0
10
20
30
40
INPUT VOLTAGE (V)
1708 F04
Figure 4. RMS Input Current Comparison
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APPLICATIO S I FOR ATIO
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite-
rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.
Figure 1 on the first page is a basic LTC1708 application
circuit. External component selection is driven by the load
requirement, and begins with the selection of RSENSE
.
Once RSENSE is known, L can be chosen. Next, the power
MOSFETs and D1 are selected. Finally, CIN and COUT are
selected . The circuit shown in Figure 1 can be configured
for operation up to an input voltage of 28V (limited by the
external MOSFETs).
Selection of Operating Frequency
RSENSE Selection For Output Current
The LTC1708 uses a constant frequency architecture with
the frequency determined by an internal oscillator capaci-
tor. This internal capacitor is charged by a fixed current
plus an additional current that is proportional to the
voltage applied to the FREQSET pin.
RSENSE is chosen based on the required output current.
The LTC1708 current comparator has a maximum thresh-
old of 75mV/RSENSE and an input common mode range of
SGND to 1.1(INTVCC). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current IMAX equal to the peak value less
half the peak-to-peak ripple current, ∆IL.
A graph for the voltage applied to the FREQSET pin vs
frequency is given in Figure 5. As the operating frequency
isincreasedthegatechargelosseswillbehigher,reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.
Allowing a margin for variations in the LTC1708 and
external component values yields:
50mV
R
=
SENSE
I
MAX
13
LTC1708-PG
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APPLICATIO S I FOR ATIO
2.5
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
2.0
1.5
1.0
0.5
0
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will in-
crease.
120
170
220
270
320
OPERATING FREQUENCY (kHz)
1708 F05
Figure 5. FREQSET Pin Voltage vs Frequency
Inductor Value Calculation
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
Molypermalloy (from Magnetics, Inc.) is a very good, low
losscorematerialfortoroids,butitismoreexpensivethan
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designsforsurfacemountareavailable
that do not increase the height significantly.
Theinductorvaluehasadirecteffectonripplecurrent.The
inductor ripple current ∆IL decreases with higher induc-
tance or frequency and increases with higher VIN:
1
V
OUT
V
IN
∆I =
V
1–
L
OUT
(f)(L)
Power MOSFET and D1 Selection
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL=0.3(IMAX). Remember, the
maximum ∆IL occurs at the maximum input voltage.
Two external power MOSFETs must be selected for each
controller with the LTC1708: One N-channel MOSFET for
each top (main) switch, and one N-channel MOSFET for
each bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC volt-
age. This voltage is typically 5V during start-up (see
EXTVCC PinConnection).Consequently,logic-levelthresh-
old MOSFETs must be used in most applications. The only
exception is if low input voltage is expected (VIN < 5V);
Kool Mµ is a registered trademark of Magnetics, Inc.
The inductor value also has secondary effects. The transi-
tion to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
14
LTC1708-PG
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APPLICATIO S I FOR ATIO
then, sub-logic level threshold MOSFETs (VGS(TH) < 3V)
should be used. Pay close attention to the BVDSS specifi-
cation for the MOSFETs as well; most of the logic level
MOSFETs are limited to 30V or less.
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specified in the
MOSFETcharacteristics. Theconstantk=1.7canbeused
to estimate the contributions of the two terms in the main
switch dissipation equation.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance RDS(ON), reverse transfer capacitance CRSS
,
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead-
time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high VIN. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
input voltage and maximum output current. When the
LTC1708 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
V
OUT
Main SwitchDuty Cycle =
V
IN
V – V
IN
OUT
Synchronous SwitchDuty Cycle =
V
IN
CIN and COUT Selection
The MOSFET power dissipations at maximum output
current are given by:
The selection of CIN is simplified by the multiphase archi-
tecture and its impact on the worst-case RMS current
drawnthroughtheinputnetwork(battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically re-
duces the input capacitor’s RMS ripple current by a factor
of 30% to 70% when compared to a single phase power
supply solution.
2
) (
V
V
OUT
P
=
I
1+δ R
+
(
)
MAIN
MAX
DS(ON)
IN
2
) (
k V
(
I
C
f
)(
)( )
IN
MAX RSS
2
) (
V – V
IN
OUT
P
=
I
(
1+δ R
)
SYNC
MAX
DS(ON)
V
IN
where δ is the temperature dependency of RDS(ON) and k
is a constant inversely related to the gate drive current.
BothMOSFETshaveI2RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increasetothepointthattheuseofahigherRDS(ON)device
with lower CRSS actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
The term (1+δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
15
LTC1708-PG
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inputcapacitors,buteachhasdrawbacks:ceramicvoltage
coefficients are very high and may have audible piezoelec-
tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22µF or two to three 10µF ceramic capaci-
tors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con-
sider parallel ceramic and high quality electrolytic capaci-
tors as an effective means of achieving ESR and bulk
capacitance goals.
theinputcapacitor’sESR. Thisiswhytheinputcapacitor’s
requirement calculated above for the worst-case control-
ler is adequate for the dual controller design. Remember
that input protection fuse resistance, battery resistance
and PC board trace resistance losses are also reduced due
to the reduced peak currents in a multiphase system. The
overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing. The drains of
thetwotopMOSFETSshouldbeplacedwithin1cmofeach
other and share a common CIN(s). Separating the drains
and CIN may produce undesirable voltage and current
resonances at VIN.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (∆VOUT) is determined by:
Incontinuousmode, thesourcecurrentofthetopN-chan-
nel MOSFET is a square wave of duty cycle VOUT/VIN. To
preventlargevoltagetransients, alowESRinputcapacitor
sized for the maximum RMS current of one channel must
beused. ThemaximumRMScapacitorcurrentisgivenby:
1
∆VOUT ≈ ∆IL ESR +
8fCOUT
Wheref=operatingfrequency,COUT =outputcapacitance,
and ∆IL= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3IOUT(MAX) the output
ripple will typically be less than 50mV at max VIN assum-
ing:
1/2
]
V
V − V
OUT
(
)
OUT IN
[
C RequiredI
≈I
IN
RMS MAX
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperaturethanrequired.Severalcapacitorsmayalsobe
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
COUT Recommended ESR < 2 RSENSE
and COUT > 1/(8fRSENSE
)
ThefirstconditionrelatestotheripplecurrentintotheESR
of the output capacitance while the second term guaran-
tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The ITH pin OPTI-LOOP compensation compo-
nents can be optimized to provide stable, high perfor-
mance transient response regardless of the output
capacitors selected.
The benefit of the LTC1708 multiphase can be calculated
by using the equation above for the higher power control-
ler and then calculating the loss that would have resulted
if both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operatingduetotheinterleavingofcurrentpulsesthrough
16
LTC1708-PG
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Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1708 to be
exceeded. The system supply current is normally domi-
nated by the gate charge current. Additional external
loading of the INTVCC and 3.3V linear regulators also
needs to be taken into account for the power dissipation
calculations. The total INTVCC current can be supplied by
either the 5V internal linear regulator or by the EXTVCC
input pin. When the voltage applied to the EXTVCC pin is
less than 4.7V, all of the INTVCC current is supplied by the
internal 5V linear regulator. Power dissipation for the IC in
this case is highest: (VIN)(IINTVCC), and overall efficiency
is lowered. The gate charge current is dependent on
operatingfrequencyasdiscussedintheEfficiencyConsid-
erations section. The junction temperature can be esti-
mated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC1708 VIN
current is limited to less than 24mA from a 24V supply
when not using the EXTVCC pin as follows:
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Spe-
cial polymer surface mount capacitors offer very low ESR
buthavelowerstoragecapacityperunitvolumethanother
capacitor types. These capacitors offer a very cost-effec-
tiveoutputcapacitorsolutionandareanidealchoicewhen
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven applica-
tionsprovidingthatconsiderationisgiventoripplecurrent
ratings, temperature and long term reliability. A typical
application will require several to many aluminum electro-
lytic capacitors in parallel. A combination of the above
mentioned capacitors will often result in maximizing per-
formance and minimizing overall cost. Other capacitor
types include Nichicon PL series, NEC Neocap, Pansonic
SP and Sprague 595D series. Consult manufacturers for
other specific recommendations.
TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C
UseoftheEXTVCC inputpinreducesthejunctiontempera-
ture to:
TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C
Dissipationshouldbecalculatedtoalsoincludeanyadded
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being ex-
ceeded, the input supply current must be checked operat-
ing in continuous mode at maximum VIN.
EXTVCC Connection
INTVCC Regulator
The LTC1708 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTVCC rises above 4.7V, the
internal regulator is turned off and the switch closes,
connecting the EXTVCC pin to the INTVCC pin thereby
supplying internal power. The switch remains closed as
longasthevoltageappliedtoEXTVCC remainsabove4.5V.
This allows the MOSFET driver and control power to be
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. INTVCC powers
the drivers and internal circuitry within the LTC1708. The
INTVCC pin regulator can supply a peak current of 50mA
and must be bypassed to ground with a minimum of
4.7µF tantalum, 10µF special polymer, or low ESR type
electrolytic capacitor. A 1µF ceramic capacitor placed
directlyadjacenttotheINTVCC andPGNDICpinsishighly
17
LTC1708-PG
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derived from the output during normal operation (4.7V <
4. EXTVCC Connected to an Output-Derived Boost Net-
work. For3.3Vandotherlowvoltageregulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive boost
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.
V
OUT <7V)andfromtheinternalregulatorwhentheoutput
is out of regulation (start-up, short-circuit). If more cur-
rent is required through the EXTVCC switch than is speci-
fied, an external Schottky diode can be added between the
EXTVCC and INTVCC pins. Do not apply greater than 7V to
the EXTVCC pin and ensure that EXTVCC < VIN.
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
Capacitor CB in the functional diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desiredMOSFET.ThisenhancestheMOSFETandturnson
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
supply means connecting the EXTVCC pin directly to VOUT
.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC LeftOpen(orGrounded).ThiswillcauseINTVCC
to be powered from the internal 5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.
on, the boost voltage is above the input supply: VBOOST
=
VIN + VINTVCC. The value of the boost capacitor CB needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter-
nal Schottky diode must be greater than VIN(MAX). When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
2. EXTVCC Connected directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTVCC Connected to an External supply. If an external
supply is available in the 5V to 7V range, it may be used to
powerEXTVCC providingitiscompatiblewiththeMOSFET
gate drive requirements.
+
V
V
IN
IN
1µF
OPTIONAL EXTV
CONNECTION
CC
+
+
5V < V
< 7V
SEC
C
C
IN
IN
0.22µF
BAT85
BAT85
BAT85
V
V
V
IN
SEC
IN
+
N-CH
N-CH
LTC1708-PG
LTC1708-PG
1µF
VN2222LL
TG1
TG1
R
R
SENSE
SENSE
V
V
OUT
OUT
T1
1:N
L1
EXTV
FCB
EXTV
CC
SW
SW
CC
R6
R5
+
+
C
C
OUT
BG1
OUT
BG1
N-CH
N-CH
SGND
PGND
PGND
1708 F06a
1708 F06b
Figure 6b. Capacitive Charge Pump for EXTVCC
Figure 6a. Secondary Output Loop & EXTVCC Connection
18
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Output Voltage Programming
being damaged or clamped if they are driven higher than
VIDVCC. The digital inputs accept CMOS voltage levels.
The LTC1708 output voltages are set by the VID logic
inputs for the first controller and by an external feedback
resistive divider carefully placed across the output capaci-
torforthesecondcontroller.Theresultantfeedbacksignal
is compared with the internal precision 0.800V voltage
reference by the error amplifier. The output voltage is
given by the equation:
VIDVCC is the supply voltage for the VID section. It is
normally connected to INTVCC but can be driven from
other sources such as a 3.3V supply. If it is driven from
another source, that source MUST be in the range of 2.7V
to 5.5V and MUST be alive prior to enabling the LTC1708.
Table 1. VID Output Voltage Programming
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
(V)
OUT
R2
R1
V
= 0.8V 1+
2.000V
1.950V
1.900V
1.850V
1.800V
1.750V
1.700V
1.650V
1.600V
1.550V
1.500V
1.450V
1.400V
1.350V
1.300V
*
OUT
The output voltage of the first controller is digitally set to
levels between 0.925V and 2.00V using the voltage iden-
tification(VID)inputsVID0toVID4. Theinternal5-bitDAC
configured as a precision resistive voltage divider sets the
output voltage in 50mV or 25mV increments according to
Table 1.
The VID codes (00000-11110) are engineered to be com-
patible with Intel Mobile Pentium® II and Pentium III
processor specifications for output voltages from 0.925V
to 2.00V.
The LSB (VID0) represents 50mV increments in the upper
voltage range (1.30V to 2.00V) and 25mV increments in
the lower voltage range (0.925V to 1.275V). The MSB is
VID4. When all bits are low, or grounded, the output
voltage is 2.00V.
1.275V
1.250V
1.225V
1.200V
1.175V
1.150V
1.125V
1.100V
1.075V
1.050V
1.025V
1.000V
0.975V
0.950V
0.925V
**
Between the ATTNOUT pin and ground is a variable resis-
tor,R1,whosevalueiscontrolledbythefiveinputpins(VID0
to VID4). Another resistor, R2, between the ATTNIN and
the ATTNOUT pins completes the resistive divider. The
output voltage is thus set by the ratio of (R1 + R2) to R1.
The LTC1708 has remote sense capability. The top of the
internal resistive divider is connected to ATTNIN, and it is
referenced to the SGND pin. This allows a Kelvin connec-
tionforremotelysensingtheoutputvoltagedirectlyacross
the load, eliminating any PC board trace resistance errors.
Each VID digital input is pulled up by a 40k resistor in
series with a diode from VIDVCC. Therefore, it must be
grounded to get a digital low input, and can be either
floated or connected to VIDVCC to get a digital high input.
The series diode is used to prevent the digital inputs from
Pentium is a registered trademark of Intel Corporation.
Note: *, ** represent codes without a defined output voltage as specified in
Intel specifications. The LTC1708 interprets these codes as valid inputs and
produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V.
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SENSE+/SENSE– Pins
RSENSE to 75mV/RSENSE. The output current limit ramps
up slowly, taking an additional 1.25s/µF to reach full
current. The output current thus ramps up slowly, reduc-
ing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTVCC. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTVCC. A differential NPN input
stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pinstothemainoutput.Theoutputcanbeeasilypreloaded
by the VOUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
1.5V
1.2µA
tDELAY
=
=
C
SS = 1.25s / µF CSS
(
)
3V − 1.5V
1.2µA
tIRAMP
C
SS = 1.25s / µF CSS
(
)
By pulling both RUN/SS pins below 1V and/or pulling the
STBYMD pin below 0.2V, the LTC1708 is put into low
current shutdown (IQ = 20µA). The RUN/SS pins can be
driven directly from logic as shown in Figure 7. Diode D1
in Figure 7 reduces the start delay but allows CSS to ramp
up slowly providing the soft-start function. Each RUN/SS
pin has an internal 6V zener clamp (See Functional
Diagram).
ISENSE+ + ISENSE– = (2.4V – VOUT)/24k
Since VEAIN is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 8 to have a maximum value to
absorb this current.
0.8V
R1
= 24k
V
INTV
(MAX)
IN
CC
R
2.4V – V
3.3V OR 5V
RUN/SS
*
OUT
R
*
SS
SS
D1
for VOUT < 2.4V
RUN/SS
C
SS
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32K. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the VEAIN
feedback current.
C
SS
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
(a)
1708 F07
(b)
Figure 7. RUN/SS Pin Interfacing
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC1708. Soft-start reduces the input power
source’s surge currents by gradually increasing the
controller’s current limit (proportional to VITH). This pin
can also be used for power supply sequencing.
Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, CSS, is used initially to turn on and
limit the inrush current. After the controller has been
started and been given adequate time to charge up the
outputcapacitorandprovidefullloadcurrent, theRUN/SS
capacitorisusedforashort-circuittimer. Iftheregulator’s
output voltage falls to less than 70% of its nominal value
after CSS reaches 4.1V, CSS begins discharging on the
assumption that the output is in an overcurrent condition.
An internal 1.2µA current source charges up the CSS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
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If the condition lasts for a long enough period as deter-
mined by the size of the CSS and the specified discharge
current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during start-
up, the time can be approximated by:
of 75mV/RSENSE. The maximum value of current limit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the highest power
dissipation in the top MOSFET.
The LTC1708 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
outputfallsbelow70%ofitsnominaloutputlevel,thenthe
maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the LTC1708 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN) of
the LTC1708 (less than 200ns), the input voltage and
inductor value:
tLO1 ≈ [CSS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)
= 2.7 • 106 (CSS)
If the overload occurs after start-up the voltage on CSS will
begin discharging from the zener clamp voltage:
t
LO2 ≈ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resis-
tor to VIN as in Figure 7a, defeats overcurrent latchoff.
Diode-connecting this pull-up resistor to INTVCC , as in
Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTVCC loading
from preventing controller start-up.
∆IL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
25mV
RSENSE
1
2
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
ISC
=
+ ∆IL(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
thereforeallowaswitchingregulatorsystemhavingapoor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if VOUT returns to a safe level,
CSS > (COUT )(VOUT) (10–4) (RSENSE
)
The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The LTC1708 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
21
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normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
VOUT
V (f)
IN
tON(MIN)
<
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC1708 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The Standby Mode (STBYMD) Pin Function
TheStandbyMode(STBYMD)pinprovidesseveralchoices
for start-up and standby operational modes. If the pin is
pulled to ground, the RUN/SS pins for both controllers are
internallypulledtoground,preventingstart-upandthereby
providing a single control pin for turning off both control-
lers at once. If the pin is left open or decoupled with a
capacitor to ground, the RUN/SS pins are each internally
provided with a starting current enabling external control
for turning on each controller independently. If the pin is
provided with a current of >3µA at a voltage greater than
2V, both internal linear regulators (INTVCC and 3.3V) will
be on even when both controllers are shut down. In this
mode, the onboard 3.3V and 5V linear regulators can
provide power to keep-alive functions such as a keyboard
controller.Thispincanalsobeusedasalatching“on”and/
or latching “off” power switch if so designed.
The minimum on-time for the LTC1708 is generally less
than200ns.However,asthepeaksensevoltagedecreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
when the FCB pin drops below 0.8V. During continuous
mode, current flows continuously in the transformer pri-
mary. The secondary winding(s) draw current only when
the bottom, synchronous switch is on. When primary load
currents are low and/or the VIN/VOUT ratio is low, the
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings providing there is sufficient synchro-
nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.
Frequency of Operation
The LTC1708 has an internal voltage controlled oscillator.
The frequency of this oscillator can be varied over a 2 to 1
range. The pin is internally self-biased at 1.19V, resulting
in a free-running frequency of approximately 220kHz. The
FREQSET pin can be grounded to lower this frequency to
approximately 140kHz or tied to the INTVCC pin to yield
approximately 310kHz. The FREQSET pin may be driven
with a voltage from 0 to INTVCC to fix or modulate the
oscillator frequency as shown in Figure 5.
The secondary output voltage VSEC is normally set as
shown in Figure 6a by the turns ratio N of the transformer:
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
thattheLTC1708iscapableofturningonthetopMOSFET.
It is determined by internal timing delays and the gate
chargerequiredtoturnonthetopMOSFET.Lowdutycycle
applications may approach this minimum on-time limit
and care should be taken to ensure that
VSEC (N + 1) VOUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then VSEC will droop. An external resistive divider from
VSEC to the FCB pin sets a minimum voltage VSEC(MIN)
:
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INTV
V
CC
OUT
R2
R6
V
≈ 0.8V 1+
R
T2
SEC(MIN)
R5
I
EAIN
LTC1708-PG
TH
R
T1
R
R1
C
If VSEC drops below this level, the FCB voltage forces
temporary continuous switching operation until VSEC is
again above its minimum.
C
C
1708 F08
Figure 8. Active Voltage Positioning Applied to the LTC1708
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
The following table summarizes the possible states avail-
able on the FCB pin:
Table 1
FCB Pin
Condition
0V to 0.75V
Forced Continuous (Current Reversal
Allowed—Burst Inhibited)
%Efficiency = 100% – (L1 + L2 + L3 + ...)
0.85V < V < 4.3V
Minimum Peak Current Induces
Burst Mode Operation
FCB
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
No Current Reversal Allowed
Feedback Resistors
>4.8V
Regulating a Secondary Winding
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1708 circuits: 1) LTC1708 VIN current (in-
cluding loading on the 3.3V internal regulator), 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Voltage Positioning
1. The VIN current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output.VINcurrenttypicallyresultsinasmall(<0.1%)loss.
Voltage positioning can be used to minimize peak-to-peak
outputvoltageexcursionunderworst-casetransientload-
ing conditions. The open-loop DC gain of the control loop
is reduced depending upon the maximum load step speci-
fications. Voltage positioning can easily be added to the
LTC1708 by loading the ITH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, IGATECHG =f(QT+QB), where QT and QB
are the gate charges of the topside and bottom side
MOSFETs.
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can be
reduced for a particular application. A complete explana-
tion is included in Design Solutions 10 or the LTC1736
data sheet. (See www.linear-tech.com)
SupplyingINTVCC powerthroughtheEXTVCC switchinput
from an output-derived source will scale the VIN current
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required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi-
mately2.5mAofVIN current. Thisreducesthemid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
maximum of 20mΩ to 50mΩ of ESR. The LTC1708 2-
phasearchitecturetypicallyhalvesthisinputcapacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
the average output current flows through L and RSENSE
,
but is “chopped” between the topside MOSFET and the
synchronousMOSFET. IfthetwoMOSFETshaveapproxi-
mately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of
L, RSENSE and ESR to obtain I2R losses. For example, if
each RDS(ON) = 10mΩ, RL = 5mΩ, RSENSE = 3mΩ and
RESR = 10mΩ (sum of both input and output capacitance
losses), then the total resistance is 28mΩ. This results in
losses ranging from 3% to 8% as the output current
increasesfrom5Ato15Afora5Voutput,oran8%to20%
loss for a 1.6V output. Efficiency varies as the inverse
square of VOUT for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadruplingtheimportanceoflosstermsintheswitching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
2
Transition Loss = (1.7) VIN IO(MAX) CRSS
f
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 100%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10%efficiencydegradationinportablesystems.Itisvery
important to include these “system” level losses during
thedesignphase.Theinternalbatteryandfuseresistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a
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give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop re-
sponse. The gain of the loop will be increased by increas-
ing RC and the bandwidth of the loop will be increased by
decreasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase the same in the most critical
frequency range of the feedback loop. The output voltage
settling behavior is related to the stability of the closed-
loopsystemandwilldemonstratetheactualoverallsupply
performance.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera-
tion. But before you connect, be advised: you are plug-
ging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.
Load-dump is the result of a loose battery cable. When the
cablebreaksconnection,thefieldcollapseinthealternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current to
about 200mA.
ThenetworkshowninFigure9isthemoststraightforward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamptheinputvoltagebelowbreakdownoftheconverter.
Although the LTC1708 has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BVDSS.
A I RATING
PK
V
IN
LTC1708-PG
T VOLTAGE
OR
NSTRUMENT
Figure 9. Automotive Application Protection
25
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Design Example
continuous mode is not selected and the programmed
voltage is less than 1.4V with no external load, it is
necessary to preload the output in order to prevent the
current comparator input bias current from causing the
output voltage to rise above the designed level. A 16k
preload resistor will prevent this from happening for all
programmedoutputvoltagesdowntotheminimum0.925V
level.
As a design example for one channel, assume VIN
12V(nominal), VIN = 22V(max), VOUT = 1.6V, IMAX = 14A,
and f = 300kHz, RSENSE can immediately be calculated:
=
RSENSE = 50mV/14A ≈ 0.0035Ω → 0.003Ω
Tie the FREQSET pin to the INTVCC pin for 300kHz opera-
tion, or use a resistive divider from INTVCC according to
Figure 5 to reduce the operating frequency.
The power dissipation on the topside MOSFET can be
easilyestimated.ChoosingaInternationalRectifierIRF7811
results in; RDS(ON) = 0.011Ω, CRSS = 240pF. At maximum
input voltage with T(estimated) = 50°C:
Assume a 1µH inductor and check the actual value of the
ripple current. The following equation is used:
V
(f)(L)
V
OUT
V
IN
OUT
∆I =
1–
L
2
1.6V
22V
PMAIN
=
14 1+(0.005)(50°C – 25°C)
( )
[
]
The highest value of the ripple current occurs at the
maximum input voltage:
2
0.011Ω + 1.7 22V 14A 240pF 300kHz
(
)
(
) (
)(
)(
)
= 1.0W
1.6V
1.6V
22V
∆IL =
1–
= 4.95A
Ashort-circuittogroundwillresultinafoldedbackcurrent
of:
300kHz(1µH)
The ripple current is 35% of maximum output current.
25mV
0.003Ω
1 200ns(22V)
Increasing the ripple current will also help ensure that the
minimum on-time of 200ns is not violated. The minimum
on-time occurs at maximum VIN:
ISC
=
+
= 12.7A
2
1µH
with a typical value of RDS(ON) and δ = (0.005/°C)(20) =
0.1. TheresultingpowerdissipatedinthebottomMOSFET
is:
VOUT
1.6V
tON(MIN)
=
=
= 242ns
V
IN(MAX)f 22V(300kHz)
2
22V – 1.6V
22V
= 1.23W
PSYNC
=
12.7A 1.1 0.0075Ω
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins current.
(
) ( )(
)
which is similar to full-load conditions.
0.8V
2.4V – VOUT
0.8V
CIN is chosen for an RMS current rating of at least 5A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.01Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
R1(MAX) = 24k
= 24K
= 24k
2.4V – 1.6V
Choosing 1% resistors; R1 = R2 = 20k yields an output
voltage of 1.600V. If the VID section of the LTC1708-PG is
used,R1willrangefromavalueof6.6kto64k.Iftheforced
VORIPPLE = RESR(∆IL) = 0.01Ω(4.95A) = 50mVP–P
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PC Board Layout Checklist
at CIN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1708. These items are also illustrated graphically in
the layout diagram of Figure 10. The Figure 11 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
2. Are the signal and power grounds kept separate? The
combined LTC1708 signal ground pin and the ground
return of CINTVCC must return to the combined COUT (–)
terminals.ThepathformedbythetopN-channelMOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminalsshouldbeconnectedascloseaspossibletothe
(–) terminals of the input capacitor by placing the
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
POWER GOOD
1
2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
INTV
CC
RUN/SS1
PGOOD
TG1
+
V
SENSE1
OUT1
3
–
SENSE1
SW1
4
EAIN1
BOOST1
5
INTV
INTV
FREQSET
STBYMD
FCB
V
IN
CC
CC
6
BG1
7
EXTV
CC
8
I
INTV
CC
TH1
9
SGND
PGND
BG2
V
IN
LTC1708-PG
10
11
12
13
14
15
16
17
18
3.3V
OUT
I
BOOST2
SW2
TH2
EAIN2
–
+
V
SENSE2
SENSE2
TG2
OUT2
RUN/SS2
ATTNOUT
ATTNIN
VID0
VIDV
CC
VID4
VID3
VID2
VID CONTROL
INPUTS
VID1
1708 F10
Figure 10. LTC1708 Recommended Printed Circuit Layout Diagram
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5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve noise
performance substantially.
capacitorsnexttoeachotherandawayfromtheSchottky
loop described above.
3. Do the LTC1708 feedback resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The R2 (Figure 8) connection should not be along
the high current input feeds from the input capacitor(s).
4. Are the SENSE – and SENSE+ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
oppositeschannel’svoltageandcurrentsensingfeedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC1708 and occupy minimum PC trace area.
SW1
D1
L1
R
SENSE1
V
OUT1
+
C
OUT1
R
L1
V
IN
+
R
IN
C
IN
SW2
L2
R
SENSE2
V
OUT2
+
D2
C
OUT2
R
L2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
1628 F11
Figure 11. Branch Current Waveforms
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7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/
SS pin(s) by resistors from VIN to prevent the short-circuit
latchoff from occurring.
ReduceVIN fromitsnominalleveltoverifyoperationofthe
regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the appli-
cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation thresh-
old—typically 10% to 20% of the maximum designed
current level in Burst Mode operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob-
lems coincide with high input voltages and low output
currents,lookforcapacitivecouplingbetweentheBOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en-
countered with high current output loading at lower input
voltages,lookforinductivecouplingbetweenCIN,Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com-
mon ground path voltage pickup between these compo-
nents and the SGND pin of the IC.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for their individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
topMOSFET. Thisoccursaround50%dutycycleoneither
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
Theoutputvoltageunderthisimproperhookupwillstillbe
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
29
LTC1708-PG
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TIGHTLY COUPLE
THESE CURRENT
SENSING FEEDBACK
PATHS
0.1µF
POWER GOOD
100k
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
L1
INTV
CC
RUN/SS1
PGOOD
TG1
2.2µH
V
OUT1
2
3
+
–
1.5V/2.5A
PEAK
SENSE1
SENSE1
EAIN1
0.015Ω
180pF
17.5k
1%
SW1
20k
1%
1000pF
0.1µF
D1
4
M1a
M1b
BOOST1
MBRM140T3
4.3k
5
FREQSET
STBYMD
FCB
V
IN
V
IN
1M
7.5V TO 24V
6
10Ω
10k
V
BG1
180µF 4V
PANASONIC SP
IN
0.01µF
CMDSH-3TR
0.1µF
7
5V
INTV
EXTV
CC
CC
CC
(OPTIONAL)
1000pF
LTC1708-PG
INTV
15k
8
I
10µF
35V
×3
TH1
270µF 2V
PANASONIC SP
×4
1µF
10V
33pF
4.7µF
9
SGND
PGND
BG2
100pF
CMDSH-3TR
10
11
12
13
14
15
16
17
18
3.3V
OUT
10µF
6.3V
CER
330pF
33k
68k
M2
M3
I
BOOST2
SW2
TH2
D2
0.47µF
MBRM340T3
EAIN2
0.003Ω
V
160k
OUT2
–
+
0.925V TO 2V
14A
SENSE2
SENSE2
TG2
1000pF
L2
1µH
INTV
CC
RUN/SS2
TIGHTLY COUPLE
THESE CURRENT
SENSING FEEDBACK
PATHS
ATTNOUT
ATTNIN
VID0
VIDV
INTV
CC
CC
1000pF
VID4
VID3
VID2
VID CONTROL
INPUTS
VID1
0.1µF
1708 F12
V
V
V
: 12V TO 22V
M1a, M1b: FDS6982
M2: IRF7811
M3: IRF7809
L1: 2.2µH
L2: 1µH
NOTE: ELECTRICAL PATHS DRAWN WITH THICK LINES
SHOULD BE KEPT AS SHORT AND WIDE AS POSSIBLE.
THESE PATHS WILL RADIATE EMI AT THE SWITCHING
FREQUENCY. KEEP THE PATHS’ ENCLOSED AREA SMALL.
IN
: 1.5V/2.5A
OUT1
OUT2
: 0.925V TO 2V/14A
SWITCHING FREQUENCY: 250kHz
Figure 12. LTC1708 High Efficiency, Constant Frequency CPU Core/IO Power Supply with Active Voltage Positioning
30
LTC1708-PG
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
12.67 – 12.93*
(0.499 – 0.509)
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.65 – 7.90
(0.301 – 0.311)
5
7
8
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.65
(0.0256)
BSC
0.13 – 0.22
0.55 – 0.95
(0.005 – 0.009)
(0.022 – 0.037)
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
G36 SSOP 1098
31
LTC1708-PG
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SENSE
1708i LT/TP 0200 4k • PRINTED IN USA
32 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2000
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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