LTC1735EGN#TR [Linear]
LTC1735 - High Efficiency Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC1735EGN#TR |
| 厂家： | 
Linear |
| 描述： | LTC1735 - High Efficiency Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 控制器 |
| 文件： | 总28页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3808
No RSENSETM, Low EMI,
Synchronous DC/DC Controller
with Output Tracking
U
FEATURES
DESCRIPTIO
The LTC®3808 is a synchronous step-down switching
regulator controller that drives external complementary
power MOSFETs using few external components. The
constantfrequencycurrentmodearchitecturewithMOSFET
VDS sensing eliminates the need for a current sense
resistor and improves efficiency.
■
Programmable Output Voltage Tracking
■
Sense Resistor Optional
■
Spread Spectrum Modulation for Low Noise
■
Constant Frequency Current Mode Operation for
Excellent Line and Load Transient Response
■
Wide VIN Range: 2.75V to 9.8V
■
Wide VOUT Range: 0.6V to VIN
Burst Mode operation provides high efficiency operation
at light loads. 100% duty cycle provides low dropout
operation, extending operating time in battery-powered
systems.
■
0.6V ±1.5% Reference
■
Low Dropout Operation: 100% Duty Cycle
■
True PLL for Frequency Locking or Adjustment
(Frequency Range: 250kHz to 750kHz)
Selectable Burst Mode®/Pulse Skipping/Forced
■
Theswitchingfrequencycanbeprogrammedupto750kHz,
allowing the use of small surface mount inductors and
capacitors. For noise sensitive applications, the LTC3808
can be externally synchronized from 250kHz to 750kHz.
Burst Mode is inhibited during synchronization or when
the SYNC/MODE pin is pulled low to reduce noise and RF
interference.TofurtherreduceEMI,theLTC3808incorpo-
rates a novel spread spectrum frequency modulation
technique.
Continuous Operation
■
■
■
■
■
■
Auxiliary Winding Regulation
Internal Soft-Start Circuitry
Power Good Output Voltage Monitor
Output Overvoltage Protection
Micropower Shutdown: IQ = 9µA
Tiny Thermally Enhanced Leadless (4mm × 3mm)
DFN or 16-lead SSOP Package
U
The LTC3808 is available in the tiny footprint thermally
enhanced DFN package or 16-lead SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode
is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5481178, 5929620, 6580258, 6304066,
5847554, 6611131, 6498466. Other Patents pending.
APPLICATIO S
■
One or Two Cell Lithium-Ion Powered Devices
Notebook and Palmtop Computers, PDAs
Portable Instruments
Distributed DC Power Systems
■
■
■
U
Efficiency and Power Loss vs Load Current
TYPICAL APPLICATIO
100
90
80
70
60
50
10k
EFFICIENCY
High Efficiency, 550kHz Step-Down Converter
V
= 3.3V
IN
V
1k
IN
2.75V TO 9.8V
V
= 4.2V
IN
V
IN
= 5V
10µF
1M
LTC3808
V
IN
+
100
10
PLLLPF
SENSE
SYNC/MODE
PGOOD
TYPICAL POWER
LOSS (V = 4.2V)
TG
IN
59k
2.2µH
47µF
V
OUT
V
SW
2.5V
2A
FB
15k
+
1
I
TH
BG
187k
FIGURE 11 CIRCUIT
RUN
IPRG
220pF
V
= 2.5V
OUT
GND
0.1
10k
1
10
100
1k
3808 TA01
LOAD CURRENT (mA)
3808 TA01b
3808f
1
LTC3808
W W U W
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (VIN)........................ –0.3V to 10V
PLLLPF, RUN, SYNC/MODE, TRACK/SS,
TG, BG Peak Output Current (<10µs)........................ 1A
Operating Temperature Range (Note 2)... – 40°C to 85°C
Storage Ambient Temperature Range ... –65°C to 125°C
Junction Temperature (Note 3)............................ 125°C
Lead Temperature (Soldering, 10 sec)
SENSE+, IPRG Voltages............ –0.3V to (VIN + 0.3V)
VFB, ITH Voltages...................................... –0.3V to 2.4V
SW, SENSE– Voltages......... –2V to VIN + 1V (10V Max)
PGOOD ..................................................... –0.3V to 10V
GN16 Package .................................................. 300°C
U
W U
PACKAGE/ORDER INFORMATION
TOP VIEW
ORDER PART
ORDER PART
TOP VIEW
NUMBER
NUMBER
GND
PLLLPF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SW
PLLLPF
SYNC/MODE
TRACK/SS
PGOOD
1
2
3
4
5
6
7
14 SW
–
+
–
+
SENSE
13 SENSE
LTC3808EDE
LTC3808EGN
12
V
SYNC/MODE
TRACK/SS
PGOOD
V
IN
IN
15
11 SENSE
SENSE
TG
V
10 TG
FB
I
9
8
BG
TH
V
BG
FB
DE PART
MARKING
RUN
IPRG
I
IPRG
GND
TH
DE PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
RUN
3808
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 15) IS GND
(MUST BE SOLDERED TO PCB)
TJMAX = 125°C, θJA = 130°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Operation
Sleep Mode
Shutdown
UVLO
(Note 4)
350
105
9
500
150
20
µA
µA
µA
µA
RUN = 0V
V
= UVLO Threshold – 200mV
9
20
IN
Undervoltage Lockout Threshold
V
V
Falling
Rising
●
●
1.95
2.15
2.25
2.45
2.55
2.75
V
V
IN
IN
Shutdown Threshold of RUN Pin
Start-Up Current Source
0.8
0.65
0.591
1.1
1
1.4
1.35
0.609
0.04
V
µA
TRACK/SS = 0V
(Note 5)
Regulated Feedback Voltage
Output Voltage Line Regulation
Output Voltage Load Regulation
●
0.6
0.01
V
2.75V < V < 9.8V (Note 5)
%/V
IN
I
I
= 0.9V (Note 5)
= 1.7V
0.1
–0.1
0.5
–0.5
%
%
TH
TH
V
Input Current
(Note 5)
9
50
nA
V
FB
Overvoltage Protect Threshold
Measured at V
0.66
0.68
0.7
FB
3808f
2
LTC3808
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
20
MAX
UNITS
mV
V
Overvoltage Protect Hysteresis
Auxiliary Feedback Threshold
Top Gate (TG) Drive Rise Time
Top Gate (TG) Drive Fall Time
Bottom Gate (BG) Drive Rise Time
Bottom Gate (BG) Drive Fall Time
Maximum Current Sense Voltage (∆V
0.325
0.4
40
0.475
C = 3000pF
L
ns
C = 3000pF
L
40
ns
CL = 3000pF
CL = 3000pF
50
ns
40
ns
)
IPRG = Floating (Note 6)
IPRG = 0V (Note 6)
●
●
●
110
70
185
125
85
204
140
100
223
mV
mV
mV
SENSE(MAX)
+
(SENSE – SW)
IPRG = V (Note 6)
IN
Soft-Start Time (Internal)
Oscillator and Phase-Locked Loop
Oscillator Frequency
Time for V to Ramp from 0.05V to 0.55V
0.5
0.74
0.9
ms
FB
Unsynchronized (SYNC/MODE Not Clocked)
PLLLPF = Floating
PLLLPF = 0V
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
PLLLPF = V
IN
Phase-Locked Loop Lock Range
SYNC/MODE Clocked
Minimum Synchronizable Frequency
Maximum Synchronizible Frequency
200
1000
250
kHz
kHz
750
Phase Detector Output Current
Sinking
Sourcing
f
f
> f
< f
–3
3
µA
µA
OSC
OSC
SYNC/MODE
SYNC/MODE
Spread Spectrum Frequency Range
Minimum Switching Frequency
Maximum Switching Frequency
460
635
kHz
kHz
SYNC/MODE Pull-Down Current
PGOOD Output
SYNC/MODE = 2.2V
2.6
µA
PGOOD Voltage Low
PGOOD Trip Level
I
Sinking 1mA
50
mV
PGOOD
V
with Respect to Set Output Voltage
FB
V
FB
V
FB
V
FB
V
FB
< 0.6V, Ramping Positive
< 0.6V, Ramping Negative
> 0.6V, Ramping Negative
> 0.6V, Ramping Positive
–13
–16
7
–10.0
–13.3
10.0
–7
–10
13
%
%
%
%
10
13.3
16
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 2: The LTC3808E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating range are
assured by design characterization, and correlation with statistical process
controls.
Note 5: The LTC3808 is tested in a feedback loop that servos I to a
TH
specified voltage and measures the resultant V voltage.
FB
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
3808f
3
LTC3808
TYPICAL PERFOR A CE CHARACTERISTICS
U W
TA = 25°C unless otherwise noted.
Maximum Current Sense Voltage
vs ITH Pin Voltage
Efficiency vs Load Current
Efficiency vs Load Current
100
80
60
40
20
0
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
50
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
Burst Mode OPERATION
V
= 2.5V
OUT
V
IN
= 5V, V
= 2.5V
(I RISING)
OUT
TH
Burst Mode OPERATION
V
OUT
= 3.3V
(I FALLING)
TH
FORCED CONTINUOUS
MODE
BURST MODE
(SYNC/MODE =
PULSE SKIPPING
MODE
V
OUT
= 1.2V
V
)
IN
FORCED
CONTINUOUS
(SYNC/MODE = 0V)
V
OUT
= 1.8V
PULSE SKIPPING
(SYNC/MODE = 0.6V)
SYNC/MODE = V
IN
V
= 5V
IN
–20
0.5
1
I
1.5
VOLTAGE (V)
2
1
10
100
1k
10k
1
10
100
1k
10k
LOAD CURRENT (mA)
LOAD CURRENT (mA)
TH
3808 G01
3808 G02
3808 G03
Load Step (Burst Mode
Operation)
Load Step (Forced Continuous
Mode)
Load Step (Pulse Skipping Mode)
V
V
V
OUT
OUT
OUT
200mV/DIV
200mV/DIV
200mV/DIV
AC COUPLED
AC COUPLED
AC COUPLED
I
I
I
L
L
L
2A/DIV
2A/DIV
2A/DIV
3808 G04
3808 G05
3808 G06
100µs/DIV
100µs/DIV
100µs/DIV
V
V
LOAD
SYNC/MODE = V
IN
FIGURE 11 CIRCUIT
= 3.3V
V
V
LOAD
SYNC/MODE = 0V
FIGURE 11 CIRCUIT
= 3.3V
V
= 3.3V
IN
IN
IN
= 1.8V
= 1.8V
V
= 1.8V
OUT
OUT
OUT
LOAD
I
= 300mA TO 3A
I
= 300mA TO 3A
I
= 300mA TO 3A
SYNC/MODE = V
FB
FIGURE 11 CIRCUIT
Start-Up with Internal Soft-Start
(TRACK/SS = VIN)
Start-Up with External Soft-Start
(CSS = 10nF)
V
V
OUT
OUT
1.8V
1.8V
500mV/DIV
500mV/DIV
3808 G07
3808 G08
200µs/DIV
1ms/DIV
V
= 4.2V
V
= 4.2V
IN
IN
R
= 1Ω
R
= 1Ω
LOAD
FIGURE 11 CIRCUIT
LOAD
FIGURE 11 CIRCUIT
3808f
4
LTC3808
U W
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Start-Up with Coincident Tracking
(VOUT = 0V at 0s)
Start-Up with Coincident Tracking
(VOUT = 0.8V at 0s)
Start-Up with Ratiometric
Tracking (VOUT = 0V at 0s)
V
V
V
x
2.5V
x
x
2.5V
2.5V
V
V
V
OUT
OUT
OUT
1.8V
1.8V
1.8V
500mV/DIV
500mV/DIV
500mV/DIV
3808 G09
3808 G10
3808 G11
10ms/DIV
10ms/DIV
10ms/DIV
V
R
R
= 4.2V
= 590Ω
= 1.18k
V
R
R
= 4.2V
= 590Ω
= 1.18k
V
R
R
= 4.2V
= 590Ω
= 1.69k
IN
TA
TB
IN
TA
TB
IN
TA
TB
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
Regulated Feedback Voltage vs
Temperature
Undervoltage Lockout Threshold
vs Temperature
Shutdown (RUN) Threshold vs
Temperature
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
1.20
1.15
1.10
1.05
1.00
0.606
0.604
0.602
0.600
0.598
0.596
0.594
V
RISING
IN
V
FALLING
IN
40 60
–60 –40 –20
TEMPERATURE (°C)
40 60
TEMPERATURE (°C)
40 60
0
20
80 100
–60 –40 –20
0
20
80 100
–60 –40 –20
0
20
80 100
TEMPERATURE (°C)
3808 G12
3808 G13
3808 G14
Maximum Current Sense
Threshold vs Temperature
TRACK/SS Start-Up Current vs
Temperature
1.04
135
130
125
120
115
IPRG = FLOAT
TRACK/SS = 0V
1.02
1.00
0.98
0.96
0.94
40 60
TEMPERATURE (°C)
40 60
TEMPERATURE (°C)
–60 –40 –20
0
20
80 100
–60 –40 –20
0
20
80 100
3808 G16
3808 G17
3808f
5
LTC3808
TYPICAL PERFOR A CE CHARACTERISTICS
U W
TA = 25°C unless otherwise noted.
SYNC/MODE Pull-Down Current
vs Temperature
Oscillator Frequency vs
Temperature
Oscillator Frequency vs Input
Voltage
10
8
5
4
2.80
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
6
3
4
2
2
1
0
0
–2
–4
–6
–8
–10
–1
–2
–3
–4
–5
40 60
–60 –40 –20
TEMPERATURE (°C)
7
8
0
20
80 100
2
3
4
5
6
9
10
40 60
–60 –40 –20
TEMPERATURE (°C)
0
20
80 100
INPUT VOLTAGE (V)
3808 G19
3808 G20
3808 G18
Shutdown Quiescent Current vs
Input Voltage
TRACK/SS Start-Up Current vs
TRACK/SS Voltage
Sleep Current vs Input Voltage
18
16
14
12
10
8
130
120
110
100
90
1.04
1.00
0.96
0.92
0.88
0.84
6
4
80
2
0
70
7
8
7
8
0.5 0.6
TRACK/SS VOLTAGE (V)
2
3
4
5
6
9
10
2
3
4
5
6
9
10
0
0.1 0.2 0.3 0.4
0.7
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3808 G21
3808 G22
3808 G24
3808f
6
LTC3808
U
U
U
PI FU CTIO S (DFN/SSOP)
PLLLPF (Pin 1/Pin 2): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the low pass filter point for the phase-locked loop.
Normally, a series RC is connected between this pin and
ground.
PGOOD (Pin 4/Pin 5): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on the feedback pin VFB is not within
±13.3% of its nominal set point.
VFB (Pin 5/Pin 6): Feedback Pin. This pin receives the
remotely sensed feedback voltage for the controller from
an external resistor divider across the output.
Whennotsynchronizingtoanexternalclock,thispinserves
asthefrequencyselectinput. TyingthispintoGNDselects
300kHz operation; tying this pin to VIN selects 750kHz
operation. Floating this pin selects 550kHz operation.
ITH (Pin 6/Pin 7): Current Threshold and Error Amplifier
Compensation Point. Nominal operating range on this pin
is from 0.7V to 2V. The voltage on this pin determines the
threshold of the main current comparator.
Connect a 2.2nF capacitor between this pin and GND and
a 1000pF capacitor between this pin and the SYNC/MODE
when using spread spectrum modulation operation.
RUN (Pin 7/Pin 8): Run Control Input. Forcing this pin
below 1.1V shuts down the chip. Driving this pin to VIN or
releasing this pin enables the chip to start-up either by
tracking the external voltage at the TRACK/SS pin or with
theinternal/externalsoft-start,allbasedontheconnection
at the TRACK/SS pin.
SYNC/MODE (Pin 2/Pin 3): This pin performs four func-
tions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, 3)
Burst Mode, pulse skipping or forced continuous mode
select, and 4) enable spread spectrum modulation opera-
tion in pulse skipping mode. Applying a clock with fre-
quency between 250kHz to 750kHz causes the internal
oscillator to phase-lock to the external clock and disables
Burst Mode operation but allows pulse skipping at low
load currents.
IPRG (Pin 8/Pin 10): Three-State Pin to Select Maximum
Peak Sense Voltage Threshold. This pin selects the maxi-
mum allowed voltage drop between the SENSE+ and
SENSE– or SW pins (i.e., the maximum allowed drop
across the sense resistor or the external P-channel
MOSFET). Tie to VIN, GND or float to select 204mV, 85mV
or 125mV respectively.
To select Burst Mode operation at light loads, tie this pin
to VIN. Grounding this pin selects forced continuous
operation, which allows the inductor current to reverse.
Tying this pin to VFB selects pulse skipping mode. In these
cases, the frequency of the internal oscillator is set by the
voltage on the PLLLPF pin. Tying to a voltage between
1.35V to VIN – 0.5V enables spread spectrum modulation
operation. In this case, an internal 2.6µA pull-down cur-
rent source helps to set the voltage at this pin by tying a
resistor with appropriate value between this pin and VIN.
Do not leave this pin floating.
BG (Pin 9/Pin 11): Bottom (NMOS) Gate Drive Output.
ThispindrivesthegateoftheexternalN-channelMOSFET.
This pin has an output swing from GND to SENSE+.
TG (Pin 10/Pin 12): Top (PMOS) Gate Drive Output. This
pindrivesthegateoftheexternalP-channelMOSFET. This
pin has an output swing from GND to SENSE+.
SENSE+ (Pin 11/Pin 13): Positive Input to Differential
Current Comparator. Also powers the gate drivers. Nor-
mally connected to the source of the external P-channel
MOSFET when the sense resistor is not used. Otherwise,
it is connected to the sense resistor.
TRACK/SS (Pin 3/Pin 4): Tracking Input for the Controller
or Optional External Soft-Start Input. This pin allows the
start-up of VOUT to “track” the external voltage at this pin
using an external resistor divider. Tying this pin to VIN
allows VOUT start-up with the internal 1ms soft-start
clamp. An external soft-start can be programmed by
connecting a capacitor between this pin and ground. Do
not leave this pin floating.
VIN (Pin 12/Pin 14): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Exter-
nally filtering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
3808f
7
LTC3808
U
U
U
PI FU CTIO S (DFN/SSOP)
SENSE– (Pin 13/Pin 15): Negative Input to Differential
Current Comparator. Normally is connected to the SW pin
when the sense resistor is not used. When using a current
sense resistor, connect the resistor between SENSE+ and
SENSE– and connect the source of the P-channel MOSFET
to the SENSE– pin.
Normally this pin is connected to the drain of the external
P-channel MOSFET, the drain of the external N-channel
MOSFET and the inductor.
GND (Pin 15/Pins 1, 9): Ground connection for internal
circuits, the gate drivers and the negative input to the
reverse current comparator. The exposed pad (Pin 15 in
DFN package) must be soldered to the PCB ground.
SW (Pin 14/Pin 16): Switch Node Connection to Inductor.
Thispinisalsoaninputtothereversecurrentcomparator.
U
U
W
FU CTIO AL DIAGRA
V
IN
C
IN
V
IN
–
SENSE
+
SENSE
I
PRG
PV
IN
VOLTAGE
REFERENCE
V
REF
SLOPE
TG
0.6V
CLK
S
R
MP
MN
+
–
Q
GND
ICMP
+
UNDERVOLTAGE
LOCKOUT
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
SENSE
L
ANTI-SHOOT-
THROUGH
V
OUT
C
OUT
SW
V
IN
PV
IN
V
IN
BG
UVSD
0.7µA
RUN
GND
+
–
FCB
SLEEP
t = 1ms
V
IN
INTERNAL
+
0.15V
SOFT-START
OV
REV
I
0.68V
–
BURSTDIS
1µA
R
MUX
B
TRK/SS
TRACK/SS
0.3V
+
0.54V
+
–
BURST DEFEAT
CLOCK DETECT
BURSTDIS
FCB
SYNC/MODE
UV
PHASE
–
V
DETECTOR
FB
0.4V
2.6µA
I
TH
R
C
V
REF
+
+
–
C
0.6V
C
TRK/SS
FB
EAMP
PLLLPF
V
V
CO
R
A
CLK
V
IN
3808 FD
SW
+
–
PGOOD
GND
I
RICMP
REV
OV
UV
UVSD
GND
3808f
8
LTC3808
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
by releasing the RUN pin, the TRACK/SS pin is charged up
by an internal 1µA current source and rises linearly from
0V to above 0.6V. The error amplifier EAMP compares the
feedbacksignalVFB tothisrampinstead,andregulatesVFB
linearly from 0V to 0.6V.
The LTC3808 uses a constant frequency, current mode
architecture. During normal operation, the top external
P-channel power MOSFET is turned on when the clock
sets the RS latch, and is turned off when the current
comparator (ICMP) resets the latch. The peak inductor
currentatwhichICMPresetstheRSlatchisdeterminedby
the voltage on the ITH pin, which is driven by the output of
theerroramplifier(EAMP).TheVFB pinreceivestheoutput
voltage feedback signal from an external resistor divider.
This feedback signal is compared to the internal 0.6V
reference voltage by the EAMP. When the load current
increases, it causes a slight decrease in VFB relative to the
0.6V reference, which in turn causes the ITH voltage to
increase until the average inductor current matches the
new load current. While the top P-channel MOSFET is off,
thebottomN-channelMOSFETisturnedonuntileitherthe
inductor current starts to reverse, as indicated by the
current reversal comparator IRCMP, or the beginning of
the next cycle.
When the voltage on the TRACK/SS pin is less than the
0.6V internal reference, the LTC3808 regulates the VFB
voltagetotheTRACK/SSpininsteadofthe0.6Vreference.
Therefore VOUT of the LTC3808 can track an external
voltage VX during start-up. Typically, a resistor divider on
VX is connected to the TRACK/SS pin to allow the start-up
ofVOUT to“track”thatofVX.Forcoincidenttrackingduring
start-up, the regulated final value of VX should be larger
than that of VOUT, and the resistor divider on VX has the
same ratio as the divider on VOUT that is connected to VFB.
See detailed discussions in the Run and Soft-Start/
Tracking Functions in the Applications Information
Section.
Light Load Operation (Burst Mode Operation,
Continuous Conduction or Pulse Skipping Mode)
(SYNC/MODE Pin)
Shutdown, Soft-Start and Tracking Start-Up
(RUN and TRACK/SS Pins)
The LTC3808 can be programmed for either high effi-
ciency Burst Mode operation, forced continuous conduc-
tion mode or pulse skipping mode at low load currents. To
select Burst Mode operation, tie the SYNC/MODE pin to
VIN. To select forced continuous operation, tie the SYNC/
MODE pin to a DC voltage below 0.4V (e.g., GND). Tying
the SYNC/MODE to a DC voltage above 0.4V and below
1.2V (e.g., VFB) enables pulse skipping mode. The 0.4V
threshold between forced continuous operation and pulse
skipping mode can be used in secondary winding regula-
tion as described in the Auxiliary Winding Control Using
SYNC/MODE Pin discussion in the Applications Informa-
tion section.
The LTC3808 is shut down by pulling the RUN pin low. In
shutdown, all controller functions are disabled and the
chip draws only 9µA. The TG output is held high (off) and
the BG output low (off) in shutdown. Releasing the RUN
pin allows an internal 0.7µA current source to pull up the
RUNpintoVIN.ThecontrollerisenabledwhentheRUNpin
reaches 1.1V.
The start-up of VOUT is based on the three different
connections on the TRACK/SS pin. The start-up of VOUT
is controlled by the LTC3808’s internal soft-start when
TRACK/SSisconnectedtoVIN.Duringsoft-start,theerror
amplifier EAMP compares the feedback signal VFB to the
internal soft-start ramp (instead of the 0.6V reference),
which rises linearly from 0V to 0.6V in about 1ms. This
allows the output voltage to rise smoothly from 0V to its
final value while maintaining control of the inductor
current.
When the LTC3808 is in Burst Mode operation, the peak
current in the inductor is set to approximate one-fourth of
the maximum sense voltage even though the voltage on
the ITH pin indicates a lower value. If the average inductor
current is higher than the load current, the EAMP will
decrease the voltage on the ITH pin. When the ITH voltage
drops below 0.85V, the internal SLEEP signal goes high
and the external MOSFET is turned off.
The 1ms soft-start time can be changed by connecting the
optional external soft-start capacitor CSS between the
TRACK/SS and GND pins. When the controller is enabled
3808f
9
LTC3808
U
(Refer to Functional Diagram)
OPERATIO
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3808 draws.
Theloadcurrentissuppliedbytheoutputcapacitor.Asthe
output voltage decreases, the EAMP increases the ITH
voltage. When the ITH voltage reaches 0.925V, the SLEEP
signal goes low and the controller resumes normal opera-
tion by turning on the external P-channel MOSFET on the
next cycle of the internal oscillator.
Short-Circuit and Current Limit Protection
The LTC3808 monitors the voltage drop ∆VSC (between
the GND and SW pins) across the external N-channel
MOSFET with the short-circuit current limit comparator.
The allowed voltage is determined by:
∆VSC(MAX) = A • 90mV
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to GND selects A = 2/3.
When the controller is enabled for Burst Mode or pulse
skipping operation, the inductor current is not allowed to
reverse. Hence, the controller operates discontinuously.
The reverse current comparator RICMP senses the drain-
to-source voltage of the bottom external N-channel
MOSFET. This MOSFET is turned off just before the
inductor current reaches zero, preventing it from going
negative.
The inductor current limit for short-circuit protection is
determined by ∆VSC(MAX) and the on-resistance of the
external N-channel MOSFET:
∆VSC(MAX)
ISC
=
RDS(ON)
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions.Thepeakinductorcurrentisdeterminedbythe
voltageontheITH pin. TheP-channelMOSFETisturnedon
every cycle (constant frequency) regardless of the ITH pin
voltage. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and no noise at
audio frequencies.
Once the inductor current exceeds ISC, the short current
comparator will shut off the external P-channel MOSFET
until the inductor current drops below ISC.
Output Overvoltage Protection
As further protection, the overvoltage comparator (OVP)
guardsagainsttransientovershoots,aswellasothermore
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
When the SYNC/MODE pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), or is set to a DC
voltage between 0.4V and several hundred mV below VIN,
the LTC3808 operates in PWM pulse skipping mode at
light loads. In this mode, the current comparator ICMP
may remain tripped for several cycles and force the
external P-channel MOSFET to stay off for the same
number of cycles. The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuousoperation, exhibitslowoutputrippleaswellas
low audio noise and reduced RF interference as compared
to Burst Mode operation. However, it provides low current
efficiency higher than forced continuous mode, but not
nearlyashighasBurstModeoperation. Duringstart-upor
an undervoltage condition (VFB ≤ 0.54V), the LTC3808
operates in pulse skipping mode (no current reversal
allowed), regardless of the state of the SYNC/MODE pin.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage.
The switching frequency of the LTC3808’s controllers can
be selected using the PLLLPF pin. If the SYNC/MODE is
not being driven by an external clock source, the PLLLPF
can be floated, tied to VIN or tied to GND to select 550kHz,
750kHz or 300kHz, respectively.
3808f
10
LTC3808
U
(Refer to Functional Diagram)
OPERATIO
A phase-locked loop (PLL) is available on the LTC3808 to
synchronize the internal oscillator to an external clock
source that connects to the SYNC/MODE pin. In this case,
a series RC should be connected between the PLLLPF pin
and GND to serve as the PLL’s loop filter. The LTC3808
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external P-channel MOSFET to the
rising edge of the synchronizing signal.
Dropout Operation
When the input supply voltage (VIN) approaches the
output voltage, the rate of change of the inductor current
while the external P-channel MOSFET is on
(ON cycle) decreases. This reduction means that the
P-channel MOSFET will remain on for more than one
oscillator cycle if the inductor current has not ramped up
to the threshold set by the EAMP on the ITH pin. Further
reduction in the input supply voltage will eventually cause
the P-channel MOSFET to be turned on 100%; i.e., DC.
The output voltage will then be determined by the input
voltage minus the voltage drop across the P-channel
MOSFET and the inductor.
The typical capture range of the LTC3808’s phase-locked
loop is from approximately 200kHz to 1MHz.
Spread Spectrum Modulation (SYNC/MODE and
PLLLPF Pins)
Connecting the SYNC/MODE pin to a DC voltage above
1.35V and several hundred mV below VIN enables spread
spectrum modulation (SSM) operation. An internal 2.6µA
pull-down current source at SYNC/MODE helps to set the
voltage at the SYNC/MODE pin for this operation by tying
a resistor with appropriate value between SYNC/MODE
and VIN. This mode of operation spreads the internal
oscillator frequency fOSC (= 550kHz) over a wider range
(460kHz to 635kHz), reducing the peaks of the harmonic
output on a spectral analysis of the output noise. In this
case, a 2.2nF filter cap should be connected between the
PLLLPF pin and GND and another 1000pF cap should be
connected between PLLLPF and the SYNC/MODE pin. The
controller operates in PWM pulse skipping mode at light
loads when spread spectrum modulation is selected. See
more discussions in the Spread Spectrum Modulation
with SYNC/MODE and PLLLPF Pins in the Applications
Information section.
Undervoltage Lockout
To prevent operation of the P-channel MOSFET below
safe input voltage levels, an undervoltage lockout is
incorporated in the LTC3808. When the input supply
voltage (VIN) drops below 2.25V, the external P- and
N-channel MOSFETs and all internal circuits are turned
off except for the undervoltage block, which draws only
a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG Pin)
WhentheLTC3808controllerisoperatingbelow20%duty
cycle,thepeakcurrentsensevoltage(betweentheSENSE+
and SENSE–/SW pins) allowed across the external P-
channel MOSFET is determined by:
V
ITH – 0.7V
∆VSENSE(MAX) = A •
10
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to GND selects A = 2/3. The
3808f
11
LTC3808
U
(Refer to Functional Diagram)
OPERATIO
If a sense resistor is used, ∆VSENSE(MAX) is the peak
current sense voltage (between the SENSE+ and SENSE–
pins) across the sense resistor. The peak inductor is
determined by the peak sense voltage and the resistance
of the sense resistor:
maximum value of VITH is typically about 1.98V, so the
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peaksensevoltagebyascalefactor(SF)givenbythecurve
in Figure 1.
∆VSENSE(MAX)
IPK
=
RSENSE
Thepeakinductorcurrentisdeterminedbythepeaksense
voltage and the on-resistance of the external P-channel
MOSFET:
Power Good (PGOOD) Pin
A window comparator monitors the feedback voltage and
the open-drain PGOOD output pin is pulled low when the
feedback voltage is not within ±10% of the 0.6V reference
voltage. PGOOD is low when the LTC3808 is shut down or
in undervoltage lockout.
∆VSENSE(MAX)
IPK
=
RDS(ON)
110
100
90
80
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3808 F01
Figure 1. Maximum Peak Current vs Duty Cycle
3808f
12
LTC3808
W U U
APPLICATIO S I FOR ATIO
U
The typical LTC3808 application circuit is shown on
Figure 11. External component selection for the controller
is driven by the load requirement and begins with the
selection of the inductor and the power MOSFETs.
where IRIPPLE is the inductor peak-to-peak ripple current
(see Inductor Value Calculation).
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
Power MOSFET Selection
∆VSENSE(MAX)
IOUT(MAX)
5
6
The LTC3808’s controller requires two external power
MOSFETs: a P-channel MOSFET for the topside (main)
switch and a N-channel MOSFET for the bottom (synchro-
nous) switch. The main selection criteria for the power
MOSFETs are the breakdown voltage VBR(DSS), threshold
voltage VGS(TH), on-resistance RDS(ON), reverse transfer
capacitance CRSS, turn-off delay tD(OFF) and the total gate
charge QG.
RDS(ON)MAX
=
•
for Duty Cycle < 20%
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
∆VSENSE(MAX)
IOUT(MAX)
5
6
RDS(ON)MAX
=
• SF •
Thegatedrivevoltageistheinputsupplyvoltage.Sincethe
LTC3808 is designed for operation down to low input
voltages, a sublogic level MOSFET (RDS(ON) guaranteed at
VGS = 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3808 is less than the
absolute maximum MOSFET VGS rating, which is typically
8V.
whereSFisascalefactorwhosevalueisobtainedfromthe
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
Thefollowingequationisagoodguidefordeterminingthe
required RDS(ON)MAX at 25°C (manufacturer’s specifica-
tion), allowing some margin for variations in the LTC3808
and external component values:
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average load
current IOUT(MAX) is equal to the peak inductor current
minus half the peak-to-peak ripple current IRIPPLE. The
LTC3808’s current comparator monitors the drain-to-
source voltage VDS of the top P-channel MOSFET, which
is sensed between the SENSE+ and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the ITH pin, of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆VSENSE(MAX) to
approximately 125mV when IPRG is floating (85mV when
IPRG is tied low; 204mV when IPRG is tied high).
∆VSENSE(MAX)
IOUT(MAX) • ρT
5
6
RDS(ON)MAX = • 0.9 • SF •
The ρT is a normalizing term accounting for the tempera-
ture variation in on-resistance, which is typically about
0.4%/°C, asshowninFigure2. Junction-to-casetempera-
ture TJC is about 10°C in most applications. For a maxi-
mum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The N-channel MOSFET’s on resistance is chosen based
on the short-circuit current limit (ISC). The LTC3808’s
short-circuit current limit comparator monitors the drain-
to-source voltage VDS of the bottom N-channel MOSFET,
The output current that the LTC3808 can provide is given
by:
∆VSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
RDS(ON)
2
3808f
13
LTC3808
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APPLICATIO S I FOR ATIO
2.0
VOUT
V
IN
Top P-Channel Duty Cycle =
1.5
1.0
0.5
0
V – VOUT
IN
Bottom N-Channel Duty Cycle =
V
IN
The MOSFET power dissipations at maximum output
current are:
VOUT
V
IN
2
PTOP
=
•IOUT(MAX)2 •ρT •RDS(ON) + 2•V
IN
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
•IOUT(MAX) •CRSS • f
V – VOUT
3808 F02
IN
PBOT
=
•IOUT(MAX)2 •ρT •RDS(ON)
Figure 2. RDS(ON) vs Temperature
V
IN
Both MOSFETs have I2R losses and the PTOP equation
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short-circuit
when the bottom duty cycle is 100%.
whichissensedbetweentheGNDandSWpins. Theshort-
circuit current sense threshold ∆VSC is set approximately
90mVwhenIPRGisfloating(60mVwhenIPRGistiedlow;
150mV when IPRG is tied high). The on-resistance of N-
channel MOSFET is determined by:
The LTC3808 utilizes a non-overlapping, anti-shoot-
through gate drive control scheme to ensure that the P-
and N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications. Many power MOSFETs, particularly P-chan-
nel MOSFETs, are intended to be used as static switches
and therefore are slow to turn on or off.
∆VSC
ISC(PEAK)
RDS(ON)MAX
=
The short-circuit current limit (ISC(PEAK)) should be larger
than the IOUT(MAX) with some margin to avoid interfering
with the peak current sensing loop. On the other hand, in
order to prevent the MOSFETs from excessive heating and
the inductor from saturation, ISC(PEAK) should be smaller
than the minimum value of their current ratings. A reason-
able range is:
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
tD(OFF) withgatedrive(VIN)voltage,theP-channelMOSFET
ultimately should be evaluated in the actual LTC3808
application circuit to ensure proper operation.
IOUT(MAX) < ISC(PEAK) < IRATING(MIN)
Therefore,theon-resistanceofN-channelMOSFETshould
be chosen within the following range:
∆VSC
IRATING(MIN)
∆VSC
IOUT(MAX)
< RDS(ON)
<
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage in-
creases,iftheinputsupplycurrentincreasesdramatically,
then the likely cause is shoot-through. Note that some
MOSFETsthatdonotworkwellathighinputvoltages(e.g.,
where ∆VSC is 90mV, 60mV or 150mV with IPRG being
floated, tied to GND or VIN respectively.
The power dissipated in the MOSFET strongly depends on
its respective duty cycles and load current. When the
LTC3808isoperatingincontinuousmode, thedutycycles
for the MOSFETs are:
3808f
14
LTC3808
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APPLICATIO S I FOR ATIO
VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
spread spectrum operation. Pulling the PLLLPF to VIN
selects 750kHz operation; pulling the PLLLPF to GND
selects 300kHz operation.
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turn-
off delays are much smaller than for a P-channel MOSFET.
Alternatively,theLTC3808willphase-locktoaclocksignal
applied to the SYNC/MODE pin with a frequency between
250kHz and 750kHz (see Phase-Locked Loop and Fre-
quency Synchronization).
Using a Sense Resistor
AsenseresistorRSENSE canbeconnectedbetweenSENSE+
and SENSE– to sense the output load current. In this case,
the source of the P-channel MOSFET is connected to
SENSE– pin and the drain is connected to SW pin of
LTC3808. Therefore the current comparator monitors the
voltage developed across RSENSE instead of VDS of the
P-channel MOSFET. The output current that the LTC3808
can provide in this case is given by:
To further reduce EMI, the nominal 550kHz frequency will
be spread over a range with frequencies between 460kHz
and 635kHz when spread spectrum modulation is
enabled (see Spread Spectrum Modulation with
SYNC/MODE and PLLLPF Pins).
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor’s peak-to-peak ripple current:
∆VSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
RSENSE
2
Setting ripple current as 40% of IOUT(MAX) and using
Figure 1 to choose SF, the value of RSENSE is:
VOUT V – VOUT
IN
IRIPPLE
=
•
V
fOSC •L
IN
∆VSENSE(MAX)
IOUT(MAX)
5
6
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
R
SENSE = • SF •
See the P-channel RDS(ON) selection in Power MOSFET
Selection.
Variation in the resistance of a sense resistor is much
smaller than the variation in on-resistance of the external
MOSFET. Thereforetheloadcurrentiswellcontrolledwith
a sense resistor. However the sense resistor causes extra
I2R losses in addition to the I2R losses of the MOSFET.
Therefore, using a sense resistor lowers the efficiency of
LTC3808, especially for large load current.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
V – VOUT VOUT
IN
L ≥
•
fOSC •IRIPPLE
V
IN
Operating Frequency and Synchronization
The choice of operating frequency, fOSC, is a trade-off
between efficiency and component size. Low frequency
operationimprovesefficiencybyreducingMOSFETswitch-
ing losses, both gate charge loss and transition loss.
However, lowerfrequencyoperationrequiresmoreinduc-
tance for a given amount of ripple current.
Burst Mode Operation Considerations
The choice of RDS(ON) and inductor value also determines
the load current at which the LTC3808 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
The internal oscillator for the LTC3808’s controller runs at
a nominal 550kHz frequency when the PLLLPF pin is left
floating and the SYNC/MODE pin is not configured for
∆VSENSE(MAX)
1
4
IBURST(PEAK)
=
•
RDS(ON)
3808f
15
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APPLICATIO S I FOR ATIO
Thecorrespondingaveragecurrentdependsontheamount
inductors wound on bobbins are generally easier to sur-
face mount. However, designs for surface mount that do
not increase the height significantly are available from
Coiltronics, Coilcraft, Dale and Sumida.
of ripple current. Lower inductor values (higher IRIPPLE
)
willreducetheloadcurrentatwhichBurstModeoperation
begins.
The ripple current is normally set so that the inductor
current is continuous during the burst periods. Therefore,
Schottky Diode Selection (Optional)
The schottky diode D in Figure 12 conducts current during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
N-channel MOSFET from turning on and storing charge
during the dead time, which could cost as much as 1% in
efficiency. A 1A Schottky diode is generally a good size for
most LTC3808 applications, since it conducts a relatively
small average current. Larger diode results in additional
transition losses due to its larger junction capacitance.
This diode may be omitted if the efficiency loss can be
tolerated.
IRIPPLE ≤ IBURST(PEAK)
This implies a minimum inductance of:
V – VOUT
fOSC •IBURST(PEAK)
VOUT
V
IN
IN
LMIN
≤
•
A smaller value than LMIN could be used in the circuit,
although the inductor current will not be continuous
during burst periods, which will result in slightly lower
efficiency. In general, though, it is a good idea to keep
IRIPPLE comparable to IBURST(PEAK)
.
CIN and COUT Selection
Inductor Core Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT/VIN). To
preventlargevoltagetransients, alowESRinputcapacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
Once the value of L is known, the type of inductor must be
selected.Highefficiencyconvertersgenerallycannotafford
the core loss found in low cost powdered iron cores, forc-
ingtheuseofmoreexpensiveferrite,molypermalloyorKool
Mµ® cores. Actual core loss is independent of core size for
a fixed inductor value, but is very dependent on the induc-
tance selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
1/2
VOUT • V – V
(
)
IN
OUT
CINRequiredIRMS ≈IMAX
•
V
IN
This formula has a maximum value at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturer’s
ripplecurrentratingsareoftenbasedon2000hoursoflife.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet the
size or height requirements in the design. Due to the high
operating frequency of the LTC3808, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
Ferritedesignshaveverylowcorelossesandarepreferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard”, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. Core saturation results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when several layers of wire can be used, while
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
Kool Mµ is a registered trademark of Magnetics, Inc.
3808f
16
LTC3808
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APPLICATIO S I FOR ATIO
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
U
3.3V OR 5V
LTC3808
RUN
LTC3808
RUN
⎛
1
⎞
3808 F04
∆VOUT ≈ IRIPPLE • ESR +
⎜
⎟
⎝
8• f •COUT
⎠
Figure 4. RUN Pin Interfacing
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increase with input voltage.
Once the controller is enabled, the start-up of VOUT is
controlled by the state of the TRACK/SS pin. If the TRACK/
SS pin is connected to VIN, the start-up of VOUT is con-
trolled by internal soft-start, which slowly ramps the
positive reference to the error amplifier from 0V to 0.6V,
allowing VOUT to rise smoothly from 0V to its final value.
The default internal soft-start time is around 1ms. The
soft-start time can be changed by placing a capacitor
betweentheTRACK/SSpinandGND. Inthiscase, thesoft-
start time will be approximately:
Setting Output Voltage
The LTC3808 output voltage is set by an external feedback
resistor divider carefully placed across the output, as
shown in Figure 3. The regulated output voltage is deter-
mined by:
⎛
RB ⎞
RA ⎠
VOUT = 0.6V • 1+
⎜
⎟
⎝
600mV
1µA
t
SS = CSS •
For most applications, a 59k resistor is suggested for RA.
In applications where minimizing the quiescent current is
critical, RA should be made bigger to limit the feedback
divider current. If RB then results in very high impedance,
it may be beneficial to bypass RB with a 50pF to 100pF
capacitor CFF.
where 1µA is an internal current source which is always
on.
When the voltage on the TRACK/SS pin is less than the
internal 0.6V reference, the LTC3808 regulates the VFB
voltage to the TRACK/SS pin voltage instead of 0.6V.
Therefore the start-up of VOUT can ratiometrically track an
external voltage VX, according to a ratio set by a resistor
divider at TRACK/SS pin (Figure 5a). The ratiometric
relation between VOUT and VX is (Figure 5c):
V
OUT
R
B
C
FF
LTC3808
V
FB
R
A
VOUT RTA RA +RB
3808 F03
=
•
VX
RA
RTA +RTB
Figure 3. Setting Output Voltage
V
OUT
Run and Soft-Start/Tracking Functions
V
X
LTC3808
R
B
A
The LTC3808 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 1.1V
puts the LTC3808 into a low quiescent current shutdown
mode (IQ = 9µA). Releasing the RUN pin, an internal 0.7µA
(at VIN = 4.2V) current source will pull the RUN pin up to
VIN, which enables the controller. The RUN pin can be
driven directly from logic as showed in Figure 4.
V
R
R
FB
TB
TA
R
TRACK/SS
3808 F5a
Figure 5a. Using the TRACK/SS Pin to Track VX
3808f
17
LTC3808
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APPLICATIO S I FOR ATIO
V
V
V
X
X
V
OUT
OUT
3808 F05b,c
TIME
TIME
(5b) Coincident Tracking
(5c) Ratiometric Tracking
Figure 5b and 5c. Two Different Modes of Output Voltage Tracking
For coincident tracking (VOUT = VX during start-up),
RTA = RA, RTB = RB
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
VX should always be greater than VOUT when using the
tracking function of TRACK/SS pin.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
MODE, is shown in Figure 6 and specified in the electrical
characteristics table. Note that the LTC3808 can only be
synchronized to an external clock whose frequency is
within range of the LTC3808’s internal VCO, which is
The internal current source (1µA), which is for external
soft-start, will cause a tracking error at VOUT. For example,
if a 59k resistor is chosen for RTA, the RTA current will be
about 10µA (600mV/59k). In this case, the 1µA internal
current source will cause about 10% (1µA/10µA • 100%)
tracking error, which is about 60mV (600mV • 10%)
referred to VFB. This is acceptable for most applications. If
a better tracking accuracy is required, the value of RTA
should be reduced.
1200
1000
800
600
400
200
0
Table 1 summarizes the different states in which the
TRACK/SS can be used.
Table 1. The States of the TRACK/SS Pin
TRACK/SS Pin
Capacitor C
FREQUENCY
External Soft-Start
Internal Soft-Start
SS
V
IN
Resistor Divider
V
Tracking an External Voltage V
OUT X
Phase-Locked Loop and Frequency Synchronization
0.2
0.7
1.2
1.7
2.2
PLLLPF PIN VOLTAGE (V)
TheLTC3808hasaphase-lockedloop(PLL)comprisedof
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the external P-channel
MOSFETtobelockedtotherisingedgeofanexternalclock
signal applied to the SYNC/MODE pin. The phase detector
3808 F06
Figure 6. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
3808f
18
LTC3808
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APPLICATIO S I FOR ATIO
U
2.4V
Table 2. The States of the PLLLPF Pin
PLLLPF PIN
R
LP
SYNC/MODE PIN
FREQUENCY
C
LP
0V
DC Voltage (<1.2V or V )
300kHz
550kHz
750kHz
PLLLPF
IN
SYNC/
MODE
Floating
DC Voltage (<1.2V or V )
DIGITAL
PHASE/
FREQUENCY
DETECTOR
IN
EXTERNAL
OSCILLATOR
V
IN
DC Voltage (<1.2V or V )
IN
OSCILLATOR
RC Loop Filter Clock Signal
Phase-Locked
to External Clock
Filter Caps DC Voltage (>1.35V and <V – 0.5V)
Spread Spectrum
460kHz to 635kHz
IN
3808 F07
Auxiliary Winding Control Using SYNC/MODE Pin
Figure 7. Phase-Locked Loop Block Diagram
The SYNC/MODE pin can be used as an auxiliary feedback
to provide a means of regulating a flyback winding output.
When this pin drops below its ground-referenced 0.4V
threshold, continuous mode operation is forced.
nominally 200kHz to 1MHz. This is guaranteed, over
temperatureandprocessvariations,tobebetween250kHz
and 750kHz. A simplified block diagram is shown in
Figure 7.
During continuous mode, current flows continuously in
the transformer primary side. The auxiliary winding draws
current only when the bottom synchronous N-channel
MOSFET is on. When primary load currents are low and/
or the VIN/VOUT ratio is close to unity, the synchronous
MOSFET may not be on for a sufficient amount of time to
transfer power from the output capacitor to the auxiliary
load. Forced continuous operation will support an auxil-
iary winding as long as there is a sufficient synchronous
MOSFET duty factor. The SYNC/MODE input pin removes
the requirement that power must be drawn from the
transformer primary side in order to extract power from
the auxiliary winding. With the loop in continuous mode,
the auxiliary output may nominally be loaded without
regard to the primary output load.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
PLLLPFpin. Iftheexternalandinternalfrequenciesarethe
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor CLP holds the voltage.
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
The auxiliary output voltage VAUX is normally set, as
shown in Figure 8, by the turns ratio N of the transformer:
VAUX = (N + 1) • VOUT
V
AUX
V
IN
Typically, the external clock (on SYNC/MODE pin) input
high level is 1.6V, while the input low level is 1.2V.
+
LTC3808
TG
SYNC/MODE
SW
L1
1:N
1µF
R6
R5
V
OUT
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
+
C
OUT
BG
3808 F08
Figure 8. Auxiliary Output Loop Connection
3808f
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APPLICATIO S I FOR ATIO
460kHz and 635kHz in spread spectrum modulation op-
eration. Figure 9 shows the spectral plots of the output
(VOUT) noise with/without spread spectrum modulation.
Note the significant reduction in peak output noise
(>20dBm).
However, if the controller goes into pulse skipping opera-
tionandhaltsswitchingduetoalightprimaryloadcurrent,
then VAUX will droop. An external resistor divider from
V
AUXtotheSYNC/MODEsetsaminimumvoltageVAUX(MIN):
R6
R5
⎛
⎝
⎞
⎟
⎠
ThespreadspectrummodulationoperationoftheLTC3808
is enabled by setting SYNC/MODE pin to a DC voltage
between1.35VandseveralhundredmVbelowVIN bytying
a resistor between SYNC/MODE and VIN.
VAUX(MIN) = 0.4V • 1+
⎜
If VAUX drops below this value, the SYNC/MODE voltage
forces temporary continuous switching operation until
VAUX is again above its minimum.
Table 3 summarizes the different states in which the
SYNC/MODE Pin can be used.
Spread Spectrum Modulation with SYNC/MODE and
PLLLPF Pins
Table 3. The States of the SYNC/MODE Pin
SYNC/MODE PIN
CONDITION
Switching regulators, which operate at fixed frequency,
conductelectromagneticinterference(EMI)totheirdown-
stream load(s) with high spectral power density at this
fundamental and harmonic frequencies. The peak energy
can be lowered and distributed to other frequencies and
their harmonics by modulating the PWM frequency. The
LTC3808’s switching noise (at 550kHz) is spread between
GND (0V to 0.35V)
Forced Continuous Mode
Current Reversal Allowed
V
(0.45V to 1.2V)
Pulse Skipping Mode
No Current Reversal Allowed
FB
Resistor to V
Spread Spectrum Modulation
Pulse Skipping at Light Loads
No Current Reversal Allowed
IN
(1.35V to V – 0.5V)
IN
V
Burst Mode Operation
No Current Reversal Allowed
IN
VOUT Spectrum without Spread Spectrum Modulation
Feedback Resistors
External Clock Signal
Regulate an Auxiliary Winding
Enable Phase-Locked Loop
(Synchronize to External Clock)
Pulse Skipping at Light Load
No Current Reversal Allowed
NOISE (dBm)
–10dBm/DIV
Fault Condition: Short-Circuit and Current Limit
3808 F09a
IftheLTC3808’sloadcurrentexceedstheshort-circuitcur-
rentlimit(ISC),whichissetbytheshort-circuitsensethresh-
old (∆VSC) and the on resistance (RDS(ON)) of bottom
N-channel MOSFET, the top P-channel MOSFET is turned
off and will not be turned on at the next clock cycle unless
the load current decreases below ISC. In this case, the
controller’s switching frequency is decreased and
the output is regulated by short-circuit (current limit)
protection.
START FREQ: 400kHz
RBW: 100Hz
STOP FREQ: 700kHz
VOUT Spectrum with Spread Spectrum Modulation
(CSSM = 2200pF)
NOISE (dBm)
–10dBm/DIV
In a hard short (VOUT = 0V), the top P-channel MOSFET is
turned off and kept off until the short-circuit condition is
cleared. In this case, there is no current path from input
supply (VIN) to either VOUT or GND, which prevents
excessive MOSFET and inductor heating.
3808 F09b
START FREQ: 400kHz
RBW: 100Hz
STOP FREQ: 700kHz
Figure 9. Spectral Response of Spread Spectrum Modulation
3808f
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APPLICATIO S I FOR ATIO
105
Efficiency Considerations
V
REF
100
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
95
90
MAXIMUM
SENSE VOLTAGE
85
80
75
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3808 F10
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3808 circuits: 1) LTC3808 DC bias current,
2) MOSFET gate charge current, 3) I2R losses and
4) transition losses.
Figure 10. Line Regulation of VREF and Maximum Sense Voltage
Low Input Supply Voltage
Although the LTC3808 can function down to below 2.4V,
the maximum allowable output current is reduced as VIN
decreases below 3V. Figure 10 shows the amount of
changeasthesupplyisreduceddownto2.4V. Alsoshown
1) The VIN (pin) current is the DC supply current, given in
the Electrical Characteristics, which excludes MOSFET
driver currents. VIN current results in a small loss that
increases with VIN.
is the effect on VREF
.
Minimum On-Time Considerations
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again, a
packet of charge dQ moves from SENSE+ to ground. The
resulting dQ/dt is a current out of SENSE+, which is
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFETs, inductor and/or sense resistor. In continuous
mode, the average output current flows through L but is
“chopped” between the top P-channel MOSFET and the
bottom N-channel MOSFET. The MOSFET RDS(ON) and/or
theresistanceofthesenseresistormultipliedbydutycycle
can be summed with the resistance of L to obtain I2R
losses.
Minimum on-time, tON(MIN) is the smallest amount of time
that the LTC3808 is capable of turning the top P-channel
MOSFET on. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle and high frequency applications may approach
the minimum on-time limit and care should be taken to
ensure that:
VOUT
OSC • V
tON(MIN)
<
f
IN
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC3808 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum on-
time for the LTC3808 is typically about 210ns. However,
as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases,
the minimum on-time gradually increases up to about
260ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If forced
continuousmodeisselectedandthedutycyclefallsbelow
the minimum on time requirement, the output will be
regulated by overvoltage protection.
4) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input volt-
ages. Transition losses can be estimated from:
Transition Loss = 2 • VIN2 • IO(MAX) • CRSS • f
Other losses, including CIN and COUT ESR dissipative
lossesandinductorcorelosses, generallyaccountforless
than 2% total additional loss.
3808f
21
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APPLICATIO S I FOR ATIO
Checking Transient Response
ponents, including a review of control loop theory, refer to
Application Note 76.
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equalto(∆ILOAD)•(ESR), whereESRistheeffectiveseries
resistance of COUT. ∆ILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. OPTI-LOOP compensation allows the transient re-
sponse to be optimized over a wide range of output
capacitance and ESR values.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25) •
(CLOAD). Thus a 10µF capacitor would be require a 250µs
rise time, limiting the charging current to about 200mA.
Design Example
As a design example, assume VIN will be operating from a
maximum of 4.2V down to a minimum of 2.75V (powered
by a single lithium-ion battery). Load current requirement
is a maximum of 2A, but most of the time it will be in a
standby mode requiring only 2mA. Efficiency at both low
andhighloadcurrentsisimportant. BurstModeoperation
at light loads is desired. Output voltage is 1.8V. The IPRG
pin will be left floating, so the maximum current sense
threshold ∆VSENSE(MAX) is approximately 125mV.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation.
The ITH external components showed in the figure on the
firstpageofthisdatasheetwillprovideadequatecompen-
sation for most applications. The values can be modified
slightly (from 0.2 to 5 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitor needs to be
decided upon because the various types and values deter-
mine the loop feedback factor gain and phase. An output
current pulse of 20% to 100% of full load current having
a rise time of 1µs to 10µs will produce output voltage and
ITH pin waveforms that will give a sense of the overall loop
stability. The gain of the loop will be increased by increas-
ing RC and the bandwidth of the loop will be increased by
decreasing CC. The output voltage settling behavior is
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For a
detailedexplanationofoptimizingthecompensationcom-
VOUT
MaximumDuty Cycle =
= 65.5%
V
IN(MIN)
From Figure 1, SF = 82%.
5
∆VSENSE(MAX)
IOUT(MAX) • ρT
RDS(ON)MAX
=
• 0.9 • SF •
= 0.032Ω
6
A 0.032Ω P-channel MOSFET in Si7540DP is close to this
value.
3808f
22
LTC3808
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APPLICATIO S I FOR ATIO
U
TheN-channelMOSFETinSi7540DPhas0.017ΩRDS(ON)
.
PC Board Layout Checklist
The short circuit current is:
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3808.
90mV
0.017Ω
ISC
=
= 5.3A
• The power loop (input capacitor, MOSFET, inductor,
output capacitor) should be as small as possible and
isolated as much as possible from LTC3808.
So the inductor current rating should be higher than 5.3A.
The PLLLPF pin will be left floating, so the LTC3808 will
operate at its default frequency of 550kHz. For continuous
Burst Mode operation with 600mA IRIPPLE, the required
minimum inductor value is:
• Put the feedback resistors close to the VFB pins. The ITH
compensation components should also be very close to
the LTC3808.
• The current sense traces (SENSE+ and SENSE–) should
be Kelvin connections right at the P-channel MOSFET
source and drain.
1.8V
1.8V
⎛
⎞
⎟
⎠
LMIN
=
• 1−
= 1.88µH
⎜
⎝
550kHz • 600mA
2.75V
• Keeping the switch node (SW) and the gate driver nodes
(TG,BG)awayfromthesmall-signalcomponents,espe-
cially the feedback resistors, and ITH compensation
components.
A 6A 2.2µH inductor works well for this application.
CIN will require an RMS current rating of at least 1A at
temperature. A COUT with 0.1 ESR will cause approxi-
mately 60mV output ripple. In most applications, the
requirements for these capacitors are fairly similar.
3808f
23
LTC3808
U
TYPICAL APPLICATIO S
V
IN
2.75V TO 8V
10µF
10Ω
1µF
2
12
11
SYNC/MODE
V
IN
+
10nF
10k
15k
1
PLLLPF
SENSE
8
4
10
13
MP
Si7540DP
IPRG
TG
L
1M
220pF
1.5µH
–
PGOOD
SENSE
V
C
OUT
ITH
R
ITH
2.5V
6
14
LTC3808EDE
I
SW
TH
(5A AT 5V )
IN
3
5
9
7
MN
Si7540DP
TRACK/SS
BG
187k
+
C
OUT
150µF
V
RUN
FB
GND
15
59k
100pF
L: VISHAY IHLD-2525CZ-01
: SANYO 4TPB150MC
C
OUT
3808 F11
Figure 11. 550kHz, Synchronous DC/DC Converter with Internal Soft-Start
V
IN
2.75V TO 8V
10µF
10Ω
1µF
2
12
SYNC/MODE
V
IN
+
1
8
4
11
10
13
PLLLPF
IPRG
SENSE
MP
TG
Si3447BDV
1M
–
PGOOD
L
SENSE
100pF
1.5µH
22k
6
3
14
9
V
1.8V
2A
OUT
LTC3808EDE
I
TH
SW
BG
10nF
MN
Si3460DV
TRACK/SS
C
OUT
118k
5
7
22µF
V
FB
RUN
GND
15
x2
D
OPT
59k
100pF
L: VISHAY IHLD-2525CZ-01
D: ON SEMI MBRM120L (OPTIONAL)
3808 F12
Figure 12. 750kHz, Synchronous DC/DC Converter with External Soft-Start, Ceramic Output Capacitor
3808f
24
LTC3808
U
TYPICAL APPLICATIO S
Synchronizable, Synchronous DC/DC Converter with Output Tracking
V
IN
2.75V TO 8V
10µF
10Ω
1µF
2
1
12
11
SYNC/MODE
PLLLPF
V
IN
+
10nF
10k
1M
SENSE
8
4
10
13
MP
Si7540DP
IPRG
TG
L
1.5µH
–
PGOOD
SENSE
V
220pF
Vx
OUT
15k
1.8V
6
3
14
9
LTC3808EDE
I
SW
BG
TH
(5A AT 5V
)
IN
1.18k
MN
Si7540DP
TRACK/SS
+
590Ω
C
OUT
150µF
118k
5
7
V
RUN
FB
GND
15
59k
100pF
L: VISHAY IHLP-2525CZ-01
C
V
: SANYO 4TPB150MC
< Vx
OUT
OUT
3808 TA02
Resistor Sensing, Synchronous DC/DC Converter with Spread Spectrum Modulation
V
IN
2.75V TO 8V
10µF
10Ω
1µF
301k
2
1
12
11
SYNC/MODE
PLLLPF
V
IN
+
1000pF
SENSE
0.03Ω
R
SENSE
8
4
13
10
–
IPRG
2200pF
SENSE
1M
MP
Si4431BDY
PGOOD
TG
L
220pF
1.5µH
15k
10nF
6
3
14
9
V
1.5V
2A
OUT
LTC3808EDE
I
TH
SW
MN
Si4860DY
TRACK/SS
BG
+
C
OUT
150µF
88.7k
5
7
V
FB
RUN
GND
15
59k
100pF
L: VISHAY IHLP-2525CZ-01
C
: SANYO 4TPB150MC
OUT
R
SENSE
: DALE 0.25W
3808 TA03
3808f
25
LTC3808
U
PACKAGE DESCRIPTIO
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708)
0.65 ±0.05
3.50 ±0.05
1.70 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.38 ± 0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.20
TYP
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
(2 SIDES)
PIN 1
PIN 1
TOP MARK
NOTCH
(SEE NOTE 6)
(DE14) DFN 1203
7
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
3.30 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3808f
26
LTC3808
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3808f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC3808
TYPICAL APPLICATIO S
U
550kHz, Pulse-Skipping Mode, Synchronous DC/DC Converter with Ceramic Output Capacitor
V
IN
3.3V
R
C
IN
22µF
VIN
10Ω
C
VIN
1µF
1
12
PLLLPF
V
IN
+
LTC3808EDE
11
10
13
14
8
4
3
6
IPRG
SENSE
MP
PGOOD
TG
Si3447BDV
C
ITH
470pF
R
–
ITH
22k
TRACK/SS
SENSE
V
2.5V
2A
OUT
L
I
SW
TH
1.5µH
2
5
9
7
MN
Si3460DV
SYNC/MODE
BG
187k
V
FB
RUN
GND
15
C
OUT
22µF
59k
2x
L: VISHAY IHLP-2525CZ-01
3808 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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IN
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2.65V ≤ V ≤ 8.5V, I
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IN
OUT
No R
, Synchronous Step-Down Controller
Current Mode Operation Without Sense Resistor,
Fast Transient Response, 4V ≤ V ≤ 36V
SENSE
IN
LTC1872
LTC3411
Constant Frequency Current Mode Step-Up Controller
1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
2.5V ≤ V ≤ 9.8V, SOT-23 Package, 550kHz
IN
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60mA,
Q
OUT
IN
OUT
I
= <1mA, MS Package
SD
LTC3412
LTC3416
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60mA,
Q
OUT
IN
OUT
I
= <1mA, TSSOP-16E Package
SD
4A, 4MHz, Monolithic Synchronous Step-Down Regulator
2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller
Tracking Input to Provide Easy Supply Sequencing,
2.25V ≤ V ≤ 5.5V, 20-Lead TSSOP Package
IN
LTC3701
LTC3708
2.5V ≤ V ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
IN
2-Phase, No R
, Dual Synchronous Controller with
Constant On-Time Dual Controller, V Up to 36V, Very Low
SENSE
IN
Output Tracking
Duty Cycle Operation, 5mm × 5mm QFN Package
LTC3736
LTC3736-1
LTC3737
2-Phase, No R
Output Tracking
, Dual Synchronous Controller with
2.75V ≤ V ≤ 9.8V, 0.6V ≤ V
≤ V , 4mm × 4mm QFN
SENSE
IN
OUT IN
Low EMI 2-Phase, Dual Synchronous Controller with
Output Tracking
Integrated Spread Spectrum for 20dB Lower EMI,
2.75V ≤ V ≤ 9.8V
IN
2-Phase, No R
, Dual DC/DC Controller with Output Tracking 2.75V ≤ V ≤ 9.8V, 0.6V ≤ V
≤ V , 4mm × 4mm QFN
SENSE
IN
OUT IN
PolyPhase is a trademark of Linear Technology Corporation.
3808f
LT/TP 0305 500 • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2005
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