LTC1741IFW_技术文档

LTC1741

12-Bit, 65Msps Low Noise ADC

U

FEATURES

DESCRIPTIO

The LTC^®1741 is an 65Msps, sampling 12-bit A/D con-

verter designed for digitizing high frequency, wide dy-

namic range signals. Pin selectable input ranges of ±1V

and ±1.6V along with a resistor programmable mode

allowtheLTC1741’sinputrangetobeoptimizedforawide

variety of applications.

■

Sample Rate: 65Msps

■

72dB SNR and 85dB SFDR (3.2V Range)

■

70.5dB SNR and 87dB SFDR (2V Range)

■

No Missing Codes

Single 5V Supply

Power Dissipation: 1.275W

■

Selectable Input Ranges: ±1V or ±1.6V

The LTC1741 is perfect for demanding communications

applications with AC performance that includes 72dB

SNRand85dBspuriousfreedynamicrange.Ultralowjitter

of0.15ps_RMSallowsundersamplingofIFfrequenciesofup

to 70MHz with excellent noise performance. DC specs

include ±1 LSB INL and ±0.8LSB DNL over temperature.

■

240MHz Full Power Bandwidth S/H

■

Pin Compatible Family

25Msps: LTC1746 (14-Bit), LTC1745(12-Bit)

50Msps: LTC1744 (14-Bit), LTC1743(12-Bit)

65Msps: LTC1742 (14-Bit), LTC1741(12-Bit)

80Msps: LTC1748 (14-Bit), LTC1747(12-Bit)

■

The digital interface is compatible with 5V, 3V, 2V and

LVDS logic systems. The ENC and ENC inputs may be

driven differentially from PECL, GTL and other low swing

logic families or from single-ended TTL or CMOS. The low

noise, high gain ENC and ENC inputs may also be driven

by a sinusoidal signal without degrading performance. A

separate output power supply can be operated from 0.5V

to 5V, making it easy to connect directly to any low voltage

DSPs or FIFOs.

48-Pin TSSOP Package

U

APPLICATIO S

■

Telecommunications

■

Receivers

■

Cellular Base Stations

Spectrum Analysis

Imaging Systems

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

The TSSOP package with a flow-through pinout simplifies

the board layout.

W

BLOCK DIAGRA

65Msps, 12-Bit ADC with a ±1V Differential Input Range

OV

DD

0.5V

TO 5V

0.1µF

+

A

IN

OF

D11

CORRECTION

LOGIC AND

SHIFT

±1V

DIFFERENTIAL

ANALOG INPUT

12

S/H

AMP

12-BIT

PIPELINED ADC

OUTPUT

LATCHES

•

–

D0

CLKOUT

A

REGISTER

IN

OGND

SENSE

BUFFER

V

DD

5V

1µF

RANGE

SELECT

DIFF AMP

1µF

V

GND

CM

2.35V

REF

CONTROL LOGIC

4.7µF

1741 BD

REFLB REFHA

4.7µF

REFLA REFHB ENC ENC MSBINV

OE

0.1µF

DIFFERENTIAL

ENCODE INPUT

1µF

1741f

1

LTC1741

W W U W

U

W U

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

OV_DD= V_DD(Notes 1, 2)

ORDER PART

NUMBER

TOP VIEW

Supply Voltage (V_DD)............................................. 5.5V

Analog Input Voltage (Note 3) .... –0.3V to (V_DD+ 0.3V)

Digital Input Voltage (Except OE)

(Note 3) .................................. –0.3V to (V_DD+ 0.3V)

OE Input Voltage (Note 4)............ –0.3V to (V_DD+ 0.3V)

Digital Output Voltage................. –0.3V to (V_DD+ 0.3V)

OGND Voltage..............................................–0.3V to 1V

Power Dissipation............................................ 2000mW

Operating Temperature Range

LTC1741C ............................................... 0°C to 70°C

LTC1741I............................................ – 40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

SENSE

1

2

3

4

5

6

7

8

9

48 OF

V

CM

47 OGND

46 D11

45 D10

44 D9

43 OV

42 D8

GND

LTC1741CFW

LTC1741IFW

+

A

IN

–

GND

DD

V

DD

41 D7

40 D6

DD

GND

REFLB 10

REFHA 11

GND 12

39 D5

38 OGND

37 GND

36 GND

35 D4

34 D3

33 D2

GND 13

REFLA 14

REFHB 15

GND 16

V

17

18

32 OV

31 D1

30 D0

29 NC

28 NC

27 OGND

26 CLKOUT

25 OE

DD

GND 19

20

V

DD

GND 21

MSBINV 22

ENC 23

ENC 24

FW PACKAGE

48-LEAD PLASTIC TSSOP

T_JMAX= 150°C, θ_JA= 35°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

U

CO VERTER CHARACTERISTICS

The ● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

PARAMETER

CONDITIONS

MIN

12

TYP

MAX

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

●

(Note 6)

– 1

±0.4

±0.2

±5

1

LSB

mV

–0.8

–35

–3.5

0.8

35

3.5

(Note 7)

Gain Error

External Reference (SENSE = 1.6V)

±1

%FS

Full-Scale Drift

Internal Reference

External Reference (Sense = 1.6V)

±40

±20

ppm/°C

Offset Drift

±20

µV/°C

Sense = 1.6V

0.21

LSB

RMS

^InputU ^{Referred Noise (Transition Noise)}

U

A ALOG I PUT

The ● indicates specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Analog Input Range (Note 8)

Analog Input Leakage Current

Analog Input Capacitance

4.75V ≤ V ≤ 5.25V

●

±1 to ±1.6

IN

DD

I

–1

1

µA

IN

C

Sample Mode ENC < ENC

Hold Mode ENC > ENC

8

4

pF

t

Sample-and-Hold Acquisition Time

●

5

0

7.3

ns

ACQ

AP

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Time Jitter

Analog Input Common Mode Rejection Ratio

0.15

80

ps

RMS

JITTER

–

+

CMRR

1.5V < (A = A ) < 3V

dB

IN

1741f

2

LTC1741

U W

DY A IC ACCURACY

T_A= 25°C. A_IN= –1dBFS. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

71

TYP

MAX

UNITS

SNR

Signal-to-Noise Ratio

5MHz Input Signal (2V Range)

5MHz Input Signal (3.2V Range)

70.5

72

dB

30MHz Input Signal (2V Range)

30MHz Input Signal (3.2V Range)

70.5

72

dB

71

70MHz Input Signal (2V Range)

70MHz Input Signal (3.2V Range)

70

71.5

dB

SFDR

Spurious Free Dynamic Range

5MHz Input Signal (2V Range)

5MHz Input Signal (3.2V Range) (2nd and 3rd)

5MHz Input Signal (3.2V Range) (Other)

87

85

92

dB

30MHz Input Signal (2V Range)

30MHz Input Signal (3.2V Range) (2nd and 3rd)

30MHz Input Signal (3.2V Range) (Other)

87

85

92

dB

77

84

70MHz Input Signal (2V Range)

70MHz Input Signal (3.2V Range) (2nd and 3rd)

70MHz Input Signal (3.2V Range) (Other)

80

75

90

dB

S/(N + D) Signal-to-(Noise + Distortion) Ratio 5MHz Input Signal (2V Range)

5MHz Input Signal (3.2V Range)

70.5

72

dB

71

30MHz Input Signal (2V Range)

30MHz Input Signal (3.2V Range)

70.5

72

dB

70MHz Input Signal (2V Range)

70MHz Input Signal (3.2V Range)

70

71.5

dB

THD

IMD

Total Harmonic Distortion

5MHz Input Signal, First 5 Harmonics (2V Range)

5MHz Input Signal, First 5 Harmonics (3.2V Range)

–85

–84

dB

30MHz Input Signal, First 5 Harmonics (2V Range)

30MHz Input Signal, First 5 Harmonics (3.2V Range)

–85

–84

dB

70MHz Input Signal, First 5 Harmonics (2V Range)

70MHz Input Signal, First 5 Harmonics (3.2V Range)

–81

–77

dB

Intermodulation Distortion

Sample-and-Hold Bandwidth

f

= 2.52MHz, f = 5.2MHz (2V Range)

87

85

dBc

IN1

IN2

= 2.52MHz, f = 5.2MHz (3.2V Range)

IN2

R

= 50Ω

240

MHz

SOURCE

U U

U

I TER AL REFERE CE CHARACTERISTICS

(Note 5)

PARAMETER

CONDITIONS

MIN

TYP

2.35

±30

3

MAX

UNITS

V

Output Voltage

Output Tempco

Line Regulation

Output Resistance

I

= 0

2.30

2.40

CM

OUT

ppm/°C

mV/V

Ω

4.75V ≤ V ≤ 5.25V

DD

1mA ≤

I

≤ 1mA

4

OUT

1741f

3

LTC1741

U

DIGITAL I PUTS A D DIGITAL OUTPUTS

The ● indicates specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

DD

V

DD

V

IN

= 5.25V

= 4.75V

= 0V to V

●

2.4

IH

IL

0.8

V

I

±10

µA

pF

V

IN

DD

C

V

Digital Input Capacitance

High Level Output Voltage

MSBINV and OE Only

OV = 4.75V

1.5

IN

I = –10µA

O

4.74

OH

DD

I = –200µA

O

●

4

V

Low Level Output Voltage

OV = 4.75V

I = 160µA

0.05

0.1

V

OL

DD

O

I = 1.6mA

O

●

0.4

±10

15

V

I

Hi-Z Output Leakage D11 to D0

Hi-Z Output Capacitance D11 to D0

Output Source Current

V

OUT

= 0V to V , OE = High

µA

pF

mA

OZ

DD

C

OZ

OE = High (Note 8)

I

V

OUT

V

OUT

= 0V

= 5V

–50

50

SOURCE

Output Sink Current

SINK

W U

POWER REQUIRE E TS

The ● indicates specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

5.25

275

UNITS

V

Positive Supply Voltage

Positive Supply Current

Power Dissipation

4.75

DD

I

●

255

mA

W

DD

P

1.275

1.375

DIS

OV

DD

Digital Output Supply Voltage

0.5

V

DD

W U

TI I G CHARACTERISTICS

The ● indicates specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Note 9)

MIN

15.3

7.3

TYP

MAX

2000

1000

UNITS

ns

t

ENC Period

●

0

1

2

3

4

5

ENC High

(Note 8)

ns

ENC Low

(Note 8)

7.3

ns

Aperture Delay

(Note 8)

0

ns

ENC to CLKOUT Falling

ENC to CLKOUT Rising

For 65Msps 50% Duty Cycle

ENC to DATA Delay

ENC to DATA Delay (Hold Time)

ENC to DATA Delay (Setup Time)

For 65Msps 50% Duty Cycle

C = 10pF (Note 8)

L

●

1

2.4

4

ns

C = 10pF (Note 8)

L

t + t

1 4

ns

C = 10pF (Note 8)

L

●

8.7

2

10.1

4.9

11.7

7.2

ns

t

C = 10pF (Note 8)

L

ns

6

7

8

(Note 8)

1.4

3.4

4.7

ns

C = 10pF (Note 8)

L

t – t

0 6

ns

C = 10pF (Note 8)

L

●

8.2

7

10.5

13.4

ns

t

CLKOUT to DATA Delay (Hold Time),

65Msps 50% Duty Cycle

(Note 8)

ns

9

CLKOUT to DATA Delay (Setup Time),

65Msps 50% Duty Cycle

C = 10pF (Note 8)

L

●

3

ns

10

t

DATA Access Time After OE

BUS Relinquish

C = 10pF (Note 8)

10

5

25

ns

11

12

L

(Note 8)

Data Latency

cycles

1741f

4

LTC1741

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

Note 5: V = 5V, f

= 65MHz, differential ENC/ENC = 2V 65MHz

SAMPLE P-P

DD

of a device may be impaired.

sine wave, input range = ±1.6V differential, unless otherwise specified.

Note 2: All voltage values are with respect to ground with GND

(unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V , they

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

DD

will be clamped by internal diodes. This product can handle input currents

Note 7: Bipolar offset is the offset voltage measured from –0.5 LSB

when the output code flickers between 0000 0000 0000 and

1111 1111 1111.

of greater than 100mA below GND or above V without latchup.

DD

Note 4: When this pin voltage is taken below GND or above 0V , it will be

DD

clamped by internal diodes. This product can handle input currents of

Note 8: Guaranteed by design, not subject to test.

Note 9: Recommended operating conditions.

>100mA below GND or above 0V without latchup.

DD

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Averaged 8192 Point FFT,

Input Frequency = 5MHz, –1dB,

3.2V Range

INL, 3.2V Range

DNL, 3.2V Range

1.0

0.8

1.0

0.8

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

1024

2048

OUTPUT CODE

3072

4096

0

1024

2048

OUTPUT CODE

3072

4096

30

0

5

10

15

20

25

FREQUENCY (MHz)

1741 G02

1741 G01

1741 G03

Averaged 8192 Point FFT,

Input Frequency = 20MHz, –1dB,

3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 5MHz, –10dB,

3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 5MHz, –20dB,

3.2V Range

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

30

0

5

10

15

20

25

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

1741 G01

1741f

5

LTC1741

TYPICAL PERFOR A CE CHARACTERISTICS

U W

Averaged 8192 Point FFT,

Input Frequency = 50MHz, –1dB,

3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 20MHz, –10dB,

3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 20MHz, –20dB,

3.2V Range

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

30

0

5

10

15

20

25

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

1741 G07

1741 G08

1741 G09

Averaged 8192 Point FFT,

Input Frequency = 70MHz, –1dB,

3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 50MHz, –10dB,

3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 50MHz, –20dB,

3.2V Range

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

30

0

5

10

15

20

25

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

1741 G10

1741 G11

1741 G12

Averaged 8192 Point 2-Tone FFT,

5.2MHz and 5.7MHz Inputs,

–7dB, 3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 70MHz, –10dB,

3.2V Range

Averaged 8192 Point FFT,

Input Frequency = 70MHz, –20dB,

3.2V Range

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

30

0

5

10

15

20

25

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

1741f

1741 G15

1741 G13

1741 G14

6

LTC1741

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Averaged 8192 Point 2-Tone FFT,

SFDR vs Input Frequency and

Amplitude, 3.2V Range, 2nd and

3rd Harmonic

25.2MHz and 30.2MHz Inputs,

68.2MHz and 70.2MHz Inputs,

–7dB, 3.2V Range

0

–10

0

100

95

90

85

80

75

70

65

60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–20dB

–10dB

–6dB

–1dB

30

0

5

10

15

20

25

30

0

5

10

15

20

25

20

40

80

0

100

80

60

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

1741 G16

1741 G17

1741 G18

SFDR vs Input Frequency and

Amplitude, 2V Range, 2nd and

3rd Harmonic

SNR vs Input Frequency, 3.2V

Range and 2V Range

Shorted Input Histogram, 3.2V

72.5

72.0

71.5

71.0

70.5

70.0

69.5

100

95

90

85

80

75

70

65

60

70000

60000

50000

40000

30000

20000

10000

0

64737

–10dB

3.2V RANGE

–20dB

–6dB

–1dB

2V RANGE

80

595

197

0

20

40

80

0

100

60

2033

2034

2035

2036

2037

0

20

40

60

INPUT FREQUENCY (MHz)

CODE

1741 G19

1741 G20

1741 G21

SFDR vs Sample Rate, 5MHz

Input, –1dB, 3.2 Range

SNR vs Sample Rate, 5MHz

Input, –1dB, 3.2V Range

Supply Current vs Sample Rate

270

260

250

240

230

220

210

100

95

90

85

80

75

70

65

60

74.0

73.5

73.0

72.5

72.0

71.5

71.0

70.5

70.0

40

SAMPLE RATE (Msps)

40

SAMPLE RATE (Msps)

0

20

60

80 85

0

20

60

80 85

0

20

40

60

SAMPLE RATE (Msps)

1741 G24

1741 G22

1741 G23

1741f

7

LTC1741

U

PI FU CTIO S

SENSE (Pin 1): Reference Sense Pin. Ground selects ±1V. MSBINV (Pin 22): MSB Inversion Control. Low inverts

V

selects ±1.6V. Greater than 1V and less than 1.6V the MSB, 2’s complement output format. High does not

DD

appliedtotheSENSEpinselectsaninputrangeof±V_SENSE

,

invert the MSB, offset binary output format.

±1.6V is the largest valid input range.

ENC(Pin23):EncodeInput.Theinputsamplestartsonthe

_CM(Pin 2): 2.35V Output and Input Common Mode Bias. positive edge.

V

Bypass to ground with 4.7µF ceramic chip capacitor.

ENC (Pin 24): Encode Complement Input. Conversion

GND(Pins3, 6, 9, 12, 13, 16, 19, 21, 36, 37):ADCPower starts on the negative edge. Bypass to ground with 0.1µF

Ground.

ceramic for single-ended ENCODE signal.

A_IN⁺(Pin 4): Positive Differential Analog Input.

A_IN^–(Pin 5): Negative Differential Analog Input.

OE (Pin 25): Output Enable. Low enables outputs. Logic

high makes outputs Hi-Z. OE should not exceed the

voltage on 0V_DD.

V_DD(Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND

with 1µF ceramic chip capacitors.

CLKOUT (Pin 26): Data Valid Output. Latch data on the

rising edge of CLKOUT.

REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11

with 0.1µF ceramic chip capacitor. Do not connect to

Pin 14.

OGND (Pins 27, 38, 47): Output Driver Ground.

NC (Pins 28, 29): Do not connect these pins.

REFHA(Pin11):ADCHighReference.BypasstoPin10with D0-D1 (Pins 30 to 31): Digital Outputs.

0.1µFceramicchipcapacitor,toPin14witha4.7µFceramic

OV_DD(Pins 32, 43): Positive Supply for the Output Driv-

ers. Bypass to ground with 0.1µF ceramic chip capacitor.

capacitor and to ground with 1µF ceramic capacitor.

REFLA(Pin14):ADCLowReference.BypasstoPin15with

0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce-

ramic capacitor and to ground with 1µF ceramic capacitor.

D2-D4 (Pins 33 to 35): Digital Outputs.

D5-D8 (Pins 39 to 42): Digital Outputs.

D9-D11 (Pins 44 to 46): Digital Outputs.

REFHB (Pin 15): ADC High Reference. Bypass to Pin 14

with 0.1µF ceramic chip capacitor. Do not connect to

Pin 11.

OF (Pin 48): Over/Under Flow Output. High when an over

or under flow has occurred.

1741f

8

LTC1741

W

BLOCK DIAGRA

+

A

IN

FIRST PIPELINED

ADC STAGE

(5 BITS)

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

(4 BITS)

FOURTH PIPELINED

INPUT

S/H

ADC STAGE

(2 BITS)

–

A

(4 BITS)

V

CM

2.35V

REFERENCE

4.7µF

SHIFT REGISTER

AND CORRECTION

RANGE

SELECT

REFL

REFH

INTERNAL CLOCK SIGNALS

OV

OF

DD

0.5V TO

5V

REF

BUF

SENSE

D11

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

CONTROL LOGIC

DIFF

OUTPUT

DRIVERS

AND

REF

CALIBRATION LOGIC

D0

AMP

CLKOUT

1741 F01

ENC

MSBINV

OE

REFLB REFHA

REFLA REFHB

OGND

4.7µF

0.1µF

1µF

0.1µF

1µF

Figure 1. Functional Block Diagram

W U

W

TI I G DIAGRA

N

•

ANALOG

INPUT

t

3

t

0

1

2

ENC

t

7

t

8

DATA (N – 5)

DB11 TO DB0

DATA (N – 4)

DB11 TO DB0

DATA

DATA (N – 3)

6

CLKOUT

t

4

t

9

5

10

OE

t

12

11

DATA N

DATA

DB11 TO DB0, OF AND CLKOUT

1741 TD

1741f

9

LTC1741

W U U

U

APPLICATIO S I FOR ATIO

DYNAMIC PERFORMANCE

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at the sum and differ-

ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,

etc. The 3rd order intermodulation products are 2fa + fb,

2fb + fa, 2fa – fb and 2fb – fa. The intermodulation

distortion is defined as the ratio of the RMS value of either

input tone to the RMS value of the largest 3rd order

intermodulation product.

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band limited

to frequencies above DC to below half the sampling

frequency.

Spurious Free Dynamic Range (SFDR)

Signal-to-Noise Ratio

Spurious free dynamic range is the peak harmonic or

spurious noise that is the largest spectral component

excluding the input signal and DC.This value is expressed

in decibels relative to the RMS value of a full scale input

signal.

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC.

Total Harmonic Distortion

Input Bandwidth

Total harmonic distortion is the ratio of the RMS sum of all

harmonicsoftheinputsignaltothefundamentalitself.The

out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency. THD is

expressed as:

The input bandwidth is that input frequency at which the

amplitude of the reconstructed fundamental is reduced by

3dB for a full scale input signal.

Aperture Delay Time

V2²+ V3²+ V4²+...Vn²

The time from when a rising ENC equals the ENC voltage

totheinstantthattheinputsignalisheldbythesampleand

hold circuit.

THD = 20Log

V1

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

secondthroughnthharmonics. TheTHDcalculatedinthis

data sheet uses all the harmonics up to the fifth.

Aperture Delay Jitter

Thevariationintheaperturedelaytimefromconversionto

conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused by

the presence of another sinusoidal input at a different

frequency.

SNR_JITTER= –20log (2π) • F_IN• T_JITTER

1741f

10

LTC1741

W U U

APPLICATIO S I FOR ATIO

U

CONVERTER OPERATION

SAMPLE/HOLD OPERATION AND INPUT DRIVE

The LTC1741 is a CMOS pipelined multistep converter.

The converter has four pipelined ADC stages; a sampled

analog input will result in a digitized value five cycles later,

see the Timing Diagram section. The analog input is

differential for improved common mode noise immunity

andtomaximizetheinputrange.Additionally,thedifferen-

tial input drive will reduce even order harmonics of the

sample-and-hold circuit. The encode input is also

differential for improved common mode noise immunity.

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC1741

CMOS differential sample-and-hold. The differential ana-

log inputs are sampled directly onto sampling capacitors

(C_SAMPLE) through CMOS transmission gates. This direct

capacitor sampling results in lowest possible noise for a

given sampling capacitor size. The capacitors shown

attached to each input (C_PARASITIC) are the summation of

all other capacitance associated with each input.

The LTC1741 has two phases of operation, determined by

the state of the differential ENC/ENC input pins. For brev-

ity, the text will refer to ENC greater than ENC as ENC high

and ENC less than ENC as ENC low.

During the sample phase when ENC/ENC is low, the

transmission gate connects the analog inputs to the sam-

pling capacitors and they charge to, and track the differen-

tial input voltage. When ENC/ENC transitions from low to

high the sampled input voltage is held on the sampling

capacitors. During the hold phase when ENC/ENC is high

the sampling capacitors are disconnected from the input

and the held voltage is passed to the ADC core for

processing. As ENC/ENC transitions from high to low the

inputs are reconnected to the sampling capacitors to

acquire a new sample. Since the sampling capacitors still

holdtheprevioussample,achargingglitchproportionalto

the change in voltage between samples will be seen at this

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

outputbytheresidueamplifier.Successivestagesoperate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and visa versa.

WhenENCislow,theanaloginputissampleddifferentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the sampled input

is held. While ENC is high, the held input voltage is

bufferedbytheS/Hamplifierwhichdrivesthefirstpipelined

ADC stage. The first stage acquires the output of the S/H

during this high phase of ENC. When ENC goes back low,

the first stage produces its residue which is acquired by

the second stage. At the same time, the input S/H goes

back to acquiring the analog input. When ENC goes back

high, the second stage produces its residue which is

acquired by the third stage. An identical process is re-

peated for the third stage, resulting in a third stage residue

that is sent to the fourth stage ADC for final evaluation.

LTC1741

V

DD

C

SAMPLE

4pF

C

PARASITIC

+

A

IN

4pF

V

DD

C

SAMPLE

4pF

–

A

5V

BIAS

2V

6k

ENC

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

thattheresultscanbeproperlycombinedinthecorrection

logic before being sent to the output buffer.

6k

2V

1741 F02

Figure 2. Equivalent Input Circuit

1741f

11

LTC1741

W U U

U

APPLICATIO S I FOR ATIO

time. If the change between the last sample and the new

sampleissmallthechargingglitchseenattheinputwillbe

small. Iftheinputchangeislarge, suchasthechangeseen

withinputfrequenciesnearNyquist,thenalargercharging

glitch will be seen.

Input Drive Circuits

Figure 3 shows the LTC1741 being driven by an RF

transformer with a center tapped secondary. The second-

arycentertapisDCbiasedwithV_CM,settingtheADCinput

signal at its optimum DC level. Figure 3 shows a 1:1 turns

ratio transformer. Other turns ratios can be used if the

source impedence seen by the ADC does not exceed

100Ω for each ADC input. A disadvantage of using a

transformer is the loss of low frequency response. Most

smallRFtransformershavepoorperformanceatfrequen-

cies below 1MHz.

Common Mode Bias

TheADCsample-and-holdcircuitrequiresdifferentialdrive

toachievespecifiedperformance.Eachinputshouldswing

±0.8V for the 3.2V range or±0.5V for the 2V range, around

a common mode voltage of 2.35V. The V_CMoutput pin

(Pin 2)maybeusedtoprovidethecommonmodebiaslevel.

V

_CMcan be tied directly to the center tap of a transformer

V

CM

tosettheDCinputlevelorasareferenceleveltoanopamp

differentialdrivercircuit. TheV_CMpinmustbebypassedto

ground close to the ADC with a 4.7µF or greater capacitor.

4.7µF

0.1µF

12pF

LTC1741

+

25Ω

100Ω

25Ω

A

1:1

IN

Input Drive Impedance

ANALOG

INPUT

100Ω

12pF

As with all high performance, high speed ADCs the dy-

namic performance of the LTC1741 can be influenced by

the input drive circuitry, particularly the second and third

harmonics. Source impedance and input reactance can

influence SFDR. At the falling edge of encode the sample-

and-holdcircuitwillconnectthe4pFsamplingcapacitorto

the input pin and start the sampling period. The sampling

periodendswhenencoderises, holdingthesampledinput

on the sampling capacitor. Ideally the input circuitry

shouldbefastenoughtofullychargethesamplingcapaci-

tor during the sampling period 1/(2F_ENCODE); however,

thisisnotalwayspossibleandtheincompletesettlingmay

degradetheSFDR. The sampling glitchhasbeen designed

to be as linear as possible to minimize the effects of

incomplete settling.

–

25Ω

12pF

1741 F03

Figure 3. Single-Ended to Differential Conversion

Using a Transformer

Figure 4 demonstrates the use of operational amplifiers to

convert a single ended input signal into a differential input

signal. Theadvantageofthismethodisthatitprovideslow

frequencyinputresponse;however,thelimitedgainband-

width of most op amps will limit the SFDR at high input

frequencies.

The 25Ω resistors and 12pF capacitors on the analog

inputs serve two purposes: isolating the drive circuitry

from the sample-and-hold charging glitches and limiting

the wideband noise at the converter input. For input

frequencieshigherthan100MHz, thecapacitorsmayneed

to be decreased to prevent excessive signal loss.

For the best performance, it is recomended to have a

source impedence of 100Ω or less for each input. The S/H

circuit is optimized for a 50Ω source impedance. If the

source impedance is less than 50Ω, a series resistor

should be added to increase this impedance to 50Ω. The

source impedence should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

1741f

12

LTC1741

W U U

U

APPLICATIO S I FOR ATIO

V

CM

LTC1741

4.7µF

4Ω

V

CM

2.35V BANDGAP

5V

2.35V

REFERENCE

SINGLE-ENDED

INPUT

4.7µF

12pF

1.6V

1V

+

2.35V ±1/2

RANGE

+

25Ω

A

IN

1/2 LT1810

RANGE

DETECT

AND

–

LTC1741

12pF

CONTROL

TIE TO V FOR 3.2V RANGE;

DD

SENSE

REFLB

100Ω

500Ω

TIE TO GND FOR 2V RANGE;

+

RANGE = 2 • V

FOR

SENSE

–

25Ω

A

BUFFER

IN

1V < V

< 1.6V

SENSE

1/2 LT1810

INTERNAL ADC

HIGH REFERENCE

0.1µF

REFHA

12pF

–

1µF

500Ω

1741 F04

4.7µF

DIFF AMP

Figure 4. Differential Drive with Op Amps

1µF

REFLA

Reference Operation

0.1µF

INTERNAL ADC

LOW REFERENCE

REFHB

Figure5showstheLTC1741referencecircuitryconsisting

of a 2.35V bandgap reference, a difference amplifier and

switching and control circuit. The internal voltage refer-

ence can be configured for two pin selectable input ranges

of 2V(±1V differential) or 3.2V(±1.6V differential). Tying

the SENSE pin to ground selects the 2V range; tying the

SENSE pin to V_DDselects the 3.2V range.

1741 F05

Figure 5. Equivalent Reference Circuit

Other voltage ranges in between the pin selectable ranges

can be programmed with two external resistors as shown

inFigure6a. Anexternalreferencecanbeusedbyapplying

its output directly or through a resistor divider to SENSE.

It is not recommended to drive the SENSE pin with a logic

device since the logic threshold is close to ground and

V_DD. The SENSE pin should be tied high or low as close to

the converter as possible. If the SENSE pin is driven

externally, it should be bypassed to ground as close to the

device as possible with a 1µF ceramic capacitor.

The 2.35V bandgap reference serves two functions: its

output provides a DC bias point for setting the common

mode voltage of any external input circuitry; additionally,

the reference is used with a difference amplifier to gener-

ate the differential reference levels needed by the internal

ADC circuitry.

An external bypass capacitor is required for the 2.35V

reference output, V_CM. This provides a high frequency low

impedance path to ground for internal and external cir-

cuitry. This is also the compensation capacitor for the

reference. It will not be stable without this capacitor.

Input Range

The input range can be set based on the application. For

oversampled signal processing in which the input fre-

quency is low (<10MHz), the largest input range will

provide the best signal-to-noise performance while main-

taining excellent SFDR. For high input frequencies

(>40MHz), the 2V range will have the best SFDR perfor-

mance for the 2nd and 3rd harmonics, but the SNR will

degrade by 1.5dB. See the Typical Performance Charac-

teristics section.

The difference amplifier generates the high and low refer-

ence for the ADC. High speed switching circuits are

connected to these outputs and they must be externally

bypassed. Each output has two pins: REFHA and REFHB

for the high reference and REFLA and REFLB for the low

reference. The doubled output pins are needed to reduce

package inductance. Bypass capacitors must be con-

nected as shown in Figure 5.

1741f

13

LTC1741

APPLICATIO S I FOR ATIO

W U U

U

2.35V

V

CM

2.35V

4.7µF

12.5k

1.1V

LTC1741

SENSE

4

6

1.25V

SENSE

5V

0.1µF

LT1790-1.25

1, 2

1µF

11k

1741 F06a

1741 F06b

Figure 6a. 2.2V Range ADC

Figure 6b. 2.5V Range ADC with External Reference

LTC1741

5V

BIAS

TO INTERNAL

ADC CIRCUITS

2V BIAS

6k

V

DD

ANALOG INPUT

ENC

0.1µF

1:4

CLOCK

INPUT

50Ω

2V BIAS

6k

V

1741 F07

Figure 7. Transformer Driven ENC/ENC

3.3V

MC100LVELT22

130Ω

Q0

130Ω

ENC

V

= 2V

THRESHOLD

D0

LTC1741

2V ENC

LTC1741

ENC

83Ω

0.1µF

Q0

83Ω

1741 F08a

1741 F08b

Figure 8a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 8b. ENC Drive Using a CMOS-to-PECL Translator

1741f

14

LTC1741

W U U

APPLICATIO S I FOR ATIO

U

Driving the Encode Inputs

Maximum and Minimum Encode Rates

The noise performance of the LTC1741 can depend on the

encode signal quality as much as on the analog input. The

ENC/ENC inputs are intended to be driven differentially,

primarily for noise immunity from common mode noise

sources. Each input is biased through a 6k resistor to a 2V

bias. The bias resistors set the DC operating point for

transformer coupled drive circuits and can set the logic

threshold for single-ended drive circuits.

ThemaximumencoderatefortheLTC1741is65Msps.For

theADCtooperateproperlytheencodesignalshouldhave

a50%(±5%)dutycycle. Eachhalfcyclemusthaveatleast

7.3nsfortheADCinternalcircuitrytohaveenoughsettling

time for proper operation. Achieving a precise 50% duty

cycle is easy with differential sinusoidal drive using a

transformer or using symmetric differential logic such as

PECL or LVDS. When using a single-ended encode signal

asymmetricriseandfalltimescanresultindutycyclesthat

are far from 50%.

Any noise present on the encode signal will result in

additionalaperturejitterthatwillbeRMSsummedwiththe

inherent ADC aperture jitter.

At sample rates slower than 65Msps the duty cycle can

vary from 50% as long as each half cycle is at least 7.3ns.

In applications where jitter is critical (high input frequen-

cies) take the following into consideration:

The lower limit of the LTC1741 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architectureofthisADCreliesonstoringanalogsignalson

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC1741 is 1Msps.

1. Differential drive should be used.

2. Use as large an amplitude as possible; if transformer

coupled use a higher turns ratio to increase the

amplitude.

3. If the ADC is clocked with a sinusoidal signal, filter the

encode signal to reduce wideband noise.

DIGITAL OUTPUTS

4. Balance the capacitance and series resistance at both

encode inputs so that any coupled noise will appear at

both inputs as common mode noise.

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OV_DDand OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

The encode inputs have a common mode range of 1.8V to

V_DD. Each input may be driven from ground to V_DDfor

single-ended drive.

LTC1741

OV

DD

0.5V TO

V

DD

V

DD

V

DD

0.1µF

OV

DD

DATA

FROM

LATCH

PREDRIVER

LOGIC

43Ω

TYPICAL

DATA

OUTPUT

OE

OGND

1741 F09

Figure 9. Equivalent Circuit for a Digital Output Buffer

1741f

15

LTC1741

W U U

U

APPLICATIO S I FOR ATIO

down to low voltages. The internal resistor in series with

the output makes the output appear as 50Ω to external

circuitry and may eliminate the need for external damping

resistors.

example if the converter is driving a DSP powered by a 3V

supply then OV_DDshould be tied to that same 3V supply.

OV_DDcan be powered with any voltage up to 5V. The logic

outputs will swing between OGND and OV_DD.

Output Loading

Output Enable

As with all high speed/high resolution converters the

digital output loading can affect the performance. The

digital outputs of the LTC1741 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

output may be used but is not required since the ADC has

a series resistor of 43Ω on chip.

The outputs may be disabled with the output enable pin,

OE. OE low disables all data outputs including OF and

CLKOUT. Thedataaccessandbusrelinquishtimesaretoo

slow to allow the outputs to be enabled and disabled

during full speed operation. The output Hi-Z state is

intended for use during long periods of inactivity. The

voltage on OE can swing between GND and 0V_DD. OE

should not be driven above 0V_DD.

GROUNDING AND BYPASSING

Lower OV_DDvoltages will also help reduce interference

from the digital outputs.

The LTC1741 requires a printed circuit board with a clean

unbroken ground plane. A multilayer board with an inter-

nal ground plane is recommended. The pinout of the

LTC1741 has been optimized for a flowthrough layout so

that the interaction between inputs and digital outputs is

minimized. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track or

underneath the ADC.

Format

The LTC1741 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MSBINV pin; high selects offset binary.

Overflow Bit

An overflow output bit indicates when the converter is

overrangedor underranged. When OF outputsa logichigh

the converter is either overranged or underranged.

High quality ceramic bypass capacitors should be used at

the V_DD,V_CM, REFHA, REFHB, REFLA and REFLB pins as

shown in the block diagram on the front page of this data

sheet. Bypass capacitors must be located as close to the

pins as possible. Of particular importance are the capaci-

tors between REFHA and REFLB and between REFHB and

REFLA. These capacitors should be as close to the device

aspossible(1.5mmorless).Size0402ceramiccapacitors

arerecomended.Thelarge4.7µFcapacitorbetweenREFHA

and REFLA can be somewhat further away. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

Output Clock

The ADC has a delayed version of the ENC input available

as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system.

This is necessary when using a sinusoidal encode. Data

will be updated just after CLKOUT falls and can be latched

on the rising edge of CLKOUT.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OV_DD, should be tied

to the same power supply as for the logic being driven. For

The LTC1741 differential inputs should run parallel and

close to each other. The input traces should be as short as

possible to minimize capacitance and to minimize noise

pickup.

1741f

16

LTC1741

W U U

APPLICATIO S I FOR ATIO

U

An analog ground plane separate from the digital process-

ing system ground should be used. All ADC ground pins

labeled GND should connect to this plane. All ADC V_DD

bypass capacitors, reference bypass capacitors and input

filter capacitors should connect to this analog plane. The

LTC1741 has three output driver ground pins, labeled

OGND (Pins 27, 38 and 47). These grounds should con-

nect to the digital processing system ground. The output

driver supply, OV_DDshould be connected to the digital

processingsystemsupply.OV_DDbypasscapacitorsshould

bypass to the digital system ground. The digital process-

ing system ground should be connected to the analog

plane at ADC OGND (Pin 38).

HEAT TRANSFER

Most of the heat generated by the LTC1741 is transferred

from the die through the package leads onto the printed

circuit board. In particular, ground pins 12, 13, 36 and 37

are fused to the die attach pad. These pins have the lowest

thermal resistance between the die and the outside envi-

ronment. It is critical that all ground pins are connected to

a ground plane of sufficient area. The layout of the evalu-

ation circuit shown on the following pages has a low ther-

mal resistance path to the internal ground plane by using

multiple vias near the ground pins. A ground plane of this

size results in a thermal resistance from the die to ambient

of35°C/W.Smallerareagroundplanesorpoorlyconnected

ground pins will result in higher thermal resistance.

1741f

17

LTC1741

W U U

U

APPLICATIO S I FOR ATIO

1741f

18

LTC1741

W U U

APPLICATIO S I FOR ATIO

U

65

Silkscreen Top

Layer 1 Component Side

Layer 2 GND Plane

Layer 3 Power Plane

Layer 4 Solder Side

1741f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1741

U

PACKAGE DESCRIPTIO

FW Package

48-Lead Plastic TSSOP (6.1mm)

(Reference LTC DWG # 05-08-1651)

12.4 – 12.6*

(.488 – .496)

44

42

41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

48 47 46 45

43

0.95 ±0.10

8.1 ±0.10

6.2 ±0.10

7.9 – 8.3

(.311 – .327)

0.32 ±0.05

0.50 TYP

5

7

8

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.0473)

MAX

6.0 – 6.2**

(.236 – .244)

0° – 8°

-T-

.10

-C-

C

0.45 – 0.75

(.018 – .029)

0.50

(.0197)

BSC

0.17 – 0.27

(.0067 – .0106)

FW48 TSSOP 0502

0.09 – 0.20

(.0035 – .008)

0.05 – 0.15

(.002 – .006)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1405

12-Bit, 5Msps Sampling ADC with Parallel Output

8-Bit, 20Msps ADC

Pin Compatible with the LTC1420

Undersampling Capability up to 70MHz

5V, No Pipeline Delay, 80dB SINAD

±5V, No Pipeline Delay, 72dB SINAD

±5V, 81dB SINAD and 95dB SFDR

LTC1406

LTC1411

14-Bit, 2.5Msps ADC

LTC1412

12-Bit, 3Msps, Sampling ADC

14-Bit, 2.2Msps ADC

LTC1414

LTC1420

12-Bit, 10Msps ADC

71dB SINAD and 83dB SFDR at Nyquist

0.04% Max Initial Accuracy, 3ppm/°C Drift

Pin Compatible with the LTC1668, LTC1667

Pin Compatible with the LTC1668, LTC1666

LT1461

Micropower Precision Series Reference

12-Bit, 50Msps DAC

LTC1666

LTC1667

LTC1668

LTC1742

LTC1743

LTC1744

LTC1745

LTC1746

LTC1747

LTC1748

LT^®1807

14-Bit, 50Msps DAC

16-Bit, 50Msps DAC

16-Bit, No Missing Codes, 90dB SINAD, –100dB THD

Pin Compatible with the LTC1741

Rail-to-Rail Input and Output

12-Bit, 65Msps ADC

12-Bit, 50Msps ADC

14-Bit, 50Msps ADC

12-Bit, 25Msps ADC

14-Bit, 25Msps ADC

12-Bit, 80Msps ADC

14-Bit, 80Msps ADC

325MHz, Low Distortion Dual Op Amp

1741f

LT/TP 0603 1K • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003


型号：	LTC1741IFW
厂家：	Linear
描述：	12-Bit, 65Msps Low Noise ADC 12位，支持65Msps低噪声ADC 转换器光电二极管
文件：	总20页 (文件大小：662K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1741IFW [Linear]

相关型号：

LTC1741IFW#PBF

LTC1742

LTC1742CFW

LTC1742IFW

LTC1742IFW#PBF

LTC1742IFW#TR

LTC1742IFW#TRPBF

LTC1743

LTC1743CFW

LTC1743CFW#PBF

LTC1743CFW#TRPBF

LTC1743IFW