LTC1760CFW#PBF [Linear]
LTC1760 - Dual Smart Battery System Manager; Package: TSSOP; Pins: 48; Temperature Range: 0°C to 70°C;![LTC1760CFW#PBF](http://pdffile.icpdf.com/pdf2/p00269/img/icpdf/LTC1760CFW-P_1615338_icpdf.jpg)
型号: | LTC1760CFW#PBF |
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描述: | LTC1760 - Dual Smart Battery System Manager; Package: TSSOP; Pins: 48; Temperature Range: 0°C to 70°C 电池 光电二极管 |
文件: | 总48页 (文件大小:396K) |
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LTC1760
Dual Smart Battery
System Manager
FEATURES
DESCRIPTION
The LTC®1760 Smart Battery System Manager is a highly-
integrated SMBus Level 3 battery charger and selector
intended for products using dual smart batteries. Three
SMBus interfaces allow the LTC1760 to servo to the
internal voltage and currents measured by the batteries
while allowing an SMBus Host device to monitor either
battery’s status. Charging accuracy is determined by the
battery’s internal voltage and current measurements,
typically better than 0.ꢀ2.
n
SMBus Charger/Selector for Two Smart Batteries*
n
Voltage and Current Accuracy within 0.2% of Value
Reported by Battery
n
Simplifies Construction of “Smart Battery System
Manager”
n
Includes All SMBus Charger V1.1 Safety Features
n
Supports Autonomous Operation without a Host
n
Allows Both Batteries to Discharge Simultaneously
into Single Load with Low Loss (Ideal Diode)
n
A proprietary PowerPatharchitecture supports simultane-
ouschargingordischargingofbothbatteries.Typicalbattery
run times are extended by up to 102, while charging times
are reduced by up to 502. The LTC1760 automatically
switchesbetweenpowersourcesinlessthan10µstoprevent
power interruption upon battery or wall adapter removal.
SMBus Switching for Dual Batteries with Alarm
Monitoring for Charging Battery at All Times
n
Pin Programmable Limits for Maximum Charge
Current and Voltage Improve Safety
n
Fast Autonomous PowerPath™ Switching (<10µs)
n
Low Loss Simultaneous Charging of Two Batteries
n
The LTC1760 implements all elements of a version 1.1
“SmartBatterySystemManager”exceptforthegeneration
of composite battery information. An internal multiplexer
cleanly switches the SMBus Host to either of the two
attached Smart Batteries without generating partial mes-
sages to batteries or SMBus Host. Thermistors on both
batteriesareautomaticallymonitoredfortemperatureand
disconnection information (SafetySignal).
>952 Efficient Synchronous Buck Charger
n
AC Adapter Current Limiting* Maximizes Charge Rate
n
SMBus Accelerator Improves SMBus Timing**
n
Available in 48-Lead TSSOP Package
APPLICATIONS
n
Portable Computers and Instruments
n
Standalone Dual Smart Battery Chargers
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath is a trademark of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including *57ꢀ3970 **6650174.
n
Battery Backup Systems
TYPICAL APPLICATION
Dual Battery Charger/Selector System Architecture
Dual vs Sequential Charging
3500
DC
IN
BAT2
BAT1
CURRENT
3000
2500
2000
1500
1000
500
CURRENT
SEQUENTIAL
SYSTEM
POWER
0
3500
3000
2500
2000
1500
1000
500
LTC1760
BAT1
CURRENT
SMBus (HOST)
BAT2
DUAL
CURRENT
100
MINUTES
SafetySignal 1
SMBus 1
0
0
100
150
200 250
300
50
TIME (MINUTES)
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
REQUESTED CURRENT = 3A
SafetySignal 2
REQUESTED VOLTAGE = 12.3V
MAX CHARGER CURRENT = 4.1A
1760 TA03
SMBus 2
1760 TA01
1760fc
1
For more information www.linear.com/LTC1760
LTC1760
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
DCIN, SCP, SCN, CLP,
PLUS
SCH1, SCHꢀ to GND................................... –0.3V to ꢀ8V
BOOST to GND...........................................–0.3V to 37V
CSP, CSN, BAT1, BATꢀ to GND................... –0.3V to ꢀ8V
LOPWR, DCDIV to GND ............................. –0.3V to 10V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
48 SCH2
47 GCH2
46 GCH1
45 SCH1
44 TGATE
43 BOOST
42 SW
V
PLUS
V
, SW to GND ..................................... –0.3V to 3ꢀV
BAT2
BAT1
SCN
SCP
GDCO
GDCI
GB1O
GB1I
GB2O
GB2I
41 DCIN
40 V
CC
V
, V
to GND.......................................–0.3V to 7V
CCꢀ DDS
SDA1, SDAꢀ, SDA, SCL1,
39 BGATE
38 PGND
37 COMP1
36 CLP
35 CSP
34 CSN
LOPWR
SCLꢀ, SCL, SMBALERT to GND....................–0.3V to 7V
MODE to GND .................................–0.3V to V
V
SET
I
+0.3V
TH
CCꢀ
I
SET
COMP1 to GND ............................................ –0.3V to 5V
Maximum DC Current Into Pin
SDA1, SDAꢀ, SDA, SCL1, SCLꢀ, SCL ................ 3mA
TH1A, THꢀA..................................................... –5mA
TH1B, THꢀB ................................................... –10ꢀµA
Operating Junction Temperature Range
33 V
DCDIV
SCL2
SCL
SCL1
V
LIMIT
32 I
LIMIT
31 TH1B
30 TH1A
29 SMBALERT
28 TH2A
27 TH2B
DDS
SDA2 21
SDA 22
SDA1 23
GND 24
26 MODE
25 V
CC2
(Note 6).................................................. –40°C to 1ꢀ5°C
Storage Temperature.............................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
FW PACKAGE
48-LEAD PLASTIC TSSOP
T
= 1ꢀ5°C, q = 110°C/W
JA
JMAX
ORDER INFORMATION
(http://www.linear.com/product/LTC1760#orderinfo)
LEAD FREE FINISH
LTC1760CFW#PBF
LTC1760IFW#PBF
TAPE AND REEL
PART MARKING
LTC1760CFW
LTC1760IFW
PACKAGE DESCRIPTION
48-Lead Plastic TSSOP
48-Lead Plastic TSSOP
TEMPERATURE RANGE
0°C to 85°C
LTC1760CFW#TRPBF
LTC1760IFW#TRPBF
–40°C to 1ꢀ5°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
1760fc
2
For more information www.linear.com/LTC1760
LTC1760
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V,
VVCC2 = 5.2V unless otherwise noted.
SYMBOL PARAMETER
Supply and Reference
CONDITIONS
MIN
TYP
MAX
UNITS
DCIN Operating Range
DCIN Operating Current
DCIN Selected
6
ꢀ8
V
I
I
Not Charging (DCIN Selected) (Note 10)
Charging (DCIN Selected) (Note 10)
1
1.3
1.5
ꢀ
mA
mA
CH0
CH1
I
I
V
CCꢀ
Operating Current
AC Present (Note 11)
AC Not Present (Note 11)
0.75
75
1
100
mA
µA
VCCꢀ_AC1
VCCꢀ_AC0
Battery Operating Voltage Range
Battery Drain Current
Battery Selected, PowerPath Function
6
0
ꢀ8
ꢀ8
V
V
Battery Selected, Charging Function (Note ꢀ)
I
Battery Selected, Not Charging, V
= 0V (Note 10)
175
µA
BAT
DCIN
V
Diodes Forward Voltage:
PLUS
V
V
V
V
DCIN to V
BAT1 to V
BATꢀ to V
I
I
I
I
= 10mA
= 0mA
= 0mA
= 0mA
0.8
0.7
0.7
0.7
V
V
V
V
FDC
FB1
FBꢀ
PLUS
PLUS
PLUS
PLUS
VCC
VCC
VCC
VCC
SCN to V
FSCN
l
l
UVLO
Undervoltage Lockout Threshold
V
Ramping Down, Measured at V
to GND
3
5
5.5
1
V
V
PLUS
PLUS
V
V
V
Regulator Output Voltage
Load Regulation
4.9
5.ꢀ
0.ꢀ
VCC
LDR
CC
CC
V
No External Connection Beyond Applications Shown
Herein
2
Switching Regulator
l
V
Voltage Accuracy
With Respect to Voltage Reported by Battery
CHMIN
–3ꢀ
3ꢀ
mV
TOL
V
< Requested Voltage < V
LIMIT
I
Current Accuracy
With Respect to Current Reported by Battery
4mV/R < Requested Current < I (Min)
TOL
SENSE
LIMIT
(Note 1ꢀ)
l
l
l
l
R
ILIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
= 0 (Short to GND)
–ꢀ
–4
–8
–8
ꢀ
4
8
8
mA
mA
mA
mA
= 10k 12
= 33k 12
= Open (or Short I
to V
)
LIMIT
CCꢀ
f
f
Regulator Switching Frequency
ꢀ55
ꢀ0
300
ꢀ5
345
kHz
kHz
0SC
Regulator Switching Frequency in Low Duty Cycle ≥992
Dropout Mode
DO
DC
Regulator Maximum Duty Cycle
99
99.5
155
150
2
mV
µA
V
MAX
I
I
Maximum Current Sense Threshold
CA1 Input Bias Current
V
V
= ꢀ.ꢀV
140
190
MAX
SNS
ITH
= V
> 5V
CSP
CSN
CMSL
CMSH
CA1 Input Common Mode Low
CA1 Input Common Mode High
CL1 Turn-On Threshold
0
V
– 0.ꢀ
V
DCIN
V
95
94
90
100
100
100
105
108
108
mV
mV
mV
CL1
l
l
C-Grade (Note 6)
I-Grade (Note 6)
TGATE Transition Time:
TGATE Rise Time
TGATE Fall Time
50
50
90
90
TG t
TG t
C
LOAD
C
LOAD
= 3300pF, 102 to 902
= 3300pF, 102 to 902
r
r
ns
ns
BGATE Transition Time
BGATE Rise Time
BGATE Fall Time
50
40
90
80
ns
ns
BG t
BG t
C
LOAD
C
LOAD
= 3300pF, 102 to 902
= 3300pF, 102 to 902
r
f
1760fc
3
For more information www.linear.com/LTC1760
LTC1760
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V,
VVCC2 = 5.2V unless otherwise noted.
SYMBOL PARAMETER
Trip Points
CONDITIONS
MIN
TYP
MAX
UNITS
V
DCDIV/LOPWR Threshold
V
or V Falling
LOPWR
TR
DCDIV
C-Grade (Note 6)
I-Grade (Note 6)
l
l
1.166
1.16ꢀ
1.19
1.19
1.ꢀ15
1.ꢀ15
V
V
V
DCDIV/LOPWR Hysteresis Voltage
DCDIV/LOPWR Input Bias Current
Short-Circuit Comparator Threshold
V
V
V
or V
or V
Rising
30
ꢀ0
mV
nA
THYS
BVT
DCDIV
DCDIV
LOPWR
LOPWR
I
= 1.19V
ꢀ00
V
TSC
– V , V ≥ 5V
SCN CC
C-Grade (Note 6)
I-Grade (Note 6)
SCP
l
l
90
88
100
100
115
115
mV
mV
V
V
Fast PowerPath Turn-Off Threshold
Overvoltage Shutdown Threshold as a
V
V
Rising from V
CC
6
7
7.9
V
FTO
DCDIV
Rising from 0.8V until TGATE and BGATE
SET
Percent of Programmed Charger Voltage Stop Switching
107
2
OVSD
DACs
I
I
I
Resolution
Guaranteed Monotonic
10
6
Bits
RES
DAC
Pulse Period:
Normal Mode
DAC
10
50
15
µs
ms
t
t
IP
ILOW
Wake-Up Mode
Charging Current Granularity
R
ILIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
= 0 (Short I
= 10k 12
= 33k 12
to GND)
1
ꢀ
4
4
mA
mA
mA
mA
LIMIT
= Open (or Short I
to V
)
LIMIT
CCꢀ
I
I
Wake-Up Charging Current (Note 5)
Charging Current Limit
60
80
100
mA
WAKE_UP
C-Grade (Note 6)
LIMIT
l
l
l
l
980
1000
ꢀ000
3000
4000
1070
ꢀ140
3ꢀ10
4ꢀ80
mA
mA
mA
mA
R
R
R
R
= 0 (Short I
= 10k 12
= 33k 12
to GND)
ILIMIT
ILIMIT
ILIMIT
ILIMIT
LIMIT
1960
ꢀ490
39ꢀ0
= Open (or Short I
to V
)
)
LIMIT
CCꢀ
CCꢀ
I-Grade (Note 6)
R
ILIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
= 0 (Short I
= 10k 12
= 33k 12
to GND)
l
l
l
l
930
1000
ꢀ000
3000
4000
1110
ꢀꢀꢀ0
33ꢀ0
4430
mA
mA
mA
mA
LIMIT
1870
ꢀ380
3750
= Open (or Short I
to V
LIMIT
V
V
V
V
V
Resolution
Granularity
Guaranteed Monotonic (5V < V < ꢀ5V)
11
Bits
mV
RES
DAC
DAC
BAT
16
STEP
LIMIT
l
l
l
l
l
Charging Voltage Limit
(Note 7)
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
= 0 (Short V
= 10k 12
= 33k 12
= 100k 12
to GND)
8400
1ꢀ608
1683ꢀ
ꢀ10ꢀ4
843ꢀ
1ꢀ640
16864
ꢀ1056
3ꢀ768
8464
1ꢀ67ꢀ
16896
ꢀ1088
mV
mV
mV
mV
mV
LIMIT
= Open (or Short V
to V
)(Note 13)
LIMIT
CCꢀ
Charge MUX Switches
t
t
GCH1/GCHꢀ Turn-On Time
GCH1/GCHꢀ Turn-Off Time
V
– V
> 3V, C = 3000pF
LOAD
5
10
ms
µs
ONC
GCHX
GCHX
SCHX
SCHX
V
V
– V
< 1V, from Time of
= 3000pF
15
OFFC
< V
– 30mV, C
CSN
BATX
LOAD
V
CH Gate Clamp Voltage
GCH1
GCHꢀ
I
= 1µA
CON
LOAD
V
V
– V
– V
5
5
5.8
5.8
7
7
V
V
GCH1
GCHꢀ
SCH1
SCHꢀ
1760fc
4
For more information www.linear.com/LTC1760
LTC1760
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V,
VVCC2 = 5.2V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
CH Gate Off Voltage
GCH1
I
=10µA
COFF
TOC
FC
LOAD
V
V
– V
– V
–0.8
–0.8
–0.4
–0.4
0
0
V
V
GCH1
GCHꢀ
SCH1
SCHꢀ
GCHꢀ
CH Switch Reverse Turn-Off Voltage
V
– V , 5V ≤ V
≤ ꢀ8V
≤ ꢀ8V
BATX
CSN
BATX
l
l
C-Grade (Note 6)
I-Grade (Note 6)
5
ꢀ
ꢀ0
ꢀ0
40
40
mV
mV
l
CH Switch Forward Regulation Voltage
V
V
– V
, 5V ≤ V
15
35
60
mV
CSN
BATX
BATX
GCH1/GCHꢀ Active Regulation:
Max Source Current
Max Sink Current
– V
= 1.5V
SCHX
GCHX
I
I
–ꢀ
ꢀ
µA
µA
OC(SRC)
OC(SNK)
V
BATX Voltage Below Which
Charging is Inhibited
(Note 14)
3.5
4.7
V
CHMIN
PowerPath Switches
t
t
t
Blanking Period after UVLO Trip
Blanking Period after LOPWR Trip
GB1O/GBꢀO/GDCO Turn-On Time
Switches Held Off
Switches in 3-Diode Mode
< –3V, from Time of Battery/DC
ꢀ50
1
ms
sec
µs
DLY
PPB
l
l
V
5
10
7
ONPO
GS
Removal, or LOPWR Indication, C
= 3000pF
= 3000pF
LOAD
t
GB1O/GBꢀO/GDCO Turn-Off Time
V
> –1V, from Time of Battery/DC
3
µs
OFFPO
GS
Removal, or LOPWR Indication, C
LOAD
V
V
V
V
Output Gate Clamp Voltage
I
LOAD
= 1µA
PONO
POFFO
TOP
GB1O
GBꢀO
GDCO
Highest (V
Highest (V
Highest (V
or V ) – V
4.75
4.75
4.75
6.ꢀ5
6.ꢀ5
6.ꢀ5
7
7
7
V
V
V
BAT1
BATꢀ
DCIN
SCP
GB1O
GBꢀO
GDCO
or V ) – V
SCP
or V ) – V
SCP
Output Gate Off Voltage
I
= –ꢀ5µA
LOAD
GB1O
GBꢀO
GDCO
Highest (V
Highest (V
Highest (V
or V ) – V
0.18
0.18
0.18
0.ꢀ5
0.ꢀ5
0.ꢀ5
V
V
V
BAT1
BATꢀ
DCIN
SCP
GB1O
GBꢀO
GDCO
or V ) – V
SCP
or V ) – V
SCP
PowerPath Switch Reverse
Turn-Off Voltage
V
– V
SCP
or V – V
SCP DCIN
SCP
BATX
6V ≤ V
≤ ꢀ8V
l
l
C-Grade (Note 6)
I-Grade (Note 6)
5
ꢀ
ꢀ0
ꢀ0
60
60
mV
mV
l
PowerPath Switch Forward
Regulation Voltage
V
– V
SCP
or V
– V
SCP
0
ꢀ5
50
mV
FP
BATX
SCP
DCIN
6V ≤ V
≤ ꢀ8V
GDCI/GB1I/GBꢀI Active Regulation:
Source Current
Sink Current
(Note 3)
I
I
–4
75
µA
µA
OP(SRC)
OP(SNK)
t
t
Gate B1I/BꢀI/DCI Turn-On Time
Gate B1I/BꢀI/DCI Turn-Off Time
V
V
< –3V, C
> –1V, C
= 3000pF (Note 4)
= 3000pF (Note 4)
300
10
µs
µs
ONPI
GS
GS
LOAD
OFFPI
LOAD
V
Input Gate Clamp Voltage
I
= 1µA
LOAD
PONI
GB1I
GBꢀI
GDCI
Highest (V
Highest (V
Highest (V
or V ) – V
4.75
4.75
4.75
6.7
6.7
6.7
7.5
7.5
7.5
V
V
V
BAT1
BATꢀ
DCIN
SCP
GB1I
GBꢀI
GDCI
or V ) – V
SCP
or V ) – V
SCP
V
POFFI
Input Gate Off Voltage
I
= –ꢀ5µA
LOAD
GB1I
GBꢀI
GDCI
Highest (V
Highest (V
Highest (V
or V ) – V
0.18
0.18
0.18
0.ꢀ5
0.ꢀ5
0.ꢀ5
V
V
V
BAT1
BATꢀ
DCIN
SCP
GB1I
GBꢀI
GDCI
or V ) – V
SCP
or V ) – V
SCP
1760fc
5
For more information www.linear.com/LTC1760
LTC1760
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V,
VVCC2 = 5.2V unless otherwise noted.
SYMBOL PARAMETER
Thermistor
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Thermistor Trip
C
= 300pF (Note 9)
95
100
105
kΩ
LOAD(MAX)
R1A = RꢀA = 1130Ω 12
R1B = RꢀB = 54900Ω 12
COLD-RANGE to OVER-RANGE
Thermistor Trip
IDEAL-RANGE to COLD-RANGE
C
= 300pF (Note 9)
ꢀ8.5
30
3ꢀ.5
kΩ
LOAD(MAX)
R1A = RꢀA = 1130Ω 12
R1B = RꢀB = 54900Ω 12
Thermistor Trip
HOT-RANGE to IDEAL-RANGE
C
= 300pF (Note 9)
LOAD(MAX)
R1A = RꢀA = 1130Ω 12
R1B = RꢀB = 54900Ω 12
C-Grade (Note 6)
l
l
ꢀ.85
ꢀ.83
3
3
3.15
3.15
kΩ
kΩ
I-Grade (Note 6)
l
Thermistor Trip
UNDER-RANGE to HOT-RANGE
C
= 300pF (Note 9)
4ꢀ5
500
575
Ω
LOAD(MAX)
R1A = RꢀA = 1130Ω 12
R1B = RꢀB = 54900Ω 12
Logic Levels
l
l
l
l
SCL/SCL1/SCLꢀ/SDA/SDA1/
0.8
v
v
SDAꢀ Input Low Voltage (V )
IL
SCL/SCL1/SCLꢀ/SDA/SDA1/
ꢀ.1
–5
SDAꢀ Input High Voltage (V )
IH
SCL/SCL1/SCLꢀ/SDA/SDA1/
SDAꢀ Input Leakage Current
V
V
, V , V
SDAꢀ SCLꢀ
, V
,
5
5
µA
µA
µA
SDA SCL SDA1 SCL1
, V
= 0.8V
SCL/SCL1/SCLꢀ/SDA/SDA1/
SDAꢀ Input Leakage Current
V
V
, V , V
, V
, V
,
–5
SDA SCL SDA1 SCL1 SDAꢀ
= ꢀ.1V
SCLꢀ
I
SCL1/SDA1/SCLꢀ/SDAꢀ Pull-Up
Current When Not Connected to
SMBus Host
V
V
, V , V , V = 0.4V
SCL1 SDA1 SCLꢀ SDAꢀ
165
ꢀꢀ0
350
PULLUP
= 4.85V and 5.55V (Current is Through
VCCꢀ
Internal Series Resistor and Schottky to V
)
CCꢀ
l
l
l
SCL1/SDA1/SCLꢀ/SDAꢀ
V
, V
, V
, V
= 0.8V
300
0.4
0.4
Ω
V
SDA1 SCL1 SDAꢀ SCLꢀ
Series Impedance to Host SMBus
SCL/SDA Output Low Voltage (V ).
LTC1760 Driving the Pin
I
I
= 350µA
OL
PULLUP
PULLUP
SCL1/SDA1/SCLꢀ/SDAꢀ Pullup
Internal to LTC1760
V
Output Low Voltage (V ).
OL
LTC1760 Driving the Pin with Battery
SMBus not Connected to Host SMBus
l
SCL1/SDA1/SCLꢀ/SDAꢀ
I
= 350µA on Host Side
0.4
ꢀ
V
PULLUP
Output Low Voltage (V ).
OL
LTC1760 Driving the Pin with Battery
SMBus Connected to Host SMBus
l
l
SCL/SCL1/SCLꢀ/SDA/SDA1/ SDAꢀ/
SMBALERT Power Down Leakage
V
V
V
= 0V, V
SCL SCL1 SCLꢀ SDA
= 0V,
VDDS
µA
VCCꢀ
, V
, V
, V
,
, V
, V
= 5.5V
SDA1 SDAꢀ SMBALERT
SMBALERT Output Low Voltage (V
)
OL
I
= 500µA
PULLUP
0.4
17.5
1.5
V
SMBALERT Output Pull-Up Current
V
= 0.4V
3.5
10
µA
SMBALERT
l
l
l
V
V
V
DDS
V
DDS
V
DDS
V
DDS
Input Low Voltage (V )
V
V
IL_VDDS
IH_VDDS
IL
IH
ꢀ.6
3
Input High Voltage (V )
5.5
18
V
Operating Voltage
Operating Current
µA
V
V
, V
= V
, V
VDDS
= 5V
SCL SDA
VDDS
l
V
MODE Input Low Voltage (V )
= 4.85V
V • 0.3
VCCꢀ
V
IL_MODE
IL
VCCꢀ
1760fc
6
For more information www.linear.com/LTC1760
LTC1760
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 6). VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V,
VVCC2 = 5.2V unless otherwise noted.
SYMBOL PARAMETER
MODE Input High Voltage (V )
CONDITIONS
= 4.85V
MIN
V • 0.7
VCCꢀ
TYP
MAX
UNITS
V
l
l
l
V
V
IH_MODE
IH
VCCꢀ
MODE Input Current (I )
MODE = V
MODE = V
• 0.7V, V
• 0.3V, V
= 4.85V
= 4.85V
–1
–1
1
1
µA
IH
VCCꢀ
VCCꢀ
VCCꢀ
MODE Input Current (I )
µA
IL
VCCꢀ
Charger Timing
l
t
Timeout for Wake-Up Charging and
Controlled Charging
140
175
1
ꢀ10
sec
sec
TIMEOUT
t
Sampling Rate Used by the LTC1760 to
Update Charging Parameters
QUERY
SMBus Timing
SCL Serial-Clock High Period(t
l
l
l
l
l
l
l
l
)
At I
At I
= 350µA, C
= 350µA, C
= 150pF (Note 8)
= 150pF (Note 8)
4
µs
µs
ns
ns
V
HIGH
PULLUP
LOAD
SCL Serial-Clock Low Period (t
)
4.7
LOW
PULLUP
LOAD
SDA/SCL Rise Time (t )
C
LOAD
C
LOAD
= 150pF, RPU = 9.31k (Note 8)
= 150pF, RPU = 9.31k (Note 8)
1000
300
r
SDA/SCL Fall Time (t )
f
SMBus Accelerator Trip Voltage Range
Start-Condition Setup Time (t
0.8
4.7
4
1.4ꢀ
)
µs
µs
ns
SU:STA
Start-Condition Hold Time (t
SDA to SCL Rising-Edge
)
HD:STA
ꢀ50
Setup Time (t
)
SU:DAT
l
l
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data (t
300
ꢀ5
ns
)
HD:DAT
t
The LTC1760 will Release the SMBus
and Terminate the Current Master or
Slave Command if the Command is not
Completed Before this Time
35
ms
TIMEOUT_
SMB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
lower than the terminal voltage. Refer to “Operation Section 3.7” for more
information.
Note 8: C
is the combined capacitance on the host’s SMBus
LOAD
connection and the selected battery’s SMBus connection.
Note 2: Battery voltage must be adequate to drive gates of PowerPath
P-channel FET switches. This does not affect charging voltage of the
battery, which can be zero volts during wake-up charging.
Note 9: C is the maximum allowed combined capacitance on
THxA, THxB and the battery’s SafetySignalx connections.
LOAD_MAX
Note 10: Does not include current supplied by V to V
(I or
CCꢀ VCCꢀ_AC1
CC
Note 3: DCIN, BAT1, BATꢀ are held at 1ꢀV and GDCI, GB1I, GBꢀI are
forced to 10.5V. SCP is set at 1ꢀV to measure source current at GDCI,
GB1I and GBꢀI. SCP is set at 11.9V to measure sink current at GDCI, GB1I
and GBꢀI.
I
)
VCCꢀ_AC0
Note 11: Measured with thermistors not present, R
removed and SMBALERT = 1. See Applications Information section:
“Calculating IC Operating Current” for example on how to calculate total IC
operating current.
and R
ILIMIT
VLIMIT
Note 4: Extrapolated from testing with C = 50pF.
L
Note 5: Accuracy dependent upon external sense resistor and
compensation components.
Note 6: The LTC1760 is tested under pulsed load conditions such that T ≈
Note 12: Requested currents below 44mV/R
may not servo correctly
SENSE
due to charger offsets. The charging current for requested currents below
4mV/R will be between 4mV/R and (Requested Current – 8mA).
J
SENSE
SENSE
T . The LTC1760C is guaranteed to meet specifications from 0°C to 70°C
Refer to Applications Information: “Setting Charger Output Current Limit”
for values of R
Note 13: This limit is greater than the absolute maximum for the charger.
Therefore, there is no effective limitation for the voltage when this option
is selected.
A
junction temperature. Specifications over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC1760I is guaranteed
over the –40°C to 1ꢀ5°C operating junction temperature range.
.
SENSE
Note 7: Charger servos to the value reported by a Voltage() query. This is
the internal cell voltage measured by the battery electronics and may be
Note 14: Does not apply to Wake-Up Mode.
1760fc
7
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LTC1760
TYPICAL PERFORMANCE CHARACTERISTICS
Dual Battery Charge Time vs
Sequential Battery Charging
Charging Voltage Accuracy
Charging Current Accuracy
0
–5
10
5
3500
3000
2500
2000
1500
1000
500
BAT2
CURRENT
BAT1
CURRENT
SEQUENTIAL
0
–10
0
–5
3500
3000
2500
2000
1500
1000
500
BAT1
CURRENT
–15
–20
–25
–10
–15
–20
BAT2
DUAL
CURRENT
100
MINUTES
0
4700
7132
9564
11996 14428 16860
0
800
1600
2400
3200
4000
0
100
150
200 250
300
50
ChargingCurrent() (mA)
TIME (MINUTES)
ChargingVoltage() (mV)
1760 G01
1760 G02
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
REQUESTED CURRENT = 3A
REQUESTED VOLTAGE = 12.3V
MAX CHARGER CURRENT = 4.1A
1760 G03
Dual Battery Discharge Time vs
Sequential Battery Discharge
(Li-Ion)
Dual Battery Dischage Time vs
Sequential Battery Discharge
(NiMH)
Dual Charging Batteries with
Different Charge State
3500
3000
2500
2000
1500
1000
500
15
14
13
12
11
10
15
14
13
12
11
10
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
BAT2
VOLTAGE
BAT1
12.0
11.0
10.0
9.0
BAT1
VOLTAGE
DUAL
BAT2
VOLTAGE
DUAL
VOLTAGE
BAT2
VOLTAGE
BAT1
VOLTAGE
BAT2
8.0
BAT2
VOLTAGE
SEQUENTIAL
VOLTAGE
12.0
11.0
10.0
9.0
SEQUENTIAL
BAT1
CURRENT
BAT1
VOLTAGE
BAT1
BAT2
CURRENT
VOLTAGE
11
MINUTES
16
MINUTES
0
8.0
20 40 60 80 100
TIME (MINUTES)
120
140 160
0
160
0
20
60
80
100
140
0
20
60 80 100
140
180
40
120
40
120
1760 G04
TIME (MINUTES)
TIME (MINUTES)
BAT1 INITIAL CAPACITY = 0%
BAT2 INITIAL CAPACITY = 90%
PROGRAMMED CHARGER CURRENT = 3A
PROGRAMMED CHARGER VOLTAGE = 16.8V
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
LOAD CURRENT = 3A
BATTERY TYPE: 12V NiMH (MOLTECH NJ1020)
1760 G06
1760 G05
LOAD: 33W
1760fc
8
For more information www.linear.com/LTC1760
LTC1760
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Charging Current
Load Dump
Load Regulation
100
90
80
70
60
50
40
30
20
10
0
14
12
10
8
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
BAT1
OUTPUT
V
= 20V
IN
V
= 12.29V
DAC
DAC
I
= 3000mA
LOAD CURRENT = 1A
T
= 25°C
A
6
LOAD
CONNECTED
4
V
V
= 20V
IN
= 12.288V
DAC
= 4000mA
DAC
LOAD
2
I
DISCONNECTED
T
= 25°C
A
0
2.5 4.0
–4 –2
0
2
4
6
8
10 12 14 16
0
0.025
0.10
0.50
0
1000
2000
3000
4000
TIME (ms)
I
(A)
CHARGE CURRENT (mA)
OUT
1760 G08
1760 G07
1760 G09
PowerPath Switching 1 and 2
SMBus Accelerator Operation
16
V
C
T
= 5V
C
I
A
= 20F
CC
LD
A
LOAD
LOAD
= 200pF
15
14
13
12
11
10
9
= 0.8A
5V
= 25°C
T
= 25°C
LTC1760
R
= 15k
PULLUP
LOPWR
THRESHOLD
0V
8
7
6
–50 –40 –30
–20 –10
0
10 20 30 40 50
1µs/DIV
TIME (µs)
1760 G11
1960 G10
PIN FUNCTIONS
Input Power Related
side) of the sense resistor, R , in series with the three
SC
PowerPath switch pairs, for detecting short-circuit cur-
SCN (Pin 4): PowerPath Current Sensing Negative Input.
rent events.
This pin should be connected directly to the “bottom”
(output side) of the sense resistor, R , in series with the
GDCO (Pin 6): DCIN Output Switch Gate Drive. Together
with GDCI, this pin drives the gate of the P-channel switch
in series with the DCIN input switch.
SC
three PowerPath switch pairs, for detecting short-circuit
currentevents.AlsopowerstheLTC1760internalcircuitry
when all other sources are absent.
GDCI(Pin7):DCINInputSwitchGateDrive. Togetherwith
GDCO, this pin drives the gate of the P-channel switch
connected to the DCIN input.
SCP (Pin 5): PowerPath Current Sensing Positive Input.
This pin should be connected directly to the “top” (switch
1760fc
9
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LTC1760
PIN FUNCTIONS
GB1O (Pin 8): BAT1 Output Switch Gate Drive. Together
with GB1I, this pin drives the gate of the P-channel switch
in series with the BAT1 input switch.
CSP (Pin 35): Current Amplifier CA1 Input. This pin and
the CSN pin measure the voltage across the charge cur-
rent sense resistor, R
, to provide the instantaneous
SENSE
currentsignalsrequiredforbothpeakandaveragecurrent
GB1I (Pin 9): BAT1 Input Switch Gate Drive. Together with
GB1O, this pin drives the gate of the P-channel switch
connected to the BAT1 input.
mode operation.
COMP1 (Pin 37): The Compensation Node for the Am-
plifier CL1. A capacitor is required from this pin to GND
if input current amplifier CL1 is used. At input adapter
current limit, this node rises to 1V. By forcing COMP1 to
GND, amplifier CL1 will be defeated (no adapter current
limit). COMP1 can source 10µA.
GB2O (Pin 10): BATꢀ Output Switch Gate Drive. Together
with GBꢀI, this pin drives the gate of the P-channel switch
in series with the BATꢀ input switch.
GB2I (Pin 11): BATꢀ Input Switch Gate Drive. Together
withGBꢀO, thispindrivesthegateoftheP-channelswitch
connected to the BATꢀ input.
BGATE (Pin 39): Drives the gate of the bottom external
MOSFET of the battery charger buck converter.
CLP (Pin 36): The Positive Input to the Supply Current
LimitingAmplifierCL1.Thethresholdissetat100mVabove
the voltage at the DCIN pin. When used to limit supply
current, a filter is needed to filter out the switching noise.
SW (Pin 42): PWM Switch Node. Connected to the source
of the top external MOSFET. Used as reference for top
gate driver.
BOOST (Pin 43): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below V to (DCIN + V ).
Battery Charging Related
V
(Pin 13): The Tap Point of a Programmable Resistor
SET
CC
CC
Divider which Provides Battery Voltage Feedback to the
TGATE(Pin44):DrivesthegateofthetopexternalMOSFET
of the battery charger buck converter.
Charger. A capacitor from CSN to V and from V to
SET
SET
GND provide necessary compensation and filtering for
the voltage loop.
SCH1 (Pin 45), SCH2 (Pin 48): Charger MUX N-Channel
Switch Source Returns. These two pins are connected to
the sources of the back-to-back switch pairs Q3/Q4 and
Q9/Q10 (see Typical Applications). A small pull-down cur-
rent source returns these nodes to 0V when the switches
are turned off.
I
(Pin 14): The Control Signal of the Inner Loop of the
TH
Current Mode PWM. Higher I voltage corresponds to
TH
higher charging current in normal operation. A capacitor
of at least 0.1µF to GND filters out PWM ripple. Typical
full-scale output current is 30µA. Nominal voltage range
for this pin is 0V to ꢀ.4V.
GCH1 (Pin 46), GCH2 (Pin 47): Charger MUX N-Channel
Switch Gate Drives. These two pins drive the gates of the
back-to-back switch pairs, Q3/Q4 and Q9/Q10, between
the charger output and the two batteries (see Typical
Applications).
I
(Pin 15): A capacitor from I to GND is required to
SET
SET
filterhigherfrequencycomponentsfromthedelta-sigmaI
.
DAC
I
(Pin 32): An external resistor (R
) is connected
ILIMIT
LIMIT
between this pin and GND. The value of the external resis-
tor programs the range and resolution of the programmed
charger current.
External Power Supply Pins
V
PLUS
(Pin 1): Supply. The V
pin is connected via
PLUS
four internal diodes to the DCIN, SCN, BAT1, and BATꢀ
pins. Bypass this pin with a 0.1µF capacitor and a 1µF
capacitor (see Typical Applications for complete circuit).
V
(Pin33):Anexternalresistor(R
)isconnected
LIMIT
VLIMIT
between this pin and GND. The value of the external resis-
tor programs the range and resolution of the voltage DAC.
BAT1 (Pin 3), BAT2 (Pin 2): These two pins are the inputs
from the two batteries for power to the LTC1760.
CSN (Pin 34): Current Amplifier CA1 Input. Connect this
to the common output of the charger MUX switches.
1760fc
10
For more information www.linear.com/LTC1760
LTC1760
PIN FUNCTIONS
LOPWR (Pin 12): LOPWR Comparator Input from SCN
ExternalResistorDividertoGND.IfthevoltageatLOPWR
pin is lower than the LOPWR comparator threshold, then
system power has failed and power is autonomously
switched to a higher voltage source, if available.
cators. RequiresanexternalpulluptoV
(normalSMBus
DDS
operating mode). Connected to internal SMBus accelerator.
SCL1(Pin19):SMBusClockSignaltoSmartBattery1. Do
not connect to an external pull-up. The LTC1760 connects
this pin to an internal pull-up (I
) when required.
PULLUP
DCDIV (Pin 16): External DC Source Comparator Input
from DCIN External Resistor Divider to GND. If the
voltage at DCDIV pin is above the DCDIV comparator
threshold, then the AC_PRESENT bit is set and the wall
adapter power is considered to be adequate to charge
SDA2 (Pin 21): SMBus Data Signal to Smart Battery ꢀ. Do
not connect to an external pull-up. The LTC1760 connects
this pin to an internal pull-up (I ) when required.
PULLUP
SDA (Pin 22): SMBus Data Signal to SMBus Host. Also
used to indicate charging status of Battery ꢀ. Requires
the batteries. If DCDIV rises more than 1.8V above V ,
CC
an external pullup to V . Connected to internal SMBus
then all of the power path switches are latched off until
all power is removed. A capacitor from DCDIV to GND is
recommendedtopreventnoise-inducedfalseemergency
turn-offconditionsfrombeingdetected.Referto“Section
8.3” and “Typical Application”.
DDS
accelerator.
SDA1 (Pin 23): SMBus Data Signal to Smart Battery 1. Do
not connect to an external pull-up. The LTC1760 connects
this pin to an internal pull-up (I ) when required.
PULLUP
DCIN(Pin41):Supply.ExternalDCpowersource.A0.1µF
bypass capacitor must be connected to this pin as close
as possible. No series resistance is allowed, since the
adapter current limit comparator input is also this pin.
MODE (Pin 26): Used in conjunction with V
to allow
DDS
SCL,SDAandSMBALERTtoindicatechargingstatus.May
also be used as a hardware charge inhibit.
TH2B (Pin 27): Thermistor Force/Sense Connection
to Smart Battery ꢀ SafetySignal. Connect to Battery ꢀ
thermistor through resistor network shown in “Typical
Application.”
Internal Power Supply Pins
V
(Pin 20): Power Supply for SMBus Accelerators.
DDS
Also used in conjunction with MODE pin to modify the
LTC1760 operating mode.
TH2A (Pin 28): Thermistor Force/Sense Connection
to Smart Battery ꢀ SafetySignal. Connect to Battery ꢀ
thermistor through resistor network shown in “Typical
Application.”
GND (Pin 24): Ground for Low Power Circuitry.
V
(Pin 25): Power Supply is used Primarily to Power
CC2
Internal Logic Circuitry. Must be connected to V .
CC
SMBALERT (Pin 29): Active Low Interrupt Pin. Signals
SMBus Host that there has been a change of status in
battery or AC presence. Open drain with weak current
PGND (Pin 38): High Current Ground Return for BGATE
Driver.
V
CC
(Pin 40): Internal Regulator Output. Bypass this
source pull-up to V
(with Schottky to allow it to be
CCꢀ
output with at least a ꢀµF to 4.7µF capacitor. Do not use
this regulator output to supply external circuitry except
as shown in the application circuit.
pulled to 5V externally). Also used to indicate charging
status of Battery 1.
TH1A (Pin 30): Thermistor Force/Sense Connection
to Smart Battery 1 SafetySignal. Connect to Battery 1
thermistor through resistor network shown in “Typical
Application.”
SBS Interface Pins
SCL2(Pin17):SMBusClockSignaltoSmartBatteryꢀ. Do
not connect to an external pull-up. The LTC1760 connects
this pin to an internal pull-up (I ) when required.
PULLUP
TH1B (Pin 31): Thermistor Force/Sense Connection
to Smart Battery 1 SafetySignal. Connect to Battery 1
thermistor through resistor network shown in “Typical
Application.”
SCL (Pin 18): SMBus Clock Signal to SMBus Host. Also
used to determine flashing rate for stand-alone charge indi-
1760fc
11
For more information www.linear.com/LTC1760
LTC1760
BLOCK DIAGRAM
GB1I GB1O
GB2I GB2O
11 10
GDCI GDCO
9
8
7
6
100mV
SCP
SCN
5
4
+
SHORT CIRCUIT
100Ω
SWB1
DRIVER
SWB2
DRIVER
SWDC
DRIVER
–
I
32
33
LIMIT
LIMIT
DECODER
V
LIMIT
CHARGE
PUMP
V
CC2
DCIN
10µA
ON
–
GCH1
SCH1
46
45
+
SMBALERT
29
26
ON
–
+
SEQUENCER
MODE
GCH2
47
CSN
AC_PRESENT
V
20
18
22
19
23
17
DDS
SCH2
BAT1
48
3
SCL
SDA
SMBus
INTERFACE
2
BAT2
SCL1
SDA1
SCL2
CHARGE
V
1
SCN
PLUS
21 SDA2
V
25
40
24
CC2
V
CC
TH1A
TH1B
30
31
28
27
15
V
CC
REGULATOR
SAFETY
SIGNAL
GND
TH2A
TH2B
DECODER
+
–
16
DCDIV
I
PowerPath
CONTROLLER
10-BIT ∆Σ
CURRENT DAC
SET
+
–
LOPWR
DCIN
12
41
1.19V
CSP-CSN
3kΩ
–
0.86V
3k
3k
0V
–
CSP
CSN
35
34
CSN
OSCILLATOR
+
–
CA1
+
LOW DROP
DETECT
BGATE
T
ON
g
= 1.4m
–
+
m
CA2
43
44
42
BOOST
TGATE
SW
0.8V
BUFFERED I
+
TH
15
S
+
PWM
LOGIC
–
I
Q
CMP
V
CC
3mV
–
R
BGATE
PGND
39
38
–
+
I
REV
40mV
Ω
DCIN
100mV
g = 0.4m
m
+
400k
CL1
–
Ω
36
CLP
V
13
11-BIT ∆Σ
VOLTAGE DAC
SET
g
m
= 1.4m
EA
+
0.8V
37
COMP1
14
1760 BD
I
TH
1760fc
12
For more information www.linear.com/LTC1760
LTC1760
(For Operation Section)
TABLE OF CONTENTS
1 Overview................................................................................................................................................................................................... 14
ꢀ The SMBus Interface................................................................................................................................................................................. 14
ꢀ.1 SMBus Interface Overview................................................................................................................................................................ 14
ꢀ.3 Description of Supported SMBus Functions ..................................................................................................................................... 17
ꢀ.3.1 BatterySystemState() (0×01) .................................................................................................................................................. 17
ꢀ.3.ꢀ BatterySystemStateCont() (0×0ꢀ)........................................................................................................................................... 18
ꢀ.3.3 BatterySystemInfo() (0×04).................................................................................................................................................... 19
ꢀ.3.4 LTC() (0×3C) ........................................................................................................................................................................... ꢀ0
ꢀ.3.5 BatteryMode() (0×03) ............................................................................................................................................................ ꢀ0
ꢀ.3.6 Voltage() (0×09)...................................................................................................................................................................... ꢀ0
ꢀ.3.7 Current() (0×0A) ..................................................................................................................................................................... ꢀ1
ꢀ.3.8 ChargingCurrent() (0×14) ....................................................................................................................................................... ꢀ1
ꢀ.3.9 ChargingVoltage() (0×15) ....................................................................................................................................................... ꢀ1
ꢀ.3.10 AlarmWarning() (0×16)........................................................................................................................................................... ꢀ1
ꢀ.3.11 AlertResponse() ...................................................................................................................................................................... ꢀꢀ
ꢀ.4 SMBus Dual Port Operation.............................................................................................................................................................. ꢀꢀ
ꢀ.5 LTC1760 SMBus Controller Operation............................................................................................................................................... ꢀ3
ꢀ.6 LTC1760 SMBALERT Operation ........................................................................................................................................................ ꢀ6
3 Charging Algorithm Overview................................................................................................................................................................... ꢀ6
3.1 Wake-Up Charging Initiation............................................................................................................................................................. ꢀ6
3.ꢀ Wake-Up Charging Termination ........................................................................................................................................................ ꢀ6
3.3 Wake-Up Charging Current and Voltage Limits................................................................................................................................. ꢀ7
3.4 Controlled Charging Initiation ........................................................................................................................................................... ꢀ7
3.5 Controlled Charging Termination ...................................................................................................................................................... ꢀ7
3.6 Controlled Charging Current Programming ...................................................................................................................................... ꢀ8
3.6.1 Current Limits When Charging A Single Battery...................................................................................................................... ꢀ8
3.6.ꢀ Current Limits When Charging Two Batteries (TURBO Mode Disabled) .................................................................................. ꢀ8
3.6.3 Current Limits When Charging Two Batteries (TURBO Mode Enabled).................................................................................... ꢀ9
3.7 Controlled Charging Voltage Programming....................................................................................................................................... ꢀ9
4 System Power Management Algorithm and Battery Calibration................................................................................................................ ꢀ9
4.1 Turning Off System Power................................................................................................................................................................ ꢀ9
4.ꢀ Power-By Algorithm When No Battery is Being Calibrated................................................................................................................ ꢀ9
4.3 Power-By Algorithm When a Battery is Being Calibrated................................................................................................................... 30
4.4 Power-By Reporting.......................................................................................................................................................................... 30
5 Battery Calibration (Conditioning)............................................................................................................................................................. 30
5.1 Selecting a Battery to be Calibrated ................................................................................................................................................. 30
5.ꢀ Initiating Calibration of Selected Battery ........................................................................................................................................... 31
5.3 Terminating Calibration of Selected Battery ...................................................................................................................................... 31
6 MODE Pin Operation................................................................................................................................................................................. 31
6.1 Standalone Charge Indication ........................................................................................................................................................... 31
6.ꢀ Hardware Charge Inhibit ................................................................................................................................................................... 3ꢀ
6.3 Charging When SCL And SDA Are Low............................................................................................................................................. 3ꢀ
6.4 Charging With an SMBus Host ......................................................................................................................................................... 3ꢀ
7 Battery Charger Controller ........................................................................................................................................................................ 3ꢀ
7.1 Charge MUX Switches ...................................................................................................................................................................... 33
7.ꢀ Dual Charging ................................................................................................................................................................................... 33
8 PowerPath Controller................................................................................................................................................................................ 33
8.1 Autonomous PowerPath Switching................................................................................................................................................... 34
8.ꢀ Short-Circuit Protection.................................................................................................................................................................... 34
8.3 Emergency Turn-Off.......................................................................................................................................................................... 34
8.4 Power-Up Strategy............................................................................................................................................................................ 34
9 The Voltage DAC Block ............................................................................................................................................................................. 35
10 The Current DAC Block ............................................................................................................................................................................. 35
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LTC1760
OPERATION (Refer to Block Diagram and Typical Application Figure)
1 Overview
diode-like behavior from the FET switches, without the
attendant high power dissipation from diodes. The Host
is informed of this 3-Diode mode status when it polls the
PowerPath status register via the SMBus interface. High
speed PowerPath switching at the LOPWR trip point is
handled autonomously.
The LTC1760 is composed of an SMBus interface with
dual port capability, a sequencer for managing system
power and the charging and discharging of two batteries,
a battery charger controller, charge MUX controller, Pow-
erPath controller, a 10-bit current DAC (I ) and 11-bit
voltage DAC (V ). When coupled with optional system
DAC
Simultaneous discharge of both batteries is supported.
The switch drivers prevent reverse current flow in the
switches and automatically discharge both batteries into
the load, sharing current according to the relative capacity
ofthebatteries.Simultaneousdualdischargecanincrease
battery operating time by up to 102 by reducing losses
in the switches and reducing internal battery losses as-
sociated with high discharge rates.
DAC
software for generating composite battery information,
it forms a complete Smart Battery System Manager for
charging and selecting two smart batteries. The battery
charger is controlled by the sequencer which uses a Level
3 SMBus interface to read ChargingVoltage(), Voltage(),
ChargingCurrent(),Current(),Alarm()andBatteryMode().
Thisinformation, together with thermistormeasurements
allows the sequencer to select the charging battery and
safely servo on voltage and current. Charging can be
accomplished only if the voltage at DCDIV indicates that
sufficientvoltageisavailablefromtheinputpowersource,
usually an AC adapter. The charge MUX, which selects
the battery to be charged, is capable of charging both
batteries simultaneously. The charge MUX switch drivers
are configured to allow charger current to share between
the two batteries and to prevent current from flowing in
a reverse direction in the switch. The amount of current
that each battery receives will depend upon the relative
capacity of each battery and the battery voltage. This can
resultinsignificantlyshorterchargingtimes(upto502for
Li-Ion batteries) than sequential charging of each battery.
2 The SMBus Interface
2.1 SMBus Interface Overview
The SMBus interface allows the LTC1760 to communi-
cate with two batteries and the SMBus Host. The SMBus
Interface supports true dual port operation by allowing
the SMBus Host to be connected to the SMBus of either
battery. The LTC1760 is able to operate as an SMBus
Master or Slave device. The LTC1760 SMBUS address is
0×14 (8-bit format).
References:
Smart Battery System Manager Specification: Revision
1.1, SBS Implementers Forum.
The sequencer also selects which of the pairs of PFET
switches will provide power to the system load. If the
system voltage drops below the threshold set by the
LOPWR resistor divider, then all of the output-side PFETs
are turned on quickly. The input-side PFETs act as diodes
in this mode and power is taken from the highest voltage
source available at the DCIN, BAT1, or BATꢀ inputs. The
input-sidePowerPathswitchdriverthatisdeliveringpower
then closes its input switch to reduce the power dissipa-
tion in the PFET bulk diode. In effect, this system provides
Smart Battery Data Specification: Revision 1.1, SBS Imp-
lementers Forum.
Smart Battery Charger Specification: Revision 1.1, SBS Imp-
lementers Forum
SystemManagementBusSpecification:Revision1.1,SBS
Implementers Forum
ꢀ
I C-Bus and How to Use it: V1.0, Philips Semiconductor.
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LTC1760
OPERATION
2.2 Data Bit Definition of Supported SMBus Functions.
LTC1760
SMBus
Mode
Data Bit or Nibble Definition/Allowed Values
(See section 2.3 for Details)
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
SMBus
Address
Command Data
Code
Function
Access
Type
BatterySystemState()
Slave
Read/ 7-bit:
Write 0001_010b
0×01
Status/
Control
8-bit:
0×14
0
0
0/1 0/1 0
0
0/1 0/1 0
0
0/1 0/1 0
0 0/1 0/1
BatterySystemStateCont()
Slave
Read/ 7-bit:
Write 0001_010b
0×0ꢀ
Status/
Control
8-bit:
0×14
0
0
0
0
0
0
0/1 0/1 0 0/1 0/1 0/1 0/1 1 0/1 0/1
BatterySystemInfo()
LTC()
Slave
Slave
Read 7-bit:
0001_010b
0×04
0×3C
Status
BATTERY
SYSTEM
REVISION
BATTERY
RESERVED
RESERVED
SUPPORTED
8-bit:
0×14
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
Read/ 7-bit:
Write 0001_010b
Status/
Control
8-bit:
0×14
0/1 0
0
0
0
0
0
1
0/1 0
0
0
0
0
0
1
BatteryMode()
Master
Read 7-bit:
0001_011b
0×03
Status
8-bit:
0×16
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
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LTC1760
OPERATION
Data Bit or Nibble Definition/Allowed Values
(See section 2.3 for Details)
LTC1760
Mode
SMBus
Address
Command Data
Function
Access
Code
Type D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
Current()
Master
Master
Master
Master
Master
Read 7-bit:
0001_011b
0×0A
Value
8-bit:
0×16
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Voltage()
Read 7-bit:
0001_011b
0×09
0×14
0×15
0×16
Status/
Control
8-bit:
0×16
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Status
ChargingCurrent()
ChargingVoltage()
AlarmWarning()
Read 7-bit:
0001_011b
8-bit:
0×16
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Read 7-bit:
0001_011b
Status/
Control
8-bit:
0×16
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Status
Read 7-bit:
0001_010b
8-bit:
0×16
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Register
AlertResponse()
see (1)
Slave
Read
Byte
7-bit:
0001_100b
N/A
8-bit:
0×18
0
0
0
1
0
1
0
0
(1) Read-byte format. 0×14 is returned as the interrupt address of the LTC1760.
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LTC1760
OPERATION
2.3 Description of Supported SMBus Functions
The functions are described as follows:
Function Name() (command code)
Description:
• TheLTC1760autonomouslychangestheconfiguration
of the batteries being charged (Polling only).
Purpose:
Used by the SMBus Host to determine the present state
of the LTC1760 and the attached batteries. It also may be
used to determine the state of the battery system after
the LTC1760 notifies the SMBus Host of a change via
SMBALERT.
A brief description of the function.
Purpose:
The purpose of the function, and an example where ap-
propriate.
SMBus Protocol: Read or Write Word.
Input/Output: word – Refer to “Section ꢀ.ꢀ” for bit
mapping.
SMBus Protocol: Refer to Section ꢀ.5 and to the SMBus
specification for more details.
SMB_BAT[4:1] Nibble
Input, Output or Input/Output: A description of the data
supplied to, or returned by, the function.
Theread/writeSMB_BAT[4:1]nibbleisusedbytheSMBus
Host to select with which individual battery to commu-
nicate or to determine with which individual battery it is
communicating.
Whenever the LTC1760 encounters a valid command with
invalid data, it ACKs the command, and ignores the invalid
data. For example, if an attempt is made to select Battery
1 and ꢀ to simultaneously communicate with the system
host, the LTC1760 will just ignore the request.
For example, an application that displays the remaining
capacity of all batteries would write to this nibble to in-
dividually select each battery in turn and get its capacity.
2.3.1 BatterySystemState() (0×01)
Allowed values are:
Description:
0010b: SMBus Host is communicating with Battery ꢀ.
ThisfunctionreturnsthepresentstateoftheLTC1760and
allows access to individual batteries. The information is
broken into four nibbles that report:
0001b: SMBus Host is communicating with Battery 1.
(Power On Reset Value)
To change this nibble, set only one of the lower two bits
of this nibble high. All other values will simply be ignored.
Which battery is communicating with the SMBus Host
Which batteries, if any, or AC is powering the system
Which batteries are connected to the Smart Charger
Which batteries are present.
POWER_BY_BAT[4:1] Nibble
The read only POWER_BY_BAT[4:1] nibble is used by the
SMBus Host to determine which batteries are powering
the system. All writes to this nibble will be ignored.
The LTC1760 provides a mechanism to notify the system
whenever there is a change in its state. Specifically, the
LTC1760providesthesystemwithanotificationwhenever:
Allowed values are:
0011b: System powered by both Battery ꢀ and Battery 1
simultaneously.
• A battery is added or removed (Polling or SMBALERT).
• AC power is connected or disconnected (Polling or
0010b: System powered by Battery ꢀ only.
0001b: System powered by Battery 1 only.
0000b: System powered by AC adapter only.
SMBALERT).
• TheLTC1760autonomouslychangestheconfigura-tion
of the batteries supplying power (Polling only).
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LTC1760
OPERATION
CHARGE_BAT[4:1] Nibble
power configuration. It may also be used by the system
to prohibit any battery charging.
The read only CHARGE_BAT[4:1]nibble is used by the
SMBus Host to determine which, if any, battery is being
charged. All writes to this nibble will be ignored.
SMBus Protocol: Read or Write Word.
Input/Output: word - Refer to “Section ꢀ.ꢀ” for bit
mapping
Allowed values are:
0011b: Both Battery ꢀ and Battery 1 being charged.
0010b: Only Battery ꢀ is being charged.
0001b: Only Battery 1 is being charged.
0000b: No battery being charged.
AC_PRESENT Bit
The read only AC_PRESENT bit is used to show the user
the status of AC availability to power the system. It may
be used internally by the SMBus Host in conjunction with
other information to determine when it is appropriate to
allow a battery conditioning cycle. Whenever there is a
change in the AC status, the LTC1760 asserts SMBALERT
low. In response, the system has to read this register to
determine the actual presence of AC. The LTC1760 uses
the DCDIV pin to measure the presence of AC.
An indication that multiple batteries are being charged
simultaneously does not indicate that the batteries are
being charged at the same rate or that they will complete
their charge at the same time. To actually determine
when an individual battery will be fully charged, use the
SMB_BAT[4:1] nibble to individually select the battery of
interest and read the TimeToFull() value.
Allowed values are:
1b: The LTC1760 has determined that AC is present.
PRESENT_BAT[4:1] Nibble
0b: The LTC1760 has determined that AC is not pres-
ent.
The read only PRESENT_BAT[4:1]nibble is used by the
SMBus Host to determine how many and which batteries
are present. All writes to this nibble will be ignored.
POWER_NOT_GOOD Bit
The read only POWER_NOT_GOOD bit is used to show
thatthevoltagedeliveredtothesystemloadisinadequate.
This is determined by the LOPWR comparator.
Allowed values are:
0011b: Both Battery ꢀ and Battery 1 are present.
0010b: Only Battery ꢀ is present.
0001b: Only Battery 1 is present.
0000b: No batteries are present.
ThePOWER_NOT_GOODbitwillalsobesetiftheLTC1760
has detected a short circuit condition (see “Section 8.ꢀ”)
or an emergency turn-off condition (see “Section 8.3”).
Under either of these conditions the power paths will be
shut off even if battery or DC power is available.
2.3.2 BatterySystemStateCont() (0×02)
Allowed values are:
Description:
1b: The LTC1760 has determined that the voltage
delivered to the system load is inadequate.
This function returns additional state information of the
LTC1760 and provides a mechanism to prohibit charging.
This command also removes any requirement for the
SMBus Host to communicate directly with the charger to
obtainACpresenceinformation.WhentheLTC1760isused,
access to the charger 8-bit address, 0×01ꢀ, is blocked.
0b: The LTC1760 has determined that the voltage
delivered to the system load is adequate.
CALIBRATE_REQUEST_SUPPORT Bit
The read only CALIBRATE_REQUEST_SUPPORT bit is
always set high to indicate that the LTC1760 has a mecha-
nism to determine when any of the attached batteries are
in need of a calibration cycle.
Purpose:
Used by the SMBus Host to retrieve additional state
information from the LTC1760 and the overall system
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LTC1760
OPERATION
CALIBRATE_REQUEST Bit
CALIBRATE_BAT[4:1] Nibble
The read only CALIBRATE_REQUEST bit is set whenever
the LTC1760 has determined that one or both of the con-
nected batteries need a calibration cycle.
The read/write CALIBRATE_BAT[4:1]nibble is used by the
SMBus Host to select the battery to be calibrated or to
determine which individual battery is being calibrated.
Allowed values are:
Allowed read values are:
1b: The LTC1760 has determined that one or both
batteries requires calibration.
0010b: Battery ꢀ is being calibrated. CALIBRATE must
be 1.
0b: The LTC1760 has determined that neither battery
require calibration.
0001b: Battery 1 is being calibrated. CALIBRATE must
be 1.
CHARGING_INHIBIT Bit
0000b: No batteries are being calibrated.
Allowed write values are:
The read/write CHARGING_INHIBIT bit is used by the
SMBusHosttoinhibitchargingortodetermineifcharging
is inhibited. This bit is also set if the MODE pin is used to
inhibit charging.
0010b: Select Battery ꢀ for calibration.
0001b: Select Battery 1 for calibration.
0000b: Allow LTC1760 to choose battery to be cali-
brated.
Allowed values are:
1b: The LTC1760 will not allow any battery charging
to occur.
All other values will simply be ignored. This provides a
mechanismtoupdatetheotherBatterySystemStateCont()
bits without altering this nibble.
0b: The LTC1760 may charge batteries as needed,
(Power On Reset Value).
2.3.3 BatterySystemInfo() (0×04)
CHARGER_POR Bit
Description:
The read/write CHARGER_POR bit is used to force a char-
ger power on reset.
The SMBus Host uses this function to determine the
capabilities of the LTC1760.
Writing a 1 to this bit will cause a charger power on reset
with the following effects.
Purpose:
• Charging will be turned off and wake-up charging will
be resumed. This is the same as if the batteries were
removed and then reinserted.
Allows the SMBus Host to determine the number of bat-
teries the LTC1760 supports as well as the specification
revision implemented by the LTC1760.
• The three minute wake-up watchdog timer will be
restarted.
SMBus Protocol: Read Word
Input/Output: word — Refer to “Section ꢀ.ꢀ” for bit map-
ping.
Writing a 0 to this bit has no effect. A read of this bit
always returns a 0.
BATTERIES_SUPPORTED Nibble
CALIBRATE Bit
The read only BATTERIES_SUPPORTED nibble is used
by the SMBus Host to determine how many batteries the
LTC1760 can support. The two-battery LTC1760 always
returns 0011b for this nibble.
The read/write CALIBRATE bit is used either to show the
status of battery calibration cycles in the LTC1760 or to
begin or end a calibration cycle.
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LTC1760
OPERATION
BATTERY_SYSTEM_REVISION Nibble
2.3.5 BatteryMode() (0×03)
The read only BATTERY_SYSTEM_REVISION nibble re-
ports the version of the Smart Battery System Manager
specification supported.
Description:
This function is used by the LTC1760 to read the battery’s
Mode register.
LTC1760 always returns 1000b for this nibble, indicating
Version 1.0 without optional PEC support.
Purpose:
Allows the LTC1760 to determine if a battery requires a
conditioning/calibration cycle.
2.3.4 LTC() (0×3C)
Description:
SMBus Protocol: Read Word. LTC1760 reads Battery 1
or Battery ꢀ as an SMBus Master.
This function returns the LTC version nibble and allows
the user to perform expanded Smart Battery System
Manager functions.
Input/Output: word — Refer to “Section ꢀ.ꢀ” for bit map-
ping.
Purpose:
CONDITION_FLAG Bit
Used by the SMBus Host to determine the version of
the LTC1760 and to program and monitor TURBO and
POWER_OFF special functions.
The CONDITION_FLAG bit is set whenever the battery
requires calibration.
Allowed values:
SMBus Protocol: Read or Write Word.
1b: Battery requires calibration. (Also known as a
Condition Cycle Request).
Input/Output: word — Refer to “Section ꢀ.ꢀ” for bit map-
ping.
0b: Battery does not require calibration.
POWER_OFF Bit
2.3.6 Voltage() (0×09)
This read/write bit allows the LTC1760 to turn off all
power paths.
Description:
Allowed values:
This function is used by the LTC1760 to read the actual
cell-pack voltage .
1b: All power paths are off.
0b: Allpowerpathsareenabled.(poweronresetvalue).
TURBO Bit
Purpose:
Allows the LTC1760 to determine the cell pack voltage
and close the charging voltage servo loop.
This read/write bit allows the LTC1760 to enter TURBO
charging mode. Refer to “section 3.6”.
SMBus Protocol: Read Word. LTC1760 reads Battery 1
or Battery ꢀ as an SMBus Master.
Allowed values:
Output: unsigned integer — battery terminal voltage in
milli-volts. Refer to “Section ꢀ.ꢀ” for bit mapping.
1b: Turbo charging mode enabled.
0b: Turbo charging mode disabled. (Power On Reset
Value).
Units: m V.
Range: 0 to 65,535 mV.
LTC_Version[3:0] Nibble
Thisreadonlynibblealwaysreturns0001bastheLTC1760
version.
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LTC1760
OPERATION
2.3.7 Current() (0×0A)
Description:
Purpose:
Allows the LTC1760 to determine the maximum charging
voltage.
This function is used by the LTC1760 to read the actual
current being supplied through the battery terminals.
SMBus Protocol: Read Word. LTC1760 reads Battery 1
or Battery ꢀ as an SMBus Master.
Purpose:
Output: unsigned integer — charger output voltage in mV.
Refer to “Section ꢀ.ꢀ” for bit mapping.
Allows the LTC1760 to determine how much current a
battery is receiving through its terminals and close the
charging current servo loop.
Units: m V.
SMBus Protocol: Read Word. LTC1760 reads Battery 1
Range: 0 to 65,534 mV.
or Battery ꢀ as an SMBus Master.
2.3.10 AlarmWarning() (0×16)
Output: signed integer (ꢀ’s complement) — charge/dis-
charge rate in mA increments - positive for charge, nega-
tive for discharge. Refer to “Section ꢀ.ꢀ” for bit mapping.
Description:
This function is used by the LTC1760 to read the Smart
Battery’s Alarm register.
Units: mA.
Purpose:
Range: 0 to 3ꢀ,767 mA for charge or 0 to -3ꢀ,768 mA
for discharge.
AllowstheLTC1760todeterminethestateofallapplicable
alarm flags.
2.3.8 ChargingCurrent() (0×14)
SMBus Protocol: Read Word. LTC1760 reads Battery 1
or Battery ꢀ as an SMBus Master.
Description:
This function is used by the LTC1760 to read the Smart
Battery’s desired charging current.
Output: unsigned integer – Refer to “Section ꢀ.ꢀ” for bit
mapping.
Purpose:
OVER_CHARGED_ALARM Bit
Allows the LTC1760 to determine the maximum charging
current.
The read only OVER_CHARGED_ALARM bit is used by the
LTC1760 to determine if charging may continue.
SMBus Protocol: Read Word. LTC1760 reads Battery 1
or Battery ꢀ as an SMBus Master.
Allowed values are:
1b: The LTC1760 will not charge this battery.
Output: unsigned integer — maximum charger output
current in mA. Refer to “Section ꢀ.ꢀ” for bit mapping.
0b: The LTC1760 may charge this battery if other
conditions permit charging.
Units: mA.
TERMINATE_CHARGE_ALARM Bit
Range: 0 to 65,534 mA.
The read only TERMINATE_CHARGE_ALARM bit is used
by the LTC1760 to determine if charging may continue.
2.3.9 ChargingVoltage() (0×15)
Description:
Allowed values are:
This function is used by the LTC1760 to read the Smart
Battery’s desired charging voltage.
1b: The LTC1760 will not charge this battery.
0b: The LTC1760 may charge this battery if other
conditions permit charging.
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LTC1760
OPERATION
TERMINATE_CHARGE_RESERVED Bit
2.3.11 AlertResponse()
Description:
The read only TERMINATE_CHARGE_RESERVED bit is
usedbytheLTC1760todetermineifchargingmaycontinue.
TheSMBusHostusestheAlertResponseAddress(ARA)to
simultaneously address all devices on the SMBus and de-
terminewhichdevicesarecurrentlyassertingSMBALERT.
Allowed values are:
1b: The LTC1760 will not charge this battery.
Purpose:
0b: The LTC1760 may charge this battery if other
conditions permit charging.
This command allows the SMBus Host to identify the
subset of devices that have new status data. This reduces
the number of reads required to refresh all status infor-
mation from the system. The SMBus Host begins an ARA
by transmitting the 8-bit address, 0×18, to all devices.
ARA-compliant devices that are asserting SMBALERT
will then simultaneously return their address on the next
read byte. While transmitting their address each device
monitors SDA. If a lower address is present, the device
transmitting the higher address will see that SDA does not
match and it will stop transmitting its address. When a
device sees its full address has been received it will stop
assertingSMBALERTandtheHostwillknowtoreadstatus
from this device. Subsequent ARA requests will allow the
Host to complete the list of devices requiring servicing.
OVER_TEMP_ALARM Bit
The read only OVER_TEMP_ALARM bit is used by the
LTC1760 to determine if charging may continue.
Allowed values are:
1b: The LTC1760 will not charge this battery.
0b: The LTC1760 may charge this battery if other
conditions permit charging.
TERMINATE_DISCHARGE_ALARM Bit
The read only TERMINATE_DISCHARGE_ALARM bit is
used by the LTC1760 to determine if discharge from the
battery is still allowed. This is used for PowerPath man-
agement and battery calibration.
Output:
Allowed values are:
The LTC1760 will transmit its 8-bit address, 0x14, in
response to an ARA request. The LTC1760 will stop trans-
mitting its address if another device with a lower address
is also responding to the ARA. The LTC1760 will de-assert
SMBALERT when it successfully returns its address.
1b: The LTC1760 will terminate calibration and should
try to not use this battery in the power path. When
all other power paths fail the LTC1760 will ignore
this alarm and still try to supply system power
from this battery.
The following events will cause the LTC1760 to pull-down
the SMBALERT# bus through the SMBALERT pin:
0b: TheLTC1760maycontinuedischargingthisbattery.
• Change of AC_PRESENT in the BatterySystemSta-
teCont() function.
FULLY_DISCHARGED Bit
The read only FULLY_DISCHARGED bit is used by the
LTC1760 to determine if discharge from the battery is
still allowed. This is used for PowerPath management
and battery calibration.
• Change of BATTERY_PRESENT in the BatterySys-
temState() function.
• Internal power on reset condition.
Refer to “Section ꢀ.ꢀ” for bit mapping.
Allowed values are:
1b: The LTC1760 will terminate calibration and should
try to not use this battery in the power path. When
all other power paths fail the LTC1760 will ignore
this alarm and still try to supply system power
from this battery.
2.4 SMBus Dual Port Operation
The SMBus Interface includes the LTC1760’s SMBus
controller, as well as circuitry to arbitrate and connect the
battery and SMBus Host interfaces. The SMBus controller
generates and interprets all LTC1760 SMBus functions.
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0b: TheLTC1760maycontinuedischargingthisbattery.
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LTC1760
OPERATION
SMB2*
SMB1*
SMB2*
BAT2
BAT2
BAT1
SMB*
HOST
SMB*
HOST
SMB1*
BAT1
LTC1760
SMBus
CONTROLLER
LTC1760
SMBus
CONTROLLER
HOST, LTC1760 AND BAT1 CAN COMMUNICATE.
BAT2 ORIGINATED COMMANDS ARE IGNORED.
LTC1760 AND BAT2 CAN COMMUNICATE. HOST AND
BAT1 ORIGINATED COMMANDS ARE STRETCHED IF
THE LTC1760 IS COMMUNICATING WITH BAT2.
(1a)
(1b)
SMB2*
SMB2*
BAT2
BAT1
BAT2
BAT1
SMB*
SMB*
HOST
HOST
SMB1*
SMB1*
LTC1760
SMBus
CONTROLLER
LTC1760
SMBus
CONTROLLER
LTC1760 AND BAT1 CAN COMMUNICATE. HOST AND
BAT2 ORIGINATED COMMANDS ARE STRETCHED IF
THE LTC1760 IS COMMUNICATING WITH BAT1.
HOST, LTC1760 AND BAT2 CAN COMMUNICATE.
BAT1 ORIGINATED COMMANDS ARE IGNORED.
1760 F01
(1c)
(1d)
*SMB INCLUDES SCL AND SDA, SMB1 INCLUDES SCL1 AND SDA1, AND SMB2 INCLUDES SCL2 AND SDA2.
Figure 1. Switch Configurations Used by the LTC1760 for Managing Dual Port Battery Communication
The dual port operation allows the SMBus Host to be
connected to the SMBus of either battery by setting the
SMB_BAT[4:1]nibble.Arbitrationishandledbystretching
anSMBusstartsequencewhenabuscollisionmightoccur.
Whenever configurations are switched, the LTC1760 will
generate a harmless SMBus reset on SMB1 and SMBꢀ as
required. The four possible configurations are illustrated
in Figure 1. Sample SMBus communications are shown
in Figures ꢀ and 3.
an invalid command code is transmitted to the LTC1760.
The SMBus Controller must respond if addressed as a
combinedSmartBatterySystemManagerat8-bitaddress
0×14. A valid address includes a legal Read/Write bit. The
SMBus Controller will ignore invalid data although the
data transmission with the invalid data will still be ACKed.
When the LTC1760, acting as a bus Master receives a
NACK, it will terminate the transmission and provide a
STOP condition on the bus.
2.5 LTC1760 SMBus Controller Operation
Detection of a STOP condition, power on reset, or SMBus
time out will reset the Controller to an initial state at any
time.
SMBuscommunicationwiththeLTC1760ishandledbythe
SMBusController,asub-blockoftheSMBusInterface.Data
is clocked into the SMBus Controller block shift register
aftertherisingSCLedge. DataisclockedoutoftheSMBus
Control block shift register after the falling edge of SCL.
The LTC1760 supports ARA, Write Word and Read Word
protocols as an SMBus Slave. The LTC1760 supports
Read Word protocol as an SMBus Master.
TheLTC1760actingasaSlavewillacknowledge(ACK)each
byte of serial data. The Command byte will be NACKed if
Refer to “System Management Bus Specification” for a
complete description of required operation and symbols.
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OPERATION
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LTC1760
OPERATION
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OPERATION
2.6 LTC1760 SMBALERT Operation
The LTC1760 will attempt to reinitiate wake-up charging
on a battery if the battery is not being charged, the therm-
istor is reporting IDEAL-RANGE, and the battery fails to
respond to an SMBus query. This is an important feature
for handling deeply discharged NiMH batteries. These
batteries may begin to talk while being charged and go
silent once charging has stopped.
The SMBALERT pin allows the LTC1760 to signal to the
SMBus Host that there has been a change of status.
This pin is asserted low whenever there is a change in
battery presence, AC presence or after a power on reset
event. This pin is cleared during an Alert Response or
any of the following reads:
Wake-up charging is disabled if the battery thermistor is
COLD-RANGEorUNDER-RANGEandthebatteryhasbeen
BatterySystemState(),BatterySystemStateCont(), Bat-
terySystemInfo(), or LTC().
charged for longer than t
.
TIMEOUT
3 Charging Algorithm Overview
3.1 Wake-Up Charging Initiation
3.2 Wake-Up Charging Termination
The LTC1760 will terminate wake-up charging when any
of the following conditions are met:
The following conditions must be met in order to allow
wake-up charging:
1. Battery removal (thermistor indicating OVER-RANGE)
ꢀ. AC is removed.
1. The battery thermistor must be COLD-RANGE, IDEAL-
RANGE, or UNDER-RANGE.
3. The SMBus Host issues a calibration request by setting
BatterySystemStateCont(CALIBRATE) high.
ꢀ. AC must be present.
3. BatterySystemStateCont(CHARGING_INHIBIT) must
be de-asserted (or low).
4. Any response to an LTC1760 Master read of Charging-
Current(), Current(), ChargingVoltage(), or Voltage().
Note that the LTC1760 ignores all writes from the bat-
tery.
4. Hardware controlled charging inhibit must be
de-asserted (MODE not low with V
“Section 6.ꢀ”.
high). Refer to
DDS
5. AnyofthefollowingAlarmWarning()bitsassertedhigh:
Wake-up charging initiates when a newly inserted battery
doesnotrespondtoanyLTC1760Masterreadcommands.
Only one battery will wake-up charge at a time. When two
batteries are inserted and both require wake-up charging,
Battery1willwake-upchargefirst.Batteryꢀwillonlywake-
up charge when Battery 1 terminates wake-up charging.
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM
TERMINATE_CHARGE_RESERVED
OVER_TEMP_ALARM
Note that the LTC1760 ignores all writes from the battery.
Eachbattery’schargealarmiscachedinsidetheLTC1760.
This internally cached bit will be set when any of the up-
per four bits of the battery’s AlarmWarning() response
are set. The cached bit will remain set if a subsequent
AlarmWarning() fails to respond. The cached alarm will
be cleared by any of the following conditions.
Wake-up charging takes priority over controlled charg-
ing; this prevents one battery from tying up the charger
when it would be advantageous to dual charge two deeply
discharged batteries.
The LTC1760 will attempt to reinitiate wake-up
charging on both batteries after the SMBus Host asserts
BatterySystemStateCont(CHARGER_POR) or a power on
reset event. This will reset any wake-up charging safety
timers and is equivalent to removing and reinserting both
batteries.
a) Associated battery is removed.
b) A subsequent AlarmWarning() clears all charge
alarm bits for the associated battery.
c) A power on reset event.
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OPERATION
d) The SMBus Host asserts
4. Hardware controlled charging inhibit must be
BatterySystemStateCont(CHARGER_POR) high.
de-asserted (MODE not low with V
“Section 6.ꢀ”.
high). Refer to
DDS
6. The SMBus Host asserts
BatterySystemStateCont(CHARGING_INHIBIT) high.
5. The battery responds to an LTC1760 Master read of
Alarm() with all charge alarms deasserted.
7. Hardwarecontrolledcharginginhibitisasserted(MODE
low with V
high). Refer to “Section 6.ꢀ”.
6. The battery responds to an LTC1760 Master read of
ChargingVoltage()withanonzerovoltagerequestvalue.
DDS
8. The thermistor of the battery being charged indicates
COLD-RANGE and the battery has been charged for
7. The battery responds to an LTC1760 Master read of
Voltage().
longer than t
.
TIMEOUT
9. The thermistor of the battery being charged indicates
UNDER-RANGE and the battery has been charged for
8. The battery responds to an LTC1760 Master read of
ChargingCurrent()withanonzerocurrentrequestvalue.
longer than t
.
TIMEOUT
9. The battery responds to an LTC1760 Master read of
Current().
10. The thermistor of the battery being charged indicates
HOT-RANGE.
The following charging related functions are polled each
11. Any SMBus communication line is held low for longer
t
: Alarm(), ChargingVoltage(), Voltage(), Charging-
QUERY
than t
Current(), and Current().
QUERY.
1ꢀ. BatterySystemStateCont(POWER_NOT_GOOD) is
high.
3.5 Controlled Charging Termination
The LTC1760 will terminate controlled charging when any
of the following conditions are met:
13. The emergency turn-off feature has been asserted
using the DCDIV input pin.
1. Batteryremoval,orthermistorindicatingOVER-RANGE.
ꢀ. AC removal.
3.3 Wake-Up Charging Current and Voltage Limits
The wake-up charging current is fixed at I
for all
WAKE_UP
3. The SMBus Host issues a calibration request by setting
BatterySystemStateCont(CALIBRATE) high.
values of I
. Wake-up charging uses the low current
LIMIT
mode described in “Section 10”.
4. AnLTC1760MasterreadofChargingCurrent()returning
a zero current request.
The wake-up charging voltage is not limited by the V
function.
LIMIT
5. AnLTC1760MasterreadofChargingVoltage()returning
a zero voltage request.
3.4 Controlled Charging Initiation
All of the following conditions must be met in order to
allow controlled charging of a given battery. One or both
batteries may be controlled charged at a time.
6. AnyofthefollowingAlarmWarning()bitsassertedhigh:
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM
TERMINATE_CHARGE_RESERVED
OVER_TEMP_ALARM
1. The battery thermistor must be COLD-RANGE, IDEAL-
RANGE, or UNDER-RANGE.
ꢀ. AC must be present.
Note that the LTC1760 ignores all writes from the battery.
Eachbattery’schargealarmiscachedinsidetheLTC1760.
This internally cached bit will be set when any of the upper
fourbitsofthebattery’sAlarmWarning()responseareset.
3. BatterySystemStateCont(CHARGING_INHIBIT) must
be de-asserted (or low).
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OPERATION
ThiscachedbitwillremainsetifasubsequentAlarmWarn-
ing() fails to respond. The cached alarm will be cleared by
any of the following conditions.
When charging a single battery, the charging algorithm
attempts to adjust the current so as to match the reported
current with the requested current. The LTC1760 con-
tinuously adjusts the charging current by the difference
between the actual and requested currents.
a) Associated battery is removed.
b) AsubsequentAlarmWarning()clearsallchargealarm
bits for the associated battery.
Whensimultaneouslychargingtwobatteries,thecharging
algorithm attempts to adjust the current so as to match
the reported current with the requested current in both
batteries. The LTC1760 calculates the difference between
the requested and actual current in both batteries and
uses the minimum of these differences to increment or
decrement the total charge current being provided by the
charging stage.
c) A power on reset event.
d) The SMBus Host asserts
BatterySystemStateCont(CHARGER_POR) high.
7. The SMBus Host asserts
BatterySystemStateCont(CHARGING_INHIBIT) high.
The charging algorithm will not allow the reported actual
current to exceed the requested current in either battery.
For this reason the most efficient charging occurs for
matched batteries at similar charge states.
8. Hardwarecontrolledcharginginhibitisasserted(MODE
low with V
high).
DDS
9. The SMBus of the battery being charged has stopped
acknowledgingSMBusreadcommandsforlongerthan
Whenever changing conditions cause either battery to
stop charging, the current algorithm is reset to zero. The
t
TIMEOUT.
10. The thermistor of the battery being charged indicates
HOT-RANGE.
programmed current is updated every t
.
QUERY
There are additional safety restrictions that limit the total
output current of the charger. These are detailed in the
following three sub-sections.
11. AnySMBuscommunicationlineisgroundedforlonger
than t
.
QUERY
1ꢀ. BatterySystemStateCont(POWER_NOT_GOOD) is
high.
3.6.1 Current Limits When Charging A Single
Battery
13. The emergency turn-off feature has been asserted
using the DCDIV input pin.
The following additional limits are applied to the charg-
ing current algorithm described in 3.6 when charging a
single battery:
Whenever changing conditions cause either battery to
stop charging, charging is stopped immediately for all
batteries and the voltage and current algorithms are reset
to zero. Charging is not resumed until all the conditions
for controlled charging are met.
a) The programmed current cannot exceed the re-
quested current + I
/3ꢀ.
LIMIT
b) The programmed current cannot exceed I
.
LIMIT
3.6.2 Current Limits When Charging Two Batteries
(TURBO Mode Disabled)
3.6 Controlled Charging Current Programming
TheLTC1760usesasinglechargerstagetosimultaneously
charge up to two batteries. The batteries are connected to
the charger using a charge MUX. The charge MUX allows
the total charger current to be shared by the two batteries
while preventing charge transfer between the batteries.
Refer to “Section 7.1” and “Section 7.ꢀ”.
The following additional limits are applied to the charging
current algorithm described in 3.6 when charging two
batteries with turbo mode disabled:
a) The programmed current cannot exceed the maxi-
mum of the two requested currents + I
.
LIMIT/3ꢀ
b) The programmed current cannot exceed I
.
LIMIT
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OPERATION
3.6.3 Current Limits When Charging Two Batteries
(TURBO Mode Enabled)
by 16mV each t
tions are met:
unless one of the following condi-
QUERY
a) The actual voltage exceeds the requested voltage in
either battery.
The following additional limits are applied to the charging
current algorithm described in 3.6 when charging two
batteries with turbo mode enabled:
b) The actual voltage exceeds V
.
LIMIT
a) The programmed current cannot exceed the maxi-
ThisisanextremelyimportantfeatureoftheLTC1760since
it allows the charger to servo on the internal cell voltage
of the battery as determined by the Smart Battery. This
voltage may be significantly lower than the battery pack
terminal voltage which is used by all Level ꢀ chargers.
The advantage for the LTC1760 is improved charge time,
safety, and a more completely charged battery.
mum of the two requested currents + I
. This
LIMIT
LIMIT
relaxed limit enables accelerated charging if I
is greater than the maximum of the two requested
currents. For the recommended matched battery
pair the requested current should be the same.
b) The programmed current cannot exceed I
LIMIT
TURBO mode provides a mechanism for the SMBus Host
to enable the charge MUX to apply additional current to
both batteries. TURBO mode only has an effect when two
batteries are being charged simultaneously. TURBO mode
does not affect wake-up charging or any other conditions
that could inhibit charging. TURBO mode is entered when
LTC(TURBO) is set high.
The voltage correction cannot exceed the minimum re-
questedvoltagebymorethan51ꢀmV.Whendecrementing,
the programmed voltage is reduced by 16mV each t
.
QUERY
Wheneverchangingconditionscauseeitherbatterytostop
charging, the voltage algorithm is reset to zero.
4 System Power Management Algorithm and Battery
Calibration
Normally the LTC1760 will limit the current into both bat-
teries to the maximum of the two requested currents +
4.1 Turning Off System Power
I
/3ꢀ. TURBO mode removes this restriction, allowing
LIMIT
TheLTC1760allowstheusertoturnoffsystempowerusing
the LTC(POWER_OFF) bit. When POWER_OFF is asserted
high all power management functions are bypassed and
the LTC1760 will turn off DCIN, BATꢀ and BAT1 power
paths. This feature allows the user to power down the
system. Charging is still allowed when POWER_OFF is
asserted high.
the charger to output as much as I
battery system.
into the combined
LIMIT
Forexample:InasystemwhereLTC(TURBO)=0,I
=4.0A
LIMIT
and each battery is requesting ꢀA the LTC1760 will not
outputmorethan ꢀ.1ꢀ5Aintothecombinedbatterysystem
or 1.06A into each battery if their charge states match.
In a system where LTC(TURBO)=1, I
= 4.0A and each
LIMIT
battery is requesting ꢀA the LTC1760 will now output up
4.2 Power-By Algorithm When No Battery is Being
Calibrated
to I
into the combined battery system or ꢀA into each
LIMIT
battery if their charge states match.
TheLTC1760willalwaysattempttomaintainsystempower.
The preferred configuration is to remain in 3- Diode mode.
In 3-Diode mode, power will be provided by BAT1, BATꢀ
and DCIN with the source at the highest voltage potential
automatically providing all the power. Sources at similar
voltagepotentialswillsharepowerbasedontheircapacity.
Even without TURBO mode, the LTC1760 offers signifi-
cantly reduced charge times for matched batteries in the
top-off state. This time savings is especially significant for
Lithium-Ion batteries. Simultaneously charging two bat-
teries reduces losses in switches and improves efficiency.
3.7 Controlled Charging Voltage Programming
ThefollowingconditionswillcausetheLTC1760tomodify
its preferred power-by algorithm.
The LTC1760 monitors the requested and actual voltages
in each battery and increments the programmed voltage
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OPERATION
1. A battery issues a TERMINATE_DISCHARGE alarm and
AC_PRESENTishigh.TheLTC1760willselecttheother
battery and DCIN to power the system.
Power Reporting with AC_PRESENT Low and both Batteries
Present, as a Function of Power Alarms.
BATTERY 2
BATTERY 1
POWER ALARM POWER ALARM POWERED_BY_
AC_PRESENT
(NOTE 1)
(NOTE 1)
BAT(4:1)
ꢀ. A battery issues a TERMINATE_DISCHARGE alarm and
AC_PRESENT is low. The LTC1760 will select the other
battery to power the system.
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
0011b
0010b
0001b
0011b
0000b
3. A battery issues a TERMINATE_DISCHARGE alarm,
AC_PRESENTislow,andtheotherbatteryisnotpresent
or has previously issued an alarm. The LTC1760 will
autonomously try to restore power by entering 3-Diode
mode. The 3-Diode mode will ignore TERMINATE_
DISCHARGE and FULLY_DISCHARGED alarms.
Note 1: A power alarm means that ALARM() has returned
TERMINATE_DISCHARGE=1 or FULLY_DISCHARGED_ALARM=1
Power Reporting When
BatterySystemStateCont(POWER_NOT_GOOD) is High
and the LTC1760 has Autonomously Entered 3-Diode Mode
4.3 Power-By Algorithm When a Battery is Being
Calibrated
POWERED_BY_
AC_PRESENT PRESENT_BAT2 PRESENT_BAT1 BAT(4:1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0000b
0001b
0010b
0011b
0000b
0000b
0000b
0000b
During battery calibration, the battery being calibrated is
the only device powering the system. This will be reflected
in the reported POWER_BY[4:1] bits. See “Section 5” for
more information on battery calibration.
4.4 Power-By Reporting
The following tables illustrate how BatterySystem
State(POWER_BY_BAT[4:1]) interprets PowerPath
conditions.
5 Battery Calibration (Conditioning)
Calibration allows the SMBus Host to fully discharge
a battery for conditioning purposes. The SMBus Host
may determine the battery to be discharged or allow the
LTC1760 to choose based on the batteries’ request to
be conditioned.
Power Reporting for Batteries Being Calibrated
POWERED_BY_
AC_PRESENT CALIBRATE_BAT2 CALIBRATE_BAT1 BAT(4:1)
1
1
1
0
1
1
0
1
0
0000b
0001b
0010b
5.1 Selecting a Battery to be Calibrated
*States not shown are not allowed
Option 1) SMBus Host chooses battery to be calibrated
using BatterySystemStateCont(CALIBRATE_BAT[4:1])
Power Reporting as a Function of Battery Presence
POWERED_BY_
AC_PRESENT PRESENT_BAT2 PRESENT_BAT1 BAT(4:1)
Allowed values:
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
0000b
0000b
0001b
0010b
0011b
0001b: Set CALIBRATE_BAT1. Only has an effect if
Battery1BatteryMode(CONDITION_FLAG)ishigh.May
not be updated if a calibration is in progress.
0010b: Set CALIBRATE_BATꢀ. Only has an effect if
BatteryꢀBatteryMode(CONDITION_FLAG)ishigh.May
not be updated if a calibration is in progress.
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0000b:ClearsCALIBRATE_BAT1andCALIBRATE_BATꢀ
and allows LTC1760 to chose. Power on reset default.
May not be updated if a calibration is in progress.
• The battery sets Alarm Warning(TERMINATE_
DISCHARGE) high.
• ThebatterysetsAlarmWarning(FULLY_DISCHARGED)
high.
Option ꢀ) SMBus Host allows LTC1760 to choose battery
to be calibrated.
• A zero is written to the CALIBRATE bit.
BatterySystemStateCont(CALIBRATE_BAT[4:1]) =0000b.
See previous option.
The LTC1760 will attempt to initiate a charge cycle after
the discharge cycle is completed.
The LTC1760 determines that the battery requires
calibration by reading BatteryMode(CONDITION_FLAG).
This flag is cached in the LTC1760. The LTC1760 sets
BatterySystemStateCont(CALIBRATE_REQUEST) high.
TheLTC1760willalwaysselectthebatterythatisrequesting
calibration. If both batteries are requesting calibration, the
LTC1760 will select Battery 1. If neither battery is request-
ing calibration, then calibration cannot occur.
6 MODE Pin Operation
TheMODEpinisamultifunctionpinthatallowstheLTC1760
to: 1) display charging status in stand alone operation; ꢀ)
activate hardware charge inhibit; 3) charge when SCL and
SDA are low and; 4) charge with an SMBus Host.
Summary of SDA, SCL and SMBALERT Operation as a Function
of MODE and VDDS Levels
CONDITION
LTC1760 OPERATING MODE
5.2 Initiating Calibration of Selected Battery
V
MODE
V
VDDS
= GND
SCL: Clock for Status Indicators
SCL: Clock for Status Indicators
SDA: Battery ꢀ Status
The SMBus Host initiates a calibration by writing to
BatterySystemStateCont(CALIBRATE). Followrulesofthe
previous section to preserve battery intended for calibra-
tion. The SMBus Host must only set the calibration bit
once per calibration.
< V
IL_VDDS
SMBALERT: Battery 1 Status
V
MODE
V
VDDS
= GND
SCL, SDA, SMBALERT: Normal Operation
LTC1760 Charging Inhibited
> V
IH_VDDS
V
MODE
V
VDDS
= V
< V
SCL, SDA Ignored and May Float Low
SMBALERT: Normal Operation
SCL1, SDA1, SCLꢀ and SDAꢀ: Normal Operation and
Charging is Allowed
VCCꢀ
TheLTC1760willdischargetheselectedbatteryaslongas
the calibration is in progress (CALIBRATE high). Updates
to the cached BatteryMode(CONDITION_FLAG) will be
inhibited while CALIBRATE is asserted. This means that
discharge of the battery will continue even if the battery
clears the CONDITION_FLAG.
IL_VDDS
V
MODE
V
VDDS
= V
Normal Operation on all Pins, Charging is Allowed
VCCꢀ
> V
IH_VDDS
6.1 Standalone Charge Indication
When MODE is tied to GND and V
5.3 Terminating Calibration of Selected Battery
< V
, the
IL_VDDS
VDDS
Calibration will end when CALIBRATE is cleared. CALI-
BRATE will be cleared when:
function of SDA, SMBALERT, and SCL are changed as
described below:
• AC is removed.
SDA is an output and is used to monitor charging status
of Battery ꢀ. Allowed values are:
• The battery being calibrated is removed. When the
battery being calibrated is removed, the LTC1760 will
automatically calibrate the other battery if it is request-
ing calibration.
Low: Battery ꢀ is charging.
High: Battery ꢀ not charging (AC is not present or bat-
tery is not present).
• BatterySystemStateCont(POWER_NOT_GOOD)ishigh.
Blinking: Battery ꢀ charge complete (AC is present,
battery is present and not charging).
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SMBALERTisusedtomonitorchargingstatusofBattery1.
Allowed values are:
to set the bottom MOSFET on time. The result is quasi-
constant frequency operation where the converter fre-
quency remains nearly constant over a wide range of
output voltages. This activity is diagrammed in Figure 4.
Low: Battery 1 is charging.
High: Battery 1 not charging (AC is not present or bat-
tery is not present).
OFF
TGATE
ON
Blinking: Battery 1 charge complete (AC is present,
battery is present and not charging).
t
OFF
ON
BGATE
SCL is an input and is used to determine the blinking rate
of SDA and SMBALERT. Tie SCL high if blinking is not
desired. This will provide two different states to indicate
charging (output low) and not charging (output high).
OFF
TRIP POINT SET BY I VOLTAGE
TH
INDUCTOR
CURRENT
1760 F04
6.2 Hardware Charge Inhibit
Figure 4.
WhenMODEistiedtoGNDandV
>V
,charging
VDDS IH_VDDS
The peak inductor current, at which I
resets the SR
TH TH
CMP
isinhibitedandBatterySystemStateCont(CHARGING_INHIBIT)
will report a logic high.
latch, is controlled by the voltage on I . I is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CAꢀ compares this current against the desired
6.3 Charging When SCL And SDA Are Low
When MODE is tied to V
and V
< V
, SDA
IL_VDDS
CCꢀ
VDDS
and SCL are not used and will not interfere with LTC1760
batterycommunication.ThisfeatureallowstheLTC1760to
autonomouslychargewhenSCLandSDAarenotavailable.
ThisscenariomightoccurwhenSMBusHosthaspowered
down and is no longer pulling up on SCL and SDA.
currentprogrammedbytheI
TH
attheI pinandadjusts
DAC
SET
I
for the desired voltage across R
.
SENSE
The voltage at BAT is divided down by an internal resis-
tor divider set by the V
and is used by error amp EA
DAC
to decrease I if the divider voltage is above the 0.8V
TH
reference.
6.4 Charging With an SMBus Host
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100 mV/
When Mode is tied to V
and V
> V
, SDA
CCꢀ
VDDS
IH_VDDS
and SCL are used to communicate with the SMBus Host.
R ). At input current limit, CL1 will decrease the I volt-
CL
TH
7 Battery Charger Controller
age and thus reduce battery charging current.
The LTC1760 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
An over-voltage comparator, OV, guards against transient
overshoots(>7.52).Inthiscase,thetopMOSFETisturned
off until the over-voltage condition is cleared. This feature
is useful for batteries which “load dump” themselves by
opening their protection switch to perform functions such
as calibration or pulse-mode charging.
main current comparator I
resets the SR latch. While
CMP
the top MOSFET is off, the bottom MOSFET is turned on
until either the inductor current trips the current compara-
The top MOSFET driver is powered from a floating boot-
strap capacitor C4. This capacitor is normally recharged
tor I , or the beginning of the next cycle. The oscillator
REV
uses the equation:
from V through an external diode when the top MOS-
CC
t
= (V
- V )/(V
• f
)
FET is turned off. As V decreases towards the selected
OFF
DCIN
BAT
DCIN OSC
IN
1760fc
32
For more information www.linear.com/LTC1760
LTC1760
OPERATION
battery voltage, the converter will attempt to turn on the
top MOSFET continuously (“dropout’’). A dropout timer
detects this condition and forces the top MOSFET to turn
off, and the bottom MOSFET on, for about ꢀ00ns at 40µs
intervals to recharge the bootstrap capacitor.
7.2 Dual Charging
Note that the charge MUX switch drivers will operate
together to allow both batteries to be charged simultane-
ously. If both charge MUX switch drivers are enabled,
only the battery with the lowest voltage will be charged
until its voltage rises to equal the higher voltage battery.
The charge current will then share between the batteries
according to the capacity of each battery.
7.1 Charge MUX Switches
The equivalent circuit of a charge MUX switch driver is
shown in Figure 5. If the charger controller is not enabled,
the charge MUX drivers will drive the gate and source of
the series-connected MOSFETs to a low voltage and the
switchisoff. Whenthe chargercontrolleris on, the charge
MUX driver will keep the MOSFETs off until the voltage at
CSN rises at least 35mV above the battery voltage. GCH1
is then driven with an error amplifier EAC until the volt-
age between BAT1 and CSN satisfies the error amplifier
or until GCH1 is clamped by the internal Zener diode.
The time required to close the switch could be quite long
(many ms) due to the small currents output by the error
amp and depending upon the size of the MOSFET switch.
Whenbatteriesarecontrolledcharging,onlybatterieswith
voltages above V
are allowed to charge. When a bat-
CHMIN
tery is wake-up charging this restriction does not apply.
8 PowerPath Controller
ThePowerPathswitchesareturnedonandoffbythepower
management algorithm. The external PFETs are usually
connected as an input switch and an output switch. The
output switch PFET is connected in series with the input
PFETandthepositivesideoftheshort-circuitsensingresis-
tor, R . The input switch is connected in series between
SC
the power source and the output PFET. The PowerPath
switch driver equivalent circuit is shown in Figure 6. The
output PFET is driven ON or OFF by the output side driver
controlling pin GB10. The gate of the input PFET is driven
by an error amplifier which monitors the voltage between
the input power source (BAT1 in this case) and SCP. If
the switch is turned off, the two outputs are driven to the
higher of the two voltages present across the input/SCP
terminals of the switch. When the switch is instructed to
turn on, the output side driver immediately drives the gate
of the output PFET approximately 6V below the highest
of the voltages present at the input/SCP. When the output
PFET turns on, the voltage at SCP will be pulled up to a
diode drop below the source voltage by the bulk diode of
the input PFET. If the source voltage is more than ꢀ5mV
above SCP, EAP will drive the gate of the input PFET low
until the input PFET turns on and reduces the voltage
across the input/SCP to the EAP set point, or until the
Zener clamp engages to limit the voltage applied to the
input PFET. If the source voltage drops more than ꢀ0mV
below SCP, then comparator CP turns on SWP to quickly
prevent large reverse current in the switch. This operation
mimics a diode with a low forward voltage drop.
If the voltage at CSN decreases below V
– ꢀ0mV a
BAT1
comparator CC quickly turns off the MOSFETs to prevent
reverse current from flowing in the switches. In essence,
this system performs as a low forward voltage diode.
Operation is identical for BATꢀ.
DCIN + 10V
(CHARGE PUMPED)
BAT1
CSN
TO
BATTERY
1
–
+
GCH1
SCH1
Q3
EAC
35mV
20mV
FROM
CHARGER
+
–
CC
10k
Q4
OFF
1760 F05
Figure 5. Charge MUX Switch Driver Equivalent Circuit
1760fc
33
For more information www.linear.com/LTC1760
LTC1760
OPERATION
SCN exceeds the short-circuit comparator threshold
for more than 15ms, then all of the PowerPath
20mV
OFF
–
V
TSC
CP
switches are turned off and BatterySystemState-Cont
(POWER_NOT_GOOD) is set. Similarly, if the voltage
at SCN falls below 3V for more than 15ms, then all of
the PowerPath switches are turned off and POWER_
NOT_GOOD is set high. The POWER_NOT_GOOD bit is
reset by removing all power sources and allowing the
+
FROM
BATTERY
1
BAT1
SWP
–
GB1I
Q7
Q8
EAP
SCP
+
25mV
GB1O
voltage at V
to fall below the UVLO threshold. If
PLUS
the POWER_NOT_GOOD bit is set, charging is disabled
OFF
until V
exceeds the UVLO threshold and the Charger
PLUS
Algorithm allows charging to resume.
R
SC
C
L
TO LOAD
1760 F06
When a hard short-circuit occurs, it might pull all of the
power sources down to near 0V potentials. The capacitors
Figure 6. PowerPath Driver Equivalent Circuit
on V and V
must be large enough to keep the circuit
CC
PLUS
operating correctly during the 15ms short-circuit event.
The charger will stop within a few microseconds, leaving
a small current which must be provided by the capacitor
8.1 Autonomous PowerPath Switching
The LOPWR comparator monitors the voltage at the
load through the resistor divider from pin SCN. If LTC
(POWER_OFF) is low and the LOPWR comparator trips,
then all of the switches are turned on (3-Diode mode)
by the Autonomous PowerPath Controller to ensure that
the system is powered from the source with the highest
voltage. The Autonomous PowerPath Controller waits
approximately 1 second, to allow power to stabilize, and
then reverts back to the PowerPath switch configuration
requested by the PowerPath Management Algorithm. A
power fail counter is incremented to indicate that a failure
has occurred. If the power fail counter equals a value of 3,
then the the Autonomous PowerPath Controller sets the
switches to 3-Diode mode and BatterySystem-
StateCont(POWER_NOT_GOOD) will be set, provided
the LOPWR comparator is still detecting a low power
event. This is a three-strikes-and-you’re-out process
which is intended to debounce the POWER_NOT_GOOD
indicator. The power fail counter is reset when battery or
AC presence change.
on V
. The recommended minimum values (1µF on
PLUS
V
and ꢀµF on V , including tolerances) should keep
PLUS
CC
the LTC1760 operating above the UVLO trip voltage long
enough to perform the short-circuit function when the
input voltages are greater than 8V. Increasing the capaci-
tor across V to 4.7µF will allow operation down to the
CC
recommended 6V minimum.
8.3 Emergency Turn-Off
All of the PowerPath switches can be forced off by set-
ting the DCDIV pin to a voltage between 8V and 10V. This
will have the same effect as a short-circuit event. DCDIV
must be less than 5V and V
must decrease below
PLUS
the UVLO threshold to re-enable the PowerPath switches.
The LTC1760 can recover from this condition without
removing power. Contact Applications Engineering for
more information.
8.4 Power-Up Strategy
All three PowerPath switches are turned on after V
PLUS
8.2 Short-Circuit Protection
exceeds the UVLO threshold for more than ꢀ50ms. This
delay is to prevent oscillation from a turn-on transient
near the UVLO threshold.
Short-circuit protection operates in both a current mode
and a voltage mode. If the voltage between SCP and
1760fc
34
For more information www.linear.com/LTC1760
LTC1760
OPERATION
9 The Voltage DAC Block
modulator and switch convert the I
value to a variable
DAC
resistance equal to 1.ꢀ5R /(I
/10ꢀ3). In regu-
SET DAC(VALUE)
The voltage DAC (V ) is a delta-sigma modulator
which controls the effective value of an internal resistor,
DAC
lation, I is servo driven to the 0.8V reference voltage,
SET
V
, and the current from R
is matched against a
REF
SET
R
= 7.ꢀk,usedtoprogramthemaximumchargervolt-
VSET
current derived from the voltage between pins CSP and
CSN. This current is (V – V )/3k.
age. Figure7isasimplifieddiagramoftheV
operation.
DAC
CSP
CSN
The delta-sigma modulator and switch SWV convert the
value to a variable resistance equal to (11/8)R
Therefore programmed current is:
V
/
VSET
DAC
(V
/ꢀ047). In regulation, V is servo driven to
DAC(VALUE)
SET
I
= V • 3k/(1.ꢀ5 RSNS R ) • (I
/10ꢀ3)
CHG
REF
SET
DAC(VALUE)
/10ꢀ3)
the 0.8V reference voltage, V
.
REF
= (10ꢀ.3mV/R ) • (I
SNS
DAC(VALUE)
Capacitors C and C are used to average the voltage
B1
Bꢀ
During wake-up current operation, the current DAC enters
a low current mode. The current DAC output is pulse-
width modulated with a high frequency clock having a
duty cycle value of 1/8. Therefore, the maximum output
present at the V
pin as well as provide a zero in the
SET
voltage loop to help stability and transient response time
to voltage variations.
currentprovidedbythechargerisI
/8. Thedelta-sigma
MAX
10The Current DAC Block
output gates this low duty cycle signal on and off. The
delta-sigma shift registers are then clocked at a slower
rate, about 40ms/bit, so that the charger has time to settle
ThecurrentDACisadelta-sigmamodulatorwhichcontrols
the effective value of an internal resistor, R
= 18.77k,
SET
to the I
/8 value.
usedtoprogramthemaximumchargercurrent.Figure8is
asimplifieddiagramoftheDACoperation.Thedelta-sigma
MAX
CSN
(V
CSP
– V
)
CSN
3kΩ
(FROM CA1 AMPLIFIER)
R
VF
C
B2
C
405.3k
I
SET
V
SET
+
–
–
+
TO
TH
TO
TH
C
SET
EA
I
I
B1
V
REF
V
REF
R
R
SET
VSET
7.2k
18.77k
DAC
VALUE
(10 BITS)
1760 F08
DAC
10
∆Σ
MODULATOR
11
∆Σ
MODULATOR
SWV
VALUE
(11 BITS)
1760 F07
Figure 7. Voltage DAC Operation
Figure 8. Current Dac Operation
1760fc
35
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
Automatic Current Sharing
it is actual physical capacity rating at the time of charge.
Capacity rating will change with age and use and hence
the current sharing ratios can change over time.
In a dual parallel charge configuration, the LTC1760 does
notactuallycontrolthecurrentflowingintoeachindividual
battery. The capacity, or Amp-Hour rating, of each battery
determines how the charger current is shared. This auto-
matic steering of current is what allows both batteries to
reach their full capacity points at the same time. In other
words, given all other things equal, charge termination
will happen simultaneously.
Adapter Limiting
An important feature of the LTC1760 is the ability to auto-
matically adjust charging current to a level which avoids
overloading the wall adapter. This allows the product to
operate at the same time that batteries are being charged
without complex load management algorithms. Addition-
ally,batterieswillautomaticallybechargedatthemaximum
possible rate of which the adapter is capable.
A battery can be modeled as a huge capacitor and hence
governed by the same laws.
This feature is created by sensing total adapter output cur-
rent and adjusting charging current downward if a preset
adapter current limit is exceeded. True analog control is
used,withclosedloopfeedbackensuringthatadapterload
current remains within limits. Amplifier CL1 in Figure 9
I = C • (dV/dt) where:
I = The current flowing through the capacitor
C = Capacity rating of battery (using amp-hour values
instead of capacitance)
senses the voltage across R , connected between the
CL
dV = Change in voltage
dt = Change in time
CLP and DCIN pins. When this voltage exceeds 100mV,
the amplifier will override programmed charging current
to limit adapter current to 100mV/R . A lowpass filter
CL
The equivalent model of a set or parallel batteries is a
set of parallel capacitors. Since they are in parallel, the
change in voltage over change in time is the same for both
batteries 1 and ꢀ.
formed by 5kΩ and 0.1µF is required to eliminate switch-
ing noise. If the current limit is not used, CLP should be
connected to DCIN.
dV/dt
= dV/dt
BATꢀ
BAT1
100mV
CLP
+
From here we can simplify.
–
0.1µF
5kΩ
CL1
I
I
/C
= dV/dt = I
/C
BAT1 BAT1
BATꢀ BATꢀ
+
AC ADAPTER
INPUT
R
CL
*
= I
C /C
BAT1 BATꢀ BAT1
DCIN
BATꢀ
V
IN
+
At this point you can see that the current divides as the
ratio of the two batteries capacity ratings. The sum of the
currentintoboth batteries is the sameasthecurrent being
supply by the charger. This is independent of the mode of
the charger (CC or CV).
1760 F09
C
IN
100mV
ADAPTER CURRENT LIMIT
*R
=
CL
Figure 9.
Setting Input Current Limit
I
= I
+ I
BAT1 BATꢀ
CHRG
To set the input current limit, you need to know the mini-
mumwalladaptercurrentrating.Subtract52fortheinput
current limit tolerance and use that current to determine
the resistor value.
From here we solve for the actual current for each battery.
I
I
= I
= I
C
/(C
+ C
+ C
)
)
BATꢀ
BAT1
CHRG BATꢀ BAT1
BATꢀ
BATꢀ
C
/(C
CHRG BAT1 BAT1
R
I
= 100mV/I
LIM
CL
Please note that the actual observed current sharing will
vary from manufacturer’s claimed capacity ratings since
= Adapter Min Current
LIM
– (Adapter Min Current • 52)
1760fc
36
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
As is often the case, the wall adapter will usually have at
least a +102 current limit margin and many times one
can simply set the adapter current limit value to the actual
adapter rating (see Figure 9 & Table 1).
Warning
DONOTCHANGETHEVALUEOFR
TION. The value must remain fixed and track the RSENSE
value at all times. Changing the current setting can result
in currents that greatly exceed the requested value and
potentiallydamagethebatteryoroverloadthewalladapter
if no input current limiting is provided.
DURINGOPERA-
ILIMIT
Table 1. Common RCL Resistor Values
Adapter
Rating A
RCL Value*
(Ω) 1%
RCL Power
Dissipation (W)
RCL Power
Rating (W)
1.5
1.8
ꢀ
0.06
0.05
0.135
0.16ꢀ
0.18
0.ꢀ5
0.ꢀ5
0.ꢀ5
0.ꢀ5
0.5
Setting Charger Output Voltage Limit
0.045
0.039
0.036
0.033
0.030
ThevalueofanexternalresistorconnectedfromtheV
LIMIT
ꢀ.3
ꢀ.5
ꢀ.7
3
0.ꢀ06
0.ꢀꢀ5
0.ꢀ41
0.ꢀ1
pin to GND determines one of five voltage limits that are
applied to the charger output value. See Table 3. These
limits provide a measure of safety with a hardware restric-
tion on charging voltage, which cannot be overridden by
software. This voltage sets the limit that will be applied
to the battery as reported by battery. Since the battery
internal voltage monitor point is the actual cell voltage,
you may see higher voltages, up to 51ꢀmV higher, at the
external charger terminals due to the voltage servo loop
action. See Operations “Section 3.7” for more information
on the voltage servo system.
0.5
0.5
*Values shown above are rounded to nearest standard value.
Table 1 RCL values take into account LTC1760 C-grade 52 tolerance for
VCL1.
Extending System to More than 2 Batteries
The LTC1760 can be extended to manage systems with
more than 3 sources of power. Contact Linear Technology
Applications Engineering for more information.
Table 3. Recommended Resistor Values for RVLIMIT
Charge Termination Issues
V
R
VLIMIT
(Ω) 1%
MAX
Up to 8.4V
0 (Short to ground)
Batteries with constant-current charging and voltage-
based charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
Up to 1ꢀ.6V
10k
Up to 16.8V
33k
Up to ꢀ1.0V
100k
Up to 3ꢀ.7V (No Limit)
Open or short to V
CCꢀ
Inductor Selection
Setting Charger Output Current Limit
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value
on ripple current and low current operation must also be
considered.Theinductorripplecurrent∆I decreaseswith
higher frequency and increases with higher V .
The LTC1760 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
Table 2. Recommended Resistor Values
L
I
(A)
R
SENSE
(Ω) 1%
R
(W)
R
(Ω) 1%
ILIMIT
MAX
SENSE
IN
1
0.100
0.ꢀ5
0.ꢀ5
0.5
0
⎛
⎞
⎟
⎠
ꢀ
3
4
0.05
0.0ꢀ5
0.0ꢀ5
10k
33k
1
VOUT
ΔIL =
VOUT 1−
⎜
f L
( )( )
V
⎝
IN
0.5
Open or short to V
CCꢀ
Accepting larger values of ∆I allows the use of low
L
inductances, but results in higher output voltage ripple
1760fc
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For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
and greater core losses. A reasonable starting point for
at high input voltage or during a short-circuit when
the duty cycle in this switch is nearly 1002. The term
(1 + d∆T) is generally given for a MOSFET in the form of a
setting ripple current is ∆I = 0.4(I
). In no case should
L
MAX
∆I exceed 0.6(I
) due to limits imposed by IREV and
L
MAX
CA1.Rememberthemaximum∆I occursatthemaximum
normalizedR
vsTemperaturecurve,butd=0.005/°C
L
DS(ON)
input voltage. In practice 10µH is the lowest value recom-
canbeusedasanapproximationforlowvoltageMOSFETs.
isusuallyspecifiedintheMOSFETcharacteristics.The
mended for use.
C
RSS
constant k = 1.7 can be used to estimate the contributions
of the two terms in the main switch dissipation equation.
Charger Switching Power MOSFET and Diode
Selection
If the LTC1760 charger is to operate in low dropout mode
or with a high duty cycle greater than 852, then the top-
side N-channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.
TwoexternalpowerMOSFETsmustbeselectedforusewith
the LTC1760 charger: An N-channel MOSFET for the top
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak gate drive levels are set by the V volt-
The Schottky diode D1, shown in the Typical Application,
conducts during the dead-time between the conduction of
the two power MOSFETs. This prevents the body diode of
the bottom MOSFET from turning on and storing charge
during the dead-time, which could cost as much as 12
in efficiency. A 1A Schottky is generally a good size for
4A regulators due to the relatively small average current.
Larger diodes can result in additional transition losses
due to their larger junction capacitance. The diode may
be omitted if the efficiency loss can be tolerated.
CC
age.Thisvoltageistypically5.ꢀV.Consequently,logic-level
threshold MOSFETs must be used. Pay close attention to
the B
specification for the MOSFETs as well; many of
VDSS
the logic level MOSFETs are limited to 30V or less.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance R
, reverse transfer capacitance C
DS(ON)
,
RSS
input voltage and maximum output current. The LTC1760
charger is always operating in continuous mode so the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = V /V
Calculating IC Operating Current
OUT IN
Synchronous Switch Duty Cycle = (V – V )/V
This section shows how to use the values supplied in the
Electrical Characteristics table to estimate operating cur-
rent for a given application.
IN
OUT IN
The MOSFET power dissipations at maximum output
current are given by:
ꢀ
ꢀ
The total IC operating current through DCIN when AC is
P
= V /V (I
RSS
) (1 + d∆T)R
+ k(V )
MAIN
OUT IN MAX
DS(ON)
IN
present and batteries are charging (I
) is given by:
DCIN_CHG
(I
MAX
)(C )(f)
ꢀ
I
I
= I
+ I
+ I
+ I
+
DCIN_CHG
CH1
+I
VCCꢀ_AC1
+I
SAFETY1
SAFETYꢀ
+I
P
= (V – V )/V (I
) (1 + d∆T) R
SYNC
IN
OUT IN MAX
DS(ON)
+I
+I
VLIM ILIM SMB SMB_BAT1 SMB_BATꢀ SMBALERT
Where d∆T is the temperature dependency of R
DS(ON)
where:
and k is a constant inversely related to the gate drive
ꢀ
current. Both MOSFETs have I R losses while the topside
I
I
I
is defined in “Electrical Characteristics.”
CH1
N-channel equation includes an additional term for transi-
tion losses, which are highest at high input voltages. For
is defined in “Electrical Characteristics.”
VCCꢀ_AC1
V < ꢀ0V the high current efficiency generally improves
isthecurrentusedtotestthebattery thermistor
SAFETYX
connected to SAFETY1 OR SAFETYꢀ.
IN
with larger MOSFETs, while for V > ꢀ0V the transition
IN
losses rapidly increase to the point that the use of a higher
For thermistors that are OVER-RANGE:
R
device with lower C
actually provides higher
DS(ON)
RSS
I
= ꢀ/64 • V
/(RXB + R
)
SAFETYX
VCCꢀ
THX
efficiency. The synchronous MOSFET losses are greatest
1760fc
38
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
For thermistors that are COLD-RANGE:
I
I
I
= I
ILIM
+ I
SMB
+ I
SMB_BAT1
+ I
SMB_BATꢀ
+
SAFETYꢀ
DCIN_CHG
CH1
+ I
VCCꢀ_AC1
+ I
SAFETY1
+ I
I
= 4/64 • V
/(RXB + R
)
+ I
+
SAFETYX
VCCꢀ
THX
VLIM
SMBALERT
For thermistors that are IDEAL-RANGE:
= 4/64 • V /(RXB + R ) + ꢀ/64 • V /
VCCꢀ
= 1.3mA + 700µA + ꢀ18µA + ꢀ18µA +81µA + 81µA
+ 0µA + 5.4µA + 5.4µA + 0µA = ꢀ.6ꢀmA
I
SAFETYX
(R1A +R
VCCꢀ
THX
)
THX
The total operating current through BAT1 and BATꢀ when
AC is not present (I
For thermistors that are HOT-RANGE:
= 4/64 • V /(RXB + R ) + 4/64 • V /
VCCꢀ
) is given by:
BAT_NOAC
I
SAFETYX
(R1A +R
VCCꢀ
THX
)
I
I
= I + I
SMB_BAT1_AC0
+ I
+ I
+
THX
BAT_NOAC
SMB
BAT
VCCꢀ_AC0
SAFETY1
SAFETYꢀ
+ I
+ I
+ I
SMB_BATꢀ_AC0 SMBALERT
R
is the impedance of the battery’s thermistor to
THX
ground.
where:
RXB = 54.9k
I
I
I
is defined in “Electrical Characteristics.”
BAT
RXA = 1.13k
is defined in “Electrical Characteristics.”
VCCꢀ_AC0
Sample calculation of I
with V
= 5.ꢀV
is the current used to test the battery
SAFETYX
thermistor connected to SAFETY1 or SAFETYꢀ.
SAFETYX
VCCꢀ
Thermistor Impedance
R
(W)
Thermistor Range
OVER_RANGE
I
(µA)
THX
SAFETYX
I
= ꢀ/64 • V /(RXB + R ).
SAFETYX
VCCꢀ
THX
400
1.05
R
is the impedance of the battery’s thermistor to
THX
3.3k
400
IDEAL_RANGE
UNDER_RANGE
4ꢀ.ꢀ
ꢀ18
ground.
RXB = 54.9k.
I
I
= V
/(R
+ R
).
VLIMIT
VCCꢀ
VLIMIT
LIM_PU
Sample calculation of I
with V
= 5.ꢀV
SAFETY
VCCꢀ
= V
/(R
+ R
).
ILIMIT
VCCꢀ
ILIMIT
LIM_PU
Thermistor Impedance
R
is the typical pull-up impedance at V
LIMIT
LIMIT.
LIM_PU
and I
R
(Ω)
Thermistor Range
I
(µA)
SAFETYX
THX
400
UNDER_RANGE
ꢀ.9
R
= 34k.
LIM_PU
I
is the current used for communicat-
SMB_BATX_ACO
ing with Battery1 or Batteryꢀ when AC in not present.
R
is the value of the resistance from V
to
VLIMIT
GND.
LIMIT
I
I
= 350µA • 0.00687 = ꢀ.404µA.
SMB_BATX_AC0
R
is the value of the resistance from I
to
ILIMIT
GND.
LIMIT
is the current used for communicating with the
SMB
SMBus Host and depends on the amount of bus
traffic.
I
is the current used for communicating with the
SMB
SMBus Host and depends on the amount of bus traffic.
Sample calculation with two Li-Ion batteries (R
400), V
=
THX
= 5.ꢀV, and no SMBus Host communication:
I
is the current used for communicating
CCꢀ
SMB_BATX
with Battery1 or Batteryꢀ.
I
I
– I + I
SMB_BAT1_AC0
+ I
+ I
SMBALERT
+
SAFETYꢀ
BAT_NOAC
SMB
BAT
VCCꢀ_AC0
SAFETY1
+ I
+ I
+ I
I
I
= 350µA • 0.0155 = 5.4ꢀ5µA.
SMB_BATꢀ_AC0
SMB_BATX
SMBALERT
= 175µA + 80µA + ꢀ.9µA + ꢀ.9µA + 0µA + ꢀ.4µA +
is defined in “Electrical Characteristics.”
ꢀ.4µA + 0µA = ꢀ65µA
Sample calculation of I
with two Li-Ion batteries
DCIN_CHG
(R
= 400), R
= R
= 30k, V
= 5.ꢀV, and
CCꢀ
THX
VLIMIT
ILIMIT
no SMBus Host communication:
1760fc
39
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
Calculating IC Power Dissipation
Capacitors C and C are used to filter the V delta-
DAC
B1
Bꢀ
sigma modulation frequency components to a level which
The power dissipation of the LTC1760 is dependent
is essentially DC. C is the primary filter capacitor and
Bꢀ
upon the gate charge of Q and Q .(Refer to Typical
TG
BG
CB1 is used to provide a zero in the response to cancel
Application). The gate charge is determined from the
manufacturer’sdatasheetandisdependentuponboththe
gate voltage swing and the drain voltage swing of the FET.
the pole associated with C . Acceptable voltage ripple
Bꢀ
at V
is about 10mV . Since the period of the delta-
SET
P-P
∆S
sigma switch closure, T , is about 11µs and the internal
P = (V
DCIN_CHG
– V ) • f
• (Q + Q ) + V
•
V
DAC
resistor, R
, is 7.ꢀkΩ, the ripple voltage can be
D
DCIN
VCC
• (I
OSC
TG
+ I
BG
)
DCIN
VSET
I
– V
approximated by:
VREF • TΔ∑
RVSET C ||C
Bꢀ
VCC
SAFETY1
SAFETYꢀ
where:
ΔVVSET
=
(
)
I
, I
, I
are defined in the
B1
DCIN_CHG SAFETY1 SAFETYꢀ
previous section.
Example:
= 5.ꢀV, V
Then the equation to extract C || C is:
B1
Bꢀ
VREF • TΔ∑
CB1 ||CBꢀ =
V
= 19V, f
= 345kHz, Q
=
VCC
DCIN
OSC
= ꢀ.6ꢀmA, I
TG
R
VSETΔVVSET
Q
= 15nC, I
=
BG
SAFETYꢀ
P = 190mW
D
DCIN_CHG
= ꢀ18µA.
SAFETY1
I
C
should be 10× to ꢀ0× C to divide the ripple voltage
B1
Bꢀ
present at the charger output. Therefore C = 0.01µF and
B1
C
= 0.1µF are good starting values. In order to prevent
Bꢀ
V /I Capacitors
SET SET
overshoot during start-up transients the time constant as-
sociated with C must be shorter than the time constant
Capacitor C7 is used to filter the delta-sigma modulation
frequency components to a level which is essentially DC.
Acceptable voltage ripple at I is about 10mV . Since
the period of the delta-sigma switch closure, T , is about
10µs and the internal I
ripple voltage can be approximated by:
Bꢀ
of C5 at the I pin. If C is increased to improve ripple
TH
Bꢀ
rejection, then C5 should be increased proportionally and
charger response time to voltage variation will degrade.
SET
P-P
∆S
resistor, R , is 18.77k, the
DAC
SET
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application
VREF • TΔ∑
RSET •C7
section), theinputcapacitor(C )isassumedtoabsorball
ΔV
=
IN
ISET
input switching ripple current in the converter, so it must
haveadequateripplecurrentrating.Worst-caseRMSripple
currentwillbeequaltoonehalfofoutputchargingcurrent.
Actual capacitance value is not critical. Solid tantalum
low ESR capacitors have high ripple current rating in a
relatively small surface mount package, but caution must
be used when tantalum capacitors are used for input or
output bypass. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capaci-
tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “Surge Robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.
Then the equation to extract C7 is:
VREF • TΔ∑
C7 =
ΔV
•RSET
ISET
= 0.8/0.01/18.77k(10µs) @ 0.043µF
In order to prevent overshoot during start-up transients
the time constant associated with C7 must be shorter than
the time constant of C5 at the I pin. If C7 is increased
to improve ripple rejection, then C5 should be increased
proportionally and charger response time to average cur-
rent variation will degrade.
TH
1760fc
40
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
The relatively high ESR of an aluminum electrolytic for
C15, located at the AC adapter input terminal, is helpful
in reducing ringing during the hot-plug event. Refer to
AN88 for more information.
current. FortheN-channelchargepath, themaximumcur-
rent is the maximum programmed current to be used. For
the P-channel discharge path maximum current typically
occurs at end of life of the battery when using only one
battery. The upper limit of R
value is a function of
DS(ON)
Highest possible voltage rating on the capacitor will
minimize problems. Consult with the manufacturer before
use. Alternatives include new high capacity ceramic (at
least ꢀ0µF) from Tokin, United Chemi-Con/Marcon, et al.
Other alternative capacitors include OSCON capacitors
from Sanyo.
the actual power dissipation capability of a given MOSFET
package that must take into account the PCB layout. As a
starting point, without knowing what the PCB dissipation
capability would be, derate the package power rating by
a factor of two.
PMOSFET
RDS(ON)MAX
=
The output capacitor (C ) is also assumed to absorb
OUT
ꢀ
ꢀ I
(
)
MAX
output switching current ripple. The general formula for
capacitor current is:
If you are using a dual MOSFET package with both MOS-
FETs in series, you must cut the package power rating in
half again and recalculate.
V
BAT
0.29 (V ) 1 –
BAT
V
DCIN
I
=
PMOSFETDUAL
RMS
(L1)(f)
RDS(ON)MAX
=
ꢀ
4 I
(
)
MAX
For example:
If you use identical MOSFETs for both battery paths,
voltage drops will track over a wide current range. The
LTC1760 linear ꢀ5mV CV drop regulation will not occur
until the current has dropped below:
V
= 19V, V = 1ꢀ.6V, L1 = 10µH, and
BAT
DCIN
f = 300kHz, I
= 0.41A.
RMS
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
maybeaddedtoincreasebatteryimpedanceatthe300kHz
switching frequency. Switching ripple current splits be-
tween the battery and the output capacitor depending on
theESRoftheoutputcapacitorandthebatteryimpedance.
If the ESR of C
raised to 4Ω with a bead or inductor, only 52 of the cur-
rent ripple will flow in the battery.
ꢀ5mV
ILINEARMAX
=
ꢀRDS(ON)MAX
However, if you try to use the above equation to determine
R
R
to force linear mode at full current, the MOSFET
value becomes unreasonably low for MOSFETs
DS(ON)
DS(ON)
is 0.ꢀΩ and the battery impedance is
OUT
available at this time. The need for the LTC1760 voltage
drop regulation only comes into play for parallel battery
configurations that terminate charge or discharge using
voltage. At first this seems to be a problem, but there are
several factors helping out:
PowerPath and Charge MUX MOSFET Selection
Three pairs of P-channel MOSFETs must be used with
the wall adapter and the two battery discharge paths. Two
pairsofN-channelMOSFETsmustbeusedwiththebattery
charge path. The nominal gate drive levels are set by the
clamp drive voltage of their respective control circuitry.
This voltage is typically 6.ꢀ5V. Consequently, logic-level
threshold MOSFETs must be used. Pay close attention to
1. When batteries are in parallel current sharing, the cur-
rent flow through any one battery is less than if it is
running stand-alone.
ꢀ. Most batteries that charge in constant voltage mode,
such as Li-ion, charge terminate at a current value of
C/10 or less which is well within the linear operation
range of the MOSFETs.
the B
specification for the MOSFETs as well; many of
VDSS
the logic level MOSFETs are limited to 30V or less.
3. Voltage tracking for the discharge process does not
need such precise voltage tracking values.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance R
, input voltage and maximum output
DS(ON)
1760fc
41
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
The LTC1760 has two transient conditions that force the
dischargepathP-channelMOSFETstohavetwoadditional
parameters to consider. The parameters are gate charge
Remember to only use the real wall adapter with a produc-
tionDCpowercordwhenperformingthewalladapterpath
test. The use of a laboratory power supply is unrealistic
for this test and will force you to over specify the MOSFET
ratings.Abatterypackusuallyhasenoughseriesresistance
to limit the peak current or are too low in voltage to create
enough instantaneous power to damage their respective
power path MOSFETs.
Q
GATE
and single pulse power capability.
When the LTC1760 senses a LOW_POWER event, all
the P-channel MOSFETs are turned on simultaneously
to allow voltage recovery due to a loss of a given power
source. However, there is a delay in the time it takes to
turn on all the MOSFETs. Slow MOSFETs will require more
bulk capacitance to hold up all the system’s power sup-
ply function during the transition and fast MOSFET will
require less bulk capacitance. The transition speed of a
MOSFET to an on or off state is a direct function of the
MOSFET gate charge.
Conditioning Systems With Large Loads
In systems where the load is too large to be used for
conditioning a single battery it may be necessary to
bypass the built in calibrate function and simply switch
in an external load. A convenient way to accomplish this
task is by using an SMBus based LTC16ꢀ3 load switch
controller. See Figure 10.
t = Q
/I
GATE DRIVE
I
is the fixed drive current into the gate from the
DRIVE
LTC1760 and “t” is the time it takes to move that charge
to a new state and change the MOSFET conduction mode.
TO
LOAD
PowerPath
MUX
HencetimeisdirectlyrelatedtoQ
.SinceQ
goesup
LTC1760
GATE
GATE
with MOSFETs of lower R
, choosing such MOSFETs
CHARGE
MUX
DS(ON)
has a counterproductive increase in gate charge making
theMOSFETslower.PleasenotethattheLTC1760recovery
time specification only refers to the time it takes for the
voltagetorecovertotheleveljustpriortotheLOW_POWER
event as opposed to full voltage.
SMBus
The single pulse current rating of MOSFET is important
when a short-circuit takes place. The MOSFET must
SMBus
TO/FROM
HOST
CONDITIONING
LOAD
LTC1623
survive a 15ms overload. MOSFETs of lower R
DS(ON)
or MOSFETs that use more powerful thermal packages
will have a high power surge rating. Using too small of a
pulse rating will allow the MOSFET to blow to the open
circuit condition instantly like a fuse. Typically there is no
outward sign of failure because it happens so fast. Please
measure the surge current for all discharge power paths
under worse case conditions and consult the MOSFET
data sheet for the limitations. Voltage sources with the
highest voltage and the most bulk capacitance are often
the biggest risk. Specifically the MOSFETs in the wall
adapter path with wall adapters of high voltage, large
bulk capacitance and low resistance DC cables between
the adapter and device are the most common failures.
1760 F10
Figure 10. Large Load Conditioning Circuit
Unique Configuration Information
This section summarizes unique LTC1760 configurations
thatallowsome LTC1760featurestobeeliminated. These
configurations may be selected in any combination with-
out adversely affecting LTC1760 operation. Refer to the
Typical Application circuit diagram located at the back of
this data sheet.
1760fc
42
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
A) Single Battery Configuration.
5) RemoveallcomponentsconnectedtoCOMP1,V
,
SET
I , I , I
and V
pins.
TH SET LIMIT
LIMIT
To limit the LTC1760 to a single battery, modify the
battery slot to be eliminated as follows:
6) Short I
and V
to GND.
LIMIT
LIMIT
1) Remove both FETs (Q5, Q6 or Q7, Q8) involved in
the discharge path.
7) Remove R1, C1 but short CLP to DCIN. Replace
with a short/trace connection.
R
CL
ꢀ) Remove both FETS (Q3, Q4 or Q9, Q10) involved in
the charge path.
8) ShortCSPtoCSNbutleavethecombinationfloating.
9) Unless otherwise specified, leave the unused pins
of the LTC1760 floating.
3) Removethethermistorsensingresistors(R1A, R1B
or RꢀA, RꢀB).
F) No DC Path And No Charge Configuration.
4) Short the thermistor sense lines (TH1A, TH1B or
THꢀA, THꢀB) together at the IC.
To limit the LTC1760 to battery discharge functions
only, merge the previous two configurations with the
following:
5) Remove the diode (Dꢀ or D3).
6) Unless otherwise specified, leave the unused pins
of the LTC1760 floating.
1) Remove C .
IN
ꢀ) Remove resistors tied to DCDIV. Ground DCDIV.
B) No Short-Circuit Protection Configuration.
PCB Layout Considerations
1) Replace R with a short.
SC
Formaximumefficiency,theswitchnoderiseandfalltimes
should be minimized. To prevent magnetic and electrical
field radiation and high frequency resonant problems,
proper layout of the components connected to the IC is
essential. (See Figure 11.) Here is a PCB layout priority list
for proper layout. Layout the PCB using this specific order.
C) No LOPWR Protection.
1) Remove resistors Rꢀ and R3 connected to LOPWR
and tie LOPWR to the V pin.
CC
D)No DC Path Configuration.
ToremovetheDCinputaspartofthepowerpathchoices
to support the load:
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
1) Remove both FETs Q1 and Qꢀ involved in the DC
path.
ꢀ) Unless otherwise specified, leave the unused pins
of the LTC1760 floating.
E) No Charge Configuration.
SWITCH NODE
L1
V
BAT
To permanently disable the battery charger function:
1) Remove ALL FETs involved in the charge path (Q3,
Q4, Q9, Q10).
HIGH
FREQUENCY
CIRCULATING
PATH
C
IN
D1
C
OUT
V
IN
BAT
ꢀ) Remove switching FETs QTG, QBG, diode D1 and
inductor L1.
1760 F10
3) RemovediodesDꢀ, D3, D4, capacitorsC4, C
and
OUT
Resistor R11 and R
.
Figure 11. High-Speed Switching Path
SENSE
4) Reduce C capacitor to 0.1µF.
IN
1760fc
43
For more information www.linear.com/LTC1760
LTC1760
APPLICATIONS INFORMATION
ꢀ. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
cleanFETdrive.ThisincludesICsupplypinsthatconnect
to the switching FET source pins. The IC can be placed
on the opposite side of the PCB relative to above.
9. A good rule of thumb for via count for a given high
current path is to use 0.5A per via. Be consistent.
10. If possible, place all the parts listed above on the
same PCB layer.
11.Copperfillsorpoursaregoodforallpowerconnections
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
-
except as noted above in Rule 3. You can also use cop
per planes on multiple layers in parallel too—this helps
with thermal management and lower trace inductance
improving EMI performance further.
1ꢀ. For best current programming accuracy provide a
Kelvin connection from R
Figure 1ꢀ as an example.
to CSP and BAT. See
SENSE
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time
with smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at
the sense resistor location.
It is important to keep the parasitic capacitance on the R ,
T
CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.
DIRECTION OF CHARGING CURRENT
R
SNS
5.Placeoutputcapacitorsnexttothesenseresistoroutput
and ground.
1760 F11
6. Output capacitor ground connections need to feed into
samecopperthatconnectstotheinputcapacitorground
before tying back into system ground.
CSN
CSP
Figure 12. Kelvin Sensing of Charging Current
General Rules
Important Safety Notes
7. Connection of switching ground to system ground or
internal ground plane should be single point. If the
system has an internal system ground plane, a good
way to do this is to cluster vias into a single star point
to make the connection.
Although every effort is made to meet and exceed all
required “SMBus Charger V1.1” safety features it is the
responsibility of the battery pack to protect itself from
excessive currents or voltages. The LTC1760 is not itself
a safety device. Consult your battery pack manufacturer
for more information.
8. Route analog ground as a trace tied back to IC ground
(analog ground pin if present) before connecting to any
other ground. Avoid using the system ground plane.
CAD trick: make analog ground a separate ground net
and use a 0Ω resistor to tie analog ground to system
ground.
1760fc
44
For more information www.linear.com/LTC1760
LTC1760
TYPICAL APPLICATIONS
PowerPath MUX
R
CL
0.03Ω
V
IN
R10
100Ω
C8
1µF
C9
C1
0.1µF
Q1
Q6
Q5
Q7
Q8
R1
4.99k
0.1µF
LTC1760
Q2
36
41
3
1
7
6
9
V
CLP
DC
BAT1
BAT2
PLUS
GDCI
GDCO
GB1I
GB1O
GB2I
GB2O
SCP
SCN
IN
R4
100pF
2
12.7k
8
11
10
5
R
SC
0.02Ω
R5
1.21k
16
37
47
48
46
45
13
40
24
4
DCDIV
COMP1
GCH2
SCH2
GCH1
SCH1
LOAD
12
34
35
14
15
42
43
44
39
38
28
27
17
21
30
31
19
23
LOPWR
CSN
CSP
R2
280k
R7
49.9k
CL
20µF
C11
1800pF
I
TH
R3
49.9k
C3
I
SET
R9
0.012µF
SW
BOOST
TGATE
BGATE
PGND
TH2A
TH2B
SCL2
SDA2
TH1A
TH1B
SCL1
V
3.3k
C12
100pF
SET
C7
0.1µF
V
CC
GND
V
DDS
C5
0.15µF
SMBALERT
SCL
V
*
DDS
R2A, 1.13k
25
29
18
22
20
33
32
26
BAT2
R
PU
R
PU
V
CC2
R2B, 54.9k
TH
SMBALERT
SCL
SCL2
SDA2
SDA
SCL
SDA
SDA
V
DDS
V
DDS
R1A, 1.13k
R1B, 54.9k
V
I
LIMIT
LIMIT
MODE
R
VLIMIT
10k
SDA1
C1
0.1µF
V
*
DDS
BAT1
TH
SCL
SDA
SCL1
SDA1
BAT2
D2
BAT1
D3
QTG
QBG
C
IN
20µF
C4
0.22µF
R11
1k
L1
10µH
D4
C
OUT
20µF
R
SENSE
0.025
C6
4.7µF
C13
0.1µF
D1
CB2
0.47µF
CB1
0.1µF
CHARGE
MUX
R6
100Ω
Q4
Q3
Q9
Q10
BAT1
BAT2
1760 TA02
D1: MBR130T3
D2, D3: BAT54A TYPE
D4: CMDSH3 TYPE
Q1, Q2, Q5, Q6, Q7, Q8: Si4925DY
Q3, Q4, Q9, Q10, QTG, QBG: FDS6912A
*OPTIONAL: ESD CLAMP DIODES FOR BATTERY HOT SWAP PROTECTION
1760fc
45
For more information www.linear.com/LTC1760
LTC1760
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC1760#packaging for the most recent package drawings.
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651 Rev A)
12.40 – 12.60*
(.488 – .496)
48
25
0.95 0.10
6.2 0.10
44
42
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
48 47 46 45
43
8.4 0.10
7.9 – 8.3
(.311 – .327)
1
24
0.32 0.05
0.50 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
6.0 – 6.2**
(.236 – .244)
0.25
REF
0° – 8°
-T-
-C-
0.10 C
FW48 TSSOP REV A 1005
0.50
(.0197)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.09 – 0.20
(.0035 – .008)
0.45 – 0.75
(.018 – .029)
0.05 – 0.15
(.002 – .006)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
**
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1760fc
46
For more information www.linear.com/LTC1760
LTC1760
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
04/11 I-Grade part added. Reflected throughout the data sheet
1-48
3
B
03/16 Revised Conditions of V Load Regulation Spec
CC
C
08/17 Revised Circuit Diagram C5 & C7, BAT1, BATꢀ added
45
1760fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
47
LTC1760
RELATED PARTS
PART NUMBER
LT®1571
DESCRIPTION
COMMENTS
1.5A Switching Regulator Battery Charger
Li-Ion Linear Charger with Thermal Regulation
ꢀA Switching Regulator Battery Charger
Dual Battery Charger/Selector with SPI
500kHz or ꢀ00kHz Switching Frequency for Small Design
Will Not Overheat, Standalone Charger, Complete Charger
Monolithic, ꢀ0-Lead TSSOP, ꢀ8-Lead SSOP Packages
LTC1733
LT1769
LTC1960
LTC4006
11-Bit V , 0.82 Voltage Accuracy, 10-Bit I
for 52 Current Accuracy
DAC
DAC
Small, High Efficiency, Fixed Voltage,
Lithium-Ion Battery Charger
Constant Current/ Constant Voltage Switching Regulator
with Termination Timer; AC Adapter Current Limit and
SafetySignal Sensor in a Small 16 Pin Package
LTC4007
LTC4008
High Efficiency, Programmable Voltage
Battery Charger with Termination
Complete Charger for 3- or 4-Cell Lithium-Ion Batteries,
AC Adapter Current Limit, SafetySignal Sensor and Indicator Outputs
High Efficiency, Programmable Voltage/
Current Battery Charger
Constant Current/ Constant Voltage Switching Regulator;
Resistor Voltage/Current Programming, AC Adapter Current
Limit and SafetySignal Sensor
LTC4100
Smart Battery Charger Controller
SMBus Rev 1.1 Compliant
1760fc
LT 0817 REV C • PRINTED IN USA
www.linear.com/LTC1760
48
LINEAR TECHNOLOGY CORPORATION 2010
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