LTC1909-8EG#TR_技术文档

LTC1909-8

Wide Operating Range,

No R_SENSE^TMStep-Down DC/DC

Controller with SMBus Programming

U

FEATURES

DESCRIPTIO

The LTC^®1909-8 is a synchronous step-down switching

regulator controller with a digitally programmable output

voltage. The output voltage is selected from one of two

5-bit settings programmed into internal registers via a

2-wire SMBus/I²C interface. The interface features safe-

guards against invalid output voltages and allows the mi-

croprocessor to turn the regulator on and off. Valley cur-

rentcontroldeliversverylowdutycycleswithoutrequiring

SMBus/I²C^TMProgrammable Output Voltage:

■

1.3V to 3.5V

■

No Sense Resistor Required

■

2% to 90% Duty Cycle at 200kHz

t

_ON(MIN)≤ 100ns

True Current Mode Control

Stable with Ceramic C_OUT

Power Good Output Voltage Monitor and 50µs Timer

Wide V_INRange: 4V to 36V (Abs Max)

Precision Resistor Divider and Reference Provide

±1.35% Output Voltage Accuracy Over Temperature

Adjustable Switching Frequency and Current Limit

Forced Continuous Control Pin

a sense resistor. Operating frequency is selected by an

external resistor and is compensated for variations in V_IN

and V_OUT

.

■

Discontinuous mode operation provides high efficiency

operation at light loads. A forced continuous control pin

reduces noise and RF interference and can assist second-

ary winding regulation by disabling discontinuous mode

operation when the main output is lightly loaded.

Programmable Soft-Start

Output Overvoltage Protection

Optional Short-Circuit Shutdown Timer

Available in a 28-Lead SSOP Package

U

Fault protection is provided by internal foldback current

limiting, an output overvoltage comparator and optional

short-circuit shutdown timer.

APPLICATIO S

■

Power Supplies for DSPs, ASICs, FPGAs and CPUs

The LTC1909-8 is available in the 28-lead SSOP package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No R_SENSEis a trademark of Linear Technology Corporation.

I²C is a trademark of Philips Electronics N.V.

■

Voltage Margining

U

TYPICAL APPLICATIO

V

IN

0.1µF

5V TO 24V

C

IN

LTC1909-8

100k

CMDSH-3

0.22µF

10µF

50V

×4

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS BOOST

100k

GND

M1

M2

V

TG

ON

L1

3

V

OUT

11k

39k

1.8µH

PGOOD

SW

+

2.5V OR 2.6V

10A

4

V

SENSE

RNG

(V

SET BY SEL)

OUT

5

100pF

FCB

PGND

BG

6

C

OUT3

I

TH

OUT1, 2

+

180µF

4V

22µF

6.3V

X7R

7

470pF

SGND

INTV

CC

1Ω

20k

8

×2

+

ION

V

IN

CC

4.7µF

6.3V

D1

9

5V

EXT

V

FB

EXTV

V

0.1µF

10

11

12

13

14

SEL

SDA

SEL

GND

: UNITED CHEMICON THCR60E1H106TZ

: CORNELL DUBILIER ESRE181ME04B/

PANASONIC EEFVEOG181R

D1: DIODES INC. B340A

L1: SUMIDA CEP125-1R8MC-H

M1: Si4884

R

ON

SDA

GND

FB

C

IN

OUT1, 2

1.4M 1%

SCL

VRON

PGTMR

V

OSENSE

VRON

19098 F01

CPUON

M2: Si4874

Figure 1. High Efficiency Step-Down Converter

19098f

1

LTC1909-8

W W U W

U W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

ORDER PART

NUMBER

Input Supply Voltage

V_IN, I_ON..................................................–0.3V to 36V

Boosted Topside Driver Supply Voltage

1

2

BOOST

TG

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS

V

ON

LTC1909-8EG

3

SW

PGOOD

BOOST.................................................. –0.3V to 42V

SW, SENSE⁺Voltages ................................. –5V to 36V

EXTV_CC, (BOOST – SW), RUN/SS, PGOOD, INTV_CC,

+

4

SENSE

PGND

BG

V

RNG

5

FCB

6

I

TH

SEL, SDA, SCL, VRON, PGTMR, V_OSENSE

,

7

INTV

CC

SGND

FB, CPUON, V_CCVoltages .......................... –0.3V to 7V

FCB, V_ON, V_RNGVoltages ....... –0.3V to (INTV_CC+ 0.3V)

I_TH, V_FBVoltages...................................... –0.3V to 2.7V

TG, BG, INTV_CC, EXTV_CCPeak Currents.................... 2A

TG, BG, INTV_CC, EXTV_CCRMS Currents .............. 50mA

Operating Ambient Temperature Range

8

V

IN

I

ON

9

EXTV

CC

V

FB

10

11

12

13

14

V

CC

SEL

SDA

GND

FB

SCL

V

VRON

PGTMR

OSENSE

CPUON

LTC1909-8EG (Note 2) ....................... –40°C to 85°C

Junction Temperature (Note 4)............................ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

G PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 95°C/ W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

(Switching Regulator Controller) The ● denotes specifications which apply

over the full operating temperature range, otherwise specifications are T_A= 25°C. V_IN= 15V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

I

Input DC Supply Current

Normal

Shutdown Supply Current

Q

900

15

2000

30

µA

V

Feedback Reference Voltage

Feedback Voltage Line Regulation

Feedback Voltage Load Regulation

Feedback Input Current

I

= 1.2V (Note 3)

TH

●

0.792

0.800

0.002

–0.05

–5

0.808

V

%/V

%

FB

∆V

V

= 4V to 30V, I = 1.2V (Note 3)

FB(LINEREG)

IN

TH

I

= 0.5V to 1.9V (Note 3)

= 0.8V

–0.3

±50

2

FB(LOADREG)

TH

I

V

nA

FB

g

Error Amplifier Transconductance

Forced Continuous Threshold

Forced Continuous Pin Current

On-Time

I

= 1.2V (Note 3)

●

1.4

1.7

mS

V

m(EA)

TH

V

FCB

0.76

0.8

0.84

–2

I

t

V

= 0.8V

FCB

–1

µA

FCB

ON

I

= 60µA, V = 1.5V

212

425

250

500

288

575

ns

ON

= 30µA, V = 1.5V

ON

t

Minimum On-Time

Minimum Off-Time

I

= 180µA, V = 0V

50

100

400

ns

ON(MIN)

OFF(MIN)

ON

= 60µA, V = 1.5V

250

ON

V

Maximum Current Sense Threshold

V

= 1V, V = 0.76V

113

79

158

133

93

186

153

107

214

mV

SENSE(MAX)

RNG

FB

+

V

– V

= 0V, V = 0.76V

●

PGND

SENSE

FB

= INTV , V = 0.76V

CC FB

V

Minimum Current Sense Threshold

V

= 1V, V = 0.84V

–67

–47

–93

mV

SENSE(MIN)

RNG

FB

+

V

– V

= 0V, V = 0.84V

PGND

SENSE

FB

= INTV , V = 0.84V

CC FB

∆V

FB(OV)

Output Overvoltage Fault Threshold

5.5

7.5

9.5

%

19098f

2

LTC1909-8

ELECTRICAL CHARACTERISTICS

(Switching Regulator Controller) The ● denotes specifications which apply

over the full operating temperature range, otherwise specifications are T_A= 25°C. V_IN= 15V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

520

0.8

TYP

600

1.5

4

MAX

680

2

UNITS

mV

V

∆V

FB(UV)

Output Undervoltage Fault Threshold

RUN Pin Start Threshold

RUN Pin Latchoff Enable Threshold

RUN Pin Latchoff Threshold

Soft-Start Charge Current

Soft-Start Discharge Current

Undervoltage Lockout

V

●

RUN/SS(ON)

RUN/SS(LE)

RUN/SS(LT)

RUN/SS(C)

RUN/SS(D)

RUN/SS Pin Rising

RUN/SS Pin Falling

4.5

4.2

–3

3

V

3.5

–1.2

1.8

3.4

3.5

2

V

I

V

= 0V

–0.5

0.8

µA

V

RUN/SS

= 4.5V, V = 0V

FB

V

Falling

●

3.9

4

IN(UVLO)

IN

Undervoltage Lockout Release

TG Driver Pull-Up On Resistance

TG Driver Pull-Down On Resistance

BG Driver Pull-Up On Resistance

BG Driver Pull-Down On Resistance

TG Rise Time

Rising

V

IN(UVLOR)

TG R

BG R

TG High

TG Low

BG High

BG Low

3

Ω

UP

2

3

Ω

DOWN

UP

3

4

Ω

1

2

Ω

DOWN

TG t

C

= 3300pF, 20% to 80% of Swing

20

ns

r

f

LOAD

TG Fall Time

BG t

BG Rise Time

r

f

BG Fall Time

Internal V Regulator

CC

V

Internal V Voltage

6V < V < 30V, V = 4V

EXTVCC

●

4.7

4.5

5

5.3

V

%

INTVCC

CC

IN

∆V

Internal V Load Regulation

I

= 0mA to 20mA, V = 4V

EXTVCC

–0.1

4.7

±2

LDO(LOADREG)

EXTVCC

CC

V

EXTV Switchover Voltage

= 20mA, V

Rising

= 5V

V

CC

EXTVCC

∆V

EXTV Switch Drop Voltage

150

200

300

mV

EXTVCC

CC

EXTV Switchover Hysteresis

EXTVCC(HYS)

CC

PGOOD Output

∆V

PGOOD Upper Threshold

PGOOD Lower Threshold

PGOOD Hysteresis

V

Rising

5.5

7.5

–7.5

1

9.5

–9.5

2

%

V

FBH

FB

Falling

–5.5

FBL

FB

Returning

FB(HYS)

FB

V

PGOOD Low Voltage

I

= 5mA

0.15

0.4

PGL

PGOOD

(SMBus VID Programmer) The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. 2.7V ≤ V_CC≤ 5.5V (Note 5) unless otherwise stated.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Operating Supply Voltage Range

Supply Current

2.7

5.5

CC

I

CPUON, PGTMR Pins Are Open

●

350

26

µA

kΩ

%

CC

R

Resistance Between V

and FB

OSENSE

14

–0.35

2.1

20

FB-SENSE

DE

Divider Error (Note 6)

V

Programmed from 1.3V to 3.5V

0.35

OSENSE

V

SCL, SDA Input High Voltage

SCL, SDA Input Low Voltage

V

IH

0.8

2

V

IL

SEL, VRON Input High Voltage

SEL, VRON Input Low Voltage

SEL, VRON Hysteresis

1.3

V

IH

●

0.8

V

IL

±50

mV

V

HYST

OL

SDA, CPUON PGTMR Output Low Voltage I = 3mA

SCL, SDA, SEL, VRON Input Current SDA Not Acknowledging, 0 ≤ V ≤ 5.5V,

●

0.4

I

±10

µA

IN

V

= 5.5V for VRON only

19098f

3

LTC1909-8

ELECTRICAL CHARACTERISTICS

(SMBus VID Programmer) The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. 2.7V ≤ V_CC≤ 5.5V (Note 5) unless otherwise stated.

SYMBOL

PARAMETER

CONDITIONS

0 ≤ V ≤ 2.7V

MIN

TYP

MAX

UNITS

I

SDA, PGTMR, CPUON

Sink Current at V = 2.7V

●

5

19

60

mA

SK1

CC

I

SDA, PGTMR, CPUON

Sink Current at V = 5.5V

0 ≤ V ≤ 5.5V

35

–1

65

150

mA

SK2

CC

I

PGTMR, CPUON Leakage Current

VRON Pull-Up Current

0 ≤ V ≤ 5.5V

±0.2

µA

LKG

PU

V

= 0

●

–2.5

–7

Timing (Note 7)

f

t

SMBus Operating Frequency

Bus Free Time Between Stop/Start

Hold Time After (Repeated) Start

Repeated Start Setup Time

Stop Condition Setup Time

Data Hold Time

●

10

4.7

4

100

KHz

µs

ns

µs

ns

SMB

BUF

HD:STA

SU:STA

SU:STO

HD:DAT

SU:DAT

LOW

HIGH

f

4.7

4

300

250

4.7

4

Data Setup Time

Clock Low Period

Clock High Period

SCL, SDA Fall Time

0.9V to 0.65V

300

CC

SCL, SDA Rise Time

0.65V to 2.25V

1000

r

SEL to V

High (Note 8)

Toggle SEL to Switch from 01111B to 10000B,

500

160

SSH

OSENSE

V

= 0.8V

FB

t

SEL to V

Low (Note 8)

Toggle SEL to Switch from 10000B to 01111B,

= 0.8V

●

ns

SSL

SPL

OSENSE

V

FB

SEL Toggling to PGTMR Low

Toggle SEL to Select New Code

C = 100pF, 10kΩ Pull-Up, S2 in Test Circuit

500

L

t

Stop Bit to CPUON High (Note 9)

Stop Bit to CPUON Low (Note 9)

Stop Bit to PGTMR Low (Note 9)

VRON High to CPUON High

VRON Low to CPUON Low

VRON Low to PGTMR Low

PGTMR Low Duration

C = 100pF, 10kΩ Pull-Up, S2 in Test Circuit

●

2

50

250

2

µs

ns

µs

ns

µs

PH

L

C = 0.1µF, 10kΩ Pull-Up, S1 in Test Circuit

L

20

PL

C = 100pF, 10kΩ Pull-Up, S2 in Test Circuit

L

PPL

VH

C = 100pF, 10kΩ Pull-Up, S2 in Test Circuit

L

C = 0.1µF, 10kΩ Pull-Up, S1 in Test Circuit

L

50

500

70

VL

C = 100pF, 10kΩ Pull-Up, S2 in Test Circuit

L

130

50

VPL

PGL

C = 100pF, 10kΩ Pull-Up, S2 in Test Circuit

L

30

Note5:Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevicepins

are negative. All voltages are referenced to device ground unless otherwise

noted.

Note 6: The divider error is tested in a feedback loop that adjusts FB to

0.8V for each 5-bit code.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LTC1909-8E is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 7: These parameters are guaranteed by design and are not tested in

production. SMBus timing is referenced to V and V levels.

Note 3: The LTC1909-8 is tested in a feedback loop that adjusts V to

IL

IH

FB

achieve a specified error amplifier output voltage (I ).

Note 8: Dominated by the switching regulator. The delay due to the SMBus

TH

VID programmer is only 500ns typ.

Note 4: T is calculated from the ambient temperature T and power

J

A

dissipation P as follows:

Note 9: Measured from the rising edge of SDA during Data High

D

acknowledgment.

LTC1909-8E: T = T + (P • 130°C/W)

J

A

D

19098f

4

LTC1909-8

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Transient Response

(Discontinuous Mode)

Efficiency vs Load Current

Transient Response

100

90

80

70

60

50

V_OUT

DISCONTINUOUS

MODE

50mV/DIV

CONTINUOUS

MODE

I_L

5A/DIV

V

= 10V

IN

= 2.5V

20µs

LOAD STEP 0A TO 10A

V_IN= 15V

19098 G16

20µs

LOAD STEP 1A TO 10A

V_IN= 15V

19098 G17

OUT

EXTV = 5V

CC

FIGURE 1 CIRCUIT

V

_OUT= 2.5V

V_OUT= 2.5V

0.01

0.1

1

0.001

10

FCB = 0V

FIGURE 1 CIRCUIT

FCB = INTV_CC

FIGURE 1 CIRCUIT

LOAD CURRENT (A)

19098 G18

Efficiency vs Input Voltage

Frequency vs Input Voltage

Load Regulation

0

–0.1

–0.2

–0.3

–0.4

100

95

300

280

260

240

220

200

FCB = 5V

FCB = 0V

FIGURE 1 CIRCUIT

I

= 10A

= 0A

OUT

I

= 1A

LOAD

90

I

= 10A

LOAD

I

OUT

85

80

0

5

10

15

20

25

30

5

10

15

INPUT VOLTAGE (V)

20

0

2

4

6

8

10

25

INPUT VOLTAGE (V)

LOAD CURRENT (A)

19098 G19

19098 G20

19098 G21

Current Sense Threshold

vs I_THVoltage

I_THVoltage vs Load Current

Current Limit Foldback

300

200

100

0

150

125

2.5

2.0

1.5

1.0

0.5

0

V

RNG

= 2V

FIGURE 1 CIRCUIT

1.4V

1V

100

75

0.7V

0.5V

CONTINUOUS

MODE

50

25

0

DISCONTINUOUS

MODE

–100

–200

0

1.0

I

1.5

2.0

2.5

3.0

0

0.2

0.4

(V)

0.6

0.8

0.5

0

5

10

LOAD CURRENT (A)

15

VOLTAGE (V)

V

TH

FB

19098 G23

1778 G09

19098 G22

19098f

5

LTC1909-8

TYPICAL PERFOR A CE CHARACTERISTICS

U W

Maximum Current Sense

Threshold vs V_RNGVoltage

Maximum Current Sense

Threshold vs Temperature

Feedback Reference Voltage

vs Temperature

150

140

130

120

110

100

300

250

200

150

100

50

0.82

0.81

0.80

0.79

V

RNG

= 1V

0

0.78

0.5

1.0

V

1.25

1.5

1.75

2.0

–50 –25

0

25

50

75 100 125

0.75

–50 –25

0

25

50

75 100 125

VOLTAGE (V)

TEMPERATURE (°C)

RNG

19098 G25

19098 G27

EXTV_CCSwitch Resistance

vs Temperature

Error Amplifier g_mvs Temperature

FCB Pin Current vs Temperature

2.0

1.8

1.6

1.4

1.2

1.0

10

8

0

–0.25

–0.50

–0.75

6

4

–1.00

–1.25

–1.50

2

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75

100 125

TEMPERATURE (°C)

19098 G28

19098 G29

19098 G30

RUN/SS Pin Current

vs Temperature

RUN/SS Latchoff Thresholds

vs Temperature

Undervoltage Lockout Threshold

vs Temperature

3

2

5.0

4.5

4.0

3.5

4.0

3.5

3.0

2.5

PULL-DOWN CURRENT

LATCHOFF ENABLE

1

0

PULL-UP CURRENT

–1

LATCHOFF THRESHOLD

3.0

–2

2.0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

TEMPERATURE (C)

TEMPERATURE (°C)

19098 G32

19098 G31

19098 G33

19098f

6

LTC1909-8

U W

TYPICAL PERFOR A CE CHARACTERISTICS

(SMBus VID Programmer)

Resistance Between V_OSENSEand

FB Pins vs Temperature

V_CCSupply Current

vs Supply Voltage

V_CCSupply Current

vs Temperature

350

300

250

200

150

100

50

300

250

200

150

100

50

20.08

20.06

20.04

20.02

20.00

19.98

19.96

19.94

19.92

19.90

19.88

T

= 25°C

V

CC

= 2.7V TO 5.5V

A

V

= 5.5V

= 2.7V

CC

V

0

1.5

2

2.5

3

3.5

4

4.5

(V)

5

5.5

6

6.5

7

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

V

TEMPERATURE (°C)

CC

19098 G01

19098 G02

19098 G03

SCL, SDA, SEL and VRON Input

High and Low Voltage

vs Temperature

SCL, SDA, SEL and VRON Input

High and Low Voltage

vs Supply Voltage

SCL, SDA, SEL and VRON

Hysteresis vs Temperature

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

T

A

= 25°C

INPUT HIGH, V = 5.5V

CC

V

= 5.5V

= 2.7V

CC

INPUT HIGH

INPUT LOW

INPUT LOW, V = 5.5V

CC

INPUT HIGH, V = 2.7V

CC

INPUT LOW, V = 2.7V

CC

–55 –35 –15

5

25 45 65 85 105 125

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

19098 G04

19098 G05

19098 G06

SCL, SDA, SEL and VRON

Hysteresis vs Supply Voltage

SDA, CPUON, PGTMR Output Low

Voltage vs Temperature

SCL, SDA, SEL Input Current

vs Temperature

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

0.25

0.20

0.15

0.10

0.05

0

15

14

13

12

11

10

9

8

7

6

5

V

= 5.5V

I

= 3mA

T

= 25°C

CC

A

V

= 2.7V

CC

SCL PIN

V

= 5.5V

CC

4

3

2

1

SEL PIN

SDA PIN

0

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

19098 G07

19098 G08

19098 G09

19098f

7

LTC1909-8

TYPICAL PERFOR A CE CHARACTERISTICS

U W

(SMBus VID Programmer)

SDA, PGTMR, CPUON Sink

Current vs Temperature

PGTMR, CPUON Leakage Current

vs Temperature

VRON Pull-Up Current

vs Temperature

7

6

5

4

3

2

1

0

2.50

2.45

2.40

2.35

2.30

2.25

2.20

2.15

2.10

2.05

2.00

1.95

1.90

80

70

60

50

40

30

20

10

0

V

= 5.5V

V

= 5.5V, I

SK2

CC

V

CC

= 5.5V

V

= 2.7V, I

CC

SK1

V

CC

= 2.7V

–60 –40 –20

0

20 40 60 80 100 120

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

19098 G11

19098 G12

19098 G10

VRON Pull-Up Current

vs Supply Voltage

Power Good Timer Low Duration

vs Temperature

Resistor Divider Error

vs Temperature

52.0

51.5

51.0

50.5

50.0

49.5

49.0

3.0

2.5

2.0

1.5

1.0

0.5

0

0.25

0.20

0.15

0.10

0.05

0

T

= 25°C

RON

V

CC

= 2.7V (MINIMUM V )

CC

A

V

= 0V

V

= 5.5V

= 2.7V

CC

CODE 15

CODE 31

CODE 0

V

CODE 16

–0.05

–0.10

–0.15

–0.20

–60 –40 –20

0

20 40 60 80 100 120

1.5

2.5

3.5

4.5

5.5

6.5

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

19098 G14

19098 G013

19098 G15

19098f

8

LTC1909-8

U

PI FU CTIO S

RUN/SS (Pin 1): Run Control and Soft-Start Input. A

capacitor to ground at this pin sets the ramp time to full

output current (approximately 3s/µF) and the time delay

for overcurrent latchoff (see Applications Information).

Forcing this pin below 0.8V shuts down the device.

SEL (Pin 10): Register Select Input. A TTL compatible

logic input pin that is used to select 1 of 2 resistor divider

settings. SEL selects the setting in Register 0 if pulled low

and the setting in Register 1 if pulled high.

SDA (Pin 11): SMBus Data Input/Output. SDA is a high

impedance input when address, command or data bits are

shifted into the SMBus interface. It is an open-drain

N-channel output when acknowledging or sending data

back to the microprocessor during read back. It requires

a pull-up resistor or current source to V_CC.

V

_ON(Pin 2): On-Time Voltage Input. Voltage trip point for

the on-time comparator. Tying this pin to the output

voltage makes the on-time proportional to V_OUT. The

comparatorinputdefaultsto0.7Vwhenthepinisgrounded

and 2.4V when the pin is tied to INTV_CC.

PGOOD (Pin 3): Power Good Output. Open-drain logic

output that is pulled to ground when the output voltage is

not within ±7.5% of the regulation point.

SCL (Pin 12): SMBus Clock Input. Data at the SDA pin is

latched into the LTC1909-8 SMBus interface at the rising

edge of the clock and is shifted out of the SDA pin at the

falling edge of the clock. SCL is a high impedance input

pin. It is driven by the open collector output of a micropro-

cessor and requires a pull-up resistor or current source to

V_CC.

V_RNG(Pin 4): Sense Voltage Range Input. The voltage at

this pin is ten times the nominal sense voltage at maxi-

mum output current and can be set from 0.5V to 2V by a

resistive divider from INTV_CC. The nominal sense voltage

defaults to 70mV when this pin is tied to ground, 140mV

when tied to INTV_CC.

VRON (Pin 13): Global Control Input. This TTL compatible

input pin is pulled up internally by a 2.5µA current source.

Pulling VRON low forces the open-drain output pins

(CPUON and PGTMR) to pull to ground. If the LTC1909-8

is programmed to turn on a DC/DC converter, pulling

VRON high three-states the CPUON pin and allows the

switching regulator to soft-start if CPUON is tied to the

RUN/SS pin.

FCB (Pin 5): Forced Continuous Input. Tie this pin to

ground to force continuous synchronous operation at low

load, to INTV_CCto enable discontinuous mode operation

atlowloadortoaresistivedividerfromasecondaryoutput

when using a secondary winding.

I_TH(Pin 6): Current Control Threshold and Error Amplifier

Compensation Point. The current comparator threshold

increases with this control voltage. The voltage ranges

from 0V to 2.4V with 0.8V corresponding to zero sense

voltage (zero current).

PGTMR (Pin 14): Power Good Timer Output. This open-

drain outputispulledlow for50µs each time the switching

regulator is turned on or SEL is toggled to select a new

code.PGTMRmaybeconnectedtotheFCBpintoforcethe

converter into continuous mode operation. This reduces

thetimeneededfortheconverteroutputtosettletoalower

output voltage under light load conditions if the SEL pin is

toggled to select a lower output voltage.

SGND (Pin 7): Signal Ground. All small-signal compo-

nents and compensation components should connect to

this ground, which in turn connects to PGND at one point.

I_ON(Pin 8): On-Time Current Input. Tie a resistor from V_IN

tothispintosettheone-shottimercurrentandtherebyset

the switching frequency.

CPUON (Pin 15): CPU DC/DC Converter Control. Open-

drainoutput, usuallyconnectedtotheRUN/SSpin. Itpulls

low to shut down the converter or becomes high imped-

ance to allow the converter to soft-start.

V_FB(Pin 9): Error Amplifier Feedback Input. This pin

connectstotheerroramplifierinputtothecentertapofthe

SMBus programmable divider at the FB pin (Pin 17).

V_OSENSE(Pin 16): Sense Input. Upper terminal of the

SMBus programmable resistor divider that is connected

directly to the regulated output voltage node.

19098f

9

LTC1909-8

U

PI FU CTIO S

FB (Pin 17): Feedback Input. Center tap of the SMBus

programmable divider that is connected to Pin 9.

BG (Pin 23): Bottom Gate Drive. Drives the gate of the

bottom N-channel MOSFET between ground and INTV_CC.

GND (Pin 18): SMBus Programmer Ground. Connect to

PGND (Pin 24): Power Ground. Connect this pin closely to

the source of the bottom N-channel MOSFET, the (–)

terminal of C_VCCand the (–) terminal of C_IN.

SENSE⁺(Pin 25): Current Sense Comparator Input. The

(+) input to the current comparator is normally connected

to the SW pin unless using a sense resistor (see Applica-

tions Information).

regulator signal ground at Pin 7.

V

_CC(Pin 19): Positive Supply of the SMBus VID Program-

mer. 2.7V ≤ V_CC≤ 5.5V. May be connected to the INTV_CC

pin. Bypass this pin to ground with a 0.1µF ceramic

capacitor if using an external supply.

EXTV_CC(Pin 20): External V_CCInput. When EXTV_CCex-

ceeds 4.7V, an internal switch connects this pin to INTV_CC

and shuts down the internal regulator so that controller

andgatedrivepowerisdrawnfromEXTV_CC.Donotexceed

7V at this pin and ensure that EXTV_CC< V_IN.

SW (Pin 26): Switch Node. The (–) terminal of the boot-

strap capacitor C_Bconnects here. This pin swings from a

diode voltage drop below ground up to V_IN.

TG (Pin 27): Top Gate Drive. Drives the top N-channel

MOSFET with a voltage swing equal to INTV_CCsuperim-

posed on the switch node voltage SW.

V_IN(Pin 21): Main Input Supply. Decouple this pin to

PGND with an RC filter (1Ω, 0.1µF).

INTV_CC(Pin 22): Internal 5V Regulator Output. The driver

and control circuits are powered from this voltage. De-

couple this pin to power ground with a minimum of 4.7µF

low ESR tantalum or other low ESR capacitor. The internal

5V regulator is shut down when V_RUN/SS<1.5V.

BOOST (Pin 28): Boosted Floating Driver Supply. The (+)

terminal of the bootstrap capacitor C_Bconnects here. This

pin swings from a diode voltage drop below INTV_CCup to

V_IN+ INTV_CC.

TEST CIRCUIT

SMBus VID Programmer Test Circuit

5V

0.1µF

S1

S2

10k

V

CC

CPUON OR

PGTMR

100pF

SCL

SDA

SCL

SDA

SEL

0.8V

+

–

SEL

VRON

GND

FB

V

OSENSE

19098 TC

19098f

10

LTC1909-8

U

W

FU CTIO AL DIAGRA

R

ON

PGTMR* 14

V

IN

V

IN

2

V

8

I

5

FCB

20 EXTV

CC

21

ON

4.7V

+

SMBON*

DCON*

50µs

TIMER*

C

IN

0.7V

2.4V

1µA

+

–

0.8V

REF

1

0.8V

5V

REG

+

–

F

OST

BOOST

28

V

VON

I

ION

t

ON

=

(10pF)

R

C

B

TG

27

S

Q

I

FCNT

M1

SW

26

ON

20k

+

–

+

–

+

SENSE

25

L1

SWITCH

LOGIC

I

V

CMP

REV

D

B

OUT

+

C

OUT

INTV

CC

V

*

OSENSE

22

SHDN

OV

16

C

1.4V

RNG

VCC

BG

23

M2

V

R

*

FB1

PGND

24

4

×

V

FB*

17

FB

PGOOD

3

9

0.7V

R

FB2

SGND GND*

18

3.3µA

7

V *

CC

SEL*

POR*

19

1

+

–

10

0.76V

240k

+

–

1V

Q2 Q4

UV

OV

1.3V

Q6

I

THB

REGISTER 0*

Q3

Q1

10:5

MUX*

+

–

SCL*

12

Q5

REGISTER 1*

DCON*

+

–

0.84V

0.8V

SMBus

INTERFACE*

RUN

SHDN

*

SDA*

11

SS

SMBON*

–

+

*

ON/OFF

STATE

MACHINE*

1.2µA

*

EA

×4

–

+

6V

0.6V

V

CC

*

C

SS

C1

I

TH

RUN/SS

CPUON*

15

6

1

0.8V

0.6V

VRON*

R

C

+

–

13

1.3V

19098 FD

*PART OF THE SMBus VID PROGRAMMER

19098f

11

LTC1909-8

W U

W

TI I G DIAGRA S

A C K

D C O N

V I D 0

V I D 1

V I D 2

V I D 3

V I D 4

A C K

D C O N

V I D 0

V I D 1

V I D 2

V I D 3

V I D 4

A C K

V I D 1

V I D 2

V I D 3

V I D 4

A C K

R / W

V I D 0

V I D 1

V I D 2

V I D 3

V I D 4

A C K

C 5

C 6

C 5

C 6

C 7

A C K

R / W

A C K

R / W

19098f

12

LTC1909-8

W U

W

TI I G DIAGRA S

Timing for SMBus Interface

t

BUF

SDA

SCL

t

HD:STA

t

f

r

t

LOW

t

HIGH

SU:STO

SU:STA

19098 TD02

t

SU:DAT

HD:DAT

STOP

START

STOP

VRON, SEL, CPUON and PGTMR Timing

P

SCL

SDA

2nd ON

PROTOCOL

2nd OFF

PROTOCOL

STOP

SMBON 1.3V

DCON 1.3V

SEL 1.3V

t

PH

t

VL

t

SPL

PL

CPU_ON 1.3V

t

PGL

PPL

t

VH

PGTMR

0.7V

t

PGL

t

VPL

VRON

t

SSH

SSL

V

MAX

MIN

0V

90%

V

REF

OSENSE

= 0.8V)

10%

(V

0V

NOTE: TIMING RELATIVE TO THE STOP BIT (P) IS MEASURED FROM THE RISING EDGE OF SDA

SEE TABLE 1 FOR V AND V SENSE VOLTAGES

19098 TD03

MIN

MAX

19098f

13

LTC1909-8

U

OPERATIO

(Refer to Functional Diagram)

The LTC1909-8 consists of two independent sections: a

current mode controller for the DC/DC step-down con-

verter and a SMBus VID voltage programmer. It simplifies

the design of SMBus controlled power supplies.

M2isturnedonandheldonuntiltheovervoltagecondition

clears.

Foldback current limiting is provided if the output is

shorted to ground. As V_FBdrops, the buffered current

threshold voltage I_THBis pulled down by clamp Q3 to a 1V

level set by Q4 and Q6. This reduces the inductor valley

current level to one sixth of its maximum value as V_FB

approaches 0V.

Current Mode Controller

In normal operation, the top MOSFET of the current mode

controller is turned on for a fixed interval determined by a

one-shot timer OST. When the top MOSFET is turned off,

the bottom MOSFET is turned on until the current com-

parator I_CMPtrips, restarting the one-shot timer and initi-

ating the next cycle. Inductor current is determined by

sensing the voltage between the PGND and SENSE⁺pins

using either the bottom MOSFET on-resistance or a sepa-

rate sense resistor. The voltage on the I_THpin sets the

comparator threshold corresponding to inductor valley

current. The error amplifier EA adjusts this voltage by

comparingthefeedbacksignalV_FBfromtheoutputvoltage

with an internal 0.8V reference. The feedback voltage is

derived from theoutputvoltageby aresistivedividerin the

SMBus VID programmer. If the load current increases, it

causes a drop in the feedback voltage relative to the

reference. The I_THvoltage then rises until the average

inductor current again matches the load current.

Pulling the RUN/SS pin low forces the controller into its

shutdown state, turning off both M1 and M2. Releasing

the pin allows an internal 1.2µA current source to charge

up an external soft-start capacitor C_SS. When this voltage

reaches 1.5V, the controller turns on and begins switch-

ing, but with the I_THvoltage clamped at approximately

0.6V below the RUN/SS voltage. As C_SScontinues to

charge, the soft-start current limit is removed. Shorting

the RUN/SS pin to the CPUON pin of the SMBus VID

programmer puts the regulator under software control.

The open-drain CPUON pin does not interfere with the

soft-start cycle.

INTV_CC/EXTV_CCPower

Power for the top and bottom MOSFET drivers and most

of the internal controller circuitry is derived from the

INTV_CCpin. The top MOSFET driver is powered from a

floating bootstrap capacitor C_B. This capacitor is re-

charged from INTV_CCthrough an external Schottky diode

D_Bwhen the top MOSFET is turned off. When the EXTV_CC

pin is grounded and V_RUN/SS>1.5V, an internal 5V low

dropout regulator supplies the INTV_CCpower from V_IN. If

EXTV_CCrises above 4.7V, the internal regulator is turned

off, and an internal switch connects EXTV_CCto INTV_CC.

This allows a high efficiency source connected to EXTV_CC,

such as an external 5V supply or a secondary output from

theconverter, toprovidetheINTV_CCpower. Voltagesupto

7VcanbeappliedtoEXTV_CCforadditionalgatedrive. Ifthe

input voltage is low and INTV_CCdrops below 3.5V,

undervoltagelockoutcircuitrypreventsthepowerswitches

from turning on.

At low load currents, the inductor current can drop to zero

and become negative. This is detected by current reversal

comparator I_REVwhich then shuts off M2, resulting in

discontinuous operation. Both switches will remain off

with the output capacitor supplying the load current until

the I_THvoltage rises above the zero current level (0.8V) to

initiate another cycle. Discontinuous mode operation is

disabled by comparator F when the FCB pin is brought

below 0.8V, forcing continuous synchronous operation.

The operating frequency is determined implicitly by the

top MOSFET on-time and the duty cycle required to

maintain regulation. The one-shot timer generates an on-

time that is proportional to the ideal duty cycle, thus

holding frequency approximately constant with changes

in V_IN. The nominal frequency can be adjusted with an

external resistor R_ON.

SMBus VID Voltage Programmer

Overvoltage and undervoltage comparators OV and UV

pull the PGOOD output low if the output feedback voltage

exits a ±7.5% window around the regulation point. Fur-

thermore,inanovervoltagecondition,M1isturnedoffand

The SMBus interface is used to program the divider (to set

the output voltage of the DC/DC converter) and to shut

down the current mode controller or allow it to soft-start.

19098f

14

LTC1909-8

U

OPERATIO

(Refer to Functional Diagram)

has a trip point of 1.3V with ±50mV of hysteresis. It is TTL

compatible and has a 2.5µA pull-up to V_CC. Pulling VRON

low will force CPUON low immediately, regardless of the

On/Off state machine. Pulling VRON high or allowing it to

float high hands control to the On/Off state machine.

Table 1 summarizes the function of the control pins. The

SMBON control bit is explained in the next section.

It uses two pins, SCL and SDA to communicate with a

master device through the Read Word and Write Word

protocols. The V_ILand V_IHlogic threshold voltages of the

SDA and SCL pins are 0.8V and 2.1V respectively, which

comply with Rev 1.1 version of the Intel System Manage-

ment Bus Specifications. Both pins require a resistor or

active pull-up (see the LTC1694 data sheet) to V_CC. Data is

clocked out of the SDA pin at the falling edge and latched

in at the rising edge of the SCL clock signal. The slave

address of the interface for both Read and Write protocols

is fixed at E2H.

Table 1. DC/DC Converter Control Pins

VRON

SMBON

DCON

PGTMR

CPUON

0

1

X

0

↑

1

↓

0

0 for 50µs

(Note 1)

Z (Note 2)

There are three types of Write Word protocols: Setup, On

and Off and one Read Word protocol called Read-Back.

The Setup Write Word protocol is used to set up two

internal 5-bit registers (Register 0 and Register 1) with

alternate resistor divider DAC settings. The On and Off

Write Word protocols do not modify register contents but

are used to shutdown the converter or to allow it to soft-

start. The Read Word protocol is used to verify the

contents of the registers as well as to check whether the

converter is operating or in shutdown from a status bit

(DCON). Table 3 in the Applications Information section

shows the data bits that identify each protocol as Setup,

On, Off or Read-Back.

↑

1

↓

0 for 50µs

Z (Note 2)

(Note 1)

Note 1: Also triggered by SEL pin toggling.

Note 2: Z = High Impedance

The LTC1909-8 provides safeguards against incorrect di-

vidercodesandtheunintentionalturn-onorturn-offofthe

DC/DC converter. Incorrect codes due to bus conflicts

duringSetupprotocolscancausedamagetocircuitspow-

ered by the DC/DC converter. The safeguards built into the

LTC1909-8 include Read-Back, repeated On and Off pro-

tocols, ignoringOnprotocolsiftheregistershavenotbeen

set up (since power-up), locking out registers while the

DC/DC converters are operating and latching in VID codes

only in Setup protocols.

Controller Control

The VID programmer provides the VRON and CPUON pins

forthepurposeofshuttingdownorallowingtheconverter

to soft-start. CPUON is an open-drain, N-channel output

pinthatisnormallytiedtotheRUN/SSpinofthecontroller

alongwithitssoft-startcapacitor.IftheN-channelisturned

off,thepinentersahighimpedancestateandthecapacitor

is allowed to charge up and soft-start the converter. When

shutting down the converter, the N-channel FET at the

CPUON pin will typically discharge a 0.1µF soft-start ca-

pacitor from 3V to 0.35V in 21µs with V_CC= 2.7V. On

power-up, the power-on reset (POR) circuit in the SMBus

VID programmer turns on the N-channel to shut down the

converter. The CPUON pin can also be controlled to clear

overcurrent faults in the switching regulator (see Soft-

Start and Latchoff with the RUN/SS Pin section).

After power-up, the microprocessor must set up the reg-

istersbeforetheLTC1909-8recognizesOnprotocols.This

requirementensuresthatthecorrectDC/DCconverterout-

put is programmed before the converters are turned on.

After setup, Read-Back allows the contents of Registers 0

and 1 to be verified in case the VID codes were corrupted

by noise or bus conflicts.

In order to turn on the DC/DC converter, two On protocols

mustbesenttoslaveaddressE2Hwithoutanyother(E2H)

protocols in between. Protocols to other slave addresses

are still allowed and are ignored. Similarly, two Off proto-

colsmustbesenttoslaveaddressE2Htoturntheconvert-

ers off. The On and Off protocols are monitored by an

internal state machine. The output of the state machine,

SMBON, is high after two On commands and low after two

Off commands. Repeated On and Off protocols reduce the

The CPUON pin is under the control of an internal On/Off

state machine that is accessed using the SMBus On/Off

Write Word protocols and the VRON pin. The VRON pin chances of bus conflicts and noise turning the converter

19098f

15

LTC1909-8

U

OPERATIO

(Refer to Functional Diagram)

Table 2. DC/DC Converter Output Voltage

VID0 OUTPUT VOLTAGE

on or off accidentally. In both On and Off protocols, the

LTC1909-8 does not latch in the Data Low and Data High

bytes. This protects the settings that have already been

loaded into the registers and verified by read-back. Once

the converter is turned on (both SMBON and VRON are

high) the contents of Registers 0 and 1 are protected and

can only be altered with Setup protocols if VRON is pulled

low or two Off protocols are sent to the LTC1909-8 (to

force SMBON low). During Read-Back, the microproces-

sorcanchecktheOnorOffstateofthecontrollerbytesting

the DCON status bit that follows each 5-bit code. This bit

is low only when both SMBON and VRON are high.

VID4

0

1

VID3

0

1

0

1

VID2

0

1

0

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.05V

2.00V

1.95V

1.90V

1.85V

1.80V

1.75V

1.70V

1.65V

1.60V

1.55V

1.50V

1.45V

1.40V

1.35V

1.30V

3.50V

3.40V

3.30V

3.20V

3.10V

3.00V

2.90V

2.80V

2.70V

2.60V

2.50V

2.40V

2.30V

2.20V

2.10V

2.00V

Resistor Divider

TheresistordividersettingscomplywiththeIntelDesktop

VRM8.4 VID Specifications. The divider consists of a fixed

20k(typical)resistor,R_FB1,connectedbetweentheV_OSENSE

and FB pins and a variable resistor, R_FB2, from FB to GND.

The FB pin is connected to the V_FBpin of the step-down

controller to set the output voltage of the converter. Each

resistor has a tolerance of ±30% but the divider ratio is

accurate to ±0.35%. The error budget for the DC/DC con-

verter output voltage must include the ±0.35% ratio toler-

ance and the ±1% tolerance in the 0.8V reference. The

output of the DC/DC converter is given by:

V

_OUT= V_REF• (R_FB2+ R_FB1)/R_FB2

where V_REF= 0.8V is the internal reference voltage of the

converter. Table 2shows the 32 possibleconverteroutput

voltages. The microprocessor controls the SEL pin to se-

lectthecontentsofoneoftheregistersastheactivedivider

setting. The SEL pin has a trip point of 1.3V with ±50mV

of hysteresis and is TTL compatible. It controls an internal

10:5digitalmultiplexerandselectsthecontentsofregister

0 when pulled low and register 1 when pulled high. When

SEL is toggled, and the new converter output is lower or

greater by 7.5%, the overvoltage and undervoltage com-

parators of the controller may trip causing the PGOOD pin

of the controller to go low. This condition will recover

automatically as the converter charges up the output or

allows the output to drop to the new voltage setting.

is in shutdown or on power-up. When the converter is

turned on, an internal timer keeps PGTMR low for 50µs

(typical)whichallowstimefortheconverterstoenterregu-

lation. Toggling the SEL pin while the converter is turned

on also causes the PGTMR pin to pull low for 50µs.

Power Good Timer

The PGTMR pin may be used to force continuous opera-

tion in the DC/DC converter. If the SEL pin is toggled to

The PGTMR or “Power Good Timer” pin is also an open-

drain,N-channeloutput.ItpullslowiftheDC/DCconverter

select a lower output voltage, if may take an unacceptably

19098f

16

LTC1909-8

U

OPERATIO

(Refer to Functional Diagram)

long time for the output of the DC/DC converter to de-

crease to the new voltage under light load conditions. To

reduce this time needed, the PGTMR pin can be connected

to the FCB (force continuous bar) pin of the converter.

When the SEL pin is toggled to select a new code, the FCB

pinisforcedlowfor50µs.ThisforcestheDC/DCconverter

out of Burst Mode^TMoperation and into continuous mode.

The PGTMR pin may be tied to the same pull-up resistor

as the PGOOD pin.

the V_CCpin can be tied to the same supply or to the INTV_CC

pin since the INTV_CCpin is connected to the EXTV_CCpin by

an internal switch when V_EXTVCC>4.7V. The EXTV_CCand

V

_CCvoltages should be kept below the absolute maximum

rating of 7V.

Power-Up Reset

On power-up, the internal POR circuit generates a low

reset pulse, which stays low until V_CCrises above approxi-

mately 2.2V. The reset pulse forces the SMBus interface

into an idle state in which it listens for a start bit. At the

same time the outputs of both Register 0 and Register 1

are set to 11111B. The DCON bit is pulled high so that the

CPUON pin is pulled low to shut down the DC/DC con-

verter. PGTMR is also pulled low as the converter is shut

down and therefore not in regulation.

SMBus Controller Supply

If the EXTV_CCpin is tied to ground, the V_CCpin of the

SMBus controller should be tied to an external 5V supply.

It should not be tied to the INTV_CCpin because the internal

5V regulator at the INTV_CCpin is shut down while V_RUN/SS

is below 1.5V and the SMBus controller will not be pow-

ered up. If the EXTV_CCpin is tied to an external 5V supply,

Burst Mode is a trademark of Linear Technology Corporation.

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The basic LTC1909-8 application circuit is shown in

Figure 1. External component selection is primarily deter-

mined by the maximum load current and begins with the

selection of the sense resistance and power MOSFET

switches. The LTC1909-8 uses either an external sense

resistor or the on-resistance of the synchronous power

MOSFETfordeterminingtheinductorcurrent. Thedesired

amount of ripple current and operating frequency largely

determines the inductor value. Finally, C_INis selected for

its ability to handle the large RMS current into the con-

verter and C_OUTis chosen with low enough ESR to meet

the output voltage ripple and transient specification.

V_RNG

10 •I_OUT(MAX)

R_SENSE

=

An external resistive divider from INTV_CCcan be used to

set the voltage of the V_RNGpin between 0.5V and 2V

resulting in nominal sense voltages of 50mV to 200mV.

Additionally, the V_RNGpin can be tied to SGND or INTV_CC

in which case the nominal sense voltage defaults to 70mV

or 140mV, respectively. The maximum allowed sense

voltage is about 1.33 times this nominal value.

Connecting the SENSE⁺Pin

The LTC1909-8 can be used with or without a sense

resistor. When using a sense resistor, it is placed between

the source of the bottom MOSFET M2 and ground. Con-

nect the SENSE⁺pin to the source of the bottom MOSFET

so that the resistor appears between the SENSE⁺and

PGND pins. Using a sense resistor provides a well defined

current limit, but adds cost and reduces efficiency. Alter-

natively, one can eliminate the sense resistor and use the

bottom MOSFET as the current sense element by simply

connecting the SENSE⁺pin to the switch node SW at the

drainofthebottomMOSFET.Thisimprovesefficiency,but

Maximum Sense Voltage and V_RNGPin

Inductor current is determined by measuring the voltage

across a sense resistance that appears between the PGND

and SENSE⁺pins. The maximum sense voltage is set by

the voltage applied to the V_RNGpin and is equal to

approximately (0.133) • V_RNG. The current mode control

loop will not allow the inductor current valleys to exceed

(0.133)•V_RNG/R_SENSE.Inpractice,oneshouldallowsome

margin for variations in the LTC1909-8 and external com-

ponent values and a good guide for selecting the sense

resistance is:

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one must carefully choose the MOSFET on-resistance as

The power dissipated by the top and bottom MOSFETs

strongly depends upon their respective duty cycles and

the load current. When the LTC1909-8 is operating in

continuous mode, the duty cycles for the MOSFETs are:

discussed below.

Power MOSFET Selection

The LTC1909-8 requires two external N-channel power

MOSFETs, one for the top (main) switch and one for the

bottom (synchronous) switch. Important parameters for

V_OUT

D_TOP

D_BOT

=

V

IN

V – V_OUT

the power MOSFETs are the breakdown voltage V_(BR)DSS

threshold voltage V_(GS)TH, on-resistance R_DS(ON), reverse

transfercapacitanceC_RSSandmaximumcurrentI_DS(MAX)

,

IN

V

IN

.

The resulting power dissipation in the MOSFETs at maxi-

mum output current are:

The gate drive voltage is set by the 5V INTV_CCsupply.

Consequently, logic-level threshold MOSFETs must be

used in LTC1909-8 applications. If the input voltage is

expected to drop below 5V, then sub-logic level threshold

MOSFETs should be considered.

P

_TOP= D_TOPI_OUT(MAX)

²ρ_T(TOP)R_DS(ON)(MAX)

2

+ k V_INI_OUT(MAX)C_RSS

f

P_BOT= D_{BOT OUT(MAX)}

I

²ρ_T(BOT)R_DS(ON)(MAX)

When the bottom MOSFET is used as the current sense

element, particular attention must be paid to its on-

resistance. MOSFET on-resistance is typically specified

with a maximum value R_DS(ON)(MAX)at 25°C. In this case,

additional margin is required to accommodate the rise in

MOSFET on-resistance with temperature:

Both MOSFETs have I²R losses and the top MOSFET

includesanadditionaltermfortransitionlosses,whichare

largest at high input voltages. The constant K = 1.7A^–1can

be used to estimate the amount of transition loss. The

bottomMOSFETlossesaregreatestwhenthebottomduty

cycle is near 100%, during a short-circuit or at high input

voltage.

R_SENSE

R_DS(ON)(MAX)

=

ρ_T

Operating Frequency

The ρ_Tterm is a normalization factor (unity at 25°C)

accounting for the significant variation in on-resistance

with temperature, typically about 0.4%/°C as shown in

Figure 2. For a maximum temperature of 100°C, using a

value ρ_T= 1.3 is reasonable.

The choice of operating frequency is a tradeoff between

efficiency and component size. Low frequency operation

improvesefficiencybyreducingMOSFETswitchinglosses

but requires larger inductance and/or capacitance in order

to maintain low output ripple voltage.

2.0

1.5

1.0

0.5

0

The operating frequency of LTC1909-8 applications is

determined implicitly by the one-shot timer that controls

the on-time t_ONof the top MOSFET switch. The on-time is

set by the current into the I_ONpin according to:

V

t_ON

=

^VON(10pF)

I

ION

Tying a resistor R_ONfrom V_INto the I_ONpin yields an on-

time inversely proportional to V_IN. For a step-down

converter, this results in approximately constant fre-

quency operation as the input supply varies:

50

100

–50

150

0

JUNCTION TEMPERATURE (°C)

19098 F02

Figure 2. R_DS(ON)vs. Temperature

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Inductor Selection

V_OUT

V_VONR_ON(10pF)

f =

Hz

[ ]

Given the desired input and output voltages, the inductor

value and operating frequency determine the ripple

current:

Toholdfrequencyconstantduringoutputvoltagechanges,

tie the V_ONpin to V_OUT. The V_ONpin has internal clamps

that limit its input to the one-shot timer. If the pin is tied

below 0.7V, the input to the one-shot is clamped at 0.7V.

Similarly, if the pin is tied above 2.4V, the input is clamped

at 2.4V.

V_OUT

fL

V_OUT

V

IN

∆I_L=

1−

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors and output voltage

ripple. Highest efficiency operation is obtained at low

frequency with small ripple current. However, achieving

this requires a large inductor. There is a tradeoff between

component size, efficiency and operating frequency.

Because the voltage at the I_ONpin is about 0.7V, the

currentintothispinisnotexactlyinverselyproportionalto

V_IN, especially in applications with lower input voltages.

To correct for this error, an additional resistor R_ON2

connected from the I_ONpin to the 5V INTV_CCsupply will

further stabilize the frequency.

A reasonable starting point is to choose a ripple current

that is about 40% of I_OUT(MAX). The largest ripple current

occurs at the highest V_IN. To guarantee that ripple current

does not exceed a specified maximum, the inductance

should be chosen according to:

5V

0.7V

R_ON2

=

R_ON

Changes in the load current magnitude will also cause

frequency shift. Parasitic resistance in the MOSFET

switches and inductor reduce the effective voltage across

the inductance, resulting in increased duty cycle as the

loadcurrentincreases.Bylengtheningtheon-timeslightly

as current increases, constant frequency operation can be

maintained. This is accomplished with a resistive divider

from the I_THpin to the V_ONpin and V_OUT. The values

required will depend on the parasitic resistances in the

specific application. A good starting point is to feed about

25% of the voltage change at the I_THpin to the V_ONpin as

shown in Figure 3a. Place capacitance on the V_ONpin to

filter out the I_THvariations at the switching frequency. The

resistor load on I_THreduces the DC gain of the error amp

and degrades load regulation, which can be avoided by

using the PNP emitter follower of Figure 3b.

V_OUT

f∆I_L(MAX)

V_OUT

V

IN(MAX)

L =

1−

Once the value for L is known, the type of inductor must be

selected. High efficiency converters generally cannot af-

ford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite, molypermalloy

orKoolMµ^®cores.Avarietyofinductorsdesignedforhigh

current, lowvoltageapplicationsareavailablefrommanu-

facturers such as Sumida, Panasonic, Coiltronics, Coil-

craft and Toko.

Kool Mµ is a registered trademark of Magnetics, Inc.

R

VON1

30k

3k

V

OUT

V

ON

OUT

C

R

VON

VON2

0.01µF

10k

LTC1909-8

R

VON2

100k

INTV

CC

R

C

I

2N5087

TH

C

19098 F03

(3a)

(3b)

Figure 3. Correcting Frequency Shift with Load Current Changes

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Schottky Diode D1 Selection

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Special polymer capacitors offer very low ESR

but have lower capacitance density than other types.

Tantalum capacitors have the highest capacitance density

but it is important to only use types that have been surge

tested for use in switching power supplies. Aluminum

electrolytic capacitors have significantly higher ESR, but

can be used in cost-sensitive applications providing that

consideration is given to ripple current ratings and long

term reliability. Ceramic capacitors have excellent low

ESRcharacteristicsbutcanhaveahighvoltagecoefficient

and audible piezoelectric effects. The high Q of ceramic

capacitors with trace inductance can also lead to signifi-

cant ringing. When used as input capacitors, care must be

taken to ensure that ringing from inrush currents and

switching does not pose an overvoltage hazard to the

power switches and controller. To dampen input voltage

transients, add a small 5µF to 50µF aluminum electrolytic

capacitor with an ESR in the range of 0.5Ω to 2Ω. High

performance through-hole capacitors may also be used,

but an additional ceramic capacitor in parallel is recom-

mended to reduce the effect of their lead inductance.

The Schottky diode D1 shown in Figure 1 conducts during

the dead time between the conduction of the power

MOSFET switches. It is intended to prevent the body diode

ofthebottomMOSFETfromturningonandstoringcharge

during the dead time, which can cause a modest (about

1%) efficiency loss. The diode can be rated for about one

half to one fifth of the full load current since it is on for only

a fraction of the duty cycle. In order for the diode to be

effective,theinductancebetweenitandthebottomMOSFET

must be as small as possible, mandating that these

components be placed adjacently. The diode can be omit-

ted if the efficiency loss is tolerable.

C_INand C_OUTSelection

The input capacitance C_INis required to filter the square

wave current at the drain of the top MOSFET. Use a low

ESR capacitor sized to handle the maximum RMS current.

V_OUT

V

IN

V

IN

I_RMSI_OUT(MAX)

– 1

V_OUT

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT(MAX)/2. This simple worst-case condition is

commonly used for design because even significant de-

viations do not offer much relief. Note that ripple current

ratings from capacitor manufacturers are often based on

only 2000 hours of life which makes it advisable to derate

the capacitor.

Top MOSFET Driver Supply (C_B, D_B)

AnexternalbootstrapcapacitorC_BconnectedtotheBOOST

pinsuppliesthegatedrivevoltageforthetopsideMOSFET.

This capacitor is charged through diode D_Bfrom INTV_CC

when the switch node is low. When the top MOSFET turns

on, the switch node rises to V_INand the BOOST pin rises

to approximately V_IN+ INTV_CC. The boost capacitor needs

to store about 100 times the gate charge required by the

top MOSFET. In most applications a 0.1µF to 0.47µF X5R

or X7R dielectric capacitor is adequate.

The selection of C_OUTis primarily determined by the ESR

required to minimize voltage ripple and load step

transients. The output ripple ∆V_OUTis approximately

bounded by:

1

∆V_OUT≤ ∆I_LESR +

8fC_OUT

Discontinuous Mode Operation and FCB Pin

The FCB pin determines whether the bottom MOSFET

remains on when current reverses in the inductor. Tying

this pin above its 0.8V threshold enables discontinuous

operation where the bottom MOSFET turns off when

inductor current reverses. The load current at which

current reverses and discontinuous operation begins de-

Since ∆I_Lincreases with input voltage, the output ripple is

highestatmaximuminputvoltage.Typically,oncetheESR

requirement is satisfied, the capacitance is adequate for

filtering and has the necessary RMS current rating.

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

pends on the amplitude of the inductor ripple current and

will vary with changes in V_IN. Tying the FCB pin below the

19098f

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LTC1909-8

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APPLICATIO S I FOR ATIO

U

0.8Vthresholdforcescontinuoussynchronousoperation,

allowing current to reverse at light loads and maintaining

high frequency operation.

V

IN

+

C

V

IN

SEC

C

V

IN

1N4148

TG

•

OPTIONAL

EXTV

+

LTC1909-8

In addition to providing a logic input to force continuous

operation, the FCB pin provides a means to maintain a

flyback winding output when the primary is operating in

discontinuous mode. The secondary output V_SECis nor-

mally set as shown in Figure 4 by the turns ratio N of the

transformer. However, if the controller goes into discon-

tinuous mode and halts switching due to a light primary

load current, then V_SECwill droop. An external resistor

divider from V_SECto the FCB pin sets a minimum voltage

V_SEC(MIN)below which continuous operation is forced

until V_SEChas risen above its minimum.

SEC

CC

EXTV

SW

1µF

CC

CONNECTION

5V < V < 7V

V

OUT

R4

R3

•

SEC

T1

1:N

+

SENSE

C

OUT

FCB

BG

SGND

PGND

19098 F04

Figure 4. Secondary Output Loop and EXTV_CCConnection

reasonable assumption is that the minimum R_DS(ON)lies

the same amount below the typical value as the maximum

liesaboveit.ConsulttheMOSFETmanufacturerforfurther

guidelines.

R4

R3

V_SEC(MIN)= 0.8V 1+

To further limit current in the event of a short circuit to

ground,theLTC1909-8includesfoldbackcurrentlimiting.

If the output falls by more than 25%, then the maximum

sense voltage is progressively lowered to about one sixth

of its full value.

Fault Conditions: Current Limit and Foldback

The maximum inductor current is inherently limited in a

currentmodecontrollerbythemaximumsensevoltage.In

the LTC1909-8, the maximum sense voltage is controlled

by the voltage on the V_RNGpin. With valley current control,

the maximum sense voltage and the sense resistance

determine the maximum allowed inductor valley current.

The corresponding output current limit is:

Minimum Off-time and Dropout Operation

The minimum off-time t_OFF(MIN)is the smallest amount of

time that the LTC1909-8 is capable of turning on the

bottom MOSFET, tripping the current comparator and

turning the MOSFET back off. This time is generally about

300ns. The minimum off-time limit imposes a maximum

duty cycle of t_ON/(t_ON+ t_OFF(MIN)). If the maximum duty

cycle is reached, due to a dropping input voltage for

example, then the output will drop out of regulation. The

minimum input voltage to avoid dropout is:

V_SNS(MAX)

1

I_LIMIT

=

+ ∆I_L

2

R_DS(ON)ρ_T

The current limit value should be checked to ensure that

I_LIMIT(MIN)>I_OUT(MAX).Theminimumvalueofcurrentlimit

generally occurs with the largest V_INat the highest ambi-

ent temperature, conditions that cause the largest power

loss in the converter. Note that it is important to check for

self-consistency between the assumed MOSFET junction

temperature and the resulting value of I_LIMITwhich heats

the MOSFET switches.

t

_ON+ t_OFF(MIN)

V_IN(MIN)= V_OUT

t_ON

INTV_CCRegulator

An internal P-channel low dropout regulator produces the

5V supply that powers the drivers and internal circuitry

within the LTC1909-8. The INTV_CCpin can supply up to

50mA RMS and must be bypassed to ground with a

minimum of 4.7µF tantalum or other low ESR capacitor.

Good bypassing is necessary to supply the high transient

Caution should be used when setting the current limit

based upon the R_DS(ON)of the MOSFETs. The maximum

current limit is determined by the minimum MOSFET on-

resistance. Data sheets typically specify nominal and

maximum values for R_DS(ON), but not a minimum. A

19098f

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currents required by the MOSFET gate drivers. Applica-

tions using large MOSFETs with a high input voltage and

high frequency of operation may cause the LTC1909-8 to

exceed its maximum junction temperature rating or RMS

current rating. Most of the supply current drives the

MOSFET gates unless an external EXTV_CCsource is used.

LTC1693. Alternately, the external buffer circuit shown in

Figure 5 can be used. Note that the bipolar devices reduce

the signal swing at the MOSFET gate and benefit from an

increased EXTV_CCvoltage of about 6V.

BOOST

INTV

CC

Q1

FMMT619

Q3

FMMT619

In continuous mode operation, this current is I_GATECHG

=

f(Q_g(TOP)+ Q_g(BOT)). The junction temperature can be

estimated from the equations given in Note 2 of the

Electrical Characteristics. For example, the LTC1909-8 is

limited to less than 14mA from a 30V supply:

10Ω

GATE

OF M1

GATE

TG

BG

OF M2

Q2

Q4

FMMT720

SW

PGND

19098 F05

T_J= 70°C + (14mA)(30V)(130°C/W) = 125°C

Figure 5. Optional External Gate Driver

Forlargercurrents, considerusinganexternalsupplywith

the EXTV_CCpin.

Soft-Start and Latchoff with the RUN/SS Pin

The RUN/SS pin provides a means to shut down the

LTC1909-8aswellasatimerforsoft-startandovercurrent

latchoff. Pulling the RUN/SS pin below 0.8V puts the

LTC1909-8 into a low quiescent current shutdown

(I_Q< 30µA). Releasing the pin allows an internal 1.2µA

current source to charge up the external timing capacitor

C_SS.IfRUN/SShasbeenpulledallthewaytoground,there

is a delay before starting of about:

EXTV_CCConnection

TheEXTV_CCpin can beusedto provideMOSFET gate drive

and control power from the output or another external

source during normal operation. Whenever the EXTV_CC

pin is above 4.7V the internal 5V regulator is shut off and

an internal 50mA P-channel switch connects the EXTV_CC

pintoINTV_CC.INTV_CCpowerissuppliedfromEXTV_CCuntil

this pin drops below 4.5V. Do not apply more than 7V to

the EXTV_CCpin and ensure that EXTV_CC≤ V_IN. The follow-

ing list summarizes the possible connections for EXTV_CC:

1.5V

1.2µA

t_DELAY

=

C

_SS= 1.3s/µF C_SS

(

)

1. EXTV_CCgrounded. INTV_CCis always powered from the

internal 5V regulator.

WhenthevoltageonRUN/SSreaches1.5V,theLTC1909-8

begins operating with a clamp on I_THof approximately

0.9V. As the RUN/SS voltage rises to 3V, the clamp on I_TH

is raised until its full 2.4V range is available. This takes an

additional 1.3s/µF, during which the load current is folded

backuntiltheoutputreaches75%ofitsfinalvalue. Thepin

can be driven from logic (Figures 6a or 6b) or from the

CPUONpin(Figures6cand6d).DiodeD1reducesthestart

delay while allowing C_SSto charge up slowly for the soft-

start function.

2. EXTV_CCconnected to an external supply. A high effi-

ciency supply compatible with the MOSFET gate drive

requirements(typically5V)canimproveoverallefficiency.

3. EXTV_CCconnected to an output derived boost network.

The low voltage output can be boosted using a charge

pump or flyback winding to greater than 4.7V. The system

will start-up using the internal linear regulator until the

boosted output supply is available.

After the controller has been started and given adequate

time to charge up the output capacitor, C_SSis used as a

short-circuit timer. After the RUN/SS pin charges above

4V, if the output voltage falls below 75% of its regulated

value, then a short-circuit fault is assumed. A 1.8µA

current then begins discharging C_SS. If the fault condition

External Gate Drive Buffers

The LTC1909-8 drivers are adequate for driving up to

about 30nC into MOSFET switches with RMS currents of

50mA. ApplicationswithlargerMOSFETswitchesoroper-

ating at frequencies requiring greater RMS currents will

benefit from using external gate drive buffers such as the

persists until the RUN/SS pin drops to 3.5V, then the

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INTV

CC

shown in Figure 6a or 6c is simple, but slightly increases

shutdown current. Connecting a resistor to INTV_CCas

shown in Figure 6b and 6d eliminates the additional

shutdown current, but requires a diode to isolate C_SS. Any

pull-up network must be able to maintain RUN/SS above

the 4.2V maximum latchoff threshold and overcome the

4µA maximum discharge current.

R *

SS

V

IN

RUN/SS

3.3V OR 5V

RUN/SS

D2*

R *

SS

D1

C

SS

C

SS

*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF

(6a)

(6b)

Efficiency Considerations

INTV

CC

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Although all dissipative

elements in the circuit produce losses, four main sources

account for most of the losses in LTC1909-8 circuits:

V

IN

R

*

SS

RUN/SS

*

RUN/SS

R

SS

D2*

CPUON

C

SS

19098 F06

*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF

(6c)

(6d)

1. DC I²R losses. These arise from the resistances of the

MOSFETs, inductor and PC board traces and cause the

efficiency to drop at high output currents. In continuous

mode the average output current flows through L, but is

chopped between the top and bottom MOSFETs. If the two

MOSFETs have approximately the same R_DS(ON), then the

resistanceofoneMOSFETcansimplybesummedwiththe

resistances of L and the board traces to obtain the DC I²R

loss.Forexample,ifR_DS(ON)=0.01ΩandR_L=0.005Ω,the

loss will range from 15mW to 1.5W as the output current

varies from 1A to 10A.

Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated

controller turns off both power MOSFETs, shutting down

the converter permanently. The RUN/SS pin must be

actively pulled down to ground in order to restart opera-

tion. If the RUN/SS pin is tied to the CPUON pin, this is

achieved by pulling the VRON pin low or by sending two

Off protocols to the SMBus VID programmer to force the

CPUON pin low.

The overcurrent protection timer requires that the soft-

start timing capacitor C_SSbe made large enough to guar-

antee that the output is in regulation by the time C_SShas

reachedthe4Vthreshold.Ingeneral,thiswilldependupon

the size of the output capacitance, output voltage and load

currentcharacteristic.Aminimumsoft-startcapacitorcan

be estimated from:

2. Transition loss. This loss arises from the brief amount

of time the top MOSFET spends in the saturated region

during switch node transitions. It depends upon the input

voltage, load current, driver strength and MOSFET

capacitance, among other factors. The loss is significant

at input voltages above 20V and can be estimated from:

C_SS> C_OUTV_OUTR_SENSE(10^–4[F/V s])

2

Transition Loss (1.7A^–1) V_INI_OUTC_RSS

f

Generally 0.1µF is more than sufficient.

3. INTV_CCcurrent. This is the sum of the MOSFET driver

and control currents. This loss can be reduced by supply-

ing INTV_CCcurrent through the EXTV_CCpin from a high

efficiency source, such as an output derived boost net-

work or alternate supply if available.

Overcurrent latchoff operation is not always needed or

desired. Load current is already limited during a short-

circuitbythecurrentfoldbackcircuitryandlatchoffopera-

tion can prove annoying during troubleshooting. The

feature can be overridden by adding a pull-up current

greaterthan5µAtotheRUN/SSpin. Theadditionalcurrent

prevents the discharge of C_SSduring a fault and also

shortens the soft-start period. Using a resistor to V_INas

4. C_INloss. The input capacitor has the difficult job of

filtering the large RMS input current to the regulator. It

must have a very low ESR to minimize the AC I²R loss and

19098f

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sufficient capacitance to prevent the RMS current from

causing additional upstream losses in fuses or batteries.

1.5V

300kHz 1µH

1.5V

24V

∆I_L=

1–

= 4.7A

(

)(

)

Other losses, including C_OUTESR loss, Schottky diode D1

conduction loss during dead time and inductor core loss

generally account for less than 2% additional loss. When

making adjustments to improve efficiency, the input cur-

rent is the best indicator of changes in efficiency. If you

make a change and the input current decreases, then the

efficiency has increased. If there is no change in input

current, then there is no change in efficiency.

Next, choose the synchronous MOSFET switch. Because

of the narrow duty cycle and large current, a single SO-8

MOSFET will have difficulty dissipating the power lost in

the switch. Choosing two IRF7811A (R_DS(ON)= 0.013Ω,

C_RSS=60pF,θ_JA=40°C/W)yieldsanominalsensevoltage

of:

V

_SNS(NOM)= (15A)(0.5)(1.3)(0.012Ω) = 117mV

Tying V_RNGto INTV_CCwill set the current sense voltage

range for a nominal value of 140mV with current limit

occurring at 186mV. To check if the current limit is

acceptable,assumeajunctiontemperatureofabout100°C

above a 50°C ambient with ρ_150°C= 1.6:

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, V_OUTimmediately shifts by an amount

equal to ∆I_LOAD(ESR), where ESR is the effective series

resistance of C_OUT. ∆I_LOADalso begins to charge or

dischargeC_OUTgeneratingafeedbackerrorsignalusedby

the regulator to return V_OUTto its steady-state value.

During this recovery time, V_OUTcan be monitored for

overshoot or ringing that would indicate a stability

problem. The I_THpin external components shown in

Figure 7 will provide adequate compensation for most

applications. For a detailed explanation of switching con-

trol loop theory see Application Note 76.

186mV

1

2

I_LIMIT

≥

+

4.7A = 18A

(

)

0.5 1.6 0.012Ω

(

)( )(

)

and double check the assumed T_Jin the MOSFET:

2

24V –1.5V

24V

21.7A

2

P_BOT

=

1.6 0.012Ω = 2.12W

)(

(

)

T_J= 50°C + (2.12W)(50°C/W) = 156°C

Because the top MOSFET is on for such a short time, a

single IRF7811A will be sufficient. Checking its power

dissipation at current limit with ρ_90°C= 1.3:

Design Example

As a design example, take a supply with the following

specifications:V_IN=7Vto24V(15Vnominal), V_OUT=1.5V

±100mV, I_OUT(MAX)= 15A, f = 300kHz. First, calculate the

2

1.5V

24V

P

BOT

=

21.7A 1.3 0.012Ω +

(

) ( )(

)

timing resistor with V_ON= V_OUT

:

2

1.7 24V 21.7A 60pF 300kHz

(

)(

) (

)(

)

1

R_ON

=

= 330k

= 0.46W + 0.38W = 0.84W

300kHz 10pF

(

)(

)

T_J= 50°C + (0.84W)(50°C/W) = 92°C

and choose the inductor for about 40% ripple current at

the maximum V_IN:

The junction temperatures will be significantly less at

nominal current, but this analysis shows that careful

attention to heat sinking will be necessary in this circuit.

1.5V

24V

L =

1−

= 0.8µH

300kHz 0.4 15A

(

)( )(

)

C_INis chosen for an RMS current rating of about 6A at

temperature. The output capacitors are chosen for a low

ESR of 0.005Ω to minimize output voltage changes due to

Selecting a standard value of 1µH results in a maximum

ripple current of:

19098f

24

LTC1909-8

W U U

APPLICATIO S I FOR ATIO

U

inductor ripple current and load steps. The ripple voltage

in applications where rapid load steps are the main cause

of error in the output voltage. By positioning the output

voltage above the regulation point at zero load, and below

the regulation point at full load, one can use more of the

error budget for the load step. This allows one to reduce

the number of output capacitors by relaxing the ESR

requirement.

will be only:

∆V_OUT(RIPPLE)= ∆I_L(MAX)(ESR)

= (4.7A) (0.005Ω) = 24mV

However, a 0A to 15A load step will cause an output

change of up to:

∆V_OUT(STEP)= ∆I_LOAD(ESR) = (15A) (0.005Ω) = 75mV

In the design example, Figure 7, five 0.025Ω capacitors

are required in parallel to keep the output voltage within

tolerance. Using active voltage positioning, the same

specification can be met with only three capacitors. In this

case, the load step will cause an output voltage change of:

The complete circuit is shown in Figure 7.

Active Voltage Positioning

Active voltage positioning (also termed load “deregula-

tion” or droop) describes a technique where the output

voltage varies with load in a controlled manner. It is useful

1

∆V_OUT(STEP)= 15A

0.025Ω = 125mV

(

)

(

)

3

V

IN

7V TO 24V

C

D

B

IN

SS

22µF

50V

×3

0.1µF

CMDSH-3

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS BOOST

C

B

0.33µF

M1

V

TG

ON

IRF7811A

R

PG

100k

L1

1µH

3

PGOOD

SW

+

V

OUT

1.5V

15A

4

V

SENSE

RNG

C

OUT

M2

IRF7811A

×2

+

5

D1

UPS840

270µF

2V

C

FCB

PGND

BG

C1

470pF

R

C

×5

20k

6

I

TH

C

C2

VCC

4.7µF

LTC1909-8

SGND INTV

100pF

7

CC

R

F

1Ω

8

I

V

ON

IN

CC

C

100pF

F

FB

0.1µF

9

V

EXTV

V

5V

FB

10

11

12

13

14

SEL

SDA

SEL

SDA

GND

FB

SCL

C2

6.8nF

VRON

PGTMR

V

OSENSE

VRON

19098 F07

R

ON

330k

CPUON

C

: UNITED CHEMICON THCR70EIH226ZT

IN

OUT

: CORNELL DUBILIER ESRE271M02B

L1: SUMIDA CEP125-IR0MC-H

Figure 7. CPU Core Voltage Regulator 1.5V, 15A at 300kHz

19098f

25

LTC1909-8

W U U

U

APPLICATIO S I FOR ATIO

By positioning the output voltage 60mV above the regula-

tion point at no load, it will only drop 65mV below the

regulationpointaftertheloadstep,wellwithinthe±100mV

tolerance. Implementing active voltage positioning re-

quires setting a precise gain between the sensed current

and the output voltage. Because of the variability of

MOSFET on-resistance, it is prudent to use a sense resis-

tor with active voltage positioning. In order to minimize

powerlostinthisresistor,alowvalueischosenof0.003Ω.

The nominal sense voltage will now be:

of these resistors must equal R_VPand their ratio deter-

mines nominal value of the I_THpin voltage when the error

amplifier input is zero. To center the load line around the

regulation point, the I_THpin voltage must be set to

correspond to half the output current. The relation be-

tween I_THvoltage and the output current is:

12V

1

I_TH(NOM)

=

R_SENSEI_OUT– ∆I_L+ 0.8V

V_RNG

2

12V

0.5V

1

2

0.003Ω 7.5A – 4.7A + 0.8V

(

)

V_SNS(NOM)= (0.003Ω)(15A) = 45mV

To maintain a reasonable current limit, the voltage on the

V_RNGpin is reduced to its minimum value of 0.5V, corre-

sponding to a 50mV nominal sense voltage.

= 1.17V

Solving for the required values of the resistors:

Next, the gain of the LTC1909-8 error amplifier must be

determined. ThechangeinI_THvoltageforacorresponding

change in the output current is:

5V

R_VP1

=

R_VP

=

9.53k

5V –I_TH(NOM)

5V – 1.17V

= 12.44k

12V

V_RNG

∆I_TH

=

R_SENSE∆I_OUT

5V

1.17V

R_VP2

=

R_VP

=

9.53k = 40.73k

I_TH(NOM)

= 24 0.003Ω 15A = 1.08V

( )( )(

)

The modified circuit is shown in Figure 8. Figures 9 and 10

show the transient response without and with active

voltagepositioning.Bothcircuitseasilystaywithin±100mV

of the 1.5V output. However, the circuit with active voltage

positioning accomplishes this with only three output ca-

pacitors rather than five. Refer to Design Solutions 10 for

additional information about active voltage positioning.

The corresponding change in the output voltage is deter-

mined by the gain of the error amplifier and feedback

divider.TheLTC1909-8erroramplifierhasatransconduc-

tanceg_mthatisconstantoverbothtemperatureandawide

±40mVinputrange.Thus,byconnectingaloadresistance

R_VPto the I_THpin, the error amplifier gain can be precisely

set for accurate active voltage positioning.

SMBus Protocols

0.8V

∆I_TH= g_mR_VP

∆V_OUT

The Write Word and Read Word protocols (Figure 11)

share three common features. First, the 7-bit slave ad-

dress for both protocols is internally hardwired to 1110

001B = E2H. A single R/W bit follows the slave address.

This bit is low for data transfer from the microprocessor

to the LTC1909-8 and high for transfers in the opposite

direction.

V_OUT

Solving for this resistance value:

V

_OUT∆I_TH

(0.8V)g_m∆V_OUT

R_VP

=

(1.5V)(1.08V)

(0.8V)(1.7mS)(125mV)

= 9.53k

Second, the LTC1909-8 decodes only the three most

significant bits of the 8-bit command code. Table 3 shows

the four valid combinations. All other combinations are

ignored.

The gain setting resistance R_VPis implemented with two

resistors, R_VP1connected from I_THto ground and R_VP2

connected from I_THto INTV_CC. The parallel combination

19098f

26

LTC1909-8

W U U

APPLICATIO S I FOR ATIO

U

V

IN

7V TO 24V

C

D

SS

0.1µF

IN

B

22µF

50V

×3

CMDSH-3

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS BOOST

C

B

0.33µF

M1

V

ON

TG

IRF7811A

R

RNG1

4.99k

R

RNG2

45.3k

R

PG

100k

L1

1µH

3

PGOOD

SW

+

V

1.5V

15A

OUT

4

V

RNG

SENSE

C

OUT

M2

IRF7811A

×2

+

5

D1

B540

270µF

2V

FCB

PGND

R

VP2

40.2k

×5

6

I

TH

BG

R

C

VP1

C1

VCC

LTC1909-8

SGND INTV

12.4k

180pF

4.7µF

7

CC

R

F

1Ω

8

R

SENSE

0.003Ω

I

V

ON

IN

CC

C

FB

100pF

F

0.1µF

9

V

EXTV

V

5V

FB

10

11

12

13

14

SEL

SDA

SEL

SDA

GND

FB

SCL

VRON

PGTMR

V

OSENSE

19098 F08

R

ON

330k

CPUON

C

: UNITED CHEMICON THCR70EIH226ZT

: CORNELL DUBILIER ESRE271M02B

IN

OUT

L1: SUMIDA CEP125-IR0MC-H

Figure 8. CPU Core Voltage Regulator with Active Voltage Positioning 1.5V/15A at 300kHz

V_OUT

100mV/DIV

1.5V

V_OUT

100mV/DIV

1.5V

I_L

10A/DIV

C

_OUT= 5 × 270µF

20µs/DIV

3711 F09

C_OUT= 3 × 270µF

V_IN= 15V

FIGURE 8 CIRCUIT

20µs/DIV

3711 F10

V_IN= 15V

FIGURE 7 CIRCUIT

Figure 9. Normal Transient Response

Figure 10. Transient Response with Active Voltage Positioning

19098f

27

LTC1909-8

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U

APPLICATIO S I FOR ATIO

SLAVE

ADDRESS

ON

COMMAND

DATA LOW

(REGISTER 0)

DATA HIGH

(REGISTER 1)

S 1110001 R/W A 000XXXXX

A

DON’T CARE

A

DON’T CARE

A P

UPDATE DCON

SLAVE

ADDRESS

OFF

COMMAND

DATA LOW

(REGISTER 0)

DATA HIGH

(REGISTER 1)

S 1110001 R/W A 011XXXXX

DON’T CARE

A P

UPDATE DCON

SLAVE

ADDRESS

SETUP

COMMAND

DATA LOW

(REGISTER 0)

DATA HIGH

(REGISTER 1)

S 1110001 R/W A 001XXXXX

VID4 VID3 VID2 VID1 VID0 X X X

A P

COMMAND

LATCHED

DATA LOW

LATCHED

DATA HIGH UPDATE DCON

LATCHED

SLAVE

ADDRESS

READ-BACK

COMMAND

DATA LOW

(REGISTER 0)

DATA HIGH

(REGISTER 1)

S 1110001 R/W A 010XXXXX

A

S 1110010 RD

A

VID4 VID3 VID2 VID1 VID0 DCON 0 0

A

VID4 VID3 VID2 VID1 VID0 DCON 0 0 A P

19098 F11

COMMAND

LATCHED

DATA LOW

LOADED

DATA HIGH

LOADED

STOP

(IGNORED)

Figure 11. Write Word and Read Word Protocols

Third, the Data Low and Data High bytes correspond to

Registers 0 and 1 respectively. In Write Word protocol with

C7 = C6 = 0, C5 = 1, the five most significant bits (VID0-

VID4) of these bytes specify a resistor divider setting.

When the microprocessor issues a start bit, all the slave

devices on the bus, including the LTC1909-8 clock in the

address byte, which consists of a 7-bit slave address and

the R/W bit (set to 0). If the slave address from the

microprocessor does not match the internal hardwired

address, the LTC1909-8 returns to an idle state and waits

for the next start bit. If the slave address matches, the

LTC1909-8 acknowledges by pulling the SDA line low for

one clock cycle after the address byte. After detecting the

acknowledgment bit (A), the microprocessor transmits

the second byte or command code.

Table 3. LTC1909-8 Command Bits

C7

0

C6

0

C5

0

COMMAND

On

PROTOCOL

Write Word

Read Word

0

1

Off

0

1

Setup

0

1

0

Read-Back

The command code identifies the type of Write Word

protocol as Setup, On or Off (Table 3). The Setup protocol

is used to load two resistor divider settings into Register

0 and 1. The On and Off protocols turn the converters on

or off in conjunction with the VRON pin. Once all 8 bits of

the command code are clocked in, the LTC1909-8 issues

a second acknowledgment bit to the microprocessor.

After detecting the acknowledgment bit, the microproces-

sor transmits two data bytes.

Write Word Protocol

Each Write Word protocol (Figure 11) begins with a start

bit (S) and ends with a stop bit (P). As shown in the Timing

Diagram the start and stop bits are defined as high-to-low

andlow-to-highSDAtransitionsrespectively, whileSCLis

high. In between the start and stop bits, the microproces-

sor transmits four bytes to the LTC1909-8. These are the

address byte, an 8-bit command code and two data bytes.

The LTC1909-8 samples each bit at the rising edges of the

SCL clock.

19098f

28

LTC1909-8

W U U

APPLICATIO S I FOR ATIO

U

Each data byte is acknowledged in turn for all three Write

Word protocols but is only latched into Register 0 or 1 in

Setup protocol. This prevents previously loaded settings

from accidentally being changed. The first or Data Low

byte is loaded into Register 0. The second or Data High

byte is loaded into Register 1. After issuing the final

acknowledgment bit, the SMBus interface returns to an

idle state and waits for the next start bit.

Operating Sequence

AtypicalcontrolsequencefortheLTC1909-8isasfollows:

• On power up, the DCON bit is preset to a high state by

the power-on reset (POR) circuit. The CPUON pin is

pulled low to shut down the DC/DC converter. PGTMR

and PGOOD pull low to indicate that the converters are

not in regulation.

• Pull VRON low as a precaution. Take SEL high or low to

selectthedividersetting;e.g.,onethatsuitstheexisting

power source (battery or wall-pack) or intended CPU

speed.

Read Word Protocol

The Read Word protocol starts off like Write Word proto-

col but after the command code acknowledgment, the

microprocessor issues a second start bit (called a re-

peatedstart).Thisisfollowedbytheslaveaddressbutwith

the R/W bit set high to indicate that data direction is now

fromtheLTC1909-8tothemicroprocessor.TheLTC1909-8

then acknowledges the slave address and clocks the

contents of Register 0 (Data Low byte) to the micropro-

cessor. The Data Low byte is acknowledged by the micro-

processor. On detecting the acknowledgment bit, the

LTC1909-8 clocks out the contents of Register 1 (Data

High byte). As defined in the SMBus specifications, the

microprocessor does not acknowledge the last data byte.

TheLTC1909-8entersanidlestatetowaitforthenextstart

bit after clocking out the Data High byte. The five most

significant bits (VID0-VID4) of the Data Low and High

bytes are the resistor divider settings previously loaded

using the Setup protocol. The next bit below the VID0-

VID4 bits is the status of the DCON signal. If this bit is low

(high), the DC/DC converters are switched on (off). The

two unused, least significant bits of the Data Low and Data

High bytes are clocked out as zeros to eliminate the need

to mask out these bits in software.

• Use the Setup protocol to load the appropriate divider

settingsinRegisters0and1andenabletheOn/Offstate

machine.

• Use the Read-Back protocol to verify the contents of

Registers 0 and 1.

• Repeat the setup and read-back if the codes are incor-

rect (due to bus conflicts).

• Send two On protocols in succession to clear the DCON

bit.

• Use the Read-Back protocol to verify that the DCON is

low. AhighstatewillindicatethatanOncommandcode

was corrupted by bus conflicts.

• Pull VRON high. Since DCON = 0, the CPUON pin enters

a high impedance state, allowing the DC/DC converter

to soft-start. PGTMR stays low for 50µs. PGOOD stays

low until the regulator output rises above the –7.5%

regulation limit.

• To shut down the supply, send two Off protocols to set

the DCON bit high or pull VRON low if immediate

shutdown is required.

19098f

29

LTC1909-8

W U U

U

APPLICATIO S I FOR ATIO

PC Board Layout Checklist

• Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of

powercomponent.Youcanconnectthecopperareasto

any DC net (V_IN, V_OUT, GND or to any other DC rail in

your system).

When laying out a PC board follow one of the two sug-

gested approaches. The simple PC board layout requires

a dedicated ground plane layer. Also, for higher currents,

it is recommended to use a multilayer board to help with

heat sinking power components.

When laying out a printed circuit board, without a ground

plane, use the following checklist to ensure proper opera-

tion of the controller. These items are also illustrated in

Figure 12.

• The ground layer should not have any traces and it

should be as close as possible to the layer with power

MOSFETs.

• Segregate the signal and power grounds. All small-

signal components should return to the SGND pin at

onepointwhichisthentiedtothePGNDpinclosetothe

source of M2. Tie the GND pin directly to SGND.

• Place C_IN, C_OUT, MOSFETs, D1 and inductor all in one

compactarea.Itmayhelptohavesomecomponentson

the bottom side of the board.

• Place LTC1909-8 chip with Pins 20 to 28 facing the

power components. Keep the components connected

to Pins 16 to 18 close to LTC1909-8 (noise sensitive

components).

• Place M2 as close to the controller as possible, keeping

the PGND, BG and SW traces short.

•

Connect the input capacitor(s) C_INclose to the power

MOSFETs. This capacitor carries the MOSFET AC

current.

•

Use an immediate via to connect the components to

ground plane including SGND, GND and PGND of

LTC1909-8. Use several bigger vias for power

components.

• Keep the high dV/dT SW, BOOST and TG nodes away

from sensitive small-signal nodes.

• Use compact plane for switch node (SW) to improve

cooling of the MOSFETs and to keep EMI down.

• Connect the INTV_CCdecoupling capacitor C_VCCclosely

to the INTV_CCand PGND pins.

• Use planes for V_INand V_OUTto maintain good voltage

filtering and to keep power losses low.

• Connect the top driver boost capacitor C_Bclosely to the

BOOST and SW pins.

• Connect the V_OSENSE, FB and GND pins of the resistor

dividerdirectlytotheoutputoftheDC/DCconverter,the

V_FBpin and the SGND pin of the controller.

• Connect the V_INpin decoupling capacitor C_Fclosely to

the V_INand PGND pins.

19098f

30

LTC1909-8

W U U

APPLICATIO S I FOR ATIO

U

C

SS

B

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS BOOST

2

V

TG

ON

D

B

3

PGOOD

SW

+

M1

D1

4

C

V

SENSE

IN

RNG

M2

5

FCB

PGND

BG

–

+

C

C1

LTC1909-8

R

C

6

I

TH

C

VCC

C

C2

C

OUT

7

SGND

ION

INTV

CC

C

F

R

F

8

V

IN

CC

C

FB

9

V

EXTV

V

FB

10

11

12

13

14

SEL

SDA

GND

FB

R

ON

SCL

VRON

PGTMR

V

OSENSE

CPUON

19098 F12

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 12. LTC1909-8 PCB Layout Diagram

U

PACKAGE DESCRIPTIO

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

9.90 – 10.50*

(.390 – .413)

1.25 ±0.12

28 27 26 25 24 23 22 21 20 19 18

16 15

17

7.8 – 8.2

5.3 – 5.7

7.40 – 8.20

(.291 – .323)

0.42 ±0.03

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60**

(.197 – .221)

2.0

(.079)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

0.55 – 0.95

(.0035 – .010)

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

(.002)

NOTE:

G28 SSOP 0802

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

19098f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.

31

LTC1909-8

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SMBus VID Programmer Compliant with Intel

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Precision ±0.35% Resistor Divider for Use with 0.8V

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≤ 2V

OUT

Up to 42A Output; VRM 8.4, 1.3V ≤ V

≤ 3.5V

OUT

Two Integrated 0.4Ω/300mA N-Channel Switches

LTC1735

High Efficiency, Synchronous Step-Down Controller

Burst Mode Operation; 16-Pin Narrow SSOP;

3.5V ≤ V ≤ 36V

IN

LTC1759

SMBus Interfaced Smart Battery Charger

ThinSOT Step-Down Controller

Constant Current/Constant Voltage Battery Charger, Up to 8A

Charge Current, High Efficiency Synchronous Charger

LTC1772

LTC1778

Current Mode; 550kHz; Very Small Solution Size

No R

Synchronous Step-Down Controller

No Sense Resistor Required, 4V ≤ V ≤ 36V,

IN

SENSE

0.8V ≤ V

≤ (0.9) V , GN16

OUT

IN

LT^®1786F

LTC1876

SMBus Programmable CCFL Switching Regulator

Precision 100µA Full-Scale DAC, Grounded Lamp or

Floating Lamp Configurations

2-Phase, Dual Synchronous Step-Down Controller with

Step-Up Regulator

3.5V ≤ V ≤ 36V, Power Good Output, 300kHz Operation

IN

LTC3701

LTC3711

Dual, Step-Down Controller

Current Mode; 550kHz; Small 16-Pin SSOP, V < 9.8V

IN

5-Bit Adjustable, Wide Operating Range, No R

Step-Down Controller

GN24, Mobile VID, 0.925V ≤ V

≤ 2V

SENSE

OUT

LTC3714

Intel Compatible, Wide Operating Range, Step-Down Controller

with Internal Op Amp

G28, 0.6V ≤ V

Offsets, 5-Bit VID

≤ 1.75V, Programmable Output

OUT

ThinSOT is a trademark of Linear Technology Corporation.

19098f

LT/TP 0603 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

LINEAR TECHNOLOGY CORPORATION 2001

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1909-8EG#TR
厂家：	Linear
描述：	LTC1909-8 - Wide Operating Range, No RSENSE Step-Down DC/DC Controller with SMBus Programming; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总32页 (文件大小：636K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1909-8EG#TR [Linear]

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