LTC1923EUH#TRPBF [Linear]
LTC1923 - High Efficiency Thermoelectric Cooler Controller; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C;
| 型号： | LTC1923EUH#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1923 - High Efficiency Thermoelectric Cooler Controller; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总28页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1923
High Efficiency Thermoelectric
Cooler Controller
U
DESCRIPTIO
FEATURES
■
High Efficiency, Low Noise Topology
The LTC®1923 is a pulse width modulator intended for
thermoelectric cooler (TEC) or heater applications requir-
ing either unidirectional or bidirectional drive circuits. All
of the necessary control circuitry and two sets of comple-
mentary output drivers are integrated into the LTC1923 to
drive a full bridge, providing an efficient means of bidirec-
tional current flow to the TEC. An accurate temperature
control loop to stabilize the temperature of a laser diode
system is easily achieved with the addition of just a few
external components. Typical temperature setpoint accu-
racy of 0.1°C is achievable with the LTC1923. Adding an
instrumentation amplifier front end allows setpoint stabil-
ity of 0.01°C.
■
Adjustable Output Slew Rate Reduces EMI
■
Full-Bridge Controller for Bidirectional
Current Control
■
Adjustable Pulse-by-Pulse Bidirectional TEC
Current Limit
■
Open/Shorted Thermistor Indication
■
Solution Footprint in Less Than 0.6" × 0.8"
(Double-Sided PCB)
■
Available in 5mm x 5mm QFN and
28-Pin SSOP Packages
TEC Voltage Clamping
■
■
TEC Current, Voltage and Heat/Cool Status Outputs
■
Adjustable/Synchronizable Oscillator Frequency
The part features independent adjustable heating and
cooling pulse-by-pulse current limit, current soft-start for
controlled start-up, output slew rate control to reduce
system noise, differential current sense and voltage am-
plifiers and a host of auxiliary circuits to protect the laser
and provide redundant system monitoring.
Reduces Filter Component Size and System Noise
■
2.5V Reference Voltage Output
2.7V Minimum Operating Voltage
■
U
APPLICATIO S
■
Laser-Based Fiber Optic Links
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Medical Instruments
■
CPU Temperature Regulators
U
TYPICAL APPLICATIO
Laser Temperature Control Loop Achieving Setpoint Stability of 0.01°C
10k
10k
0.1%
PLLLPF
R
C
T
T
330pF
82k
R
SLEW
+
1µF
REF
REF
V
DD
V
REF
LTC2053
V
SDSYNC
CNTRL
EAOUT
FB
V
REF
DD
A = 10
–
TMP
CMD
10k
NTC
LTC1658
V
OUT
PDRVB
NDRVB
10µF
4.7µF
10M
MPA*
MPB**
MNA*
L1
L2
100k
COOLER
TEC
10µH
10µH
V
DD
LTC1923
1µF
C2
22µF
C1
MNB** 22µF
AGND
PGND
NDRVA
PDRVA
1µF
SS
3
1
I
LIM
+
R
S
V
SET
CS
2
–
4
FAULT
CS
V
I
THRM
TEC
+
C1, C2: TAIYO YUDEN JMK325BJ226MM-T (X7R)
L1, L2: SUMIDA CDRH6D2B-220NC
*MNA, MPA: SILICONIX Si9801
H/C
TEC
TEC
–
1923 TA01
V
TEC
**MNB, MPB: SILICONIX Si9801
1923f
1
LTC1923
ABSOLUTE AXI U RATI GS
W W U W
(Note 1)
VDD to GND................................................. –0.3V to 6V
SDSYNC, RSLEW ......................................... –0.3V to 6V
FB, CNTRL, VTHRM, ILIM, VSET..................... –0.3V to 6V
CS+, CS–, TEC+, TEC–.................................–0.3V to 6V
FAULT, H/C ................................................. –0.3V to 6V
Operating Temperature Range (Note 2) .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
1
2
R
C
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PLLLPF
T
R
T
SLEW
32 31 30 29 28 27 26 25
LTC1923EUH
LTC1923EGN
3
V
REF
SDSYNC
CNTRL
EAOUT
FB
CNTRL
EAOUT
FB
1
2
3
4
5
6
7
8
24 PDRVB
23 NDRVB
PIN 1
TOP VIEW
4
PDRVB
NDRVB
5
V
V
22
21
DD
DD
6
V
DD
AGND
NC
7
PGND
AGND
SS
20 PGND
NDRVA
8
NDRVA
PDRVA
SS
19
9
I
18 PDRVA
I
LIM
SET
LIM
SET
+
+
V
17 CS
10
11
12
13
14
CS
V
–
9
10 11 12 13 14 15 16
CS
FAULT
I
V
TEC
THRM
+
TEC
H/C
–
UH PACKAGE
32-LEAD PLASTIC QFN
TEC
V
TEC
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD IS PGND
(MUST BE SOLDERED TO PCB)
TJMAX = 125°C, θJA = 120°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted.
SYMBOL PARAMETER
Input Supply
CONDITIONS
MIN
2.7
50
TYP
MAX
UNITS
VDD
Operating Supply Voltage
Undervoltage Lockout
●
●
●
5.5
2.7
V
V
UVLO
Low to High Threshold
High to Low
2.6
130
2
UVHYST Hysteresis
mV
mA
µA
V
I
I
Operating Supply Current
Shutdown I
No Output Load, Outputs Not Switching
SDSYNC = 0V
4
DD
10
25
1.4
DDSHDN
DD
SHDNTH Shutdown Threshold
Measured at PDRVA, PDRVB
0.3
0.8
1923f
2
LTC1923
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted.
SYMBOL PARAMETER
Reference
CONDITIONS
MIN
TYP
MAX
UNITS
V
Reference Output Voltage
No Load
2.462
2.450
2.5
2.538
2.550
V
V
REF
●
●
V
V
Good Threshold
V
Rising Threshold
= –1mA to –10mA
2.25
10
5
2.45
25
V
mV
mV
mA
REFGD
REF
REF
LDREG
LINEREG Line Regulation
Short-Circuit Current
Oscillator and Phase-Locked Loop
Load Regulation
I
LOAD
V
V
= 2.7V to 5.5V
= 0V
20
DD
V
10
20
REFISC
REF
f
f
Initial Oscillator Frequency
Frequency Variation
R = 10k, C = 330pF
190
165
1.4
225
225
1.5
260
270
1.6
kHz
kHz
V
OSCI
OSC
T
T
V
= 2.7V to 5V, C = 330pF, R = 10k
●
DD
T
T
OSCPK
OSCVLY C Ramp Valley
C Ramp Peak
T
0.4
0.5
0.6
V
T
C
C
C Charge Current
C = 0.3V, R = 10k
–150
150
–0.9
µA
µA
V/V
TICH
T
T
T
C Discharge Current
T
C = 1.8V, R = 10k
TIDIS
T
T
PLLGAIN Gain from PLLLPF to R
–1.1
–0.7
T
I
Phase Detector Output Current
PLLLPF
Sinking
f
f
< f
> f
12
–12
µA
µA
SYNC
SYNC
OSC
OSC
Sourcing
MSTTH
SDDLY
Master Threshold On PLLLPF Pin
Shutdown Delay to Output
Measured at SDSYNC Pin
V
DD
– 0.7 V – 0.4
V
DD
20
45
µs
Error Amplifier
V
Input Offset Voltage
Open-Loop Gain
EAOUT = 1V, V = 2.5V
–18
18
+ 0.2
mV
dB
V
OS
CM
AOL
EAOUT = 0.45V to 1.55V, CNTRL = 2.5V
EAOUT = 1V
80
V
Common Mode Input Range
FB and CNTRL Input Bias Currents
Output High
0.2
V
DD
CM
I
FB = CNTRL = 1.25
–100
100
nA
V
IB
V
V
I
I
= –100µA
= 100µA
1.65
0.3
–1.5
2
OH
LOAD
LOAD
Output Low
0.45
–0.5
V
OL
I
I
Sourcing Current
EAOUT = 1V, FB = 2.4V, CNTRL = 2.5V
EAOUT = 1V, FB = 5V, CNTRL = 2.5V
f = 100kHz (Note 3)
mA
mA
MHz
SOURCE
SINK
Sinking Current
1
GBW
Gain-Bandwidth Product
2
Current Sense Amplifier
ACS
Amplifier Gain
10
–2
V/V
mV
V
CSOFF
Amplifier Offset
Measured at I
–15
10
0.2
0.2
TEC
+
–
I
I
Output Sourcing Load Regulation
Output Sinking Load Regulation
–3dB Frequency
CS - CS = 100mV, I
= 0 to –50µA
= 0 to 50µA
0.1
0.1
500
145
300
–1.5
70
TECH
TECL
LOAD
LOAD
+
–
CS - CS = 100mV, I
V
f3dB
(Note 3)
kHz
mV
ns
+
–
I
I
Current Limit Threshold
Current Limit Delay to Output
Soft-Start Charge Current
Soft-Start Current Limit Threshold
Measured at CS , CS
●
125
165
450
–0.5
90
LIMTH
LIMDLY
SSI
SSI
SS = 0.75V
–2.5
50
µA
mV
mV
CHG
LIM
+
–
SS = 0.5V, Measured at CS , CS
+
–
I
I
Current Limit Threshold
I
= 0.5V, Measured at CS , CS
50
70
90
LIM
LIM
LIM
1923f
3
LTC1923
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted.
SYMBOL PARAMETER
TEC Voltage Amplifier
CONDITIONS
MIN
TYP
MAX
UNITS
ATEC
Amplifier Gain
Amplifier Offset
0.98
1
1.02
V/V
mV
dB
TECOFF
Measured at V , V = 2.5V
–7
60
4.9
0.1
1
TEC CM
TECCMR Common Mode Rejection
0.1V < V < 4.9V
CM
V
V
Output High Voltage
Output Low Voltage
–3dB Frequency
I
I
= –50µA
= 50µA
4.7
4
V
TECH
TECL
LOAD
LOAD
0.3
1.2
V
f3dB
Output Drivers
(Note 3)
MHz
OUTH
OUTL
Output High Voltage
I
I
= –100mA
= 100mA
4.5
0.7
20
V
V
OUT
OUT
Output Low Voltage
Output Rise Time
Output Fall Time
t
t
t
t
t
t
C
C
C
C
C
C
= 1nF
ns
ns
ns
ns
ns
ns
V
RISE
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 1nF
20
FALL
Output Rise Time
Output Fall Time
= 1nF, R
= 1nF, R
= 1nF, R
= 1nF, R
= 10k
20
rSLEW
fSLEW
rSLEW
fSLEW
SLEW
SLEW
SLEW
SLEW
= 10k
20
Output Rise Time
Output Slew Fall Time
= 100k
= 100k
90
90
SLEWVT
DLY
R
SLEW
Disable Threshold
2.75
90
Output Dead Time
R = 10k
T
ns
Fault
OPENTH Open Thermistor Threshold
SHRTTH Shorted Thermistor Threshold
V
V
= 5V, Measured with Respect to V
–410
0.975
150
mV
V
SET
SET
SET
= 5V, Measured with Respect to GND
FLTV
Fault Output Low Voltage
1mA Into FAULT, During Fault
300
300
mV
Direction Comparator
–
–
–
DIRH
DIRL
HCV
Low-to-High Threshold
TEC = 2.5V, Measured with Respect to TEC
Sensed When H/C Toggles Low
50
mV
mV
mV
–
High-to-Low Threshold
TEC = 2.5V, Measured with Respect to TEC
Sensed When H/C Toggles High
–50
H/C Output Low Voltage
1mA Into Pin
150
Note 3: Guaranteed by design, not tested in production.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1923E is guaranteed to meet specifications from 0°C to
70°C. Specifications over the –40°C to 85°C operating temperature range
are assured by design, characterization and correlation with statistical
process controls.
1923f
4
LTC1923
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Oscillator Frequency vs RT
VREF vs Temperature
265
245
225
205
185
165
1800
1600
1400
1200
1000
800
2.510
2.505
2.500
2.495
2.490
2.485
V
T
= 2.7V, 5V
DD
= 25°C
C
= 330pF
= 10k
T
T
A
R
C
= 68pF
C
T
= 150pF
T
600
400
200
C
= 330pF
10
T
0
–50
10
40
70
100
130
–20
5
20
15
–50
10
40
70
100
130
–20
TEMPERATURE (°C)
R
T
(kΩ)
TEMPERATURE (°C)
1923 G01
1923 G02
1923 G03
VREF vs IREF for Different
Temperatures
Output Rise/Fall Time vs RSLEW
Output Dead Time vs RT
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
2.475
2.470
150
125
100
75
250
200
150
100
50
T
= 25°C
T
= 25°C
A
A
T
= 125°C
A
V
DD
= 2.7V
V
DD
= 5V
T
A
= 25°C
50
T
= –50°C
A
25
0
0
5
15
5
7.5
10
(kΩ)
12.5
15
10
200
(kΩ)
0
100
300
I
(mA)
R
T
R
REF
SLEW
1923 G04
1923 G05
1923 G06
Shorted Thermistor Threshold
vs Temperature
Error Amplifier Offset Voltage
vs Temperature
Open Thermistor Threshold
vs Temperature
1.00
0.99
0.98
0.97
1.5
1.0
0.5
0
4.60
4.59
4.58
4.57
V
= 5V
V
= 5V
SET
SET
0.96
0.95
–0.5
–1.0
4.56
4.55
–50
10
40
70
100
130
–20
–50
10
40
70
100
130
–50
10
40
70
100
130
–20
–20
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1923 G09
1923 G07
1923 G08
1923f
5
LTC1923
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Current Limit Threshold
vs Temperature
System Power Loss
vs TEC Current
TEC Clamp Voltage
vs Temperature
0.7
0.6
0.5
2.550
2.530
2.510
2.490
2.470
2.450
165
160
155
150
145
140
135
130
125
T
= 25°C
A
0.4
0.3
0.2
0.1
0
V
= 5V
DD
V
DD
= 3.3V
40
70
0.5
TEC CURRENT (A)
1
–20
10
40
70
100
–50
–20
10
100
130
0
–50
130
TEMPERATURE (°C)
TEMPERATURE (°C)
1923 G10
1923 G11
1923 G12
Representative Waveforms for NDRVA,
NDRVB, TEC Current and CS+ – CS–
CH1: TEC CURRENT (500mA/DIV)
CH2: VOLTAGE ACROSS
0.1Ω SENSE RESISTOR
(CS+ – CS–) 100mV/DIV
CH3: NDRVA (5V/DIV)
CH4: NDRVB (5V/DIV)
VDD = 5V
1923 G15.tif
RTEC = 2.5Ω
RS = 0.1Ω
Representative Waveforms for
TEC Current, CS+ – CS– and ITEC
CH2: VOLTAGE ACROSS 0.1Ω SENSE
RESISTOR RS (CS+ – CS–) 100mV/DIV
CH2
CH3: VOLTAGE ON ITEC PIN EQUAL TO
TEN TIMES THE ABSOLUTE VALUE OF
CH2 (200mV/DIV)
CH1: TEC CURRENT (500mA/DIV)
CH1, CH3
VDD = 5V
1923 G16.tif
RTEC = 2.5Ω
RS = 0.1Ω
1923f
6
LTC1923
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Long-Term Cooling Mode Stability Measured in Environment that Steps 20 Degrees Above Ambient
Every Hour. Data Shows Resulting 0.008°C Peak-to-Peak Variation, Indicating Thermal Gain of
2500. 0.0025°C Baseline Tilt Over Plot Length Derives From Varying Ambient Temperature
1923 G13.tif
Identical Test Conditions as Above, Except in Heating Mode. TEC’s Higher Heating Mode Efficiency
Results in Higher Thermal Gain. 0.002°C Peak-to-Peak Variation Is 4x Stability Improvement.
Baseline Tilt, Just Detectable, Shows Similar 4x Improvement vs Above
1923 G14.tif
1923f
7
LTC1923
U
U
U
PI FU CTIO S
(GN Package/UH Package)
PLLLPF (Pin 1/Pin 30): This pin serves as the lowpass
filter for the phase-locked loop when the part is being
synchronized. The average voltage on this pin equally
alters both the oscillator charge and discharge currents,
thereby changing the frequency of operation. Bringing the
voltage on this pin above VDD – 0.4V signifies that the part
will be used as the synchronization master. This allows
multiple devices on the same board to be operated at the
samefrequency.TheSDSYNCpinwillbepulledlowduring
each CT charging cycle to facilitate synchronization.
SS (Pin 8/Pin 6): The TEC current can be soft-started by
adding a capacitor from this pin to ground. This capacitor
willbechargedbya1.5µAcurrentsource.Thispinconnects
to one of the inverting inputs of the current limit compara-
torandallowstheTECcurrenttobelinearlyrampedupfrom
zero. The voltage on this pin must be greater than 1.5V to
allow the open/shorted thermistor window comparitor to
signal a fault.
I
LIM (Pin 9/Pin 7): A voltage divider from VREF to this pin
sets the current limit threshold for the TEC. If the voltage
on this pin is set higher than 1V, then ILIMIT = 150mV/RS
as that is the internal current limit comparator level. If the
voltage on this pin is set less than 1V, the current limit
value where the comparator trips is:
RSLEW (Pin 2/Pin 31): Placing a resistor from this pin to
AGND sets the voltage slew rate of the output driver pins.
The minimum resistor value is 10k and the maximum
value is 300k. Slew rate limiting can be disabled by tying
this pin to VDD, allowing the outputs to transition at their
maximum rate.
ILIMIT = [0.15 • RILIM1 • VREF]/[(RILIM1 + RILIM2) • RS]
VSET (Pin 10/Pin 8): This is the input for the setpoint
reference of the temperature sense element divider net-
work or bridge. This pin must be connected to the bias
source for the thermistor divider network.
SDSYNC(Pin3/Pin32):Thispincanbeusedtodisablethe
IC, synchronize the internal oscillator or be the master to
synchronize other devices. Grounding this pin will disable
all internal circuitry and cause NDRVA and NDRVB to be
forced low and PDRVA and PDRVB to be forced to VDD.
EAOUT will be forced low. FAULT will also be asserted low
indicating a fault condition. The pin can be pulled low for
up to 20µs without triggering the shutdown circuitry. The
partcaneitherbeslavedtoanexternalclockorcanbeused
as the master (see Applications Information for a more
detailed explanantion).
FAULT(Pin11/Pin9):Open-drainoutputthatindicatesby
pulling low when the voltage on VTHRM is outside the
specified window, the part is in shutdown, undervoltage
lockout (UVLO), or the reference is not good. When the
voltage on VTHRM is outside the specified window, it
signifiesthatthethermistorimpedanceisoutofitsaccept-
ablerange.Thissignalcanbeusedtoflagamicrocontroller
toshutthesystemdownorusedtodisconnectpowerfrom
the bridge. See Applications Information for using this
signal for redundant protection.
CNTRL (Pin 4/Pin 1): Noninverting Input to the Error
Amplifier.
EAOUT (Pin 5/Pin 2): Output of the Error Amplifier. The
loopcompensationnetworkisconnectedbetweenthispin
and FB. The voltage on this pin is the input to the PWM
comparator and commands anywhere between 0% and
100% duty cycle to control the temperature of the tem-
perature sense element.
VTHRM (Pin 12/Pin 10): Voltage Across the Thermistor. If
thevoltageonthispinisoutsidetherangebetween410mV
below VSET and 0.2 • VSET, the FAULT pin will be asserted
(and latched) low indicating that the thermistor tempera-
ture has moved outside the acceptable range.
H/C (Pin 13/Pin 11): This open-drain output provides the
direction information of the TEC current flow. If TEC+ is
greater than TEC–, which typically corresponds to the
system cooling, this output will be a logic low. If the
opposite is the case, this pin will pull to a logic high.
FB(Pin6/Pin3):TheInvertingInputtotheErrorAmplifier.
ThisinputisconnectedtoEAOUTthroughacompensating
feedback network.
AGND (Pin 7/Pin 4): Signal Ground. All voltages are
measured with respect to AGND. Bypass VDD and VREF
with low ESR capacitors to the ground plane near this pin.
1923f
8
LTC1923
U
U
U
PI FU CTIO S
(GN Package/UH Package)
V
TEC (Pin14/Pin12):OutputofthedifferentialTECvoltage
NDRVA, NDRVB (Pins 21, 24/Pins 19, 23): These push-
pull outputs are configured to drive the opposite low side
switches in a full-bridge arrangement.
amplifier equal to the magnitude of the voltage across
the TEC.
TEC– (Pin15/Pin 13): InvertingInputtotheDifferentialTEC
VoltageAmplifier.Thisamplifierhasafixedgainof1withits
output being the voltage across the TEC with respect to
AGND. This input, along with TEC+, signifies whether the
TEC is heating or cooling the laser as indicated by the
H/C pin.
PGND (Pin 22/Pin 20): This is the high current ground for
the IC. The external current sense resistor should be
referenced to this point.
V
DD (Pin 23/Pins 21, 22): Positive Supply Rail for the IC.
Bypass this pin to PGND and AGND with >10µF low ESL,
ESR ceramic capacitors. The turn on voltage level for VDD
is 2.6V with 130mV of hysteresis.
TEC+ (Pin 16/Pin 14): Noninverting Input to the Differen-
tial TEC Voltage Amplifier.
VREF (Pin 26/Pin 27): This is the output of the Reference.
This pin should be bypassed to GND with a 1µF ceramic
capacitor. The reference is able to supply a minimum of
10mA of current and is internally short-circuit current
limited.
ITEC (Pin 17/Pin 15): Output of the Differential Current
Sense Amplifier. The voltage on this pin is equal to 10 •
(ITEC + IRIPPLE) • RS, where ITEC is the thermoelectric
coolercurrent,IRIPPLE istheinductorripplecurrentandRS
is the sense resistor used to sense this current. This
voltage represents only the magnitude of the current and
provides no direction information. Current limit occurs
when the voltage on this pin exceeds the lesser of 1.5
times the voltage on SS, 1.5 times the voltage on ILIM or
1.5V. When this condition is present, the pair of outputs,
which are presently conducting, are immediately turned
off. The current limit condition is cleared when the CT pin
reaches the next corresponding peak or valley (see Cur-
rent Limit section).
CS– (Pin 18/Pin 16): Inverting Input to the Differential
Current Sense Amplifier.
CS+ (Pin 19/Pin 17): Noninverting Input of the Differential
Current Sense Amplifier. The amplifier has a fixed gain
of 10.
CT (Pin 27/Pin 28): The triangular wave oscillator timing
capacitor pin is used in conjunction with RT to set the
oscillator frequency. The equation for calculating fre-
quency is:
0.75
RT •CT
fOSC
=
Hz
RT (Pin28/Pin29):AsingleresistorfromRT toAGNDsets
the charging and discharging currents for the triangle
oscillator.Thispinalsosetsthedeadtimebetweenturning
onesetofoutputsoffandturningtheothersetontoensure
the outputs do not cross conduct. The voltage on this pin
is regulated to 0.5V. For best performance, the current
sourced from the RT pin should be limited to a maximum
150µA. Selecting RT to be 10k is recommended and
provides 90ns of dead time.
PDRVA, PDRVB (Pins 20, 25/Pins 18, 24): These push-
pull outputs are configured to drive the opposite high side
PMOS switches in a full-bridge arrangement.
1923f
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MAIN CONTROL LOOP
For this condition, the state of each output driver is as
follows: PDRVA is low, NDRVA is high, PDRVB is high and
NDRVB is low. When the voltage on EAOUT is greater than
the voltage on the CT pin, the “B” side of the bridge is
turnedon.TheaveragevoltageacrosstheTEC,VTECOOLER
is approximately:
The LTC1923 uses a constant frequency, voltage mode
architecture to control temperature. The relative duty
cycles of two pairs of N-/P-channel external MOSFETs, set
up in a full-bridge (also referred to as an H-bridge)
configuration are adjusted to control the system tempera-
ture. The full-bridge architecture facilitates bidirectional
current flow through a thermoelectric cooler (TEC) or
other heating element. The direction of the current flow
determines whether the system is being heated or cooled.
Typically a thermistor, platinum RTD or other appropriate
element is used to sense the system temperature. The
control loop is closed around this sense element and TEC.
,
V
TECOOLER = VTEC+ – VTEC– = VDD • (DA – DB)
where
VDD = the full-bridge supply voltage
–
VTECOOLER = VTEC+ – VTEC
DA = the duty cycle of the “A” side of the bridge or the
amount of time the “A” side is on divided by the
oscillator period
The voltage on the output of the error amplifier, EAOUT,
relative to the triangle wave on CT, controls whether the
TEC will be heating or cooling. A schematic of the external
full bridge is shown in Figure 1. The “A” side of the bridge
is comprised of the top left PMOS, MPA, and lower right
NMOS, MNA. The gates of these devices are attached to
the PDRVA and NDRVA outputs of the LTC1923, respec-
tively. The “B” side of the bridge is comprised of PMOS,
MPB and NMOS, MNB. The gates of these MOSFETs are
controlled by the PDRVB and NDRVB outputs of the
LTC1923.
DB = the duty cycle of the “B” side of the bridge
Duty cycle terms DA and DB are related by the following
equation:
DA = 1 – DB
Insteady-state,thepolarityofVTECOOLER indicateswhether
the system is being heated or cooled. Typically, when
current flows into the TEC+ side of the cooler, the system
is being cooled and heated when current flows out of this
terminal. Note: Do not confuse the TEC+ side of the TEC
with the TEC+ input of the LTC1923, although these two
points should be connected together.
The “A” side of the bridge is turned on (NDRVA is high and
PDRVA is low) when the output of the error amplifier is
less than the voltage on the CT pin as shown in Figure 2.
V
DD
EAOUT
PDRVB
PDRVA
MPB
MNA
C
T
MPA
MNB
V
TECOOLER
+
–
B
SIDE
ON
TEC
A
SIDE
ON
NDRVA
PDRVA
NDRVB
NDRVA
1923 F01
3
+
CS
1
2
R
S
NDRVB
PDRVB
–
CS
4
+
TEC
TEC
–
1923 F02
Figure 2. Error Amplifier Output, CT and Output Driver Waveforms
Figure 1. Full-Bridge Schematic
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PROTECTION FEATURES
discharging) as when the current limit condition oc-
curred. For instance, if CT is charging when current limit
occurs, theoutputsareforcedofffortheremainderofthis
charging time, the entire CT discharge time, and are only
re-enabled when CT reaches its valley voltage and begins
charging again. An analogous sequence of events occurs
if current limit is tripped while CT is being discharged.
Many protection features have been integrated into the
LTC1923 to ensure that the TEC is not overstressed or the
system does not thermally run away. These features
includepulse-by-pulsecurrentlimiting,TECvoltageclamp-
ing and open/shorted thermistor detection.
Current Limit
The full-bridge current can be soft-started (gradually
increased) by placing a capacitor from the SS pin to
ground. A 1.5µA current is sourced from the chip and will
chargethecapacitor.Thislimitstheinrushcurrentatstart-
upandallowsthecurrentdeliveredtotheTECtobelinearly
increased from zero.
The peak current in the full bridge during each switching
cycle can be limited by placing a sense resistor, RS, from
the common NMOS source connections of MNA and MNB
to ground. The CS+ and CS– connections should be made
as shown in Figure 1. Current limit is comprised of a fixed
gain of ten differential amplifier, an attenuator (resistor
divider)andacurrentlimitcomparator.Adetaileddiagram
of the circuitry is shown in Figure 3. The differential
amplifier output, ITEC, is provided to allow the user the
ability to monitor the instantaneous current flowing in the
bridge. If an average current is desired, an external RC
filter can be used to filter the ITEC output. Approximately
50ns of leading edge blanking is also internally integrated
to prevent nuisance tripping of the current sense circuitry.
It relieves the filtering requirements for the CS input pins.
The LTC1923 features a dedicated pin, ILIM, to adjust
current limit. If the voltage placed on ILIM is greater than
1V, the default current limit, ILIMIT, is:
ILIMIT = 150mV/RS
where RS = the current sense resistor.
Utilizing the ILIM pin allows the current limit threshold to
be easily set and adjusted (the current limit threshold can
also be adjusted by changing RS). More importantly, it
facilitates independent setting of the heating and cooling
current limits with the addition of one transistor. Figure 4
shows how to implement this using three resistors and an
external NMOS, M1. In many applications, a higher cool-
ing capability is desired. When TEC+ is greater than
TEC–, the H/C output is in a low state signifying that the
system is being cooled (this is typical for most lasers).
During a switching cycle, current limit occurs when the
voltage on ITEC exceeds the lowest of the following three
conditions: 1) 1.5 times the voltage on the SS pin, 2) 1.5
times the voltage on the ILIM pin or 3) 1.5V. When a
currentlimitconditionissensed, allfourexternalFETsare
immediately shut off. These devices are turned back on
only after CT reaches the same state (either charging or
+
TEC
NDRVA
–
TEC
NDRVB
+
–
CURRENT SENSE
AMPLIFIER
CS
CS
+
–
NDRVA NDRVB
INPUT SELECT
A = 10
PULSE-BY-PULSE
CURRENT LIMIT
R
LEB
+
I
I
TEC
LIM
SHUT
OUTPUTS
OFF
2R
1V
S
R
Q
–
–
–
OSCILLATOR
PEAK/VALLEY
1923 F03
1.5µA
SS
Figure 3. Current Sense Circuitry
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OPERATIO
V
REF
V
DD
parameters including the size of the TEC and how well
heatsinked the device is. The TEC itself dissipates power
to produce the temperature differential, generating heat,
which must also be removed. At a certain level of power
dissipation in the TEC, both sides will begin to heat. This
is because the TEC will not be able to pump the self-
generated heat to the outside world, which can lead to
thermal runaway. If the device thermally runs away, dam-
age to the TEC and possibly the components whose
temperature is being regulated will occur.
R
R
PULLUP
ILIM2
I
LIM
R
ILIM1
R
LIM3
LTC1923
+
–
H/C
M1
2N7002
TEC
+
–
TEC
1923 F04
The LTC1923 contains two dedicated comparators that
directly monitor the voltage on the thermistor. If this
voltage is outside the valid window, a latch is set and the
FAULT pin is asserted low. The output drivers are not shut
off and the control circuitry is not disabled, meaning the
part will continue to try to regulate temperature. It is up to
the user to use the FAULT signal to disable the appropriate
circuitry. There are a couple of ways to do this. The first
way is to have the FAULT signal a system microprocessor
to shut the system down through the SDSYNC pin. Fig-
ure 5 shows another means of protecting the system.
External NMOS M1 and PMOS M2 have been added along
with two pull-up resistors (RP1 and RP2). M1 and RP2
invert the FAULT signal while M2 acts as a switch in series
with bridge. When no fault is present, the gate of M1 is
Figure 4. Independently Heating/Cooling Current Limit
TransistorM1isoffandthecurrentlimitthresholdisgiven
by:
0.15 •RILIM1 • VREF
ILIMIT
=
R
ILIM1 +RILIM2 •R
(
)
S
When TEC– is greater than TEC+, the open-drain output,
H/C, pulls high through RPULLUP, causing M1 to turn on.
The current limit value is given by:
0.15 • RILIM1 RILIM3 • V
(
)
REF
ILIMIT
=
R
ILIM2 +RILIM1 RILIM3 •R
(
)
S
V
V
V
DD
DD
DD
reducing the current limit threshold for heating. If the
heating current limit needs to be greater than the cooling
limit, an extra inversion can be added.
R
R
P2
P1
M2
FAULT
M1
Open/Shorted Thermistor Detection
PDRVB
PDRVA
The temperature sense element (NTC thermistor, plati-
num RTD or other appropriate component) must be prop-
erly connected in order for the system to regulate
temperature. If the sense element is incorrectly con-
nected, the system will be unable to control the tempera-
tureandthepotentialexistsforthesystemtothermallyrun
away.
TEC
NDRVB
NDRVA
1923 F05
3
4
+
CS
1
A TEC by nature produces a temperature differential be-
tween opposite sides of the device depending upon how
much current is flowing through it. There is a maximum
limit to the amount of temperature differential that can be
produced, which depends upon a number of physical
R
S
–
2
CS
Figure 5. Redundant Fault Protection
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LTC1923
U
OPERATIO
pulled to VDD forcing the gate of M2 low, which allows the
bridge to operate as described earlier. When a fault occurs
and FAULT is asserted low, M1 is shut off, forcing the gate
ofM2high, shuttingthatdeviceoff. Thepowerpathisthus
opened, ensuring no current is delivered to the TEC. M2
wants to have low RDS(ON) (less than the value of RS to
minimize the power losses associated with it). RP1 and
RP2 can be selected on the order of 100k.
Example: VREF = VSET = 2.5V
R1 = 10k, R2 = 0Ω, R3 = open
RTH = 10k NTC thermistor with a temperature coeffi-
cient of –4.4%/C at 25°C.
The acceptable thermistor impedance range before caus-
ing a fault is 2.5kΩ to 61kΩ. This corresponds to a valid
temperature range of between about –10°C and 60°C.
The lower comparator threshold level is 20% (twenty
percent) of VSET and the upper comparator threshold level
is350mVbelowVSET, whereVSET isthevoltageappliedon
the VSET pin. VSET is typically tied to the bias source for the
thermistor divider so that any variations will track out.
To ensure the part does not power up with a latched fault
at start-up, a fault will not be latched until soft-start has
completed. This corresponds to the voltage on SS reach-
ing 1.5V. For a 1µF soft-start capacitor, this delay is
approximately 1 second. This provides enough time for all
supplies (VDD, setpoint reference and VREF) to settle at
their final values.
The VSET pin has a high input impedance so that a divided-
down voltage can be supplied to this pin to modify the
acceptable thermistor impedance range. This is shown in
Figure 6. The voltage applied to the VSET pin must be a
minimum of 2V. The lower thermistor impedance thresh-
old is:
TEC Voltage Clamping
An internal clamp circuit is included to protect the TEC
from an overvoltage condition. When the differential volt-
age across the TEC exceeds 2.5V, the error amplifier
output voltage at the input of the PWM comparator is
limited. This clamps the duty cycle of the output drivers,
and therefore, the voltage across the TEC. The voltage
where clamping occurs can be increased by placing a
resistor divider in parallel with the TEC and by making the
appropriate connections to TEC+ and TEC– as shown in
Figure 7. The divider increases the voltage across the TEC,
VTECOOLER, where the clamp activates, to:
0.2 •R1•R3
R2 + 0.8 •R3
RTH(LOWER)
=
The upper impedance threshold is:
R1 R3 – α(R2 +R3)
R2 + α(R2 +R3)
(
)
RTH(UPPER)
=
where α = 0.35/VSET
.
ChangingR1alsochangesthevalidthermistorimpedance
range.
RTE1 RTE1
+
RTE1
200k
1+
•2.5 – VCM
RTE2 100k
VTECOOLER
=
RTE1
200k
1+
V
REF
R2
V
V
SET
R3
R1
V
TECOOLER
+
–
THRM
TEC
V
CM
+
TEC
R
TH
10k
NTC
–
R
R
TE1
TE2
TEC
1923 F07
1923 F06
Figure 6. Modifying the Acceptable Thermistor Range
Figure 7. Increasing Voltage Clamp Threshold
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OPERATIO
The terms containing the fixed resistance values are the
loading errors introduced by the input impedance of the
differential amplifier. A common mode voltage error is
alsointroducedsincetheadditionofRTE1 andRTE2 change
the fully differential nature of the amplifier. In order to
minimize these errors select RTE1 and RTE2 to be 10k or
less. The above equation reduces to:
capacitor) is important to ensure oscillator frequency
stability.
The frequency of oscillation is determined by:
f
OSC(kHz) = 750 • 106/[RT(kΩ) • CT(pF)]
TheLTC1923canrunatfrequenciesupto1MHz.Thevalue
selected for RT will also affect the delay time between one
side of the full bridge turning off and the opposite side
turning on. This time is also known as the “break-before-
make” time. The typical value of 10kΩ will produce a 90ns
“break-before-make” time. For higher frequency applica-
tions, a smaller value of RT may be required to reduce this
delay time. For applications where significant slew rate
limiting or external gate driver chips are used, a higher
value for RT may necessary, increasing the dead time. The
“break-before-make” time can be approximately calcu-
lated by:
RTE1
RTE2
VTECOOLER 1+
2.5
The Higher Voltage Applications section shows a fully
differential means to increase the clamp voltage.
This will similarly alter the heating and cooling direction
thresholds by the same factor, increasing the thresholds
to (RTE1 and RTE2 are assumed to be ≤10k)
:
RTE1
DIRH = 50mV 1+
RTE2
tDELAY = RT (kΩ) • 5.75 • 10–9 + 35ns
Phase-Locked Loop
RTE1
DIRL = –50mV 1+
RTE2
The LTC1923 has an internal voltage-controlled oscillator
(VCO) and phase detector comprising a phase-locked
loop. This allows the oscillator to be synchronized with
another oscillator by slaving it to a master through the
SDSYNC pin. The part can also be designated as the
master by pulling the PLLLPF pin high to VDD. This will
result in the part toggling the SDSYNC pin at its set
oscillator frequency. This signal can then be used to
synchronize additional oscillators.
The output voltage on the VTEC pin, VVTEC, will be reduced
by the same ratio:
VTECOOLER
VVTEC
=
RTE1
1+
RTE2
Oscillator Frequency
When being slaved to another oscillator, the frequency
shouldbeset20%to30%lowerthanthetargetfrequency.
The frequency lock range is approximately ±50%.
The oscillator determines the switching frequency and the
fundamental positioning of all harmonics. The switching
frequency also affects the size of the inductor that needs
to be selected for a given inductor ripple current (as
opposed to TEC ripple current which is a function of both
the filter inductor and capacitor). A higher switching
frequency allows a smaller valued inductor for a given
ripple current. The oscillator is a triangle wave design. A
current defined by external resistor RT is used to charge
and discharge the capacitor CT. The charge and discharge
rates are equal. The selection of high quality external
components(5%orbettermultilayerNPOorX7Rceramic
The phase detector is an edge sensitive digital type, which
provides zero degrees phase shift between the external
and internal oscillators. This detector will not lock up on
inputfrequenciesclosetotheharmonicsoftheVCOcenter
frequency. The VCO hold-in range is equal to the capture
range dfH = dfC = ±0.5fO.
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLLPF pin. A simplified block
diagram is shown in Figure 8.
1923f
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LTC1923
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OPERATIO
the oscillator is slaved to an external clock. Figure 9c
illustrates how one LTC1923 can be used as a master to
synchronizeotherLTC1923soradditionaldevicesrequir-
ing synchronization. To implement this, determine the
values of RT and CT to obtain the desired free-running
oscillator frequency of the master by using the equation
given in the oscillator frequency section. Tie the master’s
PLLLPF pin to VDD and the SDSYNC pin to VDD through a
resistor RPLL as shown in Figure 9c. RPLL typically can be
set to 10k, but may need to be a lower value if higher
frequency operation is desired (above 250kHz). Set the
slave free-running frequencies to be 20% to 30% less
than this. The SDSYNC pin of the master will switch at its
free-running frequency (with approximately 50% duty
cycle), and this can be used to synchronize the other
devices.
If the external frequency (fPLLIN) is greater than the oscil-
lator frequency, current is sourced continuously out of the
PLLLPF pin. When the external frequency is less than the
oscillator frequency, current is sunk by the PLLLPF pin.
The loop filter components RLP, CLP and CLP2, smooth out
current pulses from the phase detector and provide a
stableinputtotheVCO.Thesecomponentsalsodetermine
how fast the loop acquires lock. In most instances CLP2
can be omitted, RLP can be set to 1k and CLP can be
selected to be 0.01µF to 0.1µF to stabilize the loop. Make
sure that the low side of filter components is tied to AGND
tokeepunwantedswitchingnoisefromalteringtheperfor-
mance of the PLL.
Figure 9 illustrates three different ways to set the oscilla-
tor frequency. In Figure 9a, the oscillator is free running
with the frequency determined by RT and CT. In Figure 9b,
V
V
DD
DD
R
PLL
R
C
T
PLLLPF
DIGITAL
PHASE
FREQUENCY
DETECTOR
EXTERNAL
FREQUENCY
OSC
T
SDSYNCB
R
LP
C
C
LP2
LP
1923 F08
Figure 8. Phase-Locked Loop Block Diagram
NC
PLLLPF
R
C
PLLLPF
R
C
T
T
T
R
R
T
T
CLP2
RLP
CLP
LTC1923
LTC1923
V
DD
SDSYNC
CLKIN
SDSYNC
T
C
C
T
T
1923 F09a
1923 F09b
(9a) Free Running
(9b) Slave Operation with External Clock—
Set Oscillator Frequency at 70% to 80% of External Clock
V
MASTER
PLLLPF
SLAVE
DD
R
C
PLLLPF
R
T
T
R
T
1.2 • R
T
CLP2
RLP
CLP
RPLL
LTC1923
LTC1923
SDSYNC
SDSYNC
C
T
T
C
T
C
T
1923 F09c
(9c) Master/Slave Operation—Set Oscillator Frequency of Slave at 70% to 80% of Master
Figure 9. Oscillator Frequency Setup: a) Free Running b) Slaved Operation c) Master/Slave Operation
1923f
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The thermistor may be isolated from the control circuitry.
It has a relatively high input impedance and is therefore
susceptibletonoisepickup. Extremecareshouldbetaken
to ensure this signal is noise free by shielding the line
(coaxially). A lowpass filter can be added between the
thermistor and the input to the LTC2053, but since it is in
the signal path, there are limitations on how much filtering
can be added.
The peak inductor current is equal to ITEC + ∆I1/2 and is
the current level that trips the current limit comparator.
Keeping the ripple current component small relative to
I
TEC keeps the current limit trip level equal to the current
flowing through the TEC.
Example: VBRIDGE = 5V, RTEC = 2.5Ω, VTEC = 2.5V,
ITEC = 1A, L = 22µH, fOSC = 250kHz. The peak-to-peak
ripple current using the above equation is:
Inductor Ripple Current
∆I1 = 170mA
The current that flows in the bridge can be separated into
two components, the DC current that flows through the
TEC and the inductor ripple current that is present due to
the switchmode nature of the controller. Although the TEC
current has its own ripple component, proper filtering will
minimize this ripple relative to the inductor ripple current,
validatingthisassumptionthattheTECcurrentisconstant
(see TEC Ripple Current section). A simplified half-circuit
of the bridge in steady-state is shown in Figure 10. The
current, IL, through the inductor (L) consists of the ripple
current (∆I1) and static TEC current (ITEC). The ripple
current magnitude, ∆I1, can be calculated using the fol-
lowing equation:
The peak inductor current is therefore 1.085A in order to
get 1A of DC TEC current.
TEC Ripple Current
Every TEC has a fundamental limitation (based mainly on
the TEC’s physical characteristics) on the maximum
temperature differential that it can create between sides.
The ability to create this maximum temperature differen-
tial is affected by the amount of ripple current that flows
through the device, relative to the DC component. An
approximation of this degradation due to TEC ripple cur-
rent is given by the following equation:
dT/dTMAX = 1/(1 + N2)
∆I1 = (VBRIDGE2 – VTEC2)/(4 • fOSC • L • VBRIDGE
)
where:
where
dT is the adjusted achievable temperature differential
VBRIDGE is the full-bridge supply voltage (typically VDD)
fOSC is the oscillator frequency
dTMAX is the maximum possible temperature differen-
tial when the TEC is fed strictly by DC current and is
typically specified by the manufacturer
L is the filter inductor value
VTEC is the DC voltage drop across the TEC
N is the ratio of TEC ripple current to DC current
TEC manufacturers typically state that N should be no
greater than 10%.
V
BRIDGE
I
I
PDRVA
NDRVB
MPA
L
TEC
L
+
ESR
MNB
TEC
V /2
TEC
C
1/2 V
BRIDGE
1923 F10
Figure 10. Full-Bridge Half Circuit
1923f
17
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APPLICATIO S I FOR ATIO
In this application, the bridge supply voltage, oscillator
frequency and external filter components determine the
amount of ripple current that flows through the TEC.
Higher valued filter components reduce the amount of
ripple current through the TEC at the expense of increased
board area. Filter capacitor ESR along with inductor ripple
current will determine the peak-to-peak voltage ripple
across the TEC and therefore the ripple current since the
TEC appears resistive.
For this example the DC current flowing through the TEC
is1A,makingtheripplecurrentequaltoapproximately1.7%
(this illustrates why ITEC can be approximated to be DC).
Closing the Feedback Loop
Closing the feedback loop around the TEC and thermistor
(orothertemperaturesensitiveelement)involvesidentify-
ing where the thermal system’s poles are located and
placing electrical pole(s) (and zeroes) to stabilize the
control loop. High DC loop gain is desirable to keep
extremely tight control on the system temperature. Unfor-
tunately the higher the desired loop gain, the larger the
compensation values required to stabilize the system.
Given the inherently slow time constants associated with
thermal systems (on the order of many seconds), this can
lead to unreasonably large component values. Therefore,
the amount of loop gain necessary to maintain the desired
temperature accuracy should be calculated, and after
adding some margin, this should be the target DC loop
gain for the system. A block diagram of the system is
shown in Figure 11. The gain blocks are as follows:
The ripple current through the TEC, ITEC(RIPPLE), is
approximately equal to:
2
VBRIDGE2 – VTEC
ITEC(RIPPLE)
16 • fOSC2 •L •C •RTEC • VBRIDGE
2
VBRIDGE2 – VTEC •ESR
(
)
+
2 • fOSC •L • VBRIDGE •RTEC
where:
fOSC = the oscillator frequency
L = the filter inductor value
KIA = instrumentation amplifier gain (V/V)
KEA = error amplifier gain (V/V)
KMOD = modulator gain (d/V)
KPWR = power stage gain (V/d)
KTEC = TEC gain (°C/V)
C = the filter capacitor value
RTEC = the resistance of the TEC
VTEC = the DC voltage drop across the TEC
ESR = the equivalent series resistance of the filter
capacitor
KTHRM = Thermistor Gain (V/°C)
VBRIDGE = the full-bridge supply voltage typically equal
to VDD
KIA and KEA are the electrical gains associated with the
instrumentation and LTC1923 error amplifier. Switching
regulators are sampled systems that convert voltage to
duty cycle (d), which explains why the KMOD and KPWR
gain terms are expressed as a function of duty cycle and
voltage. The TEC converts voltage to temperature change,
while the thermistor’s impedance and therefore voltage
across it changes with temperature.
Theequationaboveshowsthattherearetwocomponents,
which comprise TEC ripple current. The first term is the
increase in voltage from the charging of the filter capaci-
tor. The second term is due to the filter capacitor ESR and
is typically the dominant contributor. Therefore the filter
capacitorselectedwantstohavealowESR. Thiscapacitor
can be made of multilevel ceramic, OS-CON electrolytic or
other suitable capacitor. Increasing the oscillator fre-
quency will also reduce the TEC ripple current since both
termshaveaninverserelationshiptooperatingfrequency.
The loop gain can be expressed by the following equation:
T (loop gain) = KIA • KEA • KMOD • KPWR • KTEC • KTHRM
And the error introduced by the finite gain of the system,
VE, can be expressed by:
Example: VBRIDGE = 5V, RTEC = 2.5Ω, VTEC = 2.5V,
L = 22µH, C = 22µF, fOSC = 250kHz, ESR = 100mΩ
VE = VIN/(1 + T)
ITEC(RIPPLE) = 3.1mA + 13.6mA = 16.7mA
1923f
18
LTC1923
W U U
APPLICATIO S I FOR ATIO
U
This voltage error translates back into a temperature
setpoint error.
KMOD • KPWR = 2 • VDD/VCT = 2 • VDD
whereVCT =theCT voltagewhichhasafixed1Vamplitude.
Example:
The TEC gain depends upon the TEC selected and corre-
sponds to the relationship between the voltage across the
device and what temperature differential is created. This
gaintermchangeswithoperatingtemperature,andwhether
the TEC is heating or cooling. TECs are inherently more
efficient at heating (and therefore have a higher gain) as
compared to cooling. A worst-case rough estimation of
the gain can be obtained by taking the maximum TEC
voltage required to force a given change in temperature
from the TEC specifications:
RTHRM = 10k
NTC with 4.4%/°C at 25°C
R1 = 10k
VREF = 2.5V
T = 25°C
For this thermistor with a 25°C temperature setpoint, the
change in thermistor voltage with temperature is given by
–25mV/°C. In order to maintain a 0.01°C temperature
accuracy, this translates into a 250µV error signal, VE. The
minimum loop gain can now be calculated from the above
equation:
K
TEC = dT/VTEC(MAX)
The thermistor gain should be linearized around tempera-
ture setpoint.
VE = VIN/(1 + T)
Example:
A 25°C setpoint temperature requires VIN = 1.25V for
VREF = 2.5V. The required loop gain is 5000 or 74dB.
Setpoint T = 25°C
VDD = 5V
There are two handles to adjust the loop gain, KIA and KEA,
while the other handles are fixed and depend upon the TEC
andthermistorcharacteristics(KTEC andKTHRM),VSET and
R1(KTHRM)andVDD (KMOD andKPWR).Themodulatorand
power gain product is given by:
RTHRM = 10k NTC with 4.4%/°C at 25°C
R1 = 10k
VREF = 2.5V
dT/VTEC(MAX) = 45°C/1.5V = 30°C/V
K
V
K
K
K
K
K
TEC
THRM
IA
EA
MOD
PWR
V
TECOOLER
REF
R1
LTC2053
LTC1923
+
10k
+
–
C
+
–
T
TEC
+
POWER
STAGE
V
+
10k
NTC
E
–
ERROR
AMP
–
V
IN
R
A
1923 F11
R
F
C
F
Figure 11. Simplified Loop Block Diagram
1923f
19
LTC1923
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APPLICATIO S I FOR ATIO
The linearized thermistor gain around 25°C is –25mV/°C.
For a minimum loop gain of 5000 as calculated above, the
combined gain of the instrumentation and error amplifiers
can be calculated:
system. Thecomponentvaluesshownonthefrontpageof
this data sheet provide a good starting point, but some
adjustment may be required to optimize the response.
Dominant pole compensation does have its limitations. It
provides good loop response over a wide range of laser
module types. It does not provide the fastest transient
response to step changes in temperature. If this is a
necessity, a more complex compensation approach as
shown in Figure 12 may be required. This approach adds
an additional zero into the feedback loop to speed up the
transient response. First note that the LTC2053 inputs
have been swapped as the LTC1923 error amplifier is now
running in an inverting configuration. Capacitor CA is
needed to provide the lead term. Resistor RC is used to
buffer the LTC2053 from capacitive loading and limit the
error amplifier high frequency gain.
KIA • KEA = T/(KMOD • KPWR • KTEC • KTHRM
KIA • KEA = 5000/(10 • 30 • 0.025) = 667
)
A combined gain of 1000 can be selected to provide
adequatemargin.Theinstrumentationamplifiergainshould
be set at typically 10, as this attenuates any errors by its
gain factor. The error amplifier gain would then be limited
totheremainderthroughthegainsettingresistors, RF and
RA shown in Figure 11.
RF/RA = KEA – 1
The multiple poles associated with the TEC/thermistor
system makes it difficult to compensate. Compounding
this problem is that there will be significant variations in
thermal time constants for the same system, making
elaboratecompensationschemesdifficulttoreliablyimple-
ment. The most robust method (i.e., least prone to
oscillation) is to place a dominant pole well below the
thermal system time constant (τ) (anywhere from many
seconds to minutes). This time constant will set the
capacitor value by the following equation:
Since the system thermal pole locations are not known, a
qualitative compensation approach must be employed.
This entails looking at the transient response when the
TECisheating(duetotheinherenthighergain)forasmall-
signalstepchangeintemperatureandmodifyingcompen-
sationcomponentstoimprovetheresponse.Areasonable
starting point is to select components that mimic the
response that will be obtained from the front page of this
data sheet. Therefore RA, RB and CB would be selected to
be 1MΩ, 1MΩ and 0.47µF, respectively. RC should be
selected to be a factor of 100 smaller than RA, or on the
order of 10k. Make sure that the loop is stable prior to the
introduction of capacitor CA. The addition of CA will
provide some phase boost in the loop (in effect, offsetting
oneofthepolesassociatedwiththethermalsystem).Start
CF = τ/RF
Please refer to Application Note 89 for more detailed
information on compensating the loop. Ceramic capaci-
tors are not recommended for use as the integrating
capacitor or anywhere in the signal path as they exhibit a
piezoelectric effect which can introduce noise into the
C
C
10k
C
B
C
A
R
B
REF
TMP
REF
CMD
+
V
OUT
R
C
R
A
LTC1658
6
LTC2053
–
FB
5
LTC1923
–
A = 10
EAOUT
4
+
10k
NTC
1923 F12
ERROR
CNTRL
AMPLIFIER
Figure 12. Alternative Compensation Method to Improve Transient Response
1923f
20
LTC1923
W U U
APPLICATIO S I FOR ATIO
U
with CA on the order of CB and note its affect on system
response. Adjust the values based on observing whether
the transient response was improved or not with the goal
of reducing CB to improve settling time. As the system
thermal poles can vary between “identical” laser modules
(i.e., same manufacturer and model), care must be taken
to ensure that the values selected provide the desired
response even with these thermal term variations. Com-
pensation should also be tailored for each unique laser
module as thermal terms can vary significantly between
different brands. CC rolls off high frequency gain , mini-
mizing noise in the outputs. It is typically about 25 times
smaller than CB. CA, CB and CC should be film capacitors.
cantly to temperature stability. The relatively mild operat-
ingconditionsinsidethelasermodulepromotegoodlong-
term thermistor stability. A high quality, low temperature
coefficient resistor should be selected to bias the ther-
mistor. If the 10k resistor has a 100ppm/°C temperature
coefficient, this translates into a 0.18°C setpoint tempera-
ture differential over a 0°C to 70°C ambient for a desired
25°C laser setpoint. Depending upon the temperature
stability requirements of the system, this is very signifi-
cant. A lower temperature coefficient resistor may there-
fore be desired. The LTC2053 has maximum offset drift to
50nV/°C which translates into less than 0.001°C change
for a 0°C to 70°C ambient.
The offset drift of the LTC1923 error amplifier divided by
the gain of the LTC2053 also affects temperature stability.
The offset drift of the LTC1923 (see characteristic curves)
is typically 1mV over a 0°C to 70°C ambient. After attenu-
ation by the LTC2053 gain, this translates into a tempera-
ture setpoint variation of 0.004°C. Neither of these offsets
driftssignificantlywithaging.Dependinguponthesetpoint
temperature stability requirements of the system, the
LTC2053instrumentationamplifiermaynotbenecessary.
Figure 13 shows a simplified schematic with the LTC2053
omitted.
Temperature Stability
It is important to differentiate between temperature accu-
racy and stability. Since each laser’s output maximizes at
some temperature, temperature setpoint is typically
incremented until this peak is achieved. After this, only
temperaturestabilityisrequired.Thepredominantparam-
eterswhichaffecttemperaturestabilityarethethermistor,
the thermistor biasing resistor and any offset drift of the
front-end electrical circuitry. Sufficient loop gain ensures
that any downstream variations do not contribute signifi-
10k
CNTRL
4
+
REF
LTC1923
FB
6
TMP
CMD
100k
10M
V
OUT
–
10k
NTC
ERROR
LTC1658
AMPLIFIER
4.7µF
EAOUT
5
1923 F13
Figure 13. Simplifed Temperature Control Loop Omitting
the LTC2053 Instrumentation Amplifier Front End
1923f
21
LTC1923
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APPLICATIO S I FOR ATIO
Noise and Slew Rate Control
good trade-off between switching and conduction losses.
AbovethisTECcurrentleveltheMOSFETsselectedshould
have lower RDS(ON) to maintain the high end efficiency.
One disadvantage of switching regulators is that the
switching creates wideband harmonic energy. The high
frequency content can pose problems to associated cir-
cuitry. To combat this issue, the LTC1923 offers a pin
called RSLEW that controls the slew rate of the output drive
waveforms. Slowing down the transition interval reduces
the harmonic frequency content by spreading out the
energy over a longer time period. The additional transition
time causes some efficiency loss (on the order of 2% to
3%) but significantly improves the high frequency noise
reflected onto the input supply.
Efficiency Considerations
Unliketypicalvoltageregulators, wheretheoutputvoltage
is fixed, independent of load current, the output voltage of
this regulator changes with load current. This is because
the TEC appears resistive and the current through the TEC
sets the voltage. The output power of the regulator is
defined as:
P
OUT = ITEC2 • RTEC
Slew rate control is engaged by placing a resistor from
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%.
Often it is useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most significant improvement. Efficiency can
be expressed as:
RSLEW toAGND.Ifslewratecontrolisnotdesired,theRSLEW
pin should be tied to VDD allowing the output drivers to
transition at their fastest rate. The resistor value should be
setbetween10k(fastesttransition)and300k(slowesttran-
sition). This provides about a 10:1 slew rate range to op-
timize noise performance. The “break-before-make” time
may need to be increased if slew control is implemented,
especially for slower transition rates. Adjustment can be
done by increasing the value of RT (CT can be reduced to
maintain the same frequency of operation), to ensure that
the bridge MOSFETs receive nonoverlapping drive.
Efficiency = 100% – (L1 + L2 + L3 + …)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
For this application, the main efficiency concern is typi-
cally at the high end of output power. A higher power loss
translates into a greater system temperature rise, result-
ingintheneedforheatsinking,increasingboththesystem
size and cost.
Power MOSFET Selection
Four external MOSFETs must be selected for use with the
LTC1923; a pair of N-channel MOSFETs for the bottom of
the bridge and a pair of P-channel MOSFETs for the top
diagonals of the bridge. The MOSFETs should be selected
for their RDS(ON), gate charge and maximum VDS, VGS
ratings. A maximum VDS rating of 20V is more than
sufficient for 5V and 12V bridge applications, but as
mentioned in the High Voltage Application section, a 12V
maximum VGS rating is insufficient and higher voltage
MOSFETs must be selected. There is a trade-off between
There are three main sources which usually account for
most of the losses in the application shown on the front
page of the data sheet: Input supply current, MOSFET
switching losses and I2R losses.
1) The input supply current is comprised of the quiescent
current draw from the LTC1658, LTC2053, LTC1923 and
any additional circuitry added. The total maximum supply
current for these devices is on the order of 5mA, which
gives a total power dissipation of 25mW. This power loss
is independent of TEC current.
R
DS(ON) and gate charge. The RDS(ON) affects the conduc-
2
tion losses (ITEC • RDS(ON)), while gate charge is a
dominantcontributortoswitchinglosses.AhigherRDS(ON)
MOSFET typically has a smaller gate capacitance and thus
requires less current to charge the gate for the same
BVDSS.For1ATECapplications,theSi9801DYorSi9928DY
complimentary N- and P-channel MOSFETs provide a
2) The MOSFET driver current results from switching the
gate capacitance of the power MOSFETs. Each time a gate
is switched from low to high to low again, a packet of
charge dQ moves from VDD to ground. The gate charging
current, IGATECHG = 2 • f • (QP + QN), where QP and QN are
1923f
22
LTC1923
W U U
APPLICATIO S I FOR ATIO
U
the total gate charges of the NMOS and PMOS on one side
of the bridge, and f is the oscillator frequency. The factor
of 2 arises from there being two sets of MOSFETs that
make up the full bridge. Note that increasing the switching
frequency will increase the dynamic current and therefore
power dissipation by the same factor. This power loss is
independent of TEC current.
Total series resistance = 0.055 + 0.08 + 2 • 0.1 + 0.1
= 0.435Ω
Power Loss = (1A)2 • 0.435Ω = 0.435W
Output Power = (1A)2 • 2.5Ω = 2.5W
This represents a 17% efficiency loss due to conduction
losses. The other two power loss mechanisms comprise
a little more than a 3% efficiency loss at this output power
level. Thismaysoundalarmingifelectricalefficiencyisthe
primary concern and can be easily improved by choosing
lower RDS(ON) MOSFETs, lower series resistance induc-
tors and a smaller valued sense resistor. If temperature
rise is the primary concern, this power dissipation may be
acceptable. At higher current levels, this example does
illustrate that lower resistance components should be
selected.
Example: QN = 10nC max, QP = 15nC max, f = 225kHz,
VDD = 5V
Power loss = 2 • f • (QP + QN) • VDD = 56mW
3) The DC resistances of the external bridge MOSFETs,
filter inductors and sense resistor are typically the domi-
nant loss mechanism at the high end TEC current. The
conduction path of the current includes one NMOS, one
PMOS, two inductors and the sense resistor so the DC
resistances associated with the components dissipate
power.
Low Voltage Requirements
All components shown on the front page of this data sheet
will operate with a 2.7V input supply. Minor modifications
are required to guarantee correct operation. The voltage
on the REF input of the LTC2053 should be at least 1V
below VDD. Figure 14 shows how to implement this. By
dividing down the 2.5V reference with 500Ω of imped-
ance, feeding this to the REF input of the LTC2053 and the
integrating resistor of the LTC1923 error amplifier, any
common mode issues will be avoided.
Example:
RDS(ON)NMOS at 5V = 0.055Ω max
RDS(ON)PMOS at 5V = 0.08Ω max
RS = 0.1Ω
RL = 0.1Ω,
ITEC = 1A
RTEC = 2.5Ω
250Ω
10k
250Ω
1µF
10k
NTC
REF
LTC2053
+
REF
CNTRL
EAOUT
V
REF
1µF
LTC1658
V
–
OUT
A = 10
4.7µF
LTC1923GN
FB
10M
100k
V
DD
2.7V TO 3.3V
V
DD
V
V
SET
THRM
1923 F14
Figure 14. Low Input Supply Voltage Circuit
1923f
23
LTC1923
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APPLICATIO S I FOR ATIO
Higher Voltage Applications
Two pairs of resistors, RT1 and RT2, must be added to
ensure that the absolute maximum input voltage is not
exceeded on the TEC+ and TEC– inputs. The maximum
voltage on TEC+ and TEC– must be less than the VDD input
supply to the LTC1923 which, for this example, is 5V. The
following equation will guarantee this:
A bank of TECs can be wired in series to minimize board
real estate utilized by the application. A higher voltage
supply may be required depending upon how many TECs
are placed in series and what their maximum voltage
drop is. In other applications, only one high current
supply may be available, with the output voltage of this
supply being greater than the LTC1923’s absolute maxi-
mumvoltagerating.Theabsolutemaximuminputvoltage
for the LTC1923 is 6V. Since the current drawn by the
LTC1923 is small, it can be powered from a low current,
5V (or less) supply. A 12V application for driving the full
bridge is shown in Figure 15. Two LTC1693-1 high speed
dualMOSFETdriversareusedtostepupthelowervoltage
produced by the LTC1923 drivers to the higher voltage
levels required to drive the full bridge. The LTC1693
requires proper bypassing and grounding due to its high
switching speed and large AC currents. Mount the low
ESR bypass capacitors as close to the pins as possible,
shortening the leads as much as possible to reduce
inductance. Refer to the LTC1693 data sheet for more
information. Since the LTC1693-1 low-to-high and high-
to-low propagation delays are almost identical (typically
35ns), there is minimal skew introduced by the addition
of these drivers. Sufficient dead time (typically 50ns)
between one leg of the bridge shutting off and the other
turning on, as set up by the LTC1923, will be maintained.
If this dead time is insufficient, the resistor tied to the RT
pin can be increased to increase this time.
VBRIDGE
< VDD
RT1 RT1
1+
+
RT2 100k
where VBRIDGE is the supply voltage to the external bridge
circuitry and VDD is the input supply to the LTC1923.
These additional level shifting resistors affect some pa-
rameters in the data sheet. The direction comparator
thresholds are increased to:
(1 + RT1/RT2 + RT1/100k) • 50mV and
(1 + RT1/RT2 + RT1/100k) • –50mV
The output voltage on the VTEC pin represents the voltage
across the TEC (VTECOOLER) reduced by a factor of
(1 + RT1/RT2 + RT1/100k) or:
VVTEC = VTECOOLER/(1 + RT1/RT2 + RT1/100k)
The term containing 100k is the loading error introduced
by the input impedance of the differential amplifier. Typi-
cally this value will be 100k, but can vary due to normal
process tolerances and temperature (up to±30%). Due to
this variability, it may be desirable to minimize the loading
effect to try to keep a tight tolerance on the TEC clamp
voltage. Although it will increase quiescent current draw,
this can be accomplished by making the value of RT1 as
small as possible.
Care must be taken to ensure that the external MOSFETs
areproperlyselectedbasedonthemaximumdrain-source
voltage,VDS,gate-sourcevoltage,VGS,andRDS(ON).Many
MOSFETs that have an absolute maximum VDS of 20V
have a maximum VGS of only 12V, which is insufficient for
12Vapplications.Eventhe14VmaximumVGS ratingofthe
Si9801DY may not provide adequate margin for a 12V
bridge supply voltage. Refer to Efficiency Considerations
for more discussion about selecting a MOSFET with
RDS(ON).
As a result of this level shifting, the TEC voltage necessary
to activate the clamp is raised. The voltage across the TEC
where the voltage clamp activates will be:
V
TECOOLER = (1 + RT1/RT2 + RT1/100k) • 2.5V
One drawback with using the LTC1693 MOSFET drivers is
the inability to adjust the slew rate of the output drivers to
reduce system noise.
1923f
24
LTC1923
W U U
U
APPLICATIO S I FOR ATIO
PLLLPF
R
C
T
R
SLEW
T
12V
LTC1693-1
SDSYNCB
CNTRL
EAOUT
FB
V
REF
IN1
GND1 OUT1
IN2
GND2 OUT2
0.1µF
V
CC1
10µF
47µF
PDRVB
NDRVB
V
CC2
4.7µF
0.1µF
TEC
V
DD
5V
1µF
AGND
PGND
NDRVA
PDRVA
LTC1923
4.7µF
LTC1693-1
IN1
SS
V
CC1
I
LIM
GND1 OUT1
IN2
GND2 OUT2
3
4
+
1
V
CC2
V
SET
CS
R
2
S
–
FAULT
CS
V
I
THRM
TEC
R
R
R
R
T1
T1
+
H/C
TEC
TEC
–
V
TEC
T2
T2
1923 F15
Figure 15. Higher Voltage Applications with the LTC1923
1923f
25
LTC1923
U
TYPICAL APPLICATIO
1923f
26
LTC1923
U
PACKAGE DESCRIPTIO
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
0.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.004 – 0.009
0.015 ± 0.004
(0.38 ± 0.10)
0.053 – 0.069
× 45°
(1.351 – 1.748)
(0.102 – 0.249)
0.0075 – 0.0098
(0.191 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN28 (SSOP) 1098
1923f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
27
LTC1923
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.57 ±0.05
5.35 ±0.05
4.20 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.23 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ± 0.05
0.40 ± 0.10
5.00 ± 0.10
(4 SIDES)
31 32
0.00 – 0.05
PIN 1
TOP MARK
1
2
3.45 ± 0.10
(4-SIDES)
(UH) QFN 0102
0.200 REF
0.23 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC1658
14-Bit Rail-to-Rail Micropower DAC
3V or 5V Single Supply Operation, I = 270µA,
8-Lead MSOP Package
CC
LTC1693-1
LTC2053
High Speed Dual N-Channel MOSFET Driver
Zero Drift Instrumentation Amp
1.5A Peak Output Current, 1GΩ Electrical Isolation, SO-8 Package
Max Gain Error 0.01%, Input Offset Drift of 50nV/°C, Input Offset Voltage of 10µV
1923f
LT/TP 0502 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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